cd00205953

AN2815
Application note
High-efficiency step-down controller
with embedded 2 A LDO regulator
Introduction
The PM6675AS device consists of a single, high-efficiency step-down controller and an
independent low dropout (LDO) linear regulator.
The constant on-time (COT) architecture assures fast transient response supporting both
electrolytic and ceramic output capacitors. An embedded integrator control loop
compensates the DC voltage error due to the output ripple.
Selectable low-consumption mode allows the highest efficiency over a wide range of load
conditions. The low-noise mode sets the minimum switching frequency to 33 kHz for audiosensitive applications. The LDO linear regulator can sink and source up to 2 Apk. Two fixed
current limits (±1 A and ±2 A) can be chosen.
An active soft-end is independently performed on both the switching and the linear
regulators outputs when disabled.
Figure 1.
PM6675AS demonstration board
!-V
August 2008
Rev 1
1/42
www.st.com
Contents
AN2815
Contents
1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Switching section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
LDO section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
JP3 fixed or adjustable output voltage (VSEL pin) . . . . . . . . . . . . . . . . . . 14
6.2
JP1 power-saving mode (NOSKIP pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3
JP2 LDO current limit (LILIM pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.4
JP5 compensation network (COMP pin) . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
PM6675AS demonstration tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/42
9.1
VOUT and LOUT turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.2
VOUT working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.3
VOUT and LOUT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.4
VOUT and LOUT load transient responses . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.5
VOUT efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.6
VOUT gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.7
VOUT and LOUT turn-off (soft-end) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.8
UV, OV and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.9
VOUT current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.10
LOUT current limit (foldback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AN2815
10
Contents
9.11
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.12
Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3/42
List of figures
AN2815
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
4/42
PM6675AS demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PM6675AS demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Top side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
JP3 (VSEL) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JP1 (NOSKIP) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JP2 (LILIM) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JP5 (COMP) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PM6675AS demonstration board test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VOUT soft-start at 150 mW load, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LOUT turn-on, VOUT in pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VOUT = 1.5 V, VIN = 24 V, IVOUT = 0 A, forced-PWM mode . . . . . . . . . . . . . . . . . . . . . . . . 21
VOUT = 1.5 V, VIN = 24 V, IVOUT = 0 A, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VOUT = 1.5 V, VIN = 24 V, no load, non-audible pulse-skip mode (33 kHz) . . . . . . . . . . . . 23
VOUT load regulation - VIN = 24 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LOUT load regulation - LDOIN = VOUT , VOUT in forced PWM mode . . . . . . . . . . . . . . . . . 25
VOUT load transient (VIN=24 V, LOAD=0 A to 7 A at 2.5 A/µs), pulse-skip mode. . . . . . . . 26
VOUT load transient (VIN = 24 V, LOAD=0 A to 7 A at 2.5 A/µs), pulse-skip mode. . . . . . . 27
Forced PWM (blue), non-audible pulse-skip (green), pulse-skip (red), efficiency vs.
output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External MOSFET gate signals (VIN = 24 V, LOAD = 0), pulse-skip mode . . . . . . . . . . . . 29
External MOSFET gate signals (VIN = 24 V, LOAD = 7 A), pulse-skip mode . . . . . . . . . . 29
VOUT and LOUT output voltages, VOUT soft-end, LOUT powered by an auxiliary rail. . . . . . 30
VOUT and LOUT output voltages, LOUT soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
UV protection, pulse-skip mode, LOUT powered by an auxiliary rail . . . . . . . . . . . . . . . . . . 32
OV protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VOUT and LOUT rails, thermal shutdown, pulse-skip mode, LOUT powered by VOUT . . . . . 34
VOUT current limit protection during a load transient (0 A to 9 A at 2.5 A/µs . . . . . . . . . . . 35
LOUT current limit during an output short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Switching frequency vs. input voltage, VOUT = 1.5 V, IVOUT = 2 A, forced PWM mode . . . 37
Forced PWM (blue), non-audible pulse-skip (green) and pulse-skip (red), Switching
frequency vs. output current, VOUT = 1.5 V, VIN = 24 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ILOUT = 0 A, average IC temperature = 31.0 °C, max internal IC temperature = 33.1 °C. . 39
ILOUT = 0.2 A, average IC temperature = 38.2°C, max internal IC temperature = 40.7 °C . 39
ILOUT = 0.5 A, average IC temperature = 38.2 °C, max internal IC temperature = 41.5 °C 40
ILOUT = 1.0 A, average IC temperature = 48°C, max internal IC temperature = 55.2 °C . . 40
AN2815
Main features
1
Main features
1.1
Switching section
1.2
●
4.5 V to 36 V input voltage range
●
0.6 V, ±1% voltage reference
●
1.5 V fixed output voltage
●
0.6 V to 3.3 V adjustable output voltage
●
1.237 V ±1% reference voltage available
●
Very fast load transient response constant on-time loop control
●
No-RSENSE current sensing using low-side MOSFETs' RDS(on)
●
Negative current limit
●
Latched OVP, UVP and thermal shutdown
●
Fixed 3 ms soft-start
●
Selectable pulse-skipping at light load
●
Selectable non-audible (33 kHz) pulse-skip mode
●
All ceramic output capacitor applications supported
●
Output voltage ripple compensation
●
Output soft-end
LDO section
●
0.6 V to 3.3 V adjustable output voltage
●
Selectable ±1 A or ±2 A current limit
●
Dedicated Power Good signal
●
Ceramic output capacitors supported
●
Output soft-end
5/42
PGND
LGND
LPG
LOUT
LIN
VCCGND
J9
J11
J8
J7
J6
J10
1
1
1
R18
100k
1
1
1
VCC
0
0
R20
10k
10u
C6
0
NOSKIP
JP1
10u
C7
0
R7
3R9
C10
2
C9
100n
1
0
N.M.
C19
N.M.
C20
0
R22
33k
R21
100k
1
1
2
3
4
5
6
25
2
R10
0
1
C12
100n
D1
BAT41J
0
R8
12k
R9
13k
VSEL
JP3
LILIM
JP2
18
VCC 17
LGND
LGATE 16
LFB
PGND 15
NOSKIP
LPG PM6675AS
SPG 14
LEN 13
SGND
SWEN
AVCC
THPD
U1
0
C11
10u
VCC
R3 1k5
2
0
VCC
C21
100p
1
R2
18k
1
C22
100p
C13
100n
2
0
0
0
1
100k
2
R17
R13
100k
LEN-SWEN
SW1
R12 100k
1
2
R11
1
2
R1 330k
VCC
0
R4 3R3
1
2
C14
100n
0
2
1
2
1
2
R19
7.5k
0
C5
1u
1
2
1
2
1
2
1
2
2
1
1
2
1
2
1
2
24
23
22
21
20
19
LOUT
LIN
BOOT
HGATE
PHASE
CSNS
VREF
VOSC
VSNS
VSEL
COMP
LILIM
7
8
9
10
11
12
C17
N.M.
Q2
0
C16
1
S7NF60L
4
4
Q1
D2
2
1n
0
S7NF60L
C1
10u
0
INT-VESR
JP5
TP1
GND_TP
C18
1n
R16
4R7
R14
7k5
1
2
6n8
1
C15
R15 6k8
2
MLC1538-152ML
L1 1.5u
0
C2
10u
2x UMK325BJ106KM-T
1
2
VCC
1
2
5
6
7
8
1
2
3
5
6
7
8
1
2
3
1
STPS1L60A
1
2
J5
2
4
6
1
3
5
1
2
1
2
R6
0
220u
C3
220u
C4
2x 4TPE220MF
1
2
VCC
4
3
1
2
2
4
6
1
3
5
1
2
1
2
1
2
6/42
1
2
J2
J1
VOUT
VIN
1
1
J4
J3
SPG
PGND
STPS1L60A
D3
1
1
Figure 2.
1
2
Main features
AN2815
PM6675AS demonstration board schematic
AM00963v1
AN2815
Bill of material
2
Bill of material
Table 1.
PM6675AS demonstration board bill of material
Qty
Component
Description
Package
Part number
Manufacturer
Value
2
C1, C2
Ceramic, 50 V,
X5R, 20%
SMD 1210
UMK325BJ106KM-T
Taiyo Yuden
10 µF
2
C3, C4
POSCAP, 4 V,
15 mΩ, 20%
SMD D Case
4TPE220MF
Sanyo
220 µF
1
C5
Ceramic, 6.3 V,
X5R, 10%
SMD 1206
Standard
1 µF
3
C6, C7, C11
Ceramic, 6.3 V,
X5R, 10%
SMD 0805
Taiyo Yuden
10 µF
4
C9, C10, C13,
C14
Ceramic, 50 V,
X7R, 20%
SMD 0603
Standard
100 n
1
C12
Ceramic, 50 V,
X7R, 10%
SMD 0805
Standard
100 n
1
C15
Ceramic, 50 V,
X7R, 10%
SMD 0603
Standard
6n8
1
C16
Ceramic, 50 V,
X7R, 10%
SMD 0603
Standard
1n
1
C17
Ceramic, 20%
SMD 0603
Standard
N.M.
1
C18
Ceramic, 50 V,
X7R, 10%
SMD 0805
Standard
1n
2
C19, C20
Ceramic, 6.3 V,
X5R, 10%
SMD 0805
Taiyo Yuden
N.M.
2
C21, C22
Ceramic, 50 V,
X7R, 10%
SMD 0603
Standard
100 p
1
R1
Chip resistor,
0.1W, 1%
SMD 0603
Standard
330 kΩ
1
R2
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
18 kΩ
1
R3
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
1.5 kΩ
2
R4, R7
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
3R3
1
R6
Chip resistor,
0.1 W, 1%
SMD 0805
Standard
0
1
R8
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
12 kΩ
1
R9
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
13 kΩ
JMK212BJ106KG-T
JMK212BJ106KG-T
7/42
Bill of material
Table 1.
AN2815
PM6675AS demonstration board bill of material (continued)
Qty
Component
Description
Package
3
R10, R17, R21
Chip resistor,
0.1 W, 1%
4
R11, R12,
R13,R18
1
Manufacturer
Value
SMD 0603
Standard
0
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
100 kΩ
R14
Chip resistor,
0.1 W, 1%
SMD 0805
Standard
15 kΩ
1
R15
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
3k9
1
R16
Chip resistor,
0.1 W, 1%
SMD 0805
Standard
4R7
1
R19
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
7k5
1
R20
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
10 kΩ
1
R22
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
N.M.
1
L1
MLC1538-152ML
Coilcraft
1.5 µH
2
Q1, Q2
N-Channel, 60
V
SO-8
STS7NF60L
STMicroelectronics
1
D1
Schottky, 100 V,
0.2 A
SOD-323
BAT41J
STMicroelectronics
1
D2
Schottky, 60 V,
1A
DO214-AC
STPS1L60A
STMicroelectronics
1
D3
1
U1
Controller
11
J1, J2, J3, J4,
J5, J6, J7, J8,
J9, J10,J11
Header, single
pin
3
JP1, JP2, JP3
Jumper, 2x3,
100 mils
1
JP5
PCB pads
selector
1
TP6
Test point
1
SW1
Dip switch 2
8/42
SMT, 10.6
13.8x13.2 mm
Arms, 4.36 mΩ
Part number
N.M.
VFQFPN-24
PM6675AS
STMicroelectronics
JP4 N.M.
DIP-2
Standard
AN2815
3
Component assembly and layout
Component assembly and layout
Figure 3.
Top side component placement
AM00964v1
Figure 4.
Top view
AM00965v1
9/42
Component assembly and layout
Figure 5.
AN2815
Layer 2 view
AM00966v1
Figure 6.
Layer 3 view
AM00967v1
10/42
AN2815
Component assembly and layout
Figure 7.
Bottom view
AM00968v1
Figure 8.
Bottom side component placement
AM00969v1
11/42
I/O interface
4
AN2815
I/O interface
The PM6675AS demonstration board has the following test points as shown in Table 2.
Table 2.
12/42
PM6675AS demonstration kit input and output interface
Test point
Description
VIN
Battery input voltage positive terminal
VOUT
Switching regulator output
PGND
Battery input and VOUT output common return
LIN
LDO linear regulator input
LOUT
LDO linear regulator output
LGND
LDO linear regulator output return
LPG
LDO linear regulator Power Good signal
VCC
+5 V supply, positive terminal
VCCGND
Signal ground and VCC supply return
SPG
VOUT SW regulator Power Good signal
TP1
Connection point between power and signal grounds
AN2815
5
Recommended equipment
Recommended equipment
●
4 V to 36 V, 30 W power supply
●
Active loads
●
Digital mutimeters
●
200 MHz four-trace oscilloscope
13/42
Configuration
6
AN2815
Configuration
The PM6675AS demonstration board allows the user to choose the desired mode of
operation using four jumpers (JP1, JP2, JP3 and JP5) and two resistors. Refer to the
following configuration description.
6.1
JP3 fixed or adjustable output voltage (VSEL pin)
The JP3 jumper is used to choose between fixed output voltage (1.5 V) and a user-defined
output voltage in the range 0.6 V to 3.3 V. When connected in the lower position, the fixed
1.5 V output voltage is selected (Figure 8).
If JP3 is in the upper position, the output voltage is given by:
Equation 1
VOUTADJ = 0.6 ⋅
Figure 9.
R8 + R9
R8
JP3 (VSEL) setting
!DJUSTABLEOUTPUTVOLTAGE
6
FIXEDOUTPUT
VOLTAGE DEFAULTPOSITION
!-V
The R8 and R9 resistors are set to 12 kΩ and 13 kΩ respectively (1.25 V output voltage)
and can be changed by the user.
6.2
JP1 power-saving mode (NOSKIP pin)
The JP1 jumper allows choosing the mode of operation of the switching section. Three
options (forced-PWM, pulse-skip and non-audible pulse-skip) can be selected by changing
the JP1 setting as shown in Figure 9:
14/42
AN2815
Configuration
Figure 10. JP1 (NOSKIP) setting
Forced PWM
(default position)
No-audible pulse-skip
Pulse-skip
AM00971v1
6.3
JP2 LDO current limit (LILIM pin)
The JP2 jumper is used to select the LDO current limit. In the upper position the LDO output
current limit is set to 2 A, while in the lower position the current limit is set to 1 A. The middle
position is not used.
Figure 11. JP2 (LILIM) setting
2 A LDO current limit
1 A LDO current limit
AM00972v1
15/42
Configuration
6.4
AN2815
JP5 compensation network (COMP pin)
The JP5 jumper is located on the bottom side of the PM6675AS board and allows
connecting the integrator input (COMP pin) to the output through a simple capacitor
(integrative compensation) or using the "virtual ESR" network for very low ESR output
capacitor applications (e.g. all ceramic output cap applications). The integrative
compensation is set by default. Refer to the PM6675AS datasheet for details about the allceramic output capacitor applications and the virtual ESR design.
Figure 12. JP5 (COMP) setting
)NTEGRATIVECOMPENSATION
DEFAULTPOSITION
6IRTUAL%32NETWORK
!-V
16/42
AN2815
7
Test setup
Test setup
Figure 12 shows the suggested setup connections between the PM6675AS demonstration
board, the loads and the external supply. The LDO input (LIN) is connected to VOUT by
default (R6 = 0 Ω).
Figure 13. PM6675AS demonstration board test setup
AM00974v1
17/42
Getting started
8
AN2815
Getting started
The following step-by-step power-up and power-down sequences are provided in order to
correctly evaluate the PM6675AS demonstration board performance.
●
Power-up sequence
–
Working in an ESD-protected environment is highly recommended. Check all wrist
straps and ground mat connections before handling the PM6675AS demonstration
board
–
Connect power supplies as shown in the PM6675AS demonstration board test
setup (Figure 12) and insert the meters in order to perform the desired
performance evaluation. Connect the scope-probes as desired
–
Set the JP1 through JP5 jumpers in order to properly configure the PM6675AS
board (default position suggested). Set the SWEN-LEN switches to the on position
(upper position); Do not change jumper settings when the board is powered
–
Set the VCC supply to 5 V±5% and the current limit to 100 mA
–
Set the VIN supply to a voltage in the range 4.5 V to 36 V. An initial test at 24 V and
2 A current limit is suggested
–
Set all the loads to 0 A
–
Turn-on the VIN supply
–
Turn-on the VCC supply
–
Vary the VOUT load from 0 A to 8 A
–
Vary the LOUT load from 0 A to 2 A to test source capability. If a different LDO input
is desired, connect the external rail as dashed in Figure 12 and remove the R6
resistor. All changes must be done when the board is not powered
–
Vary VIN supply from 4.5 V to 36 V
●
Power-down sequence
–
Decrease LOUT loads to 0 A
–
Reduce VOUT load to 0 A
–
Decrease VCC supply from 5 V to 3.8 V in order to test the UVLO
–
Increase VCC supply from 3.8 V to 5 V to restart the device
–
Use the SWEN-LEN switches to test soft-start and soft-end on both outputs
–
Turn-off the VOUT load
–
Turn-off the VCC supply
–
Turn-off the VIN supply
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PM6675AS demonstration tests
9
PM6675AS demonstration tests
9.1
VOUT and LOUT turn-on (soft-start)
The VOUT soft-start is divided in 4 steps. In each step the current limit is increased by ¼ of
the nominal value. This behavior is well understood by loading the rail, as performed in the
test. LOUT soft-start is performed at its maximum available current.
Figure 14. VOUT soft-start at 150 mΩ load, pulse-skip mode
AM00975v1
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Figure 15. LOUT turn-on, VOUT in pulse-skip mode
AM00976v1
9.2
VOUT working mode
●
VOUT forced PWM mode
When the forced PWM working mode is selected (JP1 in the upper position), the inductor
current is allowed to become negative and the following waveform can be captured.
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PM6675AS demonstration tests
Figure 16. VOUT = 1.5 V, VIN = 24 V, IVOUT = 0 A, forced-PWM mode
AM00977v1
●
VOUT pulse-skip mode
The default working mode is the pulse-skip algorithm, in which the low-side MOSFET is
turned off when the inductor current becomes equal to zero. This behavior allows reaching
the maximum efficiency.
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Figure 17. VOUT = 1.5 V, VIN = 24 V, IVOUT = 0 A, pulse-skip mode
AM00978v1
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PM6675AS demonstration tests
●
VOUT non-audible pulse-skip mode
In order to avoid too low switching frequencies, the non-audible pulse-skip mode can be
selected (JP1 in the middle). Doing so, the minimum switching frequency allowed is 33 kHz
as depicted in Figure 18.
Figure 18. VOUT = 1.5 V, VIN = 24 V, no load, non-audible pulse-skip mode (33 kHz)
AM00979v1
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PM6675AS demonstration tests
9.3
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VOUT and LOUT load regulation
Figure 19 and 20 refer to VOUT and LOUT output voltage variations versus load current. The
switching section directly supplies the linear LDO.
Figure 19. VOUT load regulation - VIN = 24 V
6/54LOADREGULATION
&ORCED070ULSESKIP
.ONAUDIBLE03
6OLTAGE;6=
#URRENT;!=
!-V
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Figure 20. LOUT load regulation - LDOIN = VOUT , VOUT in forced PWM mode
,/54LOADREGULATION
6OLTAGE;6=
#URRENT;!=
!-V
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PM6675AS demonstration tests
9.4
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VOUT and LOUT load transient responses
Transient load responses are evaluated by loading VOUT and LOUT output rails with a current
slew rate of 2.5A/µs.
Figure 21. VOUT load transient (VIN=24 V, LOAD=0 A to 7 A at 2.5 A/µs), pulse-skip
mode
AM00982v1
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Figure 22. VOUT load transient (VIN = 24 V, LOAD=0 A to 7 A at 2.5 A/µs), pulse-skip
mode
AM00983v1
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9.5
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VOUT efficiency
The three working modes lead to different power efficiency. The test setup is VIN=24 V,
FSW = 330 kHz, VOUT = 1.5 V. Figure 23 summarizes the results.
Figure 23. Forced PWM (blue), non-audible pulse-skip (green), pulse-skip (red),
efficiency vs. output current
6/54%FFICIENCY
%FFICIENCY;=
)RUFHG3:0
3XOVH6NLS
1RQ$XGLEOH36
#URRENT;!=
!-V
9.6
VOUT gate drivers
The PM6675AS internal MOSFET driver turns on and off the high-side and low-side
external MOSFET, avoiding cross-conduction. In the following two pictures the gates signals
are shown in two different load conditions: without load (Figure 24) and with load
(Figure 25).
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Figure 24. External MOSFET gate signals (VIN = 24 V, LOAD = 0), pulse-skip mode
AM00985v1
Figure 25. External MOSFET gate signals (VIN = 24 V, LOAD = 7 A), pulse-skip
mode
AM00986v1
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9.7
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VOUT and LOUT turn-off (soft-end)
●
VOUT soft-end
When the SWEN pin is pulled down, the switching section performs the output capacitor
discharge by turning on the discharge MOSFET. The external low-side MOSFET is turned
on when the output voltage is lower than about 400 mV.
Figure 26. VOUT and LOUT output voltages, VOUT soft-end, LOUT powered by an
auxiliary rail
AM00987v1
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PM6675AS demonstration tests
●
LOUT soft-end
By pulling down the LEN pin the linear regulator is forced to discharge its output capacitor,
by turning on its discharge MOSFET. Doing so, the LOUT rail is turned off in a safe way,
avoiding output voltage under ground spikes.
Table 3.
Typical discharge MOSFETs RDS(on) resistance
Description
VOUT output
LOUT output
Typical discharge MOSFETs RDS(on)
25 Ω
25 Ω
Figure 27. VOUT and LOUT output voltages, LOUT soft-end
AM00988v1
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PM6675AS demonstration tests
9.8
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UV, OV and thermal protections
●
Latched UV protection
If the switching section output voltage is lower than the 70% nominal value, the undervoltage
state is entered and the discharge MOSFET is turned on (as in the the soft-end state).
Figure 28. UV protection, pulse-skip mode, LOUT powered by an auxiliary rail
AM00989v1
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●
Latched OV protection
If the switching section output voltage is higher than the 115% nominal value, the
overvoltage state is entered and the low-side MOSFET is turned on in order to quickly
discharge the output capacitor and avoid load damages.
Figure 29. OV protection, pulse-skip mode
AM00990v1
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PM6675AS demonstration tests
●
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Latched thermal shutdown
If the junction temperature rises above 150 deg the thermal protection circuit turns off the
device and discharges the switching section output capacitor by performing the soft-end.
Figure 30. VOUT and LOUT rails, thermal shutdown, pulse-skip mode, LOUT powered
by VOUT
AM00991v1
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9.9
PM6675AS demonstration tests
VOUT current limit
The valley current limit avoids any high-side turn-on if the inductor current is higher than the
programmed value. This current limit can be designed with the following equation:
Equation 2
I CL =
100µA ⋅ RILIM
RLS , DSon
The current sensing is performed by comparing the voltage drop in the low-side MOSFET,
during the TOFF period, with the voltage drop given by an injected current and the current
limit resistor.
Figure 31. VOUT current limit protection during a load transient (0 A to 9 A at
2.5 A/µs
AM00992v1
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PM6675AS demonstration tests
9.10
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LOUT current limit (foldback)
The linear LDO regulator has a foldback protection feature which reduces the current limit to
about 1 A when the output voltage is outside the ±10% Power Good window. The current
limit is restored to about 2 A when the output voltage re-enters the Power Good window.
Figure 32. LOUT current limit during an output short
AM00993v1
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Switching frequency
●
Switching frequency vs. input voltage
The constant on-time controller leads to a quasi-constant switching frequency, slightly
following the input voltage.
Figure 33. Switching frequency vs. input voltage, VOUT = 1.5 V, IVOUT = 2 A, forced
PWM mode
37FREQUENCYVSINPUTVOLTAGE
&REQUENCY;K(Z=
9.11
PM6675AS demonstration tests
6OLTAGE;6=
!-V
37/42
PM6675AS demonstration tests
●
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Switching frequency vs. output current
The switching frequency can decrease to very low values in pulse-skip mode but in nonaudible pulse-skip there is a lower limit (about 33kHz). By increasing the load, however, the
switching frequency increases a bit, as a consequence of conduction and switching losses.
Figure 34. Forced PWM (blue), non-audible pulse-skip (green) and pulse-skip (red),
Switching frequency vs. output current, VOUT = 1.5 V, VIN = 24 V
37FREQUENCYVS6/54LOAD
&REQUENCY;K(Z=
&ORCED07-
0ULSESKIP
.ONAUDIBLE03
#URRENT;!=
!-V
9.12
Thermal behavior
The IC internal maximum and average temperature can be monitored by an IR camera. For
the following measures the test setup is:
–
VIN = 24 V
–
FSW = 330 kHz
–
Pulse-skip mode
–
VOUT = 1.5 V at IVOUT = 4 A
–
LOUT = 1.05 V, powered by VOUT
–
TAMB = 23 °C
By increasing the LOUT current the IC temperature changes as depicted in Figure 35
through 38.
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Figure 35. ILOUT = 0 A, average IC temperature = 31.0 °C, max internal IC
temperature = 33.1 °C
AM00996v1
Figure 36. ILOUT = 0.2 A, average IC temperature = 38.2°C, max internal IC
temperature = 40.7 °C
AM00997v1
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Figure 37. ILOUT = 0.5 A, average IC temperature = 38.2 °C, max internal IC
temperature = 41.5 °C
AM00998v1
Figure 38. ILOUT = 1.0 A, average IC temperature = 48°C, max internal IC
temperature = 55.2 °C
AM00999v1
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10
Revision history
Revision history
Table 4.
Document revision history
Date
Revision
20-Aug-2008
1
Changes
Initial release
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