Application Note 1071
Design Consideration with AP3581A/B/C and AP3583/A
Prepared by Jian Wu
System Engineering Dept.
external reference voltage from 0.4V to 3V at tracking
mode or internal 0.6V reference at stand-alone mode.
1. Introduction
The AP3581A/B/C and AP3583/A are voltage-mode single
phase synchronous buck controllers with embedded
MOSFET drivers. The AP3581A/BC and AP3583/A
operate at fixed frequency of 300kHz (AP3581A/B,
AP3583A) or 200kHz (AP3581C, AP3583). The reference
voltage is 0.8V (AP3581B/C) and 0.6V (AP3581A,
AP3583/A). The main difference between AP3581A/B/C
and AP3583/A is that: the AP3583/A has an internal
compensation, and it supports both tracking mode and
stand-alone mode operation. The output voltage is tightly
regulated to the external e
2. Functional Description
The AP3581A/B/C and AP3583/A include internal
soft-start and pre-biased output, power input detection,
over voltage protection, under voltage protection, over
current protection and shutdown function. They provide
customers a compact, high efficiency, well-protected and
cost-effective solutions. For more information, please refer
to the functional block diagram (Figure 1 and 2).l
Figure 1. Functional Block Diagram of AP3581A/B/C
Sep. 2011
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Application Note 1071
Figure 2. Functional Block Diagram of AP3583/A
2.1 Power on Reset and Chip Enable
A Power On Reset (POR) circuitry continuously monitors
the supply voltage at VCC pin. Once the rising POR
threshold is exceeded, the AP3581A/B/C and AP3583/A
set themselves to active state and are ready to accept chip
enable command. The rising POR threshold is typically
4.2V at VCC rising.
For AP3581A/B/C, the COMP/EN is a multifunctional pin:
control loop compensation and chip enable as shown in
Figure 3. An Enable Comparator monitors the COMP/EN
pin voltage for chip enable. A signal level transistor is
adequate to pull this pin down to ground and shut down
AP3581A/B/C. A 120μA current source charges the
external compensation network with 0.45V ceiling when
this pin is released. If the voltage at COMP/EN pin exceeds
0.3V, the AP3581A/B/C initiates its soft-start cycle.
Figure 3. Chip Enable (AP3581A/B/C)
For AP3583/A, The REFIN is a multifunctional pin:
external reference input and chip enable as shown in Figure
The 120μA current source keeps charging the COMP pin to
its ceiling until the feedback loop boosts the COMP pin
higher than 0.45V according to the feedback signal. The
current source is cut off when VCOMP is higher than 0.45V
during normal operation.
Sep. 2011
To select internal 0.6V reference voltage, just let REFIN
pin open. A 100μA current source tries to pull high the
REFIN voltage after POR is detected by the enable compa-
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for AP3581B; to 0.8V in 3.6ms for AP3581C) after the
soft-start cycle is initiated. The ramp is created digitally, so
there will be 100 small discrete steps. Accordingly, the
output voltage will follow the SS signal and ramp up
smoothly to its target level.
rator. An signal level transistor is adequate to pull this pin
down to ground and shut down the AP3583/A. As Q1 turns
off, the REFIN voltage is pulled high to VDD by the 100 μA
current source. As the REFIN voltage acrosses 0.3V
threshold, the enable comparator initiates the operation of
the AP3583/A. The REFIN voltage is compared with 3.0V
voltage to select the reference voltage with 1ms delay after
chip enabling. The internal 0.6V reference voltage is
selected. Soft-start cycle is initiated after reference
selection is completed.
The SS signal keeps ramping up after it exceeds the
internal 0.6V (AP3581A, AP3583/A) or 0.8V (for
AP3581B/C) reference voltage. However, the internal 0.6V
or 0.8V (for AP3581B/C) reference voltage takes over the
behavior of error amplifier after VSS>VREF. When the SS
signal climb to its ceiling voltage (4.2V), the
AP3581A/B/C and AP3583/A claims the end of soft-start
cycle and enable the under voltage protection of the output
To select external reference voltage, connect REFIN to a
voltage ranging from 0.4V to 3V. As Q1 is turned off, the
REFIN voltage is aligned to the external reference input.
As the REFIN voltage acrosses 0.3V threshold, the enable
comparator initiates the operation of AP3583/A. The
REFIN voltage is compared with 3.0V voltage to select the
reference voltage with 1ms delay after chip enabling. The
external reference input is selected as the reference voltage
when REFIN voltage is lower than 3.0V. If the reference
input voltage is higher than 3.0V, the internal 0.6V
reference voltage is still be selected. Soft-start cycle is
initiated after reference selection is completed
Figure 5 shows a typical start-up interval for
AP3581A/B/C where the COMP/EN pin has been released
from a grounded (system shutdown) state. The internal
120μA current source starts charge the compensation
network after the COMP/EN pin is released from ground at
T1. The COMP/EN exceeds 0.3V and enables the AP3581
at T2. The COMP/EN continues ramping up the stays at
0.45V before the SS starts ramping at T3. The output
voltage follows the internal SS and ramps up to its final
level during T3 and T4. At T4, the reference voltage VREF
takes over the behavior of the error amplifier as the internal
SS crosses VREF. The internal SS keeps ramping up and
stay at 4.2V at T5, where AP3581 asserts the end of
soft-start cycle.
Figure 6 shows a typical start-up waveform of AP3581 for
VIN powering on.
For the external reference voltage of AP3583/A, the
effective soft-start time is calculated as:
Figure 4. Chip Enable and Reference Selection (AP3583/A)
2.2 Soft-start
A built-in soft-start is used to prevent surge current from
power supply input VIN during turning on (Refer to the
Functional Block Diagram). The error amplifier is a
three-input device. Reference voltage VREF or the internal
soft-start voltage SS whichever is smaller dominates the
behavior of the non-inverting inputs of the error amplifier.
SS internally ramps up to 0.6V in 2.0ms for AP3581A
/AP3583A (to 0.6V in 2.6ms for AP3583; to 0.8V in 2.7ms
Sep. 2011
Figure 5. Start-up Interval
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2.4 Power Input Detection
The AP3581A/B/C and AP3583/A detect PHASE voltage
for the present of power input VIN when UGATE turns on
the first time. If the PHASE voltage does not exceed 2.0V
when UGATE turns on, the AP3581A/B/C asserts that VIN
is not ready and stops the soft-start cycle. However, the
internal SS continues ramping up to VDD. Another
soft-start is initiated after SS ramps up to VDD. The hiccup
period is about 1ms. Figure 8 shows the start-up waveform
where VIN does not present initially.
Time 10ms/div
Figure 6. Start-up Waveform of AP3581A/B/C
2.3 Pre-Biased Outputs
Figure 7 shows the normal VOUT start-up curve in blue;
Initialization begins at T0, and output ramps between T1
and T2. If the output is pre-biased to a voltage less than the
expected value, as shown by the magenta curve, the
AP3581A/B/C and AP3583/A will detect that condition.
Neither MOSFET will turn on until the soft-start ramp
voltage exceeds the output; VOUT starts seamlessly ramping
from there. If the output is pre-biased to a voltage above
the expected value, as in the black curve, neither MOSFET
will turn on until the output voltage is pulled down to the
expected value through external load. Any resistive load
connected to the output will help pull down the voltage.
Time 1ms/div
Figure 8. Soft-start (VIN not Present Initially)
2.5 Over Current Protection (OCP)
Figure 9 shows the over current protection (OCP) scheme
of AP3581A/B/C and AP3583/A. A resistor ROCSET
connected from OPS pin sets the threshold. An internal
current source IOC (40μA typically), flowing through
ROCSET determines the OCP trigger point IOCSET, which can
be calculated using the following equation:
40 μA × R OCSET
10 × R DS(ON)_L
Where RDS(ON)_L is the RDS(ON) of the low side MOSFET.
Because the RDS(ON) of MOSFET increases with
temperature, it is necessary to take this thermal effect into
consideration in calculating OCP point.
VOUT Over-Charaged
VOUT Pre-Biased
VOUT Normal
Figure 9. Over Current Protection Scheme
Figure 7. Soft-start with Pre-bias
Sep. 2011
When OCP is triggered, both UGATE and LGATE will go
low to stop the energy transferred to the load. The
controller will try to restart in a hiccupped way. Figure 10
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Application Note 1071
is not allowed.
shows the hiccupped over current protection. Only four
times of hiccup is allowed in over current. If over current
protection still exist after four times of hiccup, controller
will be latched.
A voltage divider sets the output voltage (Refer to the
typical application circuit). In real applications, choose R1
in 100Ω to 10kΩ range and choose appropriate R2
according to the desired output voltage.
For AP3581A and AP3583/A,
VOUT = 0.6V ×
R1 + R2
For AP3581B/C,
Figure 10. Hiccupped Over Current Protection
VOUT = 0.8V ×
2.6 Over Voltage Protection (OVP)
The feedback voltage is continuously monitored for over
voltage protection. When OVP is triggered, LGATE will go
high and UGATE will go low to discharge the output
3. Component Selection
Typical application circuit of AP3581A/B/C and AP3583/A
are shown in Figure 11 and 12. For the buck controller, the
major external components are power MOSFET switches,
output inductor, input capacitor and output capacitor. The
selection of external component is primarily determined by
the maximum load current and begins with the selection of
power MOSFET switches. The desired amount of ripple
current and operating frequency largely determines the
inductor value. Finally, input capacitor is selected for its
capability to handle the large RMS current and output
capacitor is chosen with low enough ESR to meet the
output voltage ripple and transient specification.
The AP3581A/B/C and AP3583/A provide full-time over
voltage protection whenever soft-start completes or not.
The typical OVP threshold is 137.5% of the internal
reference voltage VREF. The AP3581A/B/C and AP3583/A
provide non-latched OVP. The controller will return to
normal operation if over voltage condition is removed.
2.7 Under Voltage Protection (UVP)
The feedback voltage is also monitored for under voltage
protection. The UV threshold is set at 0.4V. The under
voltage protection has 15μs triggered delay. When UVP is
triggered, both UGATE and LGATE will go low. Unlike
OCP, UVP is not a latched protection; The controller will
always try to restart in a hiccupped way.
3.1 Power MOSFET Selection
The AP3581A/B/C and AP3583/A require 2 N-channel
power MOSFET for upper (controlled) and lower
(synchronous) switches. These should be selected based on
RDS(ON), gate supply requirements, and the thermal
management requirements
2.8 Thermal shutdown
If the junction temperature of the device reaches the
thermal shutdown limit of 160°C, the PWM and the
oscillator is turned off and UGATE and LGATE are driven
low, turning off both MOSFETs. When the junction cools
to the required level (140°C nominal),
The gate drive voltage is supplied by VCC pin that receives
4.5 to 13.2V supply voltage. When operating with a
7~13.2V power supply for VCC, a wide variety of NMOSFET can be used. Logic-level threshold MOSFET
should be used if the input voltage is expected to drop
below 7V. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics.
2.9 Output Voltage Selection
The output voltage can be programmed to any level
between the 0.6V internal reference (0.8V for AP3581B/C)
to the 80% of VIN supply. The lower limitation of output
voltage is caused by the internal reference. The upper
limitation of the output voltage is caused by the maximum
available duty cycle (80%). This is to leave enough time
for over current detection. Output voltage out of this range
Sep. 2011
R1 + R2
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components: conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFET.
These losses are distributed between the two MOSFETs ac-
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Figure 11. Typical Application of AP3581A/B/C
Figure 12. Typical Application of AP3583/A
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current and duty cycle.
cording to duty cycle. Since the AP3581A/B/C and
AP3583/A are operating in continuous conduction mode,
the duty cycle is:
A higher-value inductor can decrease the ripple current and
output ripple voltage, however usually with larger physical
size. And the large inductor value reduces the converter’s
response time to a load transient. So some compromise
needs to be made when selecting the inductor. In most
applications, a good compromise is choosing the ripple
current that is 20% of IOUT(MAX). And the inductance L can
be selected according to:
The resulting power dissipation in the MOSFET at
maximum output current are:
× R DS(ON) × D + × I OUT × VIN × TSW × f S
× R DS(ON) × (1 − D)
L = VOUT ×
Where tSW is the combined switch ON and OFF time, and
fS is the switching frequency.
Another important parameter for selecting the inductor is
the current rating. After fixing the inductor value, the peak
inductor current can be expressed as:
Both MOSFETs have I2R losses and the upper MOSFET
includes an additional term for switching losses, which are
largest at high input voltages. The lower MOSFET losses
are greatest when the duty cycle is near 0, during a
short-circuit or at high input voltage. These equations
assume linear voltage current transitions and do not
adequately model power loss due the reverse-recovery of
the lower MOSFET’s body diode.
2 × VIN × f S × L
The current rating of the selected inductor should be
ensured to be 1.5 times of the peak inductor current.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
The size requirements refer to the area a height
requirement for a particular design. For better efficiency,
choose a low DC resistance inductor. DCR is usually
inversely proportional to size.
3.3 Output Capacitor Selection
The selection of output capacitor is primarily determined
by the ESR (Effective Series Resistance) required to
minimize voltage ripple and load step transients. The
output ripple ΔVOUT is approximately bounded by:
The gate-charge losses are mainly dissipated by the
AP3581A/B/C and AP3583/A and don’t heat the
MOSFETs. However, large gate charge increases the
switching interval, TSW that increases the MOSFET
switching losses. The gate-charge losses are calculated as:
ΔVOUT = ΔI L × ⎜⎜ RESR +
8 × COUT × f S
PG = VCC × (VCC × (C ISS _ UP + C ISS _ LOW ) +
VIN × C RSS _ UP ) × f S
Where ΔIL is the inductor ripple current, and RESR is ESR
of output capacitor.
Where CISS_UP and CISS_LOW are the input capacitance of the
upper and lower MOSFET, and CRSS_UP is the reverse
transfer capacitance of upper MOSFET. Make sure that the
gate-charge loss will not cause over temperature at
AP3581A/B/C and AP3583/A, especially with large gate
capacitance and high supply voltage.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout. Modern components and
loads are capable of producing transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR and voltage rating requirements
rather than actual capacitance requirements.
3.2 Output Inductor Selection
Output inductor selection is usually based on the
consideration of inductance, rated current, size
requirements and DC resistance (DCR). The inductor value
relies on the switching frequency, load current, ripple
Sep. 2011
f S × VIN × I OUT × 20%
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Application Note 1071
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible.
Be careful not to add inductance in the circuit board wiring
that could cancel the usefulness of these low inductance
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP. This function is dominated by a
DC gain and the output filter (L and COUT), with a double
pole break frequency at fLC and a zero at fESR. The DC gain
of the modulator is simply the input voltage (VIN) divided
by the peak-to-peak oscillator voltage VOSC.
3.4 Input Capacitor Selection
The synchronous-rectified Buck converter draws pulsed
current with sharp edges from the input capacitor, resulting
in ripples and spikes at the input supply voltage. Use a mix
of input bypass capacitors to control the voltage overshoot
across the MOSFETs. Use small ceramic capacitors for
high frequency decoupling and bulk capacitors to supply
the current needed each time upper MOSFET turns on.
Place the small ceramic capacitors physically close to the
MOSFETs to avoid the stray inductance along the
connection trace.
The important parameters for the input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is
a conservative guideline. The RMS current rating
requirement for the input capacitor of a buck converter is
calculated as:
Figure 13. Voltage Control Loop Using AP3581
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The double pole of the LC filter
is expressed as:
f LC =
3.5 OCP Resistor ROCSET Setting
The OCP triggering point IOCSET follows the valley
detection of inductor current. For a certain application
condition, the valley inductor current can be expressed as:
2π ⋅ L × COUT
The ESR zero is contributed by the ESR associated with
the output capacitor. The ESR zero of the output capacitor
is expressed as:
2 × VIN × f S × L
f ESR =
Considering the temperature effect of MOSFET RDS(ON),
internal current source IOC difference and precision of
resistor ROCSET, the OCP trigger point IOCSET should be set
above about 15% to 20% IVALLEY for enough margin. So the
OCP resistor ROCSET can be set as:
Sep. 2011
40 μA
3.6 Feedback Loop Compensation
Figure 13 highlights the voltage-mode control loop for a
synchronous-rectified buck converter consisting of AP3581
(AP3583 has the internal compensation). The control loop
includes two stages: Modulator and Power stage & Sensor
and Compensation stage.
Use only special low-ESR capacitors intended for
switching regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
voltage and the initial voltage drop after a high slew-rate
transient. An aluminum electrolytic capacitor’s ESR value
is related to the case size with lower ESR available in
larger case sizes.
[(1 + 15% to 20%) ×I VALLEY ] × 10 × R DS(ON)_L
2π × RESR × COUT
Figure 14 illustrates the bode plot of power and modulator
using AP3581A/B/C and AP3583/A.
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Figure 16 illustrates the system bode plot. The open loop
gain is the sum of the modulation gain and the
compensation gain. The goal is to obtain the required
crossover frequency with sufficient phase margin. The
preferred phase margin is greater than 45o. Follow the
guidelines for locating the poles and zeros of the
compensation network.
1) Pick Mid-Band gain(R1) for desired crossover
frequency, which is preferred to be 1/10 to 1/5 of the
switching frequency;
2) Place compensation zero fZ(C1)below LC double
3) Place compensation pole fP(C2)at half of the switching
4) Check the system open loop gain;
5) Estimate phase margin, repeat if necessary.
Figure 14. Power and Modulator Bode Plot
The AP3581A/B/C and AP3583/A adopt operational
transconductance amplifier (OTA) as the error amplifier.
Figure 15 shows a type II compensation network using
OTA, which provides two poles and one zero to the control
Figure 15. Type II Compensation Network Using OTA
The compensator transfer function is the small-signal
transfer function of VC/VOUT. This function is dominated
by the Mid-Band gain and compensation zero and pole.
The Mid-band gain of the compensation is expressed as:
Mid _ Band _ Gain =
Figure 16. System Bode Plot
4. PCB Layout Considerations
High speed switching and relatively large peak currents in
a synchronous-rectified buck converter make the PCB
layout a very important part of design. Switching current
from one power device to another can generate voltage
spikes across the impedances of the interconnecting bond
wires and circuit traces. The voltage spikes can degrade
efficiency and radiate noise, that results in over-voltage
stress on devices. Careful component placement layout an
printed circuit design can minimize the voltage spikes
induced in the converter.
× gM
One of the poles is located at low frequency to increase the
low frequency gain to improve the DC regulation accuracy.
The location of the other pole and the single zero can be
calculated as follows:
fZ =
2π × R1 × C 2
fP =
⎛ C × C2
2π × R1 × ⎜⎜ 1
⎝ C1 + C 2
Sep. 2011
Follow the below layout guidelines for optimal
performance of the AP3581A/B/C and AP3583/A.
1) The turn-off transition of the upper MOSFET prior to
turn-off, the upper MOSFET was carrying the full load
current. During turn-off, current stops flowing in the upper
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4) Apply another solid layer as a power plane and cut this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node.
5)The PHASE node is subject to very high dV/dt voltages.
Stray capacitance between this island and the surrounding
circuitry tend to induce current spike and capacitive noise
coupling. Keep the sensitive circuit away from the PHASE
node and keep the PCB area small to limit the capacitive
coupling. However, the PCB area should be kept moderate
since it also acts as main heat convection path of the lower
6)The PCB traces between the PWM controller and the
gate of MOSFET and also the traces connecting source of
MOSFETs should be sized to carry 2A peak currents.
MOSFET and is picked up by the low side MOSFET. Any
inductance in the switched path generates a large voltage
spike during the switching interval. Careful component
selections, layout of the critical components, and use
shorter and wider PCB traces help in minimizing the
magnitude of voltage spikes.
2) The power components and the PWM controller should
be placed firstly. Place the input capacitors, especially the
high-frequency ceramic decoupling capacitors, close to the
power switches. Place the output inductor and output
capacitors between the MOSFETs and the load. Also locate
the PWM controller near by the MOSFETs.
3) Use a dedicated grounding plane and use vias to ground
all critical components to this layer. Use an immediate via
to connect the component to ground plane including GND
of the AP3581A/B/C and AP3583/A.
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