Data Sheet

PCF8563
Real-time clock/calendar
Rev. 11 — 26 October 2015
Product data sheet
1. General description
The PCF8563 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power
consumption. A programmable clock output, interrupt output, and voltage-low detector are
also provided. All addresses and data are transferred serially via a two-line bidirectional
I2C-bus. Maximum bus speed is 400 kbit/s. The register address is incremented
automatically after each written or read data byte.
2. Features and benefits
 Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
 Century flag
 Clock operating voltage: 1.0 V to 5.5 V at room temperature
 Low backup current; typical 0.25 A at VDD = 3.0 V and Tamb = 25 C
 400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V)
 Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and
1 Hz)
 Alarm and timer functions
 Integrated oscillator capacitor
 Internal Power-On Reset (POR)
 I2C-bus slave address: read A3h and write A2h
 Open-drain interrupt pin
3. Applications




1.
Mobile telephones
Portable instruments
Electronic metering
Battery powered products
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.
PCF8563
NXP Semiconductors
Real-time clock/calendar
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCF8563BS/4
HVSON10 plastic thermal enhanced very thin small outline
package; no leads; 10 terminals;
body 3  3  0.85 mm
SOT650-1
PCF8563T/5
SO8
plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
PCF8563T/F4[1]
SO8
plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
PCF8563TS/4[2]
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
PCF8563TS/5
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
[1]
Not recommended for new designs. Replacement part is PCF8563T/5.
[2]
Not recommended for new designs. Replacement part is PCF8563TS/5.
5. Marking
Table 2.
PCF8563
Product data sheet
Marking codes
Type number
Marking code
PCF8563BS/4
8563S
PCF8563T/5
PCF8563
PCF8563T/F4
8563T
PCF8563TS/4
8563
PCF8563TS/5
P8563
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PCF8563
NXP Semiconductors
Real-time clock/calendar
6. Block diagram
OSCI
OSCILLATOR
32.768 kHz
DIVIDER
CLOCK OUT
CLKOUT
OSCO
CONTROL
MONITOR
(1)
00
CONTROL_STATUS_1
01
CONTROL_STATUS_2
0D
CLKOUT_CONTROL
02
VL_SECONDS
03
MINUTES
04
HOURS
POWER ON
RESET
TIME
VDD
VSS
WATCH
DOG
05
DAYS
06
WEEKDAYS
07
CENTURY_MONTHS
08
YEARS
ALARM FUNCTION
SDA
SCL
I2C-BUS
INTERFACE
09
MINUTE_ALARM
0A
HOUR_ALARM
0B
DAY_ALARM
0C
WEEKDAY_ALARM
INT
INTERRUPT
TIMER FUNCTION
PCF8563
0E
TIMER_CONTROL
0F
TIMER
001aah658
(1) COSCO; values see Table 30.
Fig 1.
Block diagram of PCF8563
PCF8563
Product data sheet
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PCF8563
NXP Semiconductors
Real-time clock/calendar
7. Pinning information
7.1 Pinning
terminal 1
index area
OSCI
1
10 n.c.
OSCO
2
9
VDD
n.c.
3
8
CLKOUT
INT
4
7
SCL
VSS
5
6
SDA
PCF8563BS
OSCI
1
OSCO
2
VDD
7
CLKOUT
PCF8563T
001aaf981
INT
3
6
SCL
VSS
4
5
SDA
Transparent top view
001aaf975
For mechanical details, see Figure 29.
Fig 2.
8
Top view. For mechanical details, see
Figure 30.
Pin configuration for HVSON10
(PCF8563BS)
Fig 3.
Pin configuration for SO8
(PCF8563T)
OSCI
1
8
VDD
OSCO
2
7
CLKOUT
INT
3
6
SCL
VSS
4
5
SDA
PCF8563TS
001aaf976
Top view. For mechanical details, see Figure 31.
Fig 4.
PCF8563
Product data sheet
Pin configuration for TSSOP8 (PCF8563TS)
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PCF8563
NXP Semiconductors
Real-time clock/calendar
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
SO8, TSSOP8
HVSON10
OSCI
1
1
oscillator input
OSCO
2
2
oscillator output
INT
3
4
interrupt output (open-drain; active LOW)
VSS
4
5[1]
ground
SDA
5
6
serial data input and output
SCL
6
7
serial clock input
CLKOUT
7
8
clock output, open-drain
VDD
8
9
supply voltage
n.c.
-
3, 10
not connected; do not connect and do not
use as feed through
[1]
PCF8563
Product data sheet
Description
The die paddle (exposed pad) is connected to VSS through high ohmic (non-conductive) silicon attach and
should be electrically isolated. It is good engineering practice to solder the exposed pad to an electrically
isolated PCB copper pad for better heat transfer but it is not required as the RTC doesn’t consume much
power. In no case should traces be run under the package exposed pad.
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Rev. 11 — 26 October 2015
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PCF8563
NXP Semiconductors
Real-time clock/calendar
8. Functional description
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing register address,
an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which
provides the source clock for the Real-Time Clock (RTC) and calender, a programmable
clock output, a timer, an alarm, a voltage-low detector, and a 400 kHz I2C-bus interface.
All 16 registers are designed as addressable 8-bit parallel registers although not all bits
are implemented. The first two registers (memory address 00h and 01h) are used as
control and/or status registers. The memory addresses 02h through 08h are used as
counters for the clock function (seconds up to years counters). Address locations 09h
through 0Ch contain alarm registers which define the conditions for an alarm.
Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the Timer_control
and Timer registers, respectively.
The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm,
Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD)
format.
When one of the RTC registers is written or read, the contents of all time counters are
frozen. Therefore, faulty writing or reading of the clock and calendar during a carry
condition is prevented.
8.1 CLKOUT output
A programmable square wave is available at the CLKOUT pin. Operation is controlled by
the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default),
1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller
clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain
output and enabled at power-on. If disabled it becomes high-impedance.
8.2 Register organization
Table 4.
Formatted registers overview
Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they
could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.
Address Register name
Bit
7
6
5
4
3
2
1
0
Control and status registers
00h
Control_status_1
TEST1
N
STOP
N
TESTC
N
N
N
01h
Control_status_2
N
N
N
TI_TP
AF
TF
AIE
TIE
x
WEEKDAYS (0 to 6)
Time and date registers
02h
VL_seconds
VL
SECONDS (0 to 59)
03h
Minutes
x
MINUTES (0 to 59)
04h
Hours
x
x
HOURS (0 to 23)
05h
Days
x
x
DAYS (1 to 31)
06h
Weekdays
x
x
x
x
07h
Century_months
C
x
x
MONTHS (1 to 12)
08h
Years
YEARS (0 to 99)
PCF8563
Product data sheet
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PCF8563
NXP Semiconductors
Real-time clock/calendar
Table 4.
Formatted registers overview …continued
Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they
could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.
Address Register name
Bit
7
6
5
4
3
2
1
0
Alarm registers
09h
Minute_alarm
AE_M
MINUTE_ALARM (0 to 59)
0Ah
Hour_alarm
AE_H
x
HOUR_ALARM (0 to 23)
0Bh
Day_alarm
AE_D
x
DAY_ALARM (1 to 31)
0Ch
Weekday_alarm
AE_W
x
x
x
x
WEEKDAY_ALARM (0 to 6)
FE
x
x
x
x
x
FD[1:0]
x
x
x
x
x
TD[1:0]
CLKOUT control register
0Dh
CLKOUT_control
Timer registers
0Eh
Timer_control
TE
0Fh
Timer
TIMER[7:0]
8.3 Control registers
8.3.1 Register Control_status_1
Table 5.
Bit
7
Control_status_1 - control and status register 1 (address 00h) bit description
Symbol
Value
Description
Reference
TEST1
0[1]
normal mode
Section 8.9
1
EXT_CLK test mode
N
0[2]
unused
STOP
0[1]
RTC source clock runs
1
all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC
clock is stopped (CLKOUT at 32.768 kHz is still available)
must be set to logic 0 during normal operations
6
5
Section 8.10
4
N
0[2]
unused
3
TESTC
0
Power-On Reset (POR) override facility is disabled; set to logic 0 for
normal operation
1[1]
Power-On Reset (POR) override may be enabled
000[2]
unused
2 to 0
N
[1]
Default value.
[2]
Bits labeled as N should always be written with logic 0.
Section 8.11.1
8.3.2 Register Control_status_2
Table 6.
Bit
7 to 5
4
Control_status_2 - control and status register 2 (address 01h) bit description
Symbol
Value
Description
N
000[1]
Reference
unused
TI_TP
0[2]
INT is active when TF is active (subject to the status of TIE)
1
INT pulses active according to Table 7 (subject to the status of TIE);
Remark: note that if AF and AIE are active then INT will be
permanently active
PCF8563
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 26 October 2015
Section 8.3.2.1
and
Section 8.8
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCF8563
NXP Semiconductors
Real-time clock/calendar
Table 6.
Control_status_2 - control and status register 2 (address 01h) bit description …continued
Bit
Symbol
Value
Description
Reference
3
AF
0[2]
read: alarm flag inactive
Section 8.3.2.1
write: alarm flag is cleared
1
read: alarm flag active
write: alarm flag remains unchanged
2
0[2]
TF
read: timer flag inactive
write: timer flag is cleared
1
read: timer flag active
write: timer flag remains unchanged
1
0
AIE
TIE
0[2]
alarm interrupt disabled
1
alarm interrupt enabled
0[2]
timer interrupt disabled
1
timer interrupt enabled
8.3.2.1
[1]
Bits labeled as N should always be written with logic 0.
[2]
Default value.
Interrupt output
Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a
timer countdown, TF is set to logic 1. These bits maintain their value until overwritten
using the interface. If both timer and alarm interrupts are required in the application, the
source of the interrupt can be determined by reading these bits. To prevent one flag being
overwritten while clearing another, a logic AND is performed during a write access.
TI_TP
TE
TF: TIMER
COUNTDOWN COUNTER
to interface:
read TF
SET
TIE
e.g. AIE
0
1
0
CLEAR
PULSE
GENERATOR 2
TRIGGER
1
CLEAR
INT
from interface:
clear TF
set alarm
flag AF
AF: ALARM
FLAG
SET
to interface:
read AF
AIE
CLEAR
from interface:
clear AF
013aaa087
When bits TIE and AIE are disabled, pin INT will remain high-impedance.
Fig 5.
Interrupt scheme
Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when
TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions
when both AIE and TIE are set.
PCF8563
Product data sheet
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PCF8563
NXP Semiconductors
Real-time clock/calendar
Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses
an internal clock and is dependent on the selected source clock for the countdown timer
and on the countdown value n. As a consequence, the width of the interrupt pulse varies
(see Table 7).
Table 7.
INT operation (bit TI_TP = 1)[1]
Source clock (Hz)
INT period (s)
n = 1[2]
n > 1[2]
4096
1⁄
8192
1⁄
4096
64
1⁄
128
1⁄
64
1
1⁄
64
1⁄
64
1⁄
60
1⁄
64
1⁄
64
[1]
TF and INT become active simultaneously.
[2]
n = loaded countdown value. Timer stops when n = 0.
8.4 Time and date registers
The majority of the registers are coded in the BCD format to simplify application use.
8.4.1 Register VL_seconds
Table 8.
Bit
Symbol
Value
Place value Description
7
VL
0
-
clock integrity is guaranteed
1[1]
-
integrity of the clock information is not guaranteed
6 to 4 SECONDS 0 to 5
ten’s place
actual seconds coded in BCD format, see Table 9
3 to 0
unit place
[1]
Product data sheet
0 to 9
Start-up value.
Table 9.
PCF8563
VL_seconds - seconds and clock integrity status register (address 02h) bit
description
Seconds coded in BCD format
Seconds value
(decimal)
Upper-digit (ten’s place)
Digit (unit place)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
0
0
0
0
0
0
0
01
0
0
0
0
0
0
1
02
0
0
0
0
0
1
0
:
:
:
:
:
:
:
:
09
0
0
0
1
0
0
1
10
0
0
1
0
0
0
0
:
:
:
:
:
:
:
:
58
1
0
1
1
0
0
0
59
1
0
1
1
0
0
1
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PCF8563
NXP Semiconductors
Real-time clock/calendar
8.4.1.1
Voltage-low detector and clock monitor
The PCF8563 has an on-chip voltage-low detector (see Figure 6). When VDD drops below
Vlow, bit VL in the VL_seconds register is set to indicate that the integrity of the clock
information is no longer guaranteed. The VL flag can only be cleared by using the
interface.
mgr887
VDD
normal power
operation
period of battery
operation
Vlow
VL set
Fig 6.
t
Voltage-low detection
The VL flag is intended to detect the situation when VDD is decreasing slowly, for example
under battery operation. Should the oscillator stop or VDD reach Vlow before power is
re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.
8.4.2 Register Minutes
Table 10.
Minutes - minutes register (address 03h) bit description
Bit
Symbol
Value
Place value Description
7
-
-
-
unused
6 to 4 MINUTES
0 to 5
ten’s place
actual minutes coded in BCD format
3 to 0
0 to 9
unit place
8.4.3 Register Hours
Table 11.
Bit
Hours - hours register (address 04h) bit description
Symbol
Value
Place value Description
7 to 6 -
-
-
unused
5 to 4 HOURS
0 to 2
ten’s place
actual hours coded in BCD format
3 to 0
0 to 9
unit place
8.4.4 Register Days
Table 12.
Bit
Days - days register (address 05h) bit description
Symbol
7 to 6 5 to 4
3 to 0
[1]
PCF8563
Product data sheet
DAYS[1]
Value
Place value Description
-
-
unused
0 to 3
ten’s place
actual day coded in BCD format
0 to 9
unit place
The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a
value which is exactly divisible by 4, including the year 00.
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PCF8563
NXP Semiconductors
Real-time clock/calendar
8.4.5 Register Weekdays
Table 13.
Bit
Weekdays - weekdays register (address 06h) bit description
Symbol
Value
Description
7 to 3 -
-
unused
2 to 0 WEEKDAYS
0 to 6
actual weekday values, see Table 14
Table 14.
Weekday assignments
Day[1]
Bit
2
1
0
Sunday
0
0
0
Monday
0
0
1
Tuesday
0
1
0
Wednesday
0
1
1
Thursday
1
0
0
Friday
1
0
1
Saturday
1
1
0
[1]
Definition may be re-assigned by the user.
8.4.6 Register Century_months
Table 15.
Century_months - century flag and months register (address 07h) bit description
Bit
Symbol
Value
Place value Description
7
C[1]
0[2]
-
indicates the century is x
1
-
indicates the century is x + 1
6 to 5 -
-
-
unused
4
0 to 1
ten’s place
actual month coded in BCD format, see Table 16
0 to 9
unit place
MONTHS
3 to 0
[1]
This bit may be re-assigned by the user.
[2]
This bit is toggled when the register Years overflows from 99 to 00.
Table 16.
Month
PCF8563
Product data sheet
Month assignments in BCD format
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
January
0
0
0
0
1
February
0
0
0
1
0
March
0
0
0
1
1
April
0
0
1
0
0
May
0
0
1
0
1
June
0
0
1
1
0
July
0
0
1
1
1
August
0
1
0
0
0
September
0
1
0
0
1
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PCF8563
NXP Semiconductors
Real-time clock/calendar
Month assignments …continuedin BCD format
Table 16.
Month
October
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
0
0
November
1
0
0
0
1
December
1
0
0
1
0
8.4.7 Register Years
Table 17.
Bit
Years - years register (08h) bit description
Symbol
Value
Place value Description
7 to 4 YEARS
0 to 9
ten’s place
3 to 0
0 to 9
unit place
[1]
actual year coded in BCD format[1]
When the register Years overflows from 99 to 00, the century bit C in the register Century_months is
toggled.
8.5 Setting and reading the time
Figure 7 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
HOURS
LEAP YEAR
CALCULATION
DAYS
WEEKDAY
MONTHS
YEARS
C
Fig 7.
013aaa092
Data flow for the time function
During read/write operations, the time counting circuits (memory locations 02h through
08h) are blocked.
This prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers, during the read cycle
PCF8563
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Real-time clock/calendar
After this read/write access is completed, the time circuit is released again and any
pending request to increment the time counters that occurred during the read access is
serviced. A maximum of 1 request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 8).
t<1s
SLAVE ADDRESS
START
DATA
DATA
STOP
013aaa215
Fig 8.
Access time for read/write operations
As a consequence of this method, it is very important to make a read or write access in
one go, that is, setting or reading seconds through to years should be made in one single
access. Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time:
1. Send a START condition and the slave address for write (A2h).
2. Set the address pointer to 2 (VL_seconds) by sending 02h.
3. Send a RESTART condition or STOP followed by START.
4. Send the slave address for read (A3h).
5. Read VL_seconds.
6. Read Minutes.
7. Read Hours.
8. Read Days.
9. Read Weekdays.
10. Read Century_months.
11. Read Years.
12. Send a STOP condition.
8.6 Alarm registers
8.6.1 Register Minute_alarm
Table 18.
PCF8563
Product data sheet
Minute_alarm - minute alarm register (address 09h) bit description
Bit
Symbol
Value
Place value Description
7
AE_M
0
-
minute alarm is enabled
1[1]
-
minute alarm is disabled
minute alarm information coded in BCD
format
6 to 4 MINUTE_ALARM
0 to 5
ten’s place
3 to 0
0 to 9
unit place
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Rev. 11 — 26 October 2015
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PCF8563
NXP Semiconductors
Real-time clock/calendar
[1]
Default value.
8.6.2 Register Hour_alarm
Table 19.
Hour_alarm - hour alarm register (address 0Ah) bit description
Bit
Symbol
Value
Place value Description
7
AE_H
0
-
hour alarm is enabled
1[1]
-
hour alarm is disabled
6
-
-
unused
5 to 4 HOUR_ALARM
0 to 2
ten’s place
3 to 0
0 to 9
unit place
hour alarm information coded in BCD
format
[1]
-
Default value.
8.6.3 Register Day_alarm
Table 20.
Day_alarm - day alarm register (address 0Bh) bit description
Bit
Symbol
Value
Place value Description
7
AE_D
0
-
day alarm is enabled
1[1]
-
day alarm is disabled
-
-
unused
5 to 4 DAY_ALARM
6
0 to 3
ten’s place
3 to 0
0 to 9
unit place
day alarm information coded in BCD
format
[1]
-
Default value.
8.6.4 Register Weekday_alarm
Table 21.
Weekday_alarm - weekday alarm register (address 0Ch) bit description
Bit
Symbol
Value
Description
7
AE_W
0
weekday alarm is enabled
1[1]
weekday alarm is disabled
-
unused
6 to 3 -
2 to 0 WEEKDAY_ALARM 0 to 6
[1]
weekday alarm information
Default value.
8.6.5 Alarm flag
By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the
corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1.
The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the
interface.
The registers at addresses 09h through 0Ch contain alarm information. When one or
more of these registers is loaded with minute, hour, day or weekday, and its
corresponding AE_x is logic 0, then that information is compared with the current minute,
hour, day, and weekday. When all enabled comparisons first match, the alarm flag (AF in
register Control_2) is set to logic 1.
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The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is
enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the
interface. Once AF has been cleared, it will only be set again when the time increments to
match the alarm condition once more. Alarm registers which have their AE_x bit at logic 1
are ignored.
check now signal
example
AEN_M
AEN_M = 1
MINUTE ALARM
=
1
0
MINUTE TIME
AEN_H
HOUR ALARM
=
HOUR TIME
set alarm flag AF (1)
AEN_D
DAY ALARM
=
DAY TIME
AEN_W
WEEKDAY ALARM
=
013aaa088
WEEKDAY TIME
(1) Only when all enabled alarm settings are matching.
It’s only on increment to a matched case that the alarm flag is set, see Section 8.6.5.
Fig 9.
Alarm function block diagram
8.7 Register CLKOUT_control and clock output
Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz, and 1 Hz can be generated for
use as a system clock, microcontroller clock, input to a charge pump, or for calibration of
the oscillator.
Table 22.
CLKOUT_control - CLKOUT control register (address 0Dh) bit description
Bit
Symbol
Value
Description
7
FE
0
the CLKOUT output is inhibited and CLKOUT output is
set high-impedance
1[1]
the CLKOUT output is activated
-
unused
6 to 2 1 to 0 FD[1:0]
[1]
PCF8563
Product data sheet
frequency output at pin CLKOUT
00[1]
32.768 kHz
01
1.024 kHz
10
32 Hz
11
1 Hz
Default value.
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8.8 Timer function
The 8-bit countdown timer at address 0Fh is controlled by the Timer_control register at
address 0Eh. The Timer_control register determines one of 4 source clock frequencies for
the timer (4096 Hz, 64 Hz, 1 Hz, or 1⁄60 Hz), and enables or disables the timer. The timer
counts down from a software-loaded 8-bit binary value. At the end of every countdown,
the timer sets the timer flag TF. The TF may only be cleared by using the interface. The
asserted TF can be used to generate an interrupt on pin INT. The interrupt may be
generated as a pulsed signal every countdown period or as a permanently active signal
which follows the state of TF. Bit TI_TP is used to control this mode selection. When
reading the timer, the current countdown value is returned.
8.8.1 Register Timer_control
Table 23.
Timer_control - timer control register (address 0Eh) bit description
Bit
Symbol
Value
Description
7
TE
0[1]
timer is disabled
1
timer is enabled
-
unused
6 to 2 -
timer source clock frequency select[2]
1 to 0 TD[1:0]
00
4.096 kHz
01
64 Hz
10
1 Hz
11[2]
1⁄
60
Hz
[1]
Default value.
[2]
These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to
1⁄ Hz for power saving.
60
8.8.2 Register Timer
Table 24.
Timer - timer value register (address 0Fh) bit description
Bit
Symbol
Value
Description
7 to 0
TIMER[7:0]
00h to FFh
countdown period in seconds:
n
CountdownPeriod = --------------------------------------------------------------SourceClockFrequency
where n is the countdown value
Table 25.
Timer register bits value range
Bit
7
6
5
4
3
2
1
0
128
64
32
16
8
4
2
1
The register Timer is an 8-bit binary countdown timer. It is enabled and disabled via the
Timer_control register bit TE. The source clock for the timer is also selected by the
Timer_control register. Other timer properties such as interrupt generation are controlled
via the register Control_status_2.
For accurate read back of the count down value, it is recommended to read the register
twice and check for consistent results, since it is not possible to freeze the countdown
timer counter during read back.
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8.9 EXT_CLK test mode
A test mode is available which allows for on-board testing. In such a mode it is possible to
set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in register Control_status_1. Then
pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the
signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then
generate an increment of one second.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is
divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into
a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP
must be cleared before the prescaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second
increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the prescaler can be made.
8.9.1 Operation example:
1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).
2. Set STOP (Control_status_1, bit STOP = 1).
3. Clear STOP (Control_status_1, bit STOP = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to CLKOUT.
8. Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments.
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8.10 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP
bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and
thus no 1 Hz ticks will be generated (see Figure 10). The time circuits can then be set and
will not increment until the STOP bit is released (see Figure 11 and Table 26).
F13
RESET
RESET
2 Hz
F2
reset
4096 Hz
F1
8192 Hz
F0
16384 Hz
OSCILLATOR
32768 Hz
OSCILLATOR STOP
DETECTOR
F14
1 Hz tick
RESET
STOP
1 Hz
32 Hz
CLKOUT source
1024 Hz
32768 Hz
013aaa089
Fig 10. STOP bit functional diagram
The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop
the generation of 1.024 kHz, 32 Hz, and 1 Hz.
The lower two stages of the prescaler (F0 and F1) are not reset; and because the I2C-bus
is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be
between zero and one 8.192 kHz cycle (see Figure 11).
8192 Hz
stop released
0 μs to 122 μs
001aaf912
Fig 11. STOP bit release timing
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Table 26.
First increment of time circuits after STOP bit release
Bit
Prescaler bits
STOP
F0F1-F2 to F14
[1]
1 Hz tick
Time
Comment
hh:mm:ss
Clock is running normally
0
12:45:12
01-0 0001 1101 0100
prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12
prescaler is reset; time circuits are frozen
08:00:00
prescaler is reset; time circuits are frozen
08:00:00
prescaler is now running
08:00:00
-
08:00:00
-
08:00:00
-
:
:
New time is set by user
1
XX-0 0000 0000 0000
STOP bit is released by user
XX-1 0000 0000 0000
XX-0 1000 0000 0000
XX-1 1000 0000 0000
:
0.507813 to 0.507935 s
XX-0 0000 0000 0000
08:00:00
-
00-0 0000 0000 0001
08:00:01
0 to 1 transition of F14 increments the time circuits
10-0 0000 0000 0001
08:00:01
-
:
:
:
08:00:01
-
08:00:01
-
10-0 0000 0000 0000
08:00:01
-
:
:
:
11-1 1111 1111 1110
08:00:01
-
00-0 0000 0000 0001
08:00:02
0 to 1 transition of F14 increments the time circuits
11-1 1111 1111 1110
11-1 1111 1111 1111
00-0 0000 0000 0000
1.000000 s
0
013aaa076
[1]
F0 is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 26) and the unknown state of the 32 kHz clock.
8.11 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized including the address pointer and
all registers are set according to Table 27. I2C-bus communication is not possible during
reset.
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Table 27.
Register reset value[1]
Address
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_status_1
0
0
0
0
1
0
0
0
01h
Control_status_2
0
0
0
0
0
0
0
0
02h
VL_seconds
1
x
x
x
x
x
x
x
03h
Minutes
x
x
x
x
x
x
x
x
04h
Hours
x
x
x
x
x
x
x
x
05h
Days
x
x
x
x
x
x
x
x
06h
Weekdays
x
x
x
x
x
x
x
x
07h
Century_months
x
x
x
x
x
x
x
x
08h
Years
x
x
x
x
x
x
x
x
09h
Minute_alarm
1
x
x
x
x
x
x
x
0Ah
Hour_alarm
1
x
x
x
x
x
x
x
0Bh
Day_alarm
1
x
x
x
x
x
x
x
0Ch
Weekday_alarm
1
x
x
x
x
x
x
x
0Dh
CLKOUT_control
1
x
x
x
x
x
0
0
0Eh
Timer_control
0
x
x
x
x
x
1
1
0Fh
Timer
x
x
x
x
x
x
x
x
[1]
Registers marked x are undefined at power-up and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I2C-bus pins, SDA and SCL, are toggled in a specific order as
shown in Figure 12. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
500 ns
2000 ns
SDA
SCL
8 ms
power-on
override active
mgm664
Fig 12. POR override sequence
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9. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 13).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 13. Bit transfer
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 14).
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 14. Definition of START and STOP conditions
9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 15).
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SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
mba605
Fig 15. System configuration
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 16.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
mbc602
Fig 16. Acknowledgement on the I2C-bus
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9.5 I2C-bus protocol
9.5.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL
is only an input signal, but the data signal SDA is a bidirectional line.
Two slave addresses are reserved for the PCF8563:
Read: A3h (10100011)
Write: A2h (10100010)
The PCF8563 slave address is illustrated in Figure 17.
1
0
1
0
group 1
0
0
1
R/W
group 2
mce189
Fig 17. Slave address
9.5.2 Clock and calendar READ or WRITE cycles
The I2C-bus configuration for the different PCF8563 READ and WRITE cycles is shown in
Figure 18, Figure 19 and Figure 20. The register address is a 4-bit value that defines
which register is to be accessed next. The upper four bits of the register address are not
used.
acknowledgement
from slave
S
SLAVE ADDRESS
acknowledgement
from slave
0 A REGISTER ADDRESS A
R/W
acknowledgement
from slave
DATA
A
P
n bytes
auto increment
memory register address
013aaa346
Fig 18. Master transmits to slave receiver (WRITE mode)
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acknowledgement
from slave
S
SLAVE ADDRESS
0 A
acknowledgement
from slave
REGISTER ADDRESS A
S
acknowledgement
from slave
SLAVE ADDRESS
1 A
DATA
A
n bytes
R/W
R/W
acknowledgement
from master
auto increment
memory register address
(1)
no acknowledgement
from master
1
DATA
P
last byte
auto increment
memory register address
013aaa041
(1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter.
Fig 19. Master reads after setting register address (write register address; READ data)
acknowledgement
from slave
S
SLAVE ADDRESS
1 A
R/W
acknowledgement
from master
A
DATA
n bytes
no acknowledgement
from master
DATA
1
P
last byte
auto increment
register address
auto increment
register address
013aaa347
Fig 20. Master reads slave immediately after first byte (READ mode)
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9.6 Interface watchdog timer
t<1s
data
START
SLAVE ADDRESS
DATA DATA
WD timer
STOP
WD timer tracking
time
counters
running
time counters frozen
running
013aaa420
a. Correct data transfer: read or write
1s<t<2s
data
START
SLAVE ADDRESS
DATA DATA
WD timer
time
counters
data transfer fail
WD trips
WD timer tracking
running
time counters frozen
running
013aaa421
b. Incorrect data transfer; read or write
Fig 21. Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface, the
PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s
from the time a valid slave address is transmitted, then the PCF8563 will automatically
clear the interface and allow the time counting circuits to continue counting. The watchdog
will trigger between 1 s and 2 s after receiving a valid slave address. Each time the
watchdog period is exceeded, 1 s will be lost from the time counters.
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
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10. Internal circuitry
VDD
OSCI
CLKOUT
OSCO
SCL
INT
VSS
SDA
PCF8563
013aaa348
Fig 22. Device diode protection diagram
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11. Limiting values
Table 28. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
0.5
+6.5
V
IDD
supply current
VI
input voltage
on pins SCL, SDA,
and OSCI
50
+50
mA
0.5
+6.5
V
VO
output voltage
on pins CLKOUT and INT
0.5
+6.5
V
II
input current
at any input
10
+10
mA
IO
output current
at any output
10
+10
mA
Ptot
total power dissipation
-
300
mW
VESD
electrostatic discharge voltage
-
3500
V
2000
V
HBM
HVSON10 (PCF8563BS/4)
[1]
SO8 (PCF8563T/F4)
[1]
TSSOP8 (PCF8563TS/4)
[1]
SO8 (PCF8563T/5)
[1]
-
TSSOP8 (PCF8563TS/5)
[1]
-
CDM
HVSON10 (PCF8563BS/4)
[2]
-
2000
V
SO8 (PCF8563T/F4)
[2]
-
1000
V
SO8 (PCF8563T/5)
[2]
-
1500
V
TSSOP8 (PCF8563TS/4)
[2]
1500
V
TSSOP8 (PCF8563TS/5)
[2]
1750
V
latch-up current
[3]
-
200
mA
Tstg
storage temperature
[4]
65
+150
C
Tamb
ambient temperature
40
+85
C
Ilu
operating device
[1]
Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”.
[2]
Pass level; Charged-Device Model (CDM), according to Ref. 6 “JESD22-C101”.
[3]
Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (Tamb(max)).
[4]
According to the NXP store and transport requirements (see Ref. 9 “UM10569”) the devices should be stored at a temperature of +8 C
to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.
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12. Static characteristics
Table 29. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
interface inactive;
fSCL = 0 Hz;
Tamb = 25 C
1.0
-
5.5
V
interface active;
fSCL = 400 kHz
1.8
-
5.5
V
clock data integrity;
Tamb = 25 C
Vlow
-
5.5
V
-
-
800
A
-
-
200
A
VDD = 5.0 V
-
275
550
nA
VDD = 3.0 V
-
250
500
nA
-
225
450
nA
VDD = 5.0 V
-
500
750
nA
VDD = 3.0 V
-
400
650
nA
-
400
600
nA
-
825
1600
nA
Supplies
VDD
IDD
supply current
[1]
interface active
fSCL = 400 kHz
fSCL = 100 kHz
interface inactive (fSCL = 0 Hz); CLKOUT
disabled; Tamb = 25 C
[2]
VDD = 2.0 V
interface inactive (fSCL = 0 Hz); CLKOUT
disabled; Tamb = 40 C to +85 C
[2]
VDD = 2.0 V
interface inactive (fSCL = 0 Hz); CLKOUT
enabled at 32 kHz; Tamb = 25 C
[2]
VDD = 5.0 V
VDD = 3.0 V
-
550
1000
nA
VDD = 2.0 V
-
425
800
nA
interface inactive (fSCL = 0 Hz); CLKOUT
enabled at 32 kHz; Tamb = 40 C to +85 C
[2]
VDD = 5.0 V
-
950
1700
nA
VDD = 3.0 V
-
650
1100
nA
VDD = 2.0 V
-
500
900
nA
Inputs
VIL
LOW-level input
voltage
0.5
-
+0.3VDD V
VIH
HIGH-level
input voltage
0.7VDD
-
5.5
V
ILI
input leakage
current
1
0
+1
A
Ci
input
capacitance
-
-
7
pF
PCF8563
Product data sheet
VI = VDD or VSS
[3]
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Table 29. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LOW-level
output current
output sink current;
VOL = 0.4 V; VDD = 5 V
on pin SDA
3
-
-
mA
on pin INT
1
-
-
mA
on pin CLKOUT
Outputs
IOL
output leakage
current
ILO
1
-
-
mA
VO = VDD or VSS
1
0
+1
A
Tamb = 25 C; sets bit VL; see Figure 6
-
0.9
1.0
V
Voltage detector
Vlow
low voltage
[1]
For reliable oscillator start-up at power on use VDD greater than 1.3 V. If powered up at 1.0 V the oscillator will start but it might be a bit
slow, especially if at high temperature. Normally the power supply is not 1.0 V at start up and only comes at the end of battery discharge.
VDD min of 1.0 V is specified so that the customer can calculate how large a battery or capacitor they need for their application. VDD min
of 1.3 V or greater is needed to ensure speedy oscillator start-up time.
[2]
Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.
[3]
Tested on sample basis.
mgr888
1
IDD
(μA)
mgr889
1
IDD
(μA)
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
0
2
4
VDD (V)
6
Tamb = 25 C; Timer = 1 minute.
Product data sheet
2
4
VDD (V)
6
Tamb = 25 C; Timer = 1 minute.
Fig 23. Supply current IDD as a function of supply
voltage VDD; CLKOUT disabled
PCF8563
0
Fig 24. Supply current IDD as a function of supply
voltage VDD; CLKOUT = 32 kHz
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mgr891
mgr890
1
IDD
(μA)
4
frequency
deviation
(ppm)
2
0.8
0.6
0
0.4
−2
0.2
−4
0
−40
0
40
80
T (°C)
0
120
2
4
VDD (V)
6
Tamb = 25 C; normalized to VDD = 3 V.
VDD = 3 V; Timer = 1 minute.
Fig 25. Supply current IDD as a function of
temperature T; CLKOUT = 32 kHz
Fig 26. Frequency deviation as a function of supply
voltage VDD
13. Dynamic characteristics
Table 30. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
15
25
35
pF
-
0.2
-
ppm
-
-
100
k
7
-
12.5
pF
5
-
25
pF
-
50
-
%
Oscillator
COSCO
capacitance on pin OSCO
fosc/fosc
relative oscillator frequency variation
VDD = 200 mV;
Tamb = 25 C
Quartz crystal parameters (f = 32.768 kHz)
Rs
series resistance
CL
load capacitance
parallel
Ctrim
trimmer capacitance
external;
on pin OSCI
[1]
CLKOUT output
CLKOUT
I2C-bus
[2]
duty cycle on pin CLKOUT
timing characteristics (see Figure
27)[3][4]
[5]
fSCL
SCL clock frequency
-
-
400
kHz
tHD;STA
hold time (repeated) START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated START condition
0.6
-
-
s
tLOW
LOW period of the SCL clock
1.3
-
-
s
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
tr
rise time of both SDA and SCL signals
standard-mode
-
-
1
s
fast-mode
-
-
0.3
s
PCF8563
Product data sheet
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Table 30. Dynamic characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise
specified.
Symbol
Parameter
tf
Conditions
Min
Typ
Max
Unit
fall time of both SDA and SCL signals
-
-
0.3
s
tBUF
bus free time between a STOP and START
condition
1.3
-
-
s
Cb
capacitive load for each bus line
-
-
400
pF
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP condition
0.6
-
-
s
tw(spike)
spike pulse width
-
-
50
ns
on bus
 C trim  C OSCO 
 C trim + C OSCO 
[1]
CL is a calculation of Ctrim and COSCO in series: C L = ----------------------------------------- .
[2]
Unspecified for fCLKOUT = 32.768 kHz.
[3]
All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage
swing of VSS to VDD.
[4]
A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”.
[5]
I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
mga728
Fig 27. I2C-bus timing waveforms
PCF8563
Product data sheet
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14. Application information
VDD
SDA
SCL
1F
MASTER
TRANSMITTER/
RECEIVER
100 nF
VDD
SCL
CLOCK CALENDAR
OSCI
PCF8563
OSCO
VSS
SDA
VDD
R
SDA SCL
(I2C-bus)
R
R: pull-up resistor
tr
R=
Cb
mgm665
Fig 28. Application diagram
14.1 Quartz frequency adjustment
14.1.1 Method 1: fixed OSCI capacitor
By evaluating the average capacitance necessary for the application layout, a fixed
capacitor can be used. The frequency is best measured via the 32.768 kHz signal
available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz
crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average
5 ppm). Average deviations of 5 minutes per year can be easily achieved.
14.1.2 Method 2: OSCI trimmer
Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a
trimmer is possible.
14.1.3 Method 3: OSCO output
Direct measurement of OSCO out (accounting for test probe capacitance).
PCF8563
Product data sheet
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15. Package outline
HVSON10: plastic thermal enhanced very thin small outline package; no leads;
10 terminals; body 3 x 3 x 0.85 mm
SOT650-1
0
1
2 mm
scale
X
A
B
D
A
A1
E
c
detail X
terminal 1
index area
C
e1
terminal 1
index area
e
5
y
y1 C
v M C A B
w M C
b
1
L
Eh
6
10
Dh
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
2.55
2.15
3.1
2.9
1.75
1.45
0.5
2
0.55
0.30
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT650-1
---
MO-229
---
EUROPEAN
PROJECTION
ISSUE DATE
01-01-22
02-02-08
Fig 29. Package outline SOT650-1 (HVSON10) of PCF8563BS
PCF8563
Product data sheet
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SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 30. Package outline SOT96-1 (SO8) of PCF8563T
PCF8563
Product data sheet
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TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Fig 31. Package outline SOT505-1 (TSSOP8) of PCF8563TS
PCF8563
Product data sheet
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16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
PCF8563
Product data sheet
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
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17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 31 and 32
Table 31.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 32.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
PCF8563
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 33.
PCF8563
Product data sheet
Abbreviations
Acronym
Description
BCD
Binary Coded Decimal
CDM
Charged-Device Model
CMOS
Complementary Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
PCB
Printed-Circuit Board
POR
Power-On Reset
RTC
Real-Time Clock
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface Mount Device
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19. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[3]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[4]
IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[5]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[6]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[7]
JESD78 — IC Latch-Up Test
[8]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[9]
UM10569 — NXP store and transport requirements
[10] SNV-FA-01-02 — Marking Formats Integrated Circuits
[11] UM10204 — I2C-bus specification and user manual
PCF8563
Product data sheet
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20. Revision history
Table 34.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8563 v.11
20151026
Product data sheet
-
PCF8563 v.10
Modifications:
•
•
•
Removed DIP8 package
•
Table 29:
Table 3: Corrected Table note 1
Table 28, Table note 4: Corrected “the devices have to be stored” to “the devices should be
stored”
– Deleted Table note 1 from VDD fSCL = 400 kHz
– VIL: Corrected VSS to 0.5
– VIH: Corrected VDD to 5.5
– Corrected Table note 1
PCF8563 v.10
Modifications:
PCF8563 v.9
20120403
•
•
Product data sheet
-
PCF8563 v.9
-
PCF8563 v.8
Adjusted marking codes
Adjusted text for FE = 0 in Table 22
20110616
Product data sheet
PCF8563 v.8
20101118
Product data sheet
-
PCF8563 v.7
PCF8563 v.7
20100723
Product data sheet
-
PCF8563_6
PCF8563_6
20080221
Product data sheet
-
PCF8563_5
PCF8563_5
20070717
Product data sheet
-
PCF8563-04
PCF8563-04
(9397 750 12999)
20040312
Product data
-
PCF8563-03
PCF8563-03
(9397 750 11158)
20030414
Product data
-
PCF8563-02
PCF8563-02
(9397 750 04855)
19990416
Product data
-
PCF8563_N_1
PCF8563_N_1
(9397 750 03282)
19980325
Objective specification
-
-
PCF8563
Product data sheet
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21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCF8563
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 26 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
41 of 45
PCF8563
NXP Semiconductors
Real-time clock/calendar
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8563
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 26 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
42 of 45
PCF8563
NXP Semiconductors
Real-time clock/calendar
23. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Formatted registers overview . . . . . . . . . . . . . .6
Control_status_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . . .7
Control_status_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . . .7
INT operation (bit TI_TP = 1)[1] . . . . . . . . . . . . . .9
VL_seconds - seconds and clock integrity status
register (address 02h) bit description . . . . . . . .9
Seconds coded in BCD format . . . . . . . . . . . . .9
Minutes - minutes register (address 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Hours - hours register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Days - days register (address 05h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Weekdays - weekdays register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 11
Weekday assignments . . . . . . . . . . . . . . . . . . . 11
Century_months - century flag and months
register (address 07h) bit description . . . . . . . . 11
Month assignments in BCD format . . . . . . . . . . 11
Years - years register (08h) bit description . . . .12
Minute_alarm - minute alarm register
(address 09h) bit description . . . . . . . . . . . . . .13
Hour_alarm - hour alarm register (address 0Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .14
Day_alarm - day alarm register (address 0Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .14
Weekday_alarm - weekday alarm register
(address 0Ch) bit description . . . . . . . . . . . . . .14
CLKOUT_control - CLKOUT control register
(address 0Dh) bit description . . . . . . . . . . . . . .15
Timer_control - timer control register
(address 0Eh) bit description . . . . . . . . . . . . . .16
Timer - timer value register (address 0Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .16
Timer register bits value range . . . . . . . . . . . . .16
First increment of time circuits after STOP
bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Register reset value[1] . . . . . . . . . . . . . . . . . . .20
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27
Static characteristics . . . . . . . . . . . . . . . . . . . .28
Dynamic characteristics . . . . . . . . . . . . . . . . . .30
SnPb eutectic process (from J-STD-020D) . . .37
Lead-free process (from J-STD-020D) . . . . . .37
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .38
Revision history . . . . . . . . . . . . . . . . . . . . . . . .40
PCF8563
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 26 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
43 of 45
PCF8563
NXP Semiconductors
Real-time clock/calendar
24. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Block diagram of PCF8563 . . . . . . . . . . . . . . . . . .3
Pin configuration for HVSON10 (PCF8563BS) . . .4
Pin configuration for SO8 (PCF8563T) . . . . . . . . .4
Pin configuration for TSSOP8 (PCF8563TS). . . . .4
Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . .8
Voltage-low detection. . . . . . . . . . . . . . . . . . . . . .10
Data flow for the time function . . . . . . . . . . . . . . .12
Access time for read/write operations . . . . . . . . .13
Alarm function block diagram. . . . . . . . . . . . . . . .15
STOP bit functional diagram . . . . . . . . . . . . . . . .18
STOP bit release timing . . . . . . . . . . . . . . . . . . . .18
POR override sequence . . . . . . . . . . . . . . . . . . .20
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Definition of START and STOP conditions. . . . . .21
System configuration . . . . . . . . . . . . . . . . . . . . . .22
Acknowledgement on the I2C-bus . . . . . . . . . . . .22
Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Master transmits to slave receiver
(WRITE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Master reads after setting register address (write
register address; READ data) . . . . . . . . . . . . . . .24
Master reads slave immediately after first byte
(READ mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Interface watchdog timer . . . . . . . . . . . . . . . . . . .25
Device diode protection diagram . . . . . . . . . . . . .26
Supply current IDD as a function of supply voltage
VDD; CLKOUT disabled . . . . . . . . . . . . . . . . . . . .29
Supply current IDD as a function of supply voltage
VDD; CLKOUT = 32 kHz. . . . . . . . . . . . . . . . . . . .29
Supply current IDD as a function of temperature
T; CLKOUT = 32 kHz . . . . . . . . . . . . . . . . . . . . . .30
Frequency deviation as a function of supply voltage
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .31
Application diagram . . . . . . . . . . . . . . . . . . . . . . .32
Package outline SOT650-1 (HVSON10) of
PCF8563BS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Package outline SOT96-1 (SO8) of PCF8563T. .34
Package outline SOT505-1 (TSSOP8) of
PCF8563TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PCF8563
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 26 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
44 of 45
PCF8563
NXP Semiconductors
Real-time clock/calendar
25. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.2.1
8.4
8.4.1
8.4.1.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.7
8.8
8.8.1
8.8.2
8.9
8.9.1
8.10
8.11
8.11.1
9
9.1
9.2
9.3
9.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 6
Register organization . . . . . . . . . . . . . . . . . . . . 6
Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7
Register Control_status_1 . . . . . . . . . . . . . . . . 7
Register Control_status_2 . . . . . . . . . . . . . . . . 7
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8
Time and date registers . . . . . . . . . . . . . . . . . . 9
Register VL_seconds . . . . . . . . . . . . . . . . . . . . 9
Voltage-low detector and clock monitor . . . . . 10
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Days . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 11
Register Century_months . . . . . . . . . . . . . . . . 11
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting and reading the time. . . . . . . . . . . . . . 12
Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 13
Register Minute_alarm . . . . . . . . . . . . . . . . . . 13
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14
Register Weekday_alarm . . . . . . . . . . . . . . . . 14
Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register CLKOUT_control and clock output. . 15
Timer function . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Timer_control . . . . . . . . . . . . . . . . . . 16
Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 16
EXT_CLK test mode . . . . . . . . . . . . . . . . . . . . 17
Operation example: . . . . . . . . . . . . . . . . . . . . 17
STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-On Reset (POR) override . . . . . . . . . . 20
Characteristics of the I2C-bus . . . . . . . . . . . . 21
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
START and STOP conditions . . . . . . . . . . . . . 21
System configuration . . . . . . . . . . . . . . . . . . . 21
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.5
9.5.1
9.5.2
9.6
10
11
12
13
14
14.1
14.1.1
14.1.2
14.1.3
15
16
17
17.1
17.2
17.3
17.4
18
19
20
21
21.1
21.2
21.3
21.4
22
23
24
25
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and calendar READ or WRITE cycles .
Interface watchdog timer . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Quartz frequency adjustment. . . . . . . . . . . . .
Method 1: fixed OSCI capacitor . . . . . . . . . . .
Method 2: OSCI trimmer . . . . . . . . . . . . . . . .
Method 3: OSCO output . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
25
26
27
28
30
32
32
32
32
32
33
36
36
36
36
37
37
38
39
40
41
41
41
41
42
42
43
44
45
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 26 October 2015
Document identifier: PCF8563
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