Download Datasheet

L9678P
L9678P-S
Automotive user configurable airbag IC
Datasheet - production data
Features
 Squib deployment drivers
– 4 channel HSD/LSD
– 25 V maximum deployment voltage
– 1.2 A @ 2 ms and 1.75 A @ 0.5/0.7 ms
deployment profiles
– Integrated safing FET linear regulator,
20 V/25 V nominal
– Current monitoring
– Rmeasure, STB, STG and leakage
diagnostics
– High and low side driver FET tests
– Safing FET test
 AEC-Q100 qualified
 User customizable safing logic
 Energy reserve voltage power supply
– High frequency boost regulator, 1.882 MHz
– Output voltage user selectable, 23 V or
33 V ±5%
 Two channel PSI-5 remote sensor interface
(asynchronous mode), [only for L9678P-S
version]
'!0'03
LQFP64 (10x10x1.4mm)
 User configurable linear power supplies
– 5.0 V and 7.2 V ±4% output voltages
– External pass transistor
 Fully integrated 3.3 V ±4% linear regulator
 Battery voltage monitor and shutdown control
with wake-up control
 Four channel hall-effect, resistive or switch
sensor interface
 ISO9141 transceiver
 Dual channel configurable high-side/low-side
LED driver
 Watchdog timer
 Two integrated oscillators: 7.5/16 MHz
 System voltage diagnostics with integrated
ADC
 Temperature sensor
 Crossover switch
– Crossover performance, max 3 Ω, 600 mA
max.
 Minimum operating voltage = 6 V
 32 bit SPI communications
 Operating temperature, -40 °C to 95 °C
 Packaging - 64 pin
Table 1. Device summary
Order code
Package
Packing
Remote sensor interface
L9678P
LQFP64 (10 x 10 x 1.4 mm)
Tray
No
L9678P-S
LQFP64 (10 x 10 x 1.4 mm)
Tray
Yes
May 2016
This is information on a product in full production.
DocID029274 Rev 1
1/202
www.st.com
Contents
L9678P, L9678P-S
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Absolute and operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . 12
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
Operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Pin-out description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Overview and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Start-up power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
Power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
4.4
5
4.2.1
Power_off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.2
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.3
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.4
Passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.5
Power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.6
Operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Configurable system power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.1
ERBOOST switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.2
Energy reserve capacitor charging circuit . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.3
ER switch and COVRACT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.4
VDD5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.5
VDD3V3 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.6
VSUP linear regulator (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.7
VSF linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1
Global SPI register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read/write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2/202
5.1.1
Fault status register (FLTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1.2
System configuration register (SYS_CFG) . . . . . . . . . . . . . . . . . . . . . . 53
5.1.3
System control register (SYS_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DocID029274 Rev 1
L9678P, L9678P-S
Contents
5.1.4
SPI Sleep command register (SPI_SLEEP) . . . . . . . . . . . . . . . . . . . . . 56
5.1.5
System status register (SYS_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1.6
Power state register (POWER_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.1.7
Deployment configuration registers (DCR_x) . . . . . . . . . . . . . . . . . . . . 61
5.1.8
Deployment command (DEPCOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1.9
Deployment configuration registers (DSR_x) . . . . . . . . . . . . . . . . . . . . 64
5.1.10
Deployment current monitor status registers (DCMTSxy) . . . . . . . . . . . 65
5.1.11
Deploy enable register (SPIDEPEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.1.12
Squib ground loss register (LP_GNDLOSS) . . . . . . . . . . . . . . . . . . . . . 66
5.1.13
Device version register (VERSION_ID) . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.14
Watchdog retry configuration register (WD_RETRY_CONF) . . . . . . . . 67
5.1.15
Watchdog timer configuration register (WDTCR) . . . . . . . . . . . . . . . . . 68
5.1.16
WD1 timer control register (WD1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.17
WD1 state register (WDSTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.18
Clock configuration register (CLK_CONF) . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.19
Scrap state entry command register (SCRAP_STATE) . . . . . . . . . . . . . 71
5.1.20
Safing state entry command register (SAFING_STATE) . . . . . . . . . . . . 71
5.1.21
WD1 test command register (WD1_TEST) . . . . . . . . . . . . . . . . . . . . . . 72
5.1.22
System diagnostic register (SYSDIAGREQ) . . . . . . . . . . . . . . . . . . . . . 72
5.1.23
Diagnostic result register for deployment loops (LPDIAGSTAT) . . . . . . 74
5.1.24
Loops diagnostic configuration command register for low level
diagnostic (LPDIAGREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.25
Loops diagnostic configuration command register for high level
diagnostic (LPDIAGREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1.26
DC sensor diagnostic configuration command register (SWCTRL) . . . . 81
5.1.27
ADC request and data registers (DIAGCTRL_x) . . . . . . . . . . . . . . . . . . 82
5.1.28
GPO configuration register (GPOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.29
GPO configuration register (GPOCTRLx) . . . . . . . . . . . . . . . . . . . . . . . 86
5.1.30
GPO fault status register (GPOFLTSR) . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1.31
ISO fault status register (ISOFLTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.32
Remote sensor configuration register (RSCRx) . . . . . . . . . . . . . . . . . . 89
5.1.33
Remote sensor control register (RSCTRL) . . . . . . . . . . . . . . . . . . . . . . 90
5.1.34
Remote sensor data/fault registers w/o fault (RSDRx) . . . . . . . . . . . . . 91
5.1.35
Safing algorithm configuration register (SAF_ALGO_CONF) . . . . . . . . 95
5.1.36
Arming signals register (ARM_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.37
ARMx assignment registers (LOOP_MATRIX_ARMx) . . . . . . . . . . . . . 97
5.1.38
ARMx pulse stretch registers (AEPSTS_ARMx) . . . . . . . . . . . . . . . . . . 98
5.1.39
Safing records enable register (SAF_ENABLE) . . . . . . . . . . . . . . . . . . 99
DocID029274 Rev 1
3/202
6
Contents
6
L9678P, L9678P-S
5.1.41
Safing records request target registers (SAF_REQ_TARGET_x) . . . . 101
5.1.42
Safing records response mask registers (SAF_RESP_MASK_x) . . . . 102
5.1.43
Safing records response target registers (SAF_RESP_TARGET_x) . . 103
5.1.44
Safing records data mask registers (SAF_DATA_MASK_x) . . . . . . . . 104
5.1.45
Safing records threshold registers (SAF_THRESHOLD_x) . . . . . . . . . 105
5.1.46
Safing control registers (SAF_CONTROL_x) . . . . . . . . . . . . . . . . . . . 106
5.1.47
Safing record compare complete register (SAF_CC) . . . . . . . . . . . . . 109
Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
6.1.1
Deployment current selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.1.2
Deploy command expiration timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.1.3
Deployment control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.1.4
Deployment success . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2
Energy reserve - deployment voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
6.3
Deployment ground return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
6.4
Deployment driver protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
6.5
6.4.1
Delayed low-side deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.4.2
Low-side voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.4.3
Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.4.4
Short to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.4.5
Intermittent open squib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
6.5.1
Low level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.5.2
High level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.1
7.2
4/202
Safing records request mask registers (SAF_REQ_MASK_x) . . . . . . 100
Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1
7
5.1.40
PSI-5 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.1.1
Functional description - remote sensor modes . . . . . . . . . . . . . . . . . . 126
7.1.2
RSU data fields and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.1.3
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Remote sensor interface fault protection . . . . . . . . . . . . . . . . . . . . . . . . 130
7.2.1
Short to ground, current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.2.2
Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.2.3
Cross link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
DocID029274 Rev 1
L9678P, L9678P-S
8
Contents
7.2.4
Leakage to battery, open condition . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2.5
Leakage to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2.6
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.1
Temporal watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.1.1
Watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.1.2
Watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.2
Watchdog reset assertion timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.3
Watchdog timer disable input (WDT/TM) . . . . . . . . . . . . . . . . . . . . . . . . 135
9
DC sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10
Safing logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.1
Safing logic overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.2
SPI sensor data decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.3
In-frame and out-of-frame responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.4
Safing state machine operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.4.1
Simple threshold comparison operation . . . . . . . . . . . . . . . . . . . . . . . 148
10.5
Safing engine output logic (ARMxINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.6
Arming pulse stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
10.7
Additional communication line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11
General purpose output (GPO) drivers . . . . . . . . . . . . . . . . . . . . . . . . 154
12
ISO9141 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
13
System voltage diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
13.1
Analog to digital algorithmic converter . . . . . . . . . . . . . . . . . . . . . . . . . . 162
14
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.1
Configuration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.2
Internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.3
Internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
DocID029274 Rev 1
5/202
6
Contents
L9678P, L9678P-S
15.4
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
15.5
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
15.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
15.7
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
15.8
ER boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
15.9
ER charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.10 ER switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.11 COVRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
15.12 VDD5 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
15.13 VDD3V3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15.14 VSUP regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
15.15 VSF regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.16 Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.17 Squib diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.17.1 Squib resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.17.2 Squib leakage test (VRCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.17.3 High/low side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
15.17.4 Deployment timer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
15.18 Remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.19 DC sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
15.20 Safing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.21 General purpose output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.22 ISO9141 interface (K-LINE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.22.1 Analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.23 Voltage diagnostics (analog Mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
16
Quality information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
16.1
17
18
6/202
OTP trim bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
17.1
LQFP64 (10x10x1.4 mm) package information . . . . . . . . . . . . . . . . . . . 198
17.2
LQFP64 (10x10x1.4) marking information . . . . . . . . . . . . . . . . . . . . . . . 200
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DocID029274 Rev 1
L9678P, L9678P-S
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functions disabling by state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI register R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Global SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Global status word (GSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Short between loops diagnostics decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Watchdog timer status description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Records results comparison against two threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Diagnostics control register (DIAGCTRLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Diagnostics divider ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Configuration and control DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Configuration and control AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Open ground detection DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Open ground detection AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Internal regulators DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Internal regulators AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Oscillators AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Temporal watchdog timer AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Reset DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Reset AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SPI DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
SPI AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
ER Boost converter DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
ER boost converter AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ER boost converter external components (Design Info) . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ER current generator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
ER current generator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
ER switch DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
ER switch AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
COVRACT DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
COVRACT AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
VDD5 regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
VDD5 regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
VDD5 regulator external components (Design Info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
VDD3V3 regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
VDD3V3 regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
VDD3V3 regulator external components (design info) . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
VSUP regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
VSUP AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
VSUP regulator external components (Design Info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
VSF regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
VSF regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Deployment drivers - DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Deployment drivers - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Deployment drivers diagnostics (Squib resistance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
DocID029274 Rev 1
7/202
8
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
8/202
L9678P, L9678P-S
Squib leakage test (VRCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
High/low side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Deployment timer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Remote sensor I/F DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
PSI-5 remote sensor transceiver - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DC sensor interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Arming interface - DC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Arming interface - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
GPO interface DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
GPO Driver Interface - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
ISO9141 interface DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
ISO9141 interface transceiver AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Voltage diagnostics (Analog MUX) DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Temperature sensor specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
LQFP64 (10x10x1.4 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DocID029274 Rev 1
L9678P, L9678P-S
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Pin-out description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power control state flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Wake-up input signal behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Normal power-up sequence - WAKEUP controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Normal power-up sequence - VIN controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Normal power down sequence - WAKEUP and SPI controlled . . . . . . . . . . . . . . . . . . . . . 25
Normal power down sequence - VIN controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
System operating state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ERBOOST block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ERBOOST control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ER cap charging circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ER switch control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VDD5 control behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VDD3V3 control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VSUP control behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VSF control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Internal voltage errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset control diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Deployment driver control blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Deployment driver control logic - Enable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Deployment driver control logic - Turn-on signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Deployment driver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Global SPI deployment enable state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Deployment loop diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SRx pull-down enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Deployment timer diagnostic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
High level loop diagnostic flow1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
High level loop diagnostic flow2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Remote sensor interface logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Remote sensor interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PSI-5 remote sensor protocol (10-bit, 1-bit parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Manchester bit encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Manchester decoder state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Remote sensor current sensing auto adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Watchdog state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Watchdog timer refresh diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Switch sensor interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Top level safing engine flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Safing engine - 16-bit message decoding flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Safing engine - 32-bit message decoding flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Safing engine - validate data flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Safing engine - combine function flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Safing engine threshold comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Safing engine - compare complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
In-frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Out of frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Safing Engine Arming flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
DocID029274 Rev 1
9/202
10
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
10/202
L9678P, L9678P-S
Safing engine diagnostic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ARM output control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Pulse stretch timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Scrap ACL state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Disposal PWM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
GPO driver block diagram - LS configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
GPO driver block diagram - HS configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
ISO9141 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
ADC conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Deployment drivers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
LQFP64 (10x10x1.4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
LQFP64 (10x10x1.4) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DocID029274 Rev 1
L9678P, L9678P-S
1
Description
Description
The L9678P IC is a system chip solution targeted for emerging market applications. Base
system designs can be completed with the L9678P, SPC560Px microcontroller and an onboard acceleration sensor or PSI5 sensor.
Energy reserve voltage is derived through a cost effective high frequency boost regulator.
High frequency operation allows the user to pick up low value and cheap inductance. The
voltage is programmable to 23 V or 33 V nominal.
Battery voltage is sensed through the VBATMON pin providing start-up and shutdown
control for the system. Once battery voltage drops below the minimum operating voltage,
the device enables the integrated crossover switch to permit orderly shutdown.
L9678P offers two linear regulators (5 V with external pass transistor and fully integrated
3.3 V). User can use one of these regulators to supply µC. Input/output pins are compatible
with both ranges by dedicated supply pin VDDQ. External pass transistor gives the flexibility
to easily address different current loads in case of different micro-controllers.
One optional 7.2 V linear regulator with external pass transistor can be used to supply
remote sensor interface.
External acceleration data is received through the PSI-5 remote sensor interface. Both
channels have independent decoders. Sensor data and diagnostics are available via SPI.
The safing logic monitors inertial sensors (remote sensors via PSI-5 or on-board sensors via
SPI) to determine if a crash event is in progress, thereby enabling deployment to occur.
Parameters for sensor configuration and thresholds are user programmable.
Squib deployment uses four independent high and low side drivers, capable of deploying at
25 V max. Diagnostic data control is provided through the SPI interface.
The Hall-effect, resistive or switch sensor interface can be used to determine the state of
external switch devices, such as buckle switches, seat track position sensors, weight
sensors, deactivation switches.
The integrated clock module provides a fixed clock signal for the microcontroller. The clock
module provides the user the option of deleting the commonly used resonator or crystal.
DocID029274 Rev 1
11/202
201
Absolute and operative maximum ratings
L9678P, L9678P-S
2
Absolute and operative maximum ratings
2.1
Absolute maximum ratings
Warning:
This part may be irreparably damaged if taken outside the
specified absolute maximum ratings. Operation above the
absolute maximum ratings may also cause a decrease in
reliability.
Table 2. Absolute maximum ratings
Pin #
Pin name
1
RESET
2
Pin function
Min.
Max.
Unit
Reset output
-0.3
VDDQ+0.3 6.5
V
SPI_MISO
SPI interface data out / Safing sensor data in
-0.3
VDDQ+0.3 6.5
V
3
SPI_MOSI
SPI interface data in
-0.3
VDDQ+0.3 6.5
V
4
SPI_SCK
SPI interface clock
-0.3
VDDQ+0.3 6.5
V
5
SPI_CS
SPI interface chip select
-0.3
VDDQ+0.3 6.5
V
6
WDT/TM
Watchdog disable (Not for application)
-0.3
20
V
7
VDD3V3
3.3 V regulator output
-0.3
4.6
V
-
-
-
8
NC
9
CVDD
Internal 3.3 V regulator output
-0.3
4.6
V
10
GNDD
Digital ground
-0.3
0.3
V
11
SR0
Squib 0 low-side pin
-0.3
40
V
12
SF0
Squib 0 high-side pin
-1.0
40
V
13
SG01
Squib 0 & 1 deployment ground pin
-0.3
0.3
V
14
SS01
Squib 0 & 1 deployment supply pin
-0.3
40
V
15
SF1
Squib 1 high-side pin
-1.0
40
V
16
SR1
Squib 1 low-side pin
-0.3
40
V
17
DCS3
Sensor switch interface channel 3
-1.0
40
V
18
DCS2
Sensor switch interface channel 2
-1.0
40
V
19
DCS1
Sensor switch interface channel 1
-1.0
40
V
20
DCS0
Sensor switch interface channel 0
-1.0
40
V
21
VRESDIAG
Reserve voltage diagnostic input
-0.3
40
V
22
RSU0/NC
PSI-5 Ch. 0 remote sensor output (only
L9678P-S), NC on L9678P
-1.0
40
V
23
RSU1/NC
PSI-5 Ch. 1 remote sensor output (only
L9678P-S), NC on L9678P
-1.0
40
V
24
VSUP/NC
Remote sensor power supply (only L9678PS), NC(1) on L9678P
-0.3
40
V
12/202
Not connected
(1)
DocID029274 Rev 1
L9678P, L9678P-S
Absolute and operative maximum ratings
Table 2. Absolute maximum ratings (continued)
Pin #
Pin name
25
BVSUP/NC
26
Pin function
Min.
Max.
Unit
VSUP external transistor control (only
L9678P-S), NC(1) on L9678P
-0.3
40
V
GPOD0
GPO driver 1 drain output pin
-1.0
40
V
27
GPOS0
GPO driver 1 source output pin
-1.0
40
V
28
GPOS1
GPO driver 0 source output pin
-1.0
40
V
29
GPOD1
GPO driver 0 drain output pin
-1.0
40
V
-
-
-
ISO9141 bus pin (K-LINE)
-18.0
40
V
Substrate ground
-0.3
0.3
V
Not connected
(1)
30
NC
31
ISOK
32
GNDSUB1
33
SR3
Squib 3 low-side pin
-0.3
40
V
34
SF3
Squib 3 high-side pin
-1.0
40
V
35
SS23
Squib 2 & 3 deployment supply pin
-0.3
40
V
36
SG23
Squib 2 & 3 deployment ground pin
-0.3
0.3
V
37
SF2
Squib 2 high-side pin
-1.0
40
V
38
SR2
Squib 2 low-side pin
-0.3
40
V
39
GNDA
Analog ground
-0.3
0.3
V
40
ISORX
ISO9141 receiver pin
-0.3
VDDQ+0.3 6.5
V
41
ISOTX
ISO9141 transmit pin
-0.3
VDDQ+0.3 6.5
V
42
FENL
LS driver FET control input
-0.3
VDDQ+0.3 6.5
V
43
FENH
HS driver FET control input
-0.3
VDDQ+0.3 6.5
V
44
SAF_CS0
SPI interface safing sensor chip select
-0.3
VDDQ+0.3 6.5
V
45
SAF_CS1
SPI interface safing sensor chip select
-0.3
VDDQ+0.3 6.5
V
-
-
-
46
NC
47
WAKEUP
Wake-up control input
-0.3
40
V
48
VBATMON
Battery line voltage monitor
-18
40
V
49
VSF
Safing regulator supply output
-0.3
ERBOOST+0.3 40
V
50
VIN
Battery connection
-0.3
40
V
51
VER
Reserve voltage
-0.3
40
V
52
ERBOOST
Energy reserve regulator output
-0.3
40
V
53
ERBSTSW
Boost switching output
-0.3
40
V
-
-
-
Boost regulator ground
-0.3
0.3
V
EOL disposal control input
-0.3
40
V
VDD5 external transistor control
-0.3
40
V
-
-
-
-0.3
6.5
V
-
-
-
54
NC
55
BSTGND
56
ACL
57
BVDD5
58
NC
59
VDD5
60
NC
Not connected
(1)
Not connected
(1)
Not connected
5V regulator output
Not connected
(1)
DocID029274 Rev 1
13/202
201
Absolute and operative maximum ratings
L9678P, L9678P-S
Table 2. Absolute maximum ratings (continued)
Pin #
Pin name
61
COVRACT
62
VDDQ
63
ARM
64
GNDSUB2
1.
Pin function
Min.
Max.
Unit
External crossover switch control
-0.3
VDDQ+0.3 6.5
V
I/O supply
-0.3
6.5
V
Arming Output
-0.3
VDDQ+0.3 6.5
V
Substrate ground
-0.3
0.3
V
Not connected internally, should be connected to GND externally.
2.2
Operative maximum ratings
Within the operative ratings the part operates as specified and without parameter
deviations. Once taken beyond the operative ratings and returned back within, the part will
recover with no damage or degradation.
Additional supply-voltage and temperature conditions are given separately at the beginning
of each specification table.
Table 3. Operative maximum ratings
Pin #
Pin name
1
RESET
2
Min.
Max.
Unit
Reset output
-0.1
VDDQ+0.1 5.5
V
SPI_MISO
SPI interface data out / Safing sensor data in
-0.1
VDDQ+0.1 5.5
V
3
SPI_MOSI
SPI interface data in
-0.1
VDDQ+0.1 5.5
V
4
SPI_SCK
SPI interface clock
-0.1
VDDQ+0.1 5.5
V
5
SPI_CS
SPI interface chip select
-0.1
VDDQ+0.1 5.5
V
6
WDT/TM
Watchdog disable
-0.1
20
V
7
VDD3V3
3.3V regulator output
-0.1
3.6
V
8
NC
-
-
-
9
CVDD
Internal 3.3V regulator output
-0.1
3.6
V
10
GNDD
Digital ground
-0.1
0.1
V
11
SR0
Squib 0 low-side pin
-0.1
VER
V
12
SF0
Squib 0 high-side pin
-1.0
VER
V
13
SG01
Squib 0 & 1 deployment ground pin
-0.1
0.1
V
14
SS01
Squib 0 & 1 deployment supply pin
-0.1
40
V
15
SF1
Squib 1 high-side pin
-1.0
VER
V
16
SR1
Squib 1 low-side pin
-0.1
VER
V
17
DCS3
Sensor switch interface channel 3
-1.0
VDCS_L
V
18
DCS2
Sensor switch interface channel 2
-1.0
VDCS_L
V
19
DCS1
Sensor switch interface channel 1
-1.0
VDCS_L
V
20
DCS0
Sensor switch interface channel 0
-1.0
VDCS_L
V
21
VRESDIAG
Reserve voltage diagnostic input
-0.1
35
V
22
RSU0/NC
PSI-5 Ch. 0 remote sensor output (only
L9678P-S), NC on L9678P
-1.0
VSUP
V
14/202
Pin function
Not connected(1)
DocID029274 Rev 1
L9678P, L9678P-S
Absolute and operative maximum ratings
Table 3. Operative maximum ratings (continued)
Pin #
Pin name
23
RSU1/NC
24
VSUP/NC
25
BVSUP/NC
26
Pin function
Min.
Max.
Unit
PSI-5 Ch. 1 remote sensor output (only
L9678P-S), NC on L9678P
-1.0
VSUP
V
Remote sensor power supply (only L9678PS, NC(1) on L9678P)
-0.1
VIN
V
VSUP external transistor control (only
L9678P-S, NC(1) on L9678P)
-0.1
VIN
V
GPOD0
GPO driver 1 drain output pin
-0.1
40
V
27
GPOS0
GPO driver 1 source output pin
-1.0
VIN
V
28
GPOS1
GPO driver 0 source output pin
-1.0
VIN
V
29
GPOD1
GPO driver 0 drain output pin
-0.1
40
V
-
-
-
Not connected
(1)
30
NC
31
ISOK
ISO9141 bus pin
-1.0
40
V
32
GNDSUB1
Substrate ground
-0.1
0.1
V
33
SR3
Squib 3 low-side pin
-0.1
VER
V
34
SF3
Squib 3 high-side pin
-1.0
VER
V
35
SS23
Squib 2 & 3 deployment supply pin
-0.1
40
V
36
SG23
Squib 2 & 3 deployment ground pin
-0.1
0.1
V
37
SF2
Squib 2 high-side pin
-1.0
VER
V
38
SR2
Squib 2 low-side pin
-0.1
VER
V
39
GNDA
Analog ground
-0.1
0.1
V
40
ISORX
ISO9141 receiver pin
-0.1
VDDQ+0.1  5.5
V
41
ISOTX
ISO9141 transmit pin
-0.1
VDDQ+0.1  5.5
V
42
FENL
LS driver FET control input
-0.1
VDDQ+0.1  5.5
V
43
FENH
HS driver FET control input
-0.1
VDDQ+0.1  5.5
V
44
SAF_CS0
SPI interface safing sensor chip select
-0.1
VDDQ+0.1  5.5
V
45
SAF_CS1
SPI interface safing sensor chip select
-0.1
VDDQ+0.1  5.5
V
-
-
-
46
NC
47
WAKEUP
Wake-up control input
-0.1
VIN
V
48
VBATMON
Battery line voltage monitor
-0.1
18
V
49
VSF
Safing regulator supply output
-0.1
27
V
50
VIN
Battery connection
-0.1
35
V
51
VER
Reserve voltage
-0.1
35
V
52
ERBOOST
Energy reserve regulator output
-0.1
35
V
53
ERBSTSW
Boost switching output
-0.1
ERBOOST+1
V
-
-
-
Boost regulator ground
-0.1
0.1
V
EOL disposal control input
--0.1
40
V
VDD5 external transistor control
-0.1
VIN
V
54
NC
55
BSTGND
56
ACL
57
BVDD5
Not connected
(1)
Not connected
(1)
DocID029274 Rev 1
15/202
201
Absolute and operative maximum ratings
L9678P, L9678P-S
Table 3. Operative maximum ratings (continued)
Pin #
Pin name
58
NC
59
VDD5
1.
60
NC
61
COVRACT
62
VDDQ
63
ARM
64
GNDSUB2
Pin function
Min.
Max.
Unit
-
-
-
Not connected (1)
5V regulator output
-0.1
5.5
V
(1)
-
-
-
External crossover switch control
-0.1
VDDQ+0.1  5.5
V
I/O supply
-0.1
5.5
V
Arming Output
-0.1
VDDQ+0.1  5.5
V
Substrate ground
-0.1
0.1
V
Not connected
Not connected internally, should be connected to GND externally.
2.3
Pin-out description
The L9678P-S/L9678P pin-out is shown below. The package is a LQFP 64-pin full plastic
package.
96)
9,1
9(5
(5%2267
(5%676:
1&
%67*1'
$&/
%9''
1&
9''
1&
&295$&7
9''4
$50
*1'68%
Figure 1. Pin-out description
5(6(7
9%$7021
63,B0,62
:$.(83
63,B026,
1&
63,B6&.,
6$)B&6
63,B&6
6$)B&6
:'770
)(1+
9''9
)(1/
1&
,627;
&9''
,625;
*1''
*1'$
65
65
6)
6)
6*
6*
66
66
6)
6)
65
65
16/202
DocID029274 Rev 1
*1'68%
,62.
1&
*326
*32'
*326
*32'
96831&
%96831&
5681& 5681&
7KRVHSLQVDUH1&LQWKH/YHUVLRQ
1RWFRQQHFWHGLQWHUQDOO\VKRXOGEHFRQQHFWHGWR*1'H[WHUQDOO\
95(6',$*
'&6
'&6
'&6
'&6
*$3*36
L9678P, L9678P-S
3
Overview and block diagram
Overview and block diagram
The L9678P is a unique solution specifically targeted for entry level airbag systems while
permitting the system designer significant flexibility in configuring the system power and
management block. The configurable methodology allows cost versus performance tradeoff without changing devices or circuit board designs. The L9678P contains the base
functionality required for entry level systems and can complete a system design with a
microcontroller and acceleration sensor. The high level block diagram is shown below
Figure 2.
Basic features include a configurable power supply & management block, 4 channel squib
drivers, 2 channel HS/LS GPO drivers, 4 channel sensor interface, safing logic, watchdog
timer, ISO9141 communications and temperature sensor. The L9678P-S device is pin
compatible to the L9678P and includes two PSI-5 remote sensor interface channels and a
dedicated regulator for remote sensor.
DocID029274 Rev 1
17/202
201
Overview and block diagram
L9678P, L9678P-S
Figure 2. Functional block diagram
9EDW
—+
Q)
X)
66
$
X)
—)
Q)
Q)
P)WRP)
(5%676:
(5%2267
9(5
9%DW0RQ
X&B)/(1
(5&KDUJH
(5
%RRVW
%67*1'
9,1
Q)
N
%9''
%&3
9''
6DILQJ UHJXODWRU (56ZLWFK
9''
OLQHDU
UHJXODWRU
96)
*1'68%[
Q)
*32'
)
9''9
)
:$.(83
9,JQ
9''4
&9''
9''9
OLQHDUUHJ *326
*32'
*32
GULYHUV
VXSSO\
9,179
UHJ IRU
DQDORJ
EORFN V
*326
'LJLWDO
2XWSXWV
95(6',$*
Q)
&9''UHJ IRU
GLJLWDOEORFN V
*1''
66
*1'$
N
%9683
%&3
66
9683
OLQHDU
UHJXODWRU
'LJLWDO
EORFN
9683
6)
6)
)
6DWHOOLWH'ULYHU
'HFRGHU
2SWLRQDO
/6
6)
Q)
6)
(QDEOH
&RQWURO
)(1+
+9DQDORJ08;
DQG
$WR'FRQYHUWHU
ELWV )(1/
65
65
'HFRGHU
568
65
/6
568
Q)
65
'&+DOOVHQVRULQWHUIDFH
Q)
6*
(QDEOH
&RQWURO
6TXLEGULYHUV DQG
'LDJQRVWLF
'&6
6DILQJ
/RJLF
'&6
6*
$&/
$50
'&6
Q)
'&6
6\VWHPFRQWURO
FRQILJXUDWLRQ
,62
WUDQVFHLYHU
*1'68%
&295$&7
:'7',670
63,B026,
5(6(7
63,B6&.
63,B0,62
6$)B&6
6$)B&6
63,B&6
,627;
,625;
*1',62
,62.
9EDW
'!0'03
18/202
DocID029274 Rev 1
L9678P, L9678P-S
Start-up power control
4
Start-up power control
4.1
Power supply overview
The L9678P IC contains a complete power management system able to provide all
necessary voltages for an entry level airbag application. Moreover L9678P power supply is
user configurable allowing the design engineer to balance cost and performance as per their
particular application. The power supply block contains the following features:

Two 3.3 V internal regulators for operating internal logic (CVDD) and analog circuits
(VINT3V3). An external CVDD pin is used to provide filtering capacitance to digital
section supply rail.

Energy reserve supply (ERBOOST) achieved through an integrated switching boost
regulator. The design of this boost regulator is intended to be a cost effective solution
with respect to traditional boost regulators because it makes use of a low value
inductor with an operative frequency of 1.882 MHz. Switching output is ERBSTSW pin,
while voltage feedback input pin is ERBOOST. The output voltage could be set to either
23 V±5% or 33 V±5%.

Energy reserve capacitor connected to VER pin. To control in-rush current, a dedicated
current generator is implemented between ERBOOST pin and VER pin.

Capability to drive an external safing FET (n-ch type) by means of an internal voltage
regulator on VSF pin, where a 20 V level is given (configurable to 25V via SPI
command).

The integrated current limited ER switch requires no external components. This switch
is controlled through the integrated power control state machine and is enabled either
once a loss of battery is detected or a shutdown command is received. Under the same
conditions also the discrete digital pin COVRACT is activated allowing the control of an
external optional cross-over switch.

One linear regulator VDD5 (5 V nominal, ±4% tolerance) requiring external power
transistor and capacitors. VDD5 is used as micro-controller supply (in case of 5 V
family controllers) and, in any case, as supply for VDD3V3 rail.

One integrated linear regulator VDD3V3 (3.3 V nominal, ±4% tolerance) requiring
external capacitors. VDD3V3 is used as micro-controller supply (in case of 3.3 V family
controllers).

VDDQ pin to provide output voltage rail reference. VDDQ could be connected to either
VDD5 or VDD3V3 to enable 5 V or 3.3 V digital communication between device and
micro-controller.

Capability to drive an external power transistor connected to VIN to provide a 7.2 V rail
on VSUP pin. This voltage rail could be used to supply PSI-5 remote sensor.

Battery voltage sense input comparator with hysteresis connected to VBATMON pin.
Power-up and operation states are carefully handled with respect to the battery level to
provide the most effective power supply configuration.

All voltage rails (VIN, ERBOOST, VER, VRESDIAG, VDD5, VDD3V3, VSUP and VSF)
can be monitored through internal ADC diagnostics.
DocID029274 Rev 1
19/202
201
Start-up power control
4.2
L9678P, L9678P-S
Power mode control
Start-up and power down of the L9678P are controlled by the WAKEUP pin, VBATMON pin,
VIN pin device status and the SPI interface. There are four main power modes: power-off,
sleep, active and passive mode.
Each power mode is described below and represented in the state flow diagram shown in
Figure 3. The descriptions include references to conditions and sometimes nominal values.
The absolute values for each condition are listed in the electrical specifications section.
Figure 3. Power control state flow diagram
)URP
DQ\VWDWH
325
32:(5
2))
VWDWH
32:(52)) 02'(
$OOVXSSOLHVGLVDEOHG
:$.(83
:8BPRQ
:$.(83!
:8BPRQ
:$.(83
021,725
VWDWH
:$.(83!
:8BRQ
>:$.(83 :8BRII$1'
:DNH8S)LOW @
$:$.(
6WDWH
:DNH8S)LOW $1'
9,19,1*22'
:DNH8S)LOW 25
9,19,1%$'
:DNH8S)LOW $1'
9,1!9,1*22'
6/((302'(
67$5783
VWDWH
:DNH8S)LOW $1'
9,1!9,1*22'
7ZDNHXS!PV
:DNH8S)LOW $1' 63,B6/((3
581
VWDWH
9%$7 PRQ!9%*22'
EODQNLQJWLPHPV
$&7,9(02'(
9,19,1*22'
32:(502'(
6+87'2:1
VWDWH
(5
VWDWH
:DNH8S)LOW $1' 63,B6/((3
7ZDNHXS7LPHU&OHDUHGLI6WDWH :$.(83021,725RU$:$.(DQG:DNH8S)LOW 20/202
DocID029274 Rev 1
3$66,9(02'(
'!0'03
L9678P, L9678P-S
4.2.1
Start-up power control
Power_off mode
During the Power-off mode all supplies are disabled keeping the system in a quiescent state
with very low current draw from battery. As soon as WAKEUP > WU_mon the IC will move
to Sleep mode.
4.2.2
Sleep mode
During the Sleep mode the VINT3V3 and CVDD internal regulators are turned on and the IC
is ready for full activation of all the other supplies. As soon as battery voltage is over a
minimum threshold, all the other supplies are turned on and the IC enters the Active mode.
4.2.3
Active mode
This is the normal operating mode for the system.
All power supplies are enabled and the energy reserve boost converter starts to increase
the voltage at ERBOOST. Likewise, the VDD5 regulator is turned on. Once the VDD5 has
reached a good value, the VDD3V3 regulator starts up. Once the VDD3V3 regulator is in
regulation, RESET is released allowing the system microcontroller and other components to
begin their power-on sequence. Among these, also the ER charge current generator can be
enabled by the microcontroller via a dedicated SPI command.
The active mode can be left when either WAKEUP pin or VIN voltage drop down. For the
very first 9 ms after having entered the active mode, the WAKEUP pin low would
immediately cause the IC to switch back to sleep mode. After that time, WAKEUP pin low
must be first confirmed by a MCUSPI_SLEEP command prior to cause the system to switch
to passive mode. Passive mode is also entered in case of VIN voltage low.
4.2.4
Passive mode
In this state, the energy reserve charge current is disabled and the ERBOOST boost
converter is disabled only if the SYS_CFG(KEEP_ERBST_ON)=0. When in passive mode
the device automatically activates both the COVRACT output pin and the integrated ER
switch to allow VIN to be connected to the ER capacitor. In this time, VIN is supposed to be
increased up to almost VER level and the system operation relies on energy from the ER
capacitor. Two scenarios are possible: high or low battery. If VIN < VINGOOD, the device
moved from RUN state in ACTIVE mode to the ER state. Here, the ER capacitor is depleted
while supplying all the regulators until the POR on internal regulator occurs. The threshold
to decide the ER switch activation is based on VIN, because VIN is the supply voltage rail
for all regulators. If the device has still a good battery level, it entered the POWERMODE
SHUTDOWN thanks to WAKEUP pin and MCU command to switch off. In this case, the
VER node will be discharged down to approximately VIN level, which then will be supplied
out of the battery line. System will continue to run up to a dedicated SPI command which will
lead the device to enter the POWEROFF state.
The wake-up pin is filtered to suppress undesired state changes resulting from transients or
glitches. Typical conditions are shown in the chart below and summarized by state.
DocID029274 Rev 1
21/202
201
Start-up power control
L9678P, L9678P-S
Figure 4. Wake-up input signal behaviour
$&7,9(02'(
6/((302'(
3$66,9(02'(
:8BRQ
:8BRII
:$.(83
W
PV
PV
PV
PV
PV
:DNH8S)LOW
W
'!0'03
Condition summary:
1.
No change of sleep mode state but current consumption may exceed specification for
sleep mode.
2.
The sleep mode current returns within the specified limits.
3.
Power supply exits sleep mode. Switchers start operating if applicable voltages exceed
under voltage lockouts. As Twakeup time-out is not elapsed, a low level at WAKEUP
instantaneously sends the system back to sleep.
4.
Sleep Reset is released and the entire system starts operating. A SPI command to
enter sleep state would be ignored.
5.
No change in system status, a SPI command to enter sleep state would be ignored.
6.
No change in system status, but a SPI command to turn off switchers would be
accepted and turn the system off.
With the below table, all the functionalities of the device are shown with respect to the power
states. When one function is flagged, the related circuitry cannot be activated on that state.
Table 4. Functions disabling by state
Power
Off
Wake-up
monitor
Awake
Start-up
Run
Power
mode
shutdown
ER
Wakeup detector
X
-
-
-
-
-
-
Internal regulator
X
X
-
-
-
-
-
ERBOOST regulator
X
X
X
-
-
X
X
VSUP regulator (L9678P-S only)
X
X
X
-
-
-
-
ER CAP charge current source
X
X
X
-
-
X
X
ER switch
X
X
X
X
X
-
-
COVRACT Output
X
X
X
X
X
-
-
Function
VDD5 regulator
X
X
X
-
-
-
-
VDD3V3 regulator
X
X
X
-
-
-
-
Deployment drivers
X
X
X
-
-
-
-
VSF safing FET regulator
X
X
X
-
-
-
-
Remote sensor interfaces
(L9678P-S only)
X
X
X
-
-
-
-
22/202
DocID029274 Rev 1
L9678P, L9678P-S
Start-up power control
Table 4. Functions disabling by state (continued)
Power
Off
Wake-up
monitor
Awake
Start-up
Run
Power
mode
shutdown
ER
Watchdog
X
X
X
-
-
-
-
Diagnostics
X
X
X
-
-
-
-
DC sensor interface
X
X
X
-
-
-
-
GPO drivers
X
X
X
-
-
-
-
Safing logic
X
X
X
-
-
-
-
ISO9141
X
X
X
-
-
-
-
Function
Power-up and power-down sequence
The behavior of the IC during normal power-up and power-down is shown from Figure 5 to
Figure 8. The following sequences represent just a subset of all possible power-up and
power-down scenarios.
In Figure 5 a normal IC power-up controlled by the state of the WAKEUP pin is shown.
Figure 5. Normal power-up sequence - WAKEUP controlled
9,1FXUUHQW
9%$7 9%*22'
9%$7PRQ
:8BRQ
:$.(83
:8BPRQ
9,17&9''
325
(5%2267
9''
9''9
9''9B8
9
5(6(7
5(6(7
+ROG7LPH
63,(5
FKDUJHRQ
4.2.5
9(5
DocID029274 Rev 1
*$3*36
23/202
201
Start-up power control
L9678P, L9678P-S
Figure 6. Normal power-up sequence - VIN controlled
9,1FXUUHQW
9,1*22'
9%$7
9,1
:8BRQ
:8BPRQ
:$.(83
9,17&9''
325
(5%2267
9''
9''9
9''9B8
9
5(6(7
5(6(7
+ROG7LPH
63,(5
FKDUJHRQ
9(5
*$3*36
Two different scenarios for power-down of the IC are shown here below. Figure 7 describes
the powering down for the case when WAKEUP pin is released. As soon as a SPI_SLEEP
command is received by the MCU the System will immediately move to the energy reserve
(PASSIVE mode). In Figure 8, VIN release begins the shutdown process.
24/202
DocID029274 Rev 1
L9678P, L9678P-S
Start-up power control
Figure 7. Normal power down sequence - WAKEUP and SPI controlled
9%$7
9%$7021
9%*22'
9%%$'
63,
:8BRQ
:8BRII
63,B6/((3
FRPPDQG
:$.(83
63,B2))
FRPPDQG
(56ZLWFKHQDEOH
&295$&7
9(5
9''
9''989
9''9
5(6(7
9,17&9''
325
9,17&9''89
7KLVSHULRGRIWLPHFDQEHKROGIRUORQJ
WLPHEHFDXVHEDWWHU\LVJRRG7KHV\VWHP
ZDLWVXQWLODGHGLFDWHGIUDPHWRVZLWFKRII
DocID029274 Rev 1
*$3*36
25/202
201
Start-up power control
L9678P, L9678P-S
Figure 8. Normal power down sequence - VIN controlled
9,1*22'
9,1
9%$7 :$.(83
9,17&9''89
9,17&9''
(56ZLWFKHQDEOH
&295$&7
9(5
9''
9''9
9''989
5(6(7
325
*$3*36
4.2.6
Operating states
Different states can be identified while operating the device. These states allow safe and
predictable initialization, test, operation and end of line disposal of the part (scrapping).
As soon as the RESET signal is de-asserted at the beginning of the ACTIVE mode, the
microcontroller powers up. At this stage, L9678P is in the Init state: during this state the
device must be initialized by the controller. In particular, the watchdog timer window can be
programmed during this state.
When the watchdog service begins (upon the first successful watchdog feed), the device
switches to Diag state for diagnostics purposes. The remaining configuration of the device is
allowed in this state, in particular for safing records and deployment masks. Several tests
are also enabled while in this state and all these tests are mutually exclusive to one another.
HS and LS switch tests of the squib drivers can only be processed during this diag state.
Also high side safing FET can only be run during this state. When not in diag state, any
26/202
DocID029274 Rev 1
L9678P, L9678P-S
Start-up power control
commands for squib driver switch tests will be ignored. Other checks are also performed: on
the arming output to check for non stuck-at conditions on the pin and for the configured firing
time. The SSM remains in this state until commanded to transition into the Safing state or
Scrap state via the dedicated SPI commands.
Upon reception of the SAFING_STATE command while in Diag state, the device enters
Safing state. This is the primary run-time state for normal operation, and the logic performs
the safing function, including monitoring of sensor data and setting of the ARM signal. The
only means of exiting Safing state is by the assertion of the SSM_Reset signal.
The Scrap state is entered upon reception of the SCRAP_STATE command while in Diag
state. While in Scrap state, the part allows the main microcontroller to initiate a transition to
Arming state, and monitoring of the Remote Sensor SPI interface (in L9678P-S) and the
safing logic is disabled. From Scrap state, the device can transition to Arming state only, and
the only means of moving back to Init state is through an SSM_Reset.
In order to protect from inadvertent entry into Arming state, and to prevent undesired
activation of the safing signals, a dedicated mechanism is used to control entry into, and exit
from Arming state. This mechanism is described further in Section 10.7: Additional
communication line. While in Arming state, the arming output is asserted. Exit from Arming
state occurs when the time-out is reached without a correct ACL signal or when SSM_Reset
is asserted. Upon exit, the device re-enters Scrap state, except for the case of SSM_Reset,
which results in entry into Init state.
System Operating states are shown in Figure 9.
Figure 9. System operating state diagram
33-2ESET
#ONFIGURATIONENABLEDFOR
7ATCHDOGTIMINGTHRESHOLDS
!2-INOUTSELECT
235OUTPUTTYPE'M37
$IAGSAMPLESELECT
63&VOLTAGESELECT
)NIT
3TATE
7$25.
7$/6%22)$%
#ONFIGURATIONENABLEDFOR
3AFINGRECORDSANDCONTROL
$EPLOYMASK
(3,3'0/
$IAG
3TATE
30)3!&).'?34!4%
4ESTINGENABLEDFOR
!2-X63&
$EPLOYTIME
(3,3(33&%4
30)3#2!0?34!4%
!2-63&DETERMINED
BYSAFINGENGINE
3AFING
3TATE
3CRAP
3TATE
!2-X
63&
!#,'//$
!#,"!$
!RMING
3TATE
!2-X
63&
'!0'03
DocID029274 Rev 1
27/202
201
Start-up power control
4.3
L9678P, L9678P-S
Configurable system power control
The overall operating voltage requirements of the device are different considering the
L9678P device (without VSUP regulator and remote sensor interface) or the L9678P-S
device (with VSUP regulator and remote sensor interface). Performance for the L9678P-S
device is influenced by the PSI-5 remote sensor interfaces. This function requires a minimum
voltage at the channel's input (VSUP) to ensure a proper functionality for the sensor.
An integrated current generator (30 mA nominal) is used to charge the external energy
reserve capacitor connected to VER pin. Any system load (regulators, interfaces, squib
driver diagnostics) operates directly from battery until battery is lost. Upon detecting low or
loss of battery, the crossover switch enables operation from energy reserve.
4.3.1
ERBOOST switching regulator
The L9678P IC uses an advanced energy reserve switching regulator operating at 1.882
MHz nominal. The higher switching frequency enables the user to select smaller less
expensive inductors and moves the operating frequency to permit easier compliance with
system emissions.
The energy reserve boost regulator charges the external system tank capacitor through an
integrated fixed current source significantly reducing in-rush currents typical of large energy
reserve capacitors. The boost circuit provides energy for the reserve capacitor with
assumed run time load of less than 20 mA and to the VSF regulator. Once system shutdown
is initiated or a loss of battery condition is diagnosed, the boost regulator is disabled so that
system power can be taken from the energy reserve capacitor.
The energy reserve boost regulator defaults to 23 V at power-on and can be set to 33 V
nominal by the user through an SPI command. The boost converter can also be disabled by
the user through an SPI command. Enabling, disabling and setting the boost output voltage
are done through the System Control (SYS_CTL) register. Boost converter diagnostics
include over voltage and under voltage. The under voltage condition is reported by the
ER_BST_NOK bit in the POWER_STATE register. The integrated FET featuring the boost
switch is protected against short to battery by means of a thermal shutdown circuit. When
thermal fault is detected the FET is switched off and latched in this state until the related
fault flag ERBST_OT in the FLTSR register is read. In case of loss of ground the FET is
switched off and automatically reactivated as soon as ground connection is restored. Overvoltage protection from load dump and inductive flyback is provided via an active clamp and
an ER_Boost disable circuitry, see Figure 10.
Figure 10. ERBOOST block diagram
9,1
&/$03B(17+
(5%67
'ULYHU &RQWURO
(5%67B',6$%/( 7+
HQDEOH
(5%2267
(5%676:
&RPS
&/$03
%67*1'
*$3*36
28/202
DocID029274 Rev 1
L9678P, L9678P-S
Start-up power control
Normal run time power for the system is provided directly from the battery input, not from the
boost. Boost energy is available to the system through the energy reserve crossover switch
once battery is lost or a commanded system shutdown is initiated. By default, the ERBoost
regulator is switched off once enetered in passive mode. To keep active the ERBoost also in
passive mode the SPI bit SYS_CFG(KEEP_ERBST_ON) must be set to 1.
Figure 11. ERBOOST control behaviour
32:(52))B02'(
256/((3B02'(
(5%2267
SRZHUPRGHFRQWURO
(5%672))
'HIDXOW6<6B&7/(5B%67B(1 DW325 $FWLYHBPRGH $1'
9%$7021!9%*22'
$1'
9,1!9,1*22'
$1'
6<6B&7/(5 B%67 B(1 $1'
*1'%2267BORVV $1'
(5%67 B27 $1'
(5%67B',6$%/( 63,B6<6B&7/(5B%67B(1 $1'
(5%67 B27 >$FWLYHBPRGH 25
(5%6767%<
9%$70219%%$'
$1'
(5BVWDWH 25
6<6B&)*.((3B(5%67B21 @
25
9,19,1%$'
63,B)/7655($'
25
$1'
6<6&7/(5B%67B(1 (5%67 B27 25
*1'%2267BORVV 25
(5%67B',6$%/( (5%6721
(5%6727
(5%67 B27 '!0'03
4.3.2
Energy reserve capacitor charging circuit
The energy reserve capacitor connected to VER pin can be charged in an efficient way by
means of a current generator. Its capability is 30 mA nominal, so that for example a 2.2 mF
capacitor can be charged in approximately 2 s to 24 V. The current generator is activated or
deactivated by SPI command only while in ACTIVE mode. When not in ACTIVE mode, the
generator is always switched off in order to decouple ERBOOST node voltage from VER
reserve voltage.
Figure 12. ER cap charging circuit
660B5HVHW
(5&$3FKDUJHFRQWURO
'HIDXOW6<6B&7/(5B&85B(1 DW 660B5(6(7 (5BFKDUJHB21 $FWLYHBPRGH $1'
6<6B&7/(5B&85B(1 $FWLYHBPRGH 25
6<6B&7/(5B&85B(1 (5BFKDUJHB21 '!0'03
DocID029274 Rev 1
29/202
201
Start-up power control
4.3.3
L9678P, L9678P-S
ER switch and COVRACT pin
L9678P has an integrated circuit that can operate as a crossover switch with Rds(on) = 1.5 Ω
nominal. The ER switch is automatically activated upon entering the PASSIVE mode.
Voltage difference between VIN and VER is monitored in order to prevent VER back-feeding
when VIN exceeds VER by 0.1V max. The ER switch is automatically deactivated upon the
above mentioned overvoltage detection. The ER control implements a thermal protection
and a current limitation guard to avoid in-rush charge current at ER switch enabling or at
fault condition for short to ground. During PASSIVE mode the discrete digital output pin
COVRACT is activated to allow for external optional cross-over switch control.
Figure 13. ER switch control behaviour
77LPHRXW
325
³'HSOR\PHQWLQSURJUHVV´
(5BVZLWFKB67%<
6WDUW7PV
(5BVZLWFKB2))
3DVVLYHBPRGH $1'
(5B6:B29 3DVVLYHBPRGH 25
(5B6:B29 (5B6:,7&+B76' $1'
³GHSOR\PHQWQRWLQ
SURJUHVV´
(5B6:,7&+B76' (5BVZLWFKB2))B27
(5BVZLWFKB21
(5B6:B29 LI9,19(59
30/202
(5B6:,7&+B76' $1'
³GHSOR\PHQWQRWLQSURJUHVV´
'!0'03
DocID029274 Rev 1
L9678P, L9678P-S
4.3.4
Start-up power control
VDD5 linear regulator
The VDD5 linear regulator provides 5 V system voltage derived directly from battery line
with an external power transistor to reduce integrated circuit power dissipation. This voltage
rail is used in case a 5 V micro-controller is adopted. The stability of the regulation loop is
guaranteed by use of a small external capacitor. Current limitation is provided by means of
controlling output current on BVDD5 pin. The external pass transistor gives the flexibility to
easily address different current loads in case of different micro-controllers. The VDD5
regulator is enabled in the ACTIVE mode and continues operation in the PASSIVE mode
using power from energy reserve. VDD5 supply is monitored for system reset (see Power
On Reset and Reset); voltage monitoring is based on a second redundant bandgap voltage
reference.
Figure 14. VDD5 control behavior
9''
SRZHUPRGHFRQWURO
32:(52))B02'(
256/((3B02'(
9''B2))
&OHDU9''B29
7WLPHRXW
$&7,9(B02'(25
3$66,9(B02'(
9''BUDPSXS
9''B896' $1'7WLPHRXW
25
9''B29 6WDUW7PV
9''B896'PDVNLQJ
9''
6+87'2:1
6WDUW7PV
/DWFK9''B29
9''B89/ $1'
7WLPHRXW
9''B21
9''B89/ 25
9''B29 25
9''9B29 '!0'03
DocID029274 Rev 1
31/202
201
Start-up power control
4.3.5
L9678P, L9678P-S
VDD3V3 linear regulator
The fully integrated VDD3V3 linear regulator provides 3.3 V system voltage derived directly
from VDD5. This voltage rail is used in case a 3.3 V micro-controller is adopted. The stability
of the regulation loop is guaranteed by use of a small external capacitor. Current limitation is
implemented and its maximum current capability on VDD3V3 is 125 mA. The VDD3V3
regulator is enabled in the ACTIVE mode and continues operation in the PASSIVE mode
using power from energy reserve. VDD3V3 supply is monitored for system reset (see Power
On Reset and Reset); voltage monitoring is based on a second redundant bandgap voltage
reference.
Note that if the VDDQ pin (digital outputs supply) is connected to the VDD3V3, and any of
the digital output pins are connected to 5 V logic, there is no internal blocking diode to
prevent back-feeding this 3.3 V supply.
Figure 15. VDD3V3 control behaviour
6/((3B02'( 25
32:(52))B02'(
9''9
2))
9''9
SRZHUPRGHFRQWURO
7WLPHRXW
,Q9''B21VWDWH
9''9
6+87'2:1
6WDUW7PV
1RWLQ9''B21VWDWH
9''9B21
'!0'03
32/202
DocID029274 Rev 1
L9678P, L9678P-S
4.3.6
Start-up power control
VSUP linear regulator (optional)
The VSUP linear regulator can be used to provide 7 V derived directly from battery line with
an external power transistor. This voltage rail can be used mainly to supply PSI-5 remote
sensor interface. The stability of the regulation loop is guaranteed by use of a small external
capacitor. Current limitation is provided by means of controlling output current on BVSUP
pin. The external pass transistor gives the flexibility to easily address different current loads.
The VSUP regulator is enabled in the ACTIVE mode and continues operation in the
PASSIVE mode using power from energy reserve. In the case of L9678P (no remote sensor
interfaces), VSUP can be externally connected to ground.
Figure 16. VSUP control behavior
9683
SRZHUPRGHFRQWURO
32:(52))B02'(
256/((3B02'(
'HIDXOW6<6B&7/9683B(1 DW325 9683
2))
$&7,9(B02'(25
3$66,9(B02'(
$1'
6<6B&7/9683B(1 9683
UDPSXS
6WDUW7PV
9683B89PDVNLQJ
7WLPHRXW
6<6B&7/9683B(1 9683B89 $1'7WLPHRXW
9683
6+87'2:1
6WDUW7 PV
9683B89 $1'
7WLPHRXW
9683B89 9683B21
'!0'03
4.3.7
VSF linear regulator
The fully integrated VSF linear regulator provides a 20V voltage nominal (configurable to
25V via SPI command) derived directly from ERBOOST. This voltage rail is used in case an
external n-ch safing FET has to be used. The stability of the regulation loop is guaranteed
by use of a small external capacitor. Current limitation is implemented. A minimum drop-out
of 2V between ERBOOST and VSF is needed. VSF is enabled by the assertion of any
ARMxINT signal, or by the assertion of (FENH and not (FENL)), as shown in Figure 17
DocID029274 Rev 1
33/202
201
Start-up power control
L9678P, L9678P-S
Figure 17. VSF control logic
!2-?%.
3!&%3%,
!2-).4
!2-).4
&%.(
&%.,
3!&).'34!4%
$)!'34!4%
63&?%.
$34%3463&
!2-).'34!4%
4.4
'!0'03
Reset functions
The device provides reset logic to safely control system operation in the event of internal
ECU failures. Several internal reset signals are generated depending on the type of failure
detected. In the following figure, the voltage monitoring diagram is shown. BG_ERR reports
error on the bandgap reference voltage, VREG_ERR reports errors on any of the internal
regulators (VINT3V3 for 3.3 V analog circuitry, CVDD for 3.3 V digital circuitry),
VDD3V3_ERR and VDD5_ERR report errors on VDD3V3 and VDD5 regulators,
respectively.
Figure 18. Internal voltage errors
9%*5
5HIHUHQFH
9,179
5HIHUHQFHIRU
&RQWUROOLQJDOOVXSSOLHV
9%*0
0RQLWRU
9%*B5($'<
9,179
0RQLWRU
9''
9''9
9''
*1'68%[
9''
0RQLWRU
9''9
0RQLWRU
9''
0RQLWRU
*1'$
*1'$
0RQLWRU
*1''
*1''
0RQLWRU
9,17B29
9,17B89
9''B29
9''B89
9''9B29
9''9B89
9''B29
9''B89
95(*B(55
9''9B(55
9''B(55
*1'$B(55
*1'B(55
34/202
*1''B(55
'!0'03
DocID029274 Rev 1
L9678P, L9678P-S
Start-up power control
An active low pin output (RESET pin) is driven from the L9678P to allow resetting of external
devices such as the microcontroller, sensors, and other ICs within the ECU.
Three internal reset signals are generated by the device:

POR
Power On Reset - This reset is asserted when a failure is detected in the internal
supplies or bandgap circuits. When active, all other resets are asserted.

WSM_RESET
Watchdog State Machine Reset - This reset is generated when the POR is active.

SSM_RESET
System State Machine Reset - This reset is asserted when the POR or the
WSM_RESET are active, or when a failure is detected in either Watchdog state
machine.
The RESET pin is the active-low signal driven on the output pin, and is an inverted form of
SSM_RESET. The cause of a RESET activation is latched and reported into the Fault Status
Register FLTSR and cleared on SPI reading.
The reset logic shall be controlled as shown in the diagram below:
Figure 19. Reset control diagram
*1'B(55
&/.)5(55
325
9%*B5($'<
95(*B(55
9''B(55
:60B5HVHW
6<6B&)*',6B9''B(55
9''9B(55
PV
VWUHWFK
660B5HVHW
:'5(6(7VWDWH
5(6(7SLQ
'!0'03
GND_ERR is a general fault signal with the purpose of driving the device into POR when
either GNDA or GNDD is shifted more than 300 mV nominal with respect to the reference
ground pins GNDSUB.
DocID029274 Rev 1
35/202
201
SPI interface
5
L9678P, L9678P-S
SPI interface
The L9678P system solution device has many user selectable features controlled through
serial communications by the integrated microcontroller. The SPI interface provides
configuration, control and status functions for the device. The global SPI interface consists
of an input shift register, output shift register and four control signals. SPI_MOSI is the data
input to the input shift register. SPI_MISO is the data output from the output shift register.
SPI_SCK is the clock source input while SPI_CS is the active-low chip select input.
All SPI communications are executed in exact 32 bit increments. The general format of the
32 bit transmission is shown in Table 5.
Data to the IC (i.e. SPI_MOSI) consists of a target read register ID (RID), a target write
register ID (WID), write data parity (WPAR) and 16 bits of data (WRITE). WRITE data is the
data to be written to the target write register indicated by WID. Data returned from the IC
(i.e. SPI_MISO) consists of a global status word (GSW), read data parity (RPAR) and 20 bits
of data (READ). READ data will be the contents of the target read register as indicated by
the RID bits. The parity bits WPAR and RPAR cover all the 32 bits of the MOSI and MISO
frames, respectively. Odd parity type is used.
Table 5. SPI register R/W
SPI register R/W
SPI_MOSI
SPI_MISO
SPI_MOSI
SPI_MISO
31
GID
30
29
15
14
13
28
27
26
25
RID[6:0]
GSW[10:0]
12
11
10
9
24
23
22
8
7
6
WRITE[15:0]
READ[15:0]
21
20
19
WID[6:0]
RPAR
5
4
3
18
17
16
WPAR
READ[19:16]
2
1
0
The communications is controlled through SPI_CS, enabling and disabling communication.
When SPI_CS is at logic high, all SPI communication I/O is tri-stated and no data is
accepted. When SPI_CS is low, data is latched on the rising edge of SPI_SCK and data is
shifted on the falling edge. The SPI_MOSI pin receives serial data from the master with
MSB first. Likewise for SPI_MISO, data is read MSB first, LSB last.
The L9678P IC contains a data validation method through the SPI_SCK input to keep
transmissions with not exactly 32 bits from being written to the device. The SPI_SCK input
counts the number of received clocks and should the clock counter exceed or count fewer
than 32 clocks, the received message is discarded and a SPI_FLT bit is flagged in the
Global Status Word (GSW). The SPI_FLT bit is also set in case of parity error detected on
the MOSI frame. Any attempt access to a register with a forbidden access mode (read or
write) is not leading to changes to the internal registers but the SPI_FLT bit is not set in this
case.
The SPI interface consists of several 32-bit registers to allow for configuration, control and
status of the IC as well as special manufacturing test modes. The register definition is
defined by the read register ID (RID) and the write register ID (WID) as shown in Table 6 Global SPI Register Table. Global ID bit (GID) is used to extend available register
addresses, but it is shared between RID and WID; only RID and WID with the same GID
value can be addressed within the same SPI word. The operating states here show in which
states the SPI write command is processed.
36/202
DocID029274 Rev 1
L9678P, L9678P-S
SPI interface
The L9678P checks the validity of the received WID and RID fields in the SPI_MOSI frame.
Should a SPI write command with WID matching a writeable register be received in an
illegal operating state, the command will be discarded and the ERR_WID bit will be flagged
in the next Global Status Word GSW. The ERR_WID flag is not set in case WID is
addressing a read/only register. Should a SPI read command be received containing an
unused RID address, the command will be discarded and the ERR_RID bit will be flagged in
the current GSW.
DocID029274 Rev 1
37/202
201
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
Arming
DocID029274 Rev 1
0
0 0 0 0 0 0 0
$00
R
FLTSR
0
0 0 0 0 0 0 1
$01
R/W
SYS_CFG
Power supply configuration (regulators'
output voltage selection, enable internal
safing engine)
X
0
0 0 0 0 0 1 0
$02
R/W
SYS_CTL
Register to control the power management
(enable for tests in diag state, enable for
power mode control bits)
X
X
X
X
X
0
0 0 0 0 0 1 1
$03
W
SPI_SLEEP
Sleep Mode command
X
X
X
X
X
0
0 0 0 0 1 0 0
$04
R
SYS_STATE
Read register to report in which state the
power control state machine is and also in
which Operating state we are.
0
0 0 0 0 1 0 1
$05
R
POWER_STATE
0
0 0 0 0 1 1 0
$06
R/W
DCR_0
X
X
X
X
0
0 0 0 0 1 1 1
$07
R/W
DCR_1
X
X
X
X
0
0 0 0 1 0 0 0
$08
R/W
DCR_2
X
X
X
X
0
0 0 0 1 0 0 1
$09
R/W
DCR_3
X
X
X
X
0
0 0 0 1 0 1 0
$0A
0
0 0 0 1 0 1 1
$0B
0
0 0 0 1 1 0 0
$0C
0
0 0 0 1 1 0 1
$0D
0
0 0 0 1 1 1 0
$0E
0
0 0 0 1 1 1 1
$0F
0
0 0 1 0 0 0 0
$10
0
0 0 1 0 0 0 1
$11
0
0 0 1 0 0 1 0
$12
R/W
DEPCOM
SPI interface
38/202
Table 6. Global SPI register map
Global fault status register
Power state register (feedback on regulators'
status and voltage thresholds)
Deployment configuration register
X
X
L9678P, L9678P-S
Deployment command register
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
DocID029274 Rev 1
0 0 1 0 0 1 1
$13
R
DSR_0
0
0 0 1 0 1 0 0
$14
R
DSR_1
0
0 0 1 0 1 0 1
$15
R
DSR_2
0
0 0 1 0 1 1 0
$16
R
DSR_3
0
0 0 1 0 1 1 1
$17
0
0 0 1 1 0 0 0
$18
0
0 0 1 1 0 0 1
$19
0
0 0 1 1 0 1 0
$1A
0
0 0 1 1 0 1 1
$1B
0
0 0 1 1 1 0 0
$1C
0
0 0 1 1 1 0 1
$1D
0
0 0 1 1 1 1 0
$1E
0
0 0 1 1 1 1 1
$1F
R
DCMTS01
0
0 1 0 0 0 0 0
$20
R
DCMTS23
0
0 1 0 0 0 0 1
$21
0
0 1 0 0 0 1 0
$22
0
0 1 0 0 0 1 1
$23
0
0 1 0 0 1 0 0
$24
0
0 1 0 0 1 0 1
$25
R/W
SPIDEPEN
0
0 1 0 0 1 1 0
$26
R
LP_GNDLOSS
0
0 1 0 0 1 1 1
$27
R
VERSION_ID
0
0 1 0 1 0 0 0
$28
R/W
WD_RETRY_CONF
Watchdog Retry Configuration
X
0
0 1 0 1 0 0 1
$29
0
0 1 0 1 0 1 0
$2A R/W
WDTCR
Watchdog timer configuration
X
0
0 1 0 1 0 1 1
$2B R/W
WD1T
Watchdog key transmission & Test mode
X
Arming
Deployment status register
Deployment current monitor register
Lock/Unlock command
X
X
Loss of ground fault for squib loops
Device version
X
X
X
X
SPI interface
39/202
0
Diag Ssafing Scrap
L9678P, L9678P-S
Table 6. Global SPI register map (continued)
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
R
WD_STATE
Watchdog state
CLK_CONF
Clock Configuration
Diag Ssafing Scrap
DocID029274 Rev 1
0
0 1 0 1 1 0 0
$2C
0
0 1 0 1 1 0 1
$2D R/W
0
0 1 0 1 1 1 0
$2E
0
0 1 0 1 1 1 1
$2F
0
0 1 1 0 0 0 0
$30
W
SCRAP_STATE
Scrap State command
X
0
0 1 1 0 0 0 1
$31
W
SAFING_STATE
Safing State command
X
0
0 1 1 0 0 1 0
$32
0
0 1 1 0 0 1 1
$33
0
0 1 1 0 1 0 0
$34
0
0 1 1 0 1 0 1
$35
W
WD_TEST
0
0 1 1 0 1 1 0
$36
R/W
SYSDIAGREQ
Diagnostic command for system safing
0
0 1 1 0 1 1 1
$37
R
LPDIAGSTAT
Diagnostic results register for deployment
loops
0
0 1 1 1 0 0 0
$38
R/W
LPDIAGREQ
Diagnostic configuration command for
deployment loops
0
0 1 1 1 0 0 1
$39
R/W
SWCTRL
0
0 1 1 1 0 1 0
$3A R/W
0
0 1 1 1 0 1 1
0
Watchdog first and second level test
Arming
SPI interface
40/202
Table 6. Global SPI register map (continued)
X
X
X
X
X
X
X
X
X
X
DC sensor diagnostic configuration
X
X
X
X
DIAGCTRL_A
In WID is AtoD converter control register A.
In RID is AtoD result A request.
X
X
X
X
$3B R/W
DIAGCTRL_B
In WID is AtoD converter control register B.
In RID is AtoD result B request.
X
X
X
X
0 1 1 1 1 0 0
$3C R/W
DIAGCTRL_C
In WID is AtoD converter control register C.
In RID is AtoD result C request.
X
X
X
X
0
0 1 1 1 1 0 1
$3D R/W
DIAGCTRL_D
In WID is AtoD converter control register D.
In RID is AtoD result D request.
X
X
X
X
0
0 1 1 1 1 1 0
$3E
0
0 1 1 1 1 1 1
$3F
0
1 0 0 0 0 0 0
$40
X
L9678P, L9678P-S
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
0
1 0 0 0 0 0 1
$41
0
1 0 0 0 0 1 0
$42
R/W
GPOCR
0
1 0 0 0 0 1 1
$43
R/W
0
1 0 0 0 1 0 0
$44
0
1 0 0 0 1 0 1
$45
0
1 0 0 0 1 1 0
0
Diag Ssafing Scrap
Arming
DocID029274 Rev 1
X
X
GPOCTRL0
General Purpose Output control register
X
X
X
X
X
R/W
GPOCTRL1
General Purpose Output control register
X
X
X
X
X
$46
R
GPOFLTSR
General Purpose Output fault status register
1 0 0 0 1 1 1
$47
R
ISOFLTSR
ISO9141 fault status register
0
1 0 0 1 0 0 0
$48
0
1 0 0 1 0 0 1
$49
0
1 0 0 1 0 1 0
$4A R/W
RSCR1
0
1 0 0 1 0 1 1
$4B R/W
RSCR2
0
1 0 0 1 1 0 0
$4C
0
1 0 0 1 1 0 1
$4D
0
1 0 0 1 1 1 0
$4E R/W
X
X
X
0
1 0 0 1 1 1 1
$4F
0
1 0 1 0 0 0 0
$50
R
RSDR1
0
1 0 1 0 0 0 1
$51
R
RSDR2
0
1 0 1 0 0 1 0
$52
0
1 0 1 0 0 1 1
$53
0
1 0 1 0 1 0 0
$54
0
1 0 1 0 1 0 1
$55
0
1 0 1 0 1 1 0
$56
0
1 0 1 0 1 1 1
$57
0
1 0 1 1 0 0 0
$58
0
1 0 1 1 0 0 1
$59
RSCTRL
PSI5 configuration register
X
X
Remote sensor control register
X
Remote sensor data and fault flag registers
SPI interface
41/202
General Purpose Output configuration
L9678P, L9678P-S
Table 6. Global SPI register map (continued)
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
DocID029274 Rev 1
0
1 0 1 1 0 1 0
$5A
0
1 0 1 1 0 1 1
$5B
0
1 0 1 1 1 0 0
$5C
0
1 0 1 1 1 0 1
$5D
0
1 0 1 1 1 1 0
$5E
0
1 0 1 1 1 1 1
$5F
0
1 1 0 0 0 0 0
$60
0
1 1 0 0 0 0 1
$61
0
1 1 0 0 0 1 0
$62
0
1 1 0 0 0 1 1
$63
0
1 1 0 0 1 0 0
$64
0
1 1 0 0 1 0 1
$65
0
1 1 0 0 1 1 0
$66
0
1 1 0 0 1 1 1
$67
0
1 1 0 1 0 0 0
$68
0
1 1 0 1 0 0 1
$69
0
1 1 0 1 0 1 0
$6A
0
1 1 0 1 0 1 1
$6B
0
1 1 0 1 1 0 0
$6C
0
1 1 0 1 1 0 1
$6D
0
1 1 0 1 1 1 0
$6E R/W
LOOP_MATRIX_ARM1 Assignment of ARM 1 pin to which LOOPS
X
0
1 1 0 1 1 1 1
$6F
LOOP_MATRIX_ARM2 Assignment of ARM 2 pin to which LOOPS
X
0
1 1 1 0 0 0 0
$70
0
1 1 1 0 0 0 1
$71
R/W
SAF_ALGO_CONF
Safing Algorithm configuration register
R
ARM_STATE
Status of internal arming signals FENH,
FENL, ARMx
X
L9678P, L9678P-S
R/W
Arming
SPI interface
42/202
Table 6. Global SPI register map (continued)
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
DocID029274 Rev 1
1 1 1 0 0 1 0
$72
0
1 1 1 0 0 1 1
$73
R
AEPSTS_ARM1
0
1 1 1 0 1 0 0
$74
R
AEPSTS_ARM2
0
1 1 1 0 1 0 1
$75
0
1 1 1 0 1 1 0
$76
0
1 1 1 0 1 1 1
$77
0
1 1 1 1 0 0 0
$78
0
1 1 1 1 0 0 1
$79
0
1 1 1 1 0 1 0
$7A
0
1 1 1 1 0 1 1
$7B
0
1 1 1 1 1 0 0
$7C
0
1 1 1 1 1 0 1
$7D
0
1 1 1 1 1 1 0
$7E
0
1 1 1 1 1 1 1
$7F
R/W
SAF_ENABLE
1
0 0 0 0 0 0 0
$80
R/W
SAF_REQ_MASK_1
X
1
0 0 0 0 0 0 1
$81
R/W
SAF_REQ_MASK_2
X
1
0 0 0 0 0 1 0
$82
R/W
SAF_REQ_MASK_3
X
1
0 0 0 0 0 1 1
$83
R/W
SAF_REQ_MASK_4
X
1
0 0 0 0 1 0 0
$84
1
0 0 0 0 1 0 1
$85
1
0 0 0 0 1 1 0
$86
1
0 0 0 0 1 1 1
$87
1
0 0 0 1 0 0 0
$88
1
0 0 0 1 0 0 1
$89
1
0 0 0 1 0 1 0
$8A
Arming pulse stretch timer value
Safing record enable
X
X
X
X
Safing record request mask
SPI interface
43/202
0
Arming
L9678P, L9678P-S
Table 6. Global SPI register map (continued)
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
DocID029274 Rev 1
1
0 0 0 1 0 1 1
$8B
1
0 0 0 1 1 0 0
$8C
1
0 0 0 1 1 0 1
$8D
1
0 0 0 1 1 1 0
$8E
1
0 0 0 1 1 1 1
$8F
1
0 0 1 0 0 0 0
$90
1
0 0 1 0 0 0 1
$91
1
0 0 1 0 0 1 0
$92
1
0 0 1 0 0 1 1
$93
R/W
SAF_REQ_TARGET_1
X
1
0 0 1 0 1 0 0
$94
R/W
SAF_REQ_TARGET_2
X
1
0 0 1 0 1 0 1
$95
R/W
SAF_REQ_TARGET_3
X
1
0 0 1 0 1 1 0
$96
R/W
SAF_REQ_TARGET_4
X
1
0 0 1 0 1 1 1
$97
1
0 0 1 1 0 0 0
$98
1
0 0 1 1 0 0 1
$99
1
0 0 1 1 0 1 0
$9A
1
0 0 1 1 0 1 1
$9B
1
0 0 1 1 1 0 0
$9C
1
0 0 1 1 1 0 1
$9D
1
0 0 1 1 1 1 0
$9E
1
0 0 1 1 1 1 1
$9F
1
0 1 0 0 0 0 0
$A0
1
0 1 0 0 0 0 1
$A1
1
0 1 0 0 0 1 0
$A2
1
0 1 0 0 0 1 1
$A3
Arming
SPI interface
44/202
Table 6. Global SPI register map (continued)
Safing record request mask
Safing record request target
L9678P, L9678P-S
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
DocID029274 Rev 1
0 1 0 0 1 0 0
$A4
1
0 1 0 0 1 0 1
$A5
1
0 1 0 0 1 1 0
$A6 R/W
SAF_RESP_MASK_1
X
1
0 1 0 0 1 1 1
$A7 R/W
SAF_RESP_MASK_2
X
1
0 1 0 1 0 0 0
$A8 R/W
SAF_RESP_MASK_3
X
1
0 1 0 1 0 0 1
$A9 R/W
SAF_RESP_MASK_4
X
1
0 1 0 1 0 1 0 $AA
1
0 1 0 1 0 1 1 $AB
1
0 1 0 1 1 0 0 $AC
1
0 1 0 1 1 0 1 $AD
1
0 1 0 1 1 1 0 $AE
1
0 1 0 1 1 1 1
$AF
1
0 1 1 0 0 0 0
$B0
1
0 1 1 0 0 0 1
$B1
1
0 1 1 0 0 1 0
$B2
1
0 1 1 0 0 1 1
$B3
1
0 1 1 0 1 0 0
$B4
1
0 1 1 0 1 0 1
$B5
1
0 1 1 0 1 1 0
$B6
1
0 1 1 0 1 1 1
$B7
1
0 1 1 1 0 0 0
$B8
1
0 1 1 1 0 0 1
$B9 R/W SAF_RESP_TARGET_1
1
0 1 1 1 0 1 0 $BA R/W SAF_RESP_TARGET_2
1
0 1 1 1 0 1 1 $BB R/W SAF_RESP_TARGET_3
1
0 1 1 1 1 0 0 $BC R/W SAF_RESP_TARGET_4
Safing record request target
Safing record response mask
X
Safing record response target
X
X
X
SPI interface
45/202
1
Arming
L9678P, L9678P-S
Table 6. Global SPI register map (continued)
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
DocID029274 Rev 1
1
0 1 1 1 1 0 1 $BD
1
0 1 1 1 1 1 0 $BE
1
0 1 1 1 1 1 1
$BF
1
1 0 0 0 0 0 0
$C0
1
1 0 0 0 0 0 1
$C1
1
1 0 0 0 0 1 0
$C2
1
1 0 0 0 0 1 1
$C3
1
1 0 0 0 1 0 0
$C4
1
1 0 0 0 1 0 1
$C5
1
1 0 0 0 1 1 0
$C6
1
1 0 0 0 1 1 1
$C7
1
1 0 0 1 0 0 0
$C8
1
1 0 0 1 0 0 1
$C9
1
1 0 0 1 0 1 0 $CA
1
1 0 0 1 0 1 1 $CB
1
1 0 0 1 1 0 0 $CC R/W
SAF_DATA_MASK_1
X
1
1 0 0 1 1 0 1 $CD R/W
SAF_DATA_MASK_2
X
1
1 0 0 1 1 1 0 $CE R/W
SAF_DATA_MASK_3
X
1
1 0 0 1 1 1 1 $CF R/W
SAF_DATA_MASK_4
X
1
1 0 1 0 0 0 0
$D0
1
1 0 1 0 0 0 1
$D1
1
1 0 1 0 0 1 0
$D2
1
1 0 1 0 0 1 1
$D3
1
1 0 1 0 1 0 0
$D4
1
1 0 1 0 1 0 1
$D5
Arming
SPI interface
46/202
Table 6. Global SPI register map (continued)
Safing record response target
L9678P, L9678P-S
Safing record data mask
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
DocID029274 Rev 1
1 0 1 0 1 1 0
$D6
1
1 0 1 0 1 1 1
$D7
1
1 0 1 1 0 0 0
$D8
1
1 0 1 1 0 0 1
$D9
1
1 0 1 1 0 1 0 $DA
1
1 0 1 1 0 1 1 $DB
1
1 0 1 1 1 0 0 $DC
1
1 0 1 1 1 0 1 $DD
1
1 0 1 1 1 1 0 $DE
1
1 0 1 1 1 1 1 $DF R/W
SAF_THRESHOLD_1
X
1
1 1 0 0 0 0 0
$E0 R/W
SAF_THRESHOLD_2
X
1
1 1 0 0 0 0 1
$E1 R/W
SAF_THRESHOLD_3
X
1
1 1 0 0 0 1 0
$E2 R/W
SAF_THRESHOLD_4
X
1
1 1 0 0 0 1 1
$E3
1
1 1 0 0 1 0 0
$E4
1
1 1 0 0 1 0 1
$E5
1
1 1 0 0 1 1 0
$E6
1
1 1 0 0 1 1 1
$E7
1
1 1 0 1 0 0 0
$E8
1
1 1 0 1 0 0 1
$E9
1
1 1 0 1 0 1 0 $EA
1
1 1 0 1 0 1 1 $EB
1
1 1 0 1 1 0 0 $EC
1
1 1 0 1 1 0 1 $ED
1
1 1 0 1 1 1 0 $EE
Safing record data mask
Safing record threshold
SPI interface
47/202
1
Arming
L9678P, L9678P-S
Table 6. Global SPI register map (continued)
Operating State(1)
GID
RID / WID
Hex R/W
Name
Description
Init
Diag Ssafing Scrap
DocID029274 Rev 1
1
1 1 0 1 1 1 1
$EF R/W
SAF_CONTROL_1
X
1
1 1 1 0 0 0 0
$F0
R/W
SAF_CONTROL_2
X
1
1 1 1 0 0 0 1
$F1
R/W
SAF_CONTROL_3
X
1
1 1 1 0 0 1 0
$F2
R/W
SAF_CONTROL_4
X
1
1 1 1 0 0 1 1
$F3
1
1 1 1 0 1 0 0
$F4
1
1 1 1 0 1 0 1
$F5
1
1 1 1 0 1 1 0
$F6
1
1 1 1 0 1 1 1
$F7
1
1 1 1 1 0 0 0
$F8
1
1 1 1 1 0 0 1
$F9
1
1 1 1 1 0 1 0
$FA
1
1 1 1 1 0 1 1
$FB
1
1 1 1 1 1 0 0 $FC
1
1 1 1 1 1 0 1 $FD
1
1 1 1 1 1 1 0
$FE
1
1 1 1 1 1 1 1
$FF
Arming
SPI interface
48/202
Table 6. Global SPI register map (continued)
Safing record control
R
SAF_CC
Safing record compare complete
1. A check mark indicates in which operating state a WRITE-command is valid.
L9678P, L9678P-S
L9678P, L9678P-S
5.1
SPI interface
Global SPI register
A summary of all the read/write registers contained within the SPI map are shown below
and are further referenced throughout the specification as they apply. The SPI register
tables also specify the effect of the internal reset signals assertion on each bit field (the
symbol '-' is used to indicate that the register is not affected by the relevant reset signal).
Global status word
L9678P contains an 11-bit word that returns global status information. The GSW is the most
significant 11 bits of SPI_MISO data.
MISO BIT
31
30
29
28
27
26
25
24
23
22
21
MISO
CONVRDY2
CONVRDY1
ERR_WID
ERR_RID
Global Status Word
FLT
GSW
POWERFLT
Description
ERSTATE
Register name
WDTDIS_S
R
RSFLT
-
DEPOK
R/W/RW
SPIFLT
ID
GSW
BIT
10
9
8
7
6
5
4
3
2
1
0
Table 7. Global status word (GSW)
Bit
10
9
Name
SPIFLT
DEPOK
POR WSM SSM
0
0
0
0
Description
0
SPI Fault, set if previous SPI frame had wrong parity check or wrong
number of bits, cleared upon read
0 No fault
1 Fault
0
General Deployment Successful Flag, logical OR of the corresponding
CHxDS bits (bit 15) in DSRx Registers
0 All the DSRx-CHDS bits are 0
1 At least one of the DSRx-CHDS bits is 1
8
RSFLT
0
0
0
Remote Sensor Interface Fault Present, logical OR of the corresponding
FLTBIT bits (bit 15) in RSDRx Registers
0 All the RSDRx-FLTBIT bits are 0
1 At least one of the RSDRx-FLTBIT bits is 1
7
WDTDIS_S
0
0
0
State of WDTDIS pin
0 WDTDIS = 0
1 WDTDIS = 1
DocID029274 Rev 1
49/202
201
SPI interface
L9678P, L9678P-S
Table 7. Global status word (GSW) (continued)
Bit
Name
6
5
ERSTATE
POWERFLT
4
3
2
FLT
CONVRDY2
CONVRDY1
1
0
50/202
ERR_WID
ERR_RID
POR WSM SSM
0
0
1
0
0
0
0
0
0
1
0
0
0
0
Description
0
Set when Power mode state machine is in ER state
0 Power mode state machine is not in ER state
1 Power mode state machine is in ER state
0
Fault present in Power State Register, logical OR between bits from 18 to
9 of POWER_STATE Register
0 All the bits from 18 to 9 in the POWER_STATE Registers are 0s
1 At least one of the bits from 18 to 9 in the POWER_STATE Registers is 1
1
Fault present in Fault Status Register (FLTSR), logical OR between all bits
of FLTSR
0 All the bits in the Fault Status Register (FLTSR) are 0s
1 At least one of the bits in the Fault Status Register (FLTSR) is 1
0
ADC Conversion of request 3 or 4 has been completed so new results are
available
0 No new data available
1 New data available
0
ADC Conversion of request 1 or 2 has been completed so new results are
available
0 No new data available
1 New data available
0
Write address of previous SPI frame is not permitted in current operating
phase (INIT, DIAG, SAFING, SCRAP, ARMING)
0 No Error
1 Error
0
Read address received in the actual SPI frame is unused so data in the
response is don't care
0 No Error
1 Error
DocID029274 Rev 1
L9678P, L9678P-S
SPI interface
Read/write register
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
SSMRST
0
0
-
-
00
Type:
R
Buffer:
$0000
Reset:
-
POR
11
-
Address:
EBST_OT
12
SSM
0
13
CLKFRERR
0
ERBST_OT
MISO
14
WSM
-
15
WSMRST
16
POR
MOSI
17
WD1_WDR
18
WD1_TM
19
WD1_LO
Fault status register (FLTSR)
OTPCRC_ERR
5.1.1
ER Boost over-temperature bit
Set when over-temp condition detected, cleared on SPI read or POR=1
0 No Fault
1 Fault
CLKFRERR
0
-
-
Internal oscillator cross-check error bit
Set when osc error detected, cleared on SPI read or POR=1
0 No Fault
1 Fault
OTPCRC_ERR
0
-
-
OTP CRC error bit
Set when OTP error detected (tested at release of POR), cleared by POR=1
0 No Fault
1 Fault
WD1_LO
0
0
-
WD1 lockout - reflects WD1 lockout state
Set and cleared per Watchdog Timer Flow Diagram
0 WD1 Lockout inactive
1 WD1 Lockout active
WD1_TM
0
0
0
WD1 test mode - reflects WD1TM signal state
Set and cleared per Watchdog Timer Flow Diagram
0 WD1TM=0
1 WD1TM=1
DocID029274 Rev 1
51/202
201
SPI interface
WD1_WDR
L9678P, L9678P-S
0
0
-
WD1 reset latch
Set and cleared per Watchdog Timer Flow Diagram
0 WD1_WDR signal = 0
1 WD1_WDR signal = 1
WSMRST
1
1
-
Watchdog state machine reset
Set when WSM reset goes to '1', cleared upon SPI read
0 WSM reset has not occurred
1 WSM Reset has occurred
SSMRST
1
1
1
Safing state machine reset
Set when SSM reset goes to '1', cleared upon SPI read
0 SSM reset has not occurred
1 SSM Reset has occurred
POR
1
-
-
Power on Reset
Set when POR goes to '1', cleared upon SPI read
0 POR reset has not occurred
1 POR Reset has occurred
52/202
DocID029274 Rev 1
L9678P, L9678P-S
RW
Buffer:
$0100
Reset:
$0002
EN_AUTO_SWITC
H_OFF
SSM
Type:
WSM
01
POR
Address:
0
0
0
-
0
0
-
5
3
2
1
X
X
0
0
0
WD1_TOVR
X
6
WD1_TOVR
X
4
VSF_V
7
VSF_V
8
SAFESEL
9
SAFESEL
0
10
VMEAS
0
11
VMEAS
0
12
SQMEAS
0
13
SQMEAS
MISO
14
V_DIAG
-
15
V_DIAG
16
KEEP_ERBST_ON
MOSI
17
KEEP_ERBST_ON
18
DIS_VDD5_ERR
19
DIS_VDD5_ERR
System configuration register (SYS_CFG)
EN_AUTO_SWITCH_OFF EN_AUTO_SWITCH_OFF
5.1.2
SPI interface
Enable auto switch off ISRC current source and DCS regulator after
measurement completion
0 Auto switch off disabled
1 Auto switch off enabled
DIS_VDD5_ERR
0
0
-
Disable VDD5 OV/UV to generate reset
0 OV/UV generate reset
1 OV/UV don’t generate reset
KEEP_ERBST_ON
0
0
0
ER Boost behaviour during ER state
0 ER Boost is disabled
1 ER Boost stay enabled
HI_LEV_DIAG_TIM
E
0
0
0
Selection of duration of high level squib diagnostics
0 Short time (see high level diag diagram)
1 Long time (see high level diag diagram)
SQMEAS
00
00
00 Sample number in DC sensor, squib measurement and temperature
conversions
Updated by SSM_RESET or SPI write
DocID029274 Rev 1
53/202
201
SPI interface
L9678P, L9678P-S
0
1
10
11
VMEAS
00
00
8 samples
16 samples
4 samples
1 sample
00 Sample number in any other voltage measurement conversions
Updated by SSM_RESET or SPI write
Updated by SSM_RESET or SPI write
0
1
10
11
SAFESEL
1
1
1
4 samples
16 samples
8 samples
1 sample
Safing engine mode select
Updated by SSM_RESET or SPI write
0 Internal safing engine
1 external safing engine
VSF_V
0
0
0
VSF voltage select
Updated by SSM_RESET or SPI write
0 20V
1 25V
WD1_TOVR
0
0
-
Override of initial 500ms time-out of WD1 state machine
Set and cleared per Watchdog Timer Flow Diagram
0 time-out is active
1 time-out is disabled
54/202
DocID029274 Rev 1
L9678P, L9678P-S
RW
Buffer:
$0200
Reset:
$0004
VIN_TH_SEL
0
0
0
8
7
6
5
4
3
2
1
0
X
SPI_OFF
0
9
X
X
X
X
0
SPI_OFF
0
SSM
Type:
-
WSM
02
X
POR
Address:
0
X
10
VSUP_EN
0
X
11
VSUP_EN
0
12
ER_BST_EN
0
13
ER_BST_EN
MISO
14
ER_CUR_EN
-
15
ER_CUR_EN
16
ER_BST_V
MOSI
17
ER_BST_V
18
VBATMON_TH_SEL VBATMON_TH_SEL
19
VIN_TH_SEL
System control register (SYS_CTL)
VIN_TH_SEL
5.1.3
SPI interface
0
0
0
0
VIN comparators threshold selector
0 5.5V
1 7.5V
VBATMON_TH_SEL
00
00
00 VBATMON comparators threshold selector
00
01
10
11
ER_BST_V
0
0
0
6V
6.8V
8V
8.8V
ER Boost voltage select
Updated by SSM_RESET or SPI write
0 set 23V boost
1 set 33V boost
ER_CUR_EN
0
0
0
ER charge / discharge control
Updated by SSM_RESET or SPI write
0 ER current source OFF request
1 ER current source ON request
ER_BST_EN
1
1
1
Boost enable
Updated by SSM_RESET or SPI write
DocID029274 Rev 1
55/202
201
SPI interface
L9678P, L9678P-S
0 ER_BOOST OFF request
1 ER_BOOST ON request
VSUP_EN
0
0
0
Supplemental supply for satellites
Updated by SSM_RESET or SPI write
0 VSUP commanded off
1 VSUP
SPI_OFF
0
0
0
Go to POWER OFF state from POWERMODE SHUTDOWN state
Updated by SSM_RESET or SPI write while in POWERMODE SHUTDOWN
state
0 no effect
1 transition to POWER OFF state
5.1.4
SPI Sleep command register (SPI_SLEEP)
19
18
15
14
13
12
11
10
9
0
0
0
Type:
W
Buffer:
-
Reset:
$0006
POR
03
SLEEP_MODE
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
$3C95
Address:
56/202
16
0
-
SSM
MISO
17
-
WSM
MOSI
0
0
0
0
0
0
0
0
N/A N/A N/A Non-latched command that allows transition into
POWERMODE_SHUTDOWN state according to the Power Control State
Flow Diagram
DocID029274 Rev 1
L9678P, L9678P-S
System status register (SYS_STATE)
MISO
16
-
0
0
0
04
Type:
R
Buffer:
$0400
Reset:
POR
Address:
OPER_CTL_STAT
E[2:0]
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
POWER_CTL_STATE
MOSI
17
OPER_CTL_STATE
18
SSM
19
WSM
5.1.5
SPI interface
000 000 000 Reports Operating Control State
Updated per Power Up Phases diagram
000 = INIT
001 = DIAG
010 = SAFING
011 = SCRAP
100 = ARMING
101 unused
110 unused
111 unused
POWER_CTL_STA
TE[2:0]
000
-
-
Reports Power Control State
Updated per Power Control State Flow Diagram
000 = AWAKE
001 = STARTUP
010 = RUN
011 = ER
100 = POWER MODE SHUTDOWN
101 unused
110 unused
111 unused
DocID029274 Rev 1
57/202
201
SPI interface
R
Buffer:
$0500
Reset:
-
WAKEUP
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VSUP_NOK
ER_BST_ON
ER_CHRG_ON
0
0
ER_SW_ON
VDD5_ACT
VSUP_ACT
VDD3V3_ACT
VSF_ACT
SSM
Type:
12
WSM
05
13
POR
Address:
14
VDD5_OV
VINBAD
NOT_VBGOOD
VBBAD
MISO
15
VDD5_UV
16
WAKEUP
MOSI
17
ER_BST_NOK
18
VDD3V3_OV
19
VDD3V3_UV
Power state register (POWER_STATE)
NOT_VINGOOD
5.1.6
L9678P, L9678P-S
-
-
-
WAKEUP pin status
Set and cleared based on voltage
0 WAKEUP pin < WU_off
1 WAKEUP pin > WU_on
VBBAD
-
-
-
VBATMON bad pin status
Set and cleared based on voltage
1 VBATMON < VBBAD
0 VBATMON > VBBAD
NOT_VBGOOD
-
-
-
VBATMON good pin status
Set and cleared based on voltage
1 VBATMON < VBGOOD
0 VBATMON > VBGOOD
VINBAD
-
-
-
VIN bad pin status
Set and cleared based on voltage
0 VIN > VINBAD
1 VIN < VINBAD
NOT_VINGOOD
-
-
-
VIN good pin status
Set and cleared based on voltage
0 VIN > VINGOOD
1 VIN < VINGOOD
VDD3V3_UV
58/202
-
-
-
VDD3V3 bad pin status
DocID029274 Rev 1
L9678P, L9678P-S
SPI interface
Set based on voltage, cleared on SPI read
0 VDD3V3 > VDD3V3_UV
1 VDD3V3 < VDD3V3_UV
VDD3V3_OV
-
-
-
VDD3V3 bad pin status
Set based on voltage, cleared on SPI read
0 VDD3V3 < VDD3V3_OV
1 VDD3V3 > VDD3V3_OV
ER_BST_NOK
-
-
-
ERBOOST pin status
Set and cleared based on voltage
1 V_ERBOOST < ERBOOST_OK
0 V_ERBOOST > ERBOOST_OK
VDD5_UV
-
-
-
VDD5_UV status
Set based on voltage, cleared on SPI read
0 VDD5 > VDD5_UV
1 VDD5 < VDD5_UV
VDD5_OV
-
-
-
VDD5_OV status
Set based on voltage, cleared on SPI read
0 VDD5 < VDD5_OV
1 VDD5 > VDD5_OV
VSUP_NOK
-
-
-
VSUP status
Set and cleared based on voltage
0 VSUP > VSUP_OK
1 VSUP < VSUP_OK
ER_BST_ON
0
-
-
ERBOOST_ON state
Updated according to ER_BOOST Control Behavior diagram
0 RBOOST_OFF or ERBOOST_OT state or ER_BST_STBY state (boost
not running)
1 ERBOOST_ON state (boost running)
ER_CHRG_ON
0
0
0
ERCHARGE_ON state
Updated according to ER_CHARGE Power Mode Control diagram
0 ERCHARGE_ON = 0
1 ERCHARGE_ON = 1
DocID029274 Rev 1
59/202
201
SPI interface
ER_SW_ON
L9678P, L9678P-S
0
-
-
ER_SWITCH State
Updated according to ER Switch state diagram
0 ER_SWITCH_OFF
1 ER_SWITCH_ON
VDD5_ACT
0
-
-
VDD5 Active state
Updated according to VDD5 Power Mode Control state diagram
0 VDD5 supply in VDD5_OFF or VDD5_SHUTDOWN states
1 VDD5 supply in VDD5_RAMPUP or VDD5_ON states
VSUP_ACT
0
0
0
VSUP Active state
Updated according to VSUP Power Mode Control state diagram
0 VSUP supply in VSUP_OFF or VSUP_SHUTDOWN states
1 VSUP supply in VSUP_RAMPUP or VSUP_ON states
VDD3V3_ACT
0
-
-
VDD3V3 Active state
Updated according to VDD3V3 Power Mode Control state diagram
0 VDD3V3 supply in VDD3V3_OFF or VDD3V3_SHUTDOWN states
1 VDD3V3 supply in VSUP_ON state
VSF_ACT
0
0
0
VSF Active state
Updated according to VSF Control Logic diagram
0 VSF_EN = 0
1 VSF_EN = 1
60/202
DocID029274 Rev 1
L9678P, L9678P-S
5.1.7
SPI interface
Deployment configuration registers (DCR_x)
Channel 0 (DCR_0)
Channel 1 (DCR_1)
Channel 2 (DCR_2)
-
0
0
0
0
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
RW
Buffer:
$0600 (DCR_0)
$0700 (DCR_1)
$0800 (DCR_2)
$0900 (DCR_3)
Reset:
$000C (DCR_0)
$000E (DCR_1)
$0010 (DCR_2)
$0012 (DCR_3)
Deploy_Time[1:0]
SSM
Type:
WSM
06 (DCR_0)
07 (DCR_1)
08 (DCR_2)
09 (DCR_3)
POR
Address:
00
00
00 Default deployment time select
7
6
5
4
3
2
Dep_expire_time Dep_expire_time
MISO
16
Dep_Current
MOSI
17
Dep_Current
18
Deploy_Time
19
Deploy_Time
Channel 3 (DCR_3)
1
0
X
X
0
0
Updated by SSM_RESET or SPI write while in DIAG state
00 Unused (no deploy, 8 us pulse output on ARM1 pin during PULSE TEST)
01 0.5 ms
10 0.7 ms
11 2.0 ms
Dep_Current[1:0]
00
00
00 Deployment Current limit select
Updated by SSM_RESET or SPI write while in DIAG state
00 Unused (no deploy)
DocID029274 Rev 1
61/202
201
SPI interface
L9678P, L9678P-S
01 1.75A min
10 1.2A min
11 Unused (no deploy)
Dep_expire_time[1:
0]
00
00
00 Deploy command expiration timer select
Updated by SSM_RESET or SPI write while in DIAG state
00 500ms
01 250ms
10 125ms
11 0ms
62/202
DocID029274 Rev 1
L9678P, L9678P-S
-
MISO
0
0
0
12
Type:
RW
Buffer:
$1200
Reset:
$0024
POR
Address:
CHxDEPREQ
0
15
14
13
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
CH0DEP CH0DEPREQ
16
WSM
MOSI
17
CH1DEP CH1DEPREQ
18
CH2DEP CH2DEPREQ
19
CH3DEP CH3DEPREQ
Deployment command (DEPCOM)
SSM
5.1.8
SPI interface
N/A N/A N/A Channel x Deploy Request - non-latched channel-specific deploy request
0 No change to deployment control for channel x
1 Clear and start Expiration timer if in ARMING or SAFING state and in
DEPLOY_ENABLED state
CHxDEP
0
0
0
Channel x deployment expiration timer enable
Set when SPI_DEPCOM(CHxDEPREQ=1) AND in ARMING or SAFING state
AND in DEP_ENABLED state
Cleared on SSM_RESET OR when in DEP_DISABLED state OR when
Deploy Expiration Timer x reaches time-out threshold
0 Expiration timer enabled - Deploy command still valid
1 Expiration Timer disabled - Deploy command no more valid
DocID029274 Rev 1
63/202
201
SPI interface
5.1.9
L9678P, L9678P-S
Deployment configuration registers (DSR_x)
Channel 0 (DSR_0)
Channel 1 (DSR_1)
Channel 2 (DSR_2)
-
MISO
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
R
Buffer:
$1300 (DSR_0)
$1400 (DSR_1)
$1500 (DSR_2)
$1600 (DSR_3)
Reset:
-
CHxDS
SSM
Type:
WSM
13 (DSR_0)
14 (DSR_1)
15 (DSR_2)
16 (DSR_3)
POR
Address:
0
0
0
DEP_CHx_ExpTimer
16
DCRxERR
MOSI
17
CHxDD
18
CHxSTAT
19
CHxDS
Channel 3 (DSR_3)
Channel x deployment successful
Updated according to Deployment Driver Control Logic
(set when deployment terminates on ch x due to deploy timer time-out,
cleared on SSM_RESET OR when deployment starts on ch x)
0 Deployment not successful
1 Deployment successful
CHxSTAT
0
0
0
(set when deployment starts on ch x, cleared on SSM_RESET OR when
deployment terminates due to deploy timer time-out, LS Over current OR
GND Loss)
0 Deployment not in progress
1 Deployment in progress
CHxDD
0
0
0
Default Deploy Flag on Channel x
Updated by SSM_RESET, or when the Deployment Configuration Register is
written with an incorrect configuration
64/202
DocID029274 Rev 1
L9678P, L9678P-S
SPI interface
0 Correct Time/Current combination selected
1 Incorrect Time/Current combination selected (default time/current is set)
DCRxERR
0
0
0
Deployment configuration register err
0 Deploy configuration change accepted and stored in memory
1 Deploy configuration change rejected because deploy is in progress
(or DEP_EXPIRE_TIME changed when in DEP_ENABLED state)
DEP_CHx_ExpTimer 0000 0000 0000 Channel x Deployment Expiration Timer value 8ms/count
[5:0] 00 00 00 Updated according to Deployment Driver Control Logic
(Cleared on SSM_RESET OR when Exp Timer times out OR when
SPI_DEPREQx is received while in DEP_ENABLED state AND in ARMING
or SAFING states)
5.1.10
Deployment current monitor status registers (DCMTSxy)
Channels 0, 1 (DCMTS01)
Channels 2, 3 (DCMTS23)
19
18
0
0
MOSI
MISO
17
16
0
0
-
15
14
X
X
11
10
9
8
7
6
X
X
X
X
X
X
X
X
R
Buffer:
$1F00 (DCMTS01)
$2000 (DCMTS23)
Reset:
-
5
4
3
2
1
0
X
X
X
X
X
X
Current_Mon_Timer_x[7:0]
SSM
Type:
WSM
1F (DCMTS01))
20 (DCMTS23)
POR
12
Current_Mon_Timer_y[7:0]
Address:
Current_Mon_Time
r_y[7:0]
13
$00 $00 $00 Channel y current monitor timer value corresponding to SPI command
DCMTSxy.
Set to default (cleared) on SSM_RESET or when a new deployment starts on
channel y. Increments each 16µs while deployment current exceeds monitor
threshold on channel y
Current_Mon_Time
r_x[7:0]
$00 $00 $00 Channel x current monitor timer value corresponding to SPI command
DCMTSxy.
Set to default (cleared) on SSM_RESET or when a new deployment starts on
channel x. Increments each 16µs while deployment current on channel x
exceeds monitor threshold
DocID029274 Rev 1
65/202
201
SPI interface
Deploy enable register (SPIDEPEN)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
10
-
8
7
6
5
4
3
2
1
0
DEPEN_WR[15:0
25
Type:
RW
Buffer:
$2500
Reset:
$004A
DEPEN_STATE[15:0]
POR
WSM
Address:
DEPEN_WR[15:0]
9
SSM
5.1.11
L9678P, L9678P-S
N/A N/A N/A Non-latched encoded value for LOCK / UNLOCK command
$0FF0 LOCK - enter DEP_DISABLED state
$F00F UNLOCK - enter DEP_ENABLED state
DEPEN_STATE[15:
$0FF0$0FF0$0FF0Deploy Enabled State
0]
Updated according to Global SPI Deployment Enable State Diagram
$0FF0 In DEP_DISABLED state
$F00F In DEP_ENABLED state
MISO
17
16
-
0
0
0
R
Buffer:
$2600
Reset:
-
GNDLOSSx
66/202
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
X
WSM
26
14
X
POR
Address:
0
15
GNDLOSS0
18
GNDLOSS1
19
MOSI
GNDLOSS2
Squib ground loss register (LP_GNDLOSS)
GNDLOSS3
5.1.12
0
0
0
Loop x Squib Ground loss
DocID029274 Rev 1
L9678P, L9678P-S
SPI interface
Cleared upon SSM_RESET or SPI read. Set when GND loss is detected
during deployment or loop diag's (HS sw test, LS sw test, squib resistance)
0 Loss of ground not detected
1 Loss of ground detected
5.1.13
Device version register (VERSION_ID)
19
18
MOSI
17
16
-
MISO
0
0
0
0
R
Buffer:
$2700
Reset:
-
DEVICE ID
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
0
SSM
Type:
13
WSM
27
14
POR
Address:
15
-
-
-
DEVICE ID
VERSN
Identification of the device
Static value - never updated
001 Low end
010 Medium end
011 High end
VERSN
-
-
-
Identification of the silicon version
CB version
previous versions
000011
other codes
5.1.14
Watchdog retry configuration register (WD_RETRY_CONF)
19
18
17
16
15
14
13
12
MOSI
MISO
11
10
9
8
7
6
5
4
3
0
0
0
RW
Buffer:
$2800
Reset:
$0050
WD1_RETRY_TH
SSM
Type:
0
WSM
28
0
POR
Address:
0
7
7
-
0
0
0
2
WD1_RETRY_TH
0
0
0
0
0
0
0
0
WD1_RETRY_TH
WD1 retry counter threshold (number of WD errors permitted before latching
WD1_LOCKOUT=1)
DocID029274 Rev 1
67/202
201
SPI interface
Watchdog timer configuration register (WDTCR)
19
18
MOSI
MISO
17
16
-
0
0
14
X
0
0
RW
Buffer:
$2A00
Reset:
$0054
SSM
Type:
WSM
2A
0
POR
Address:
WD1_MODE
15
13
12
WD1_MODE WD1_MODE
5.1.15
L9678P, L9678P-S
0
0
-
11
10
9
8
7
6
5
4
3
2
WDTMIN[6:0]
WDTDELTA[6:0]
WDTMIN[6:0]
WDTDELTA[6:0]
1
0
WD1 Mode
Updated by WSM_RESET or SPI write while in WD1_INIT state
0 Fast WD1 mode - nominal 8µs timer resolution (2ms max value)
1 Slow WD1 mode - nominal 64µs timer resolution (16.3ms max value)
WDTMIN[6:0]
$32 $32
-
WD1 window minimum value - resolution according to WD1_MODE bit ($32 =
400µs in WD1 fast mode)
Updated by WSM_RESET or SPI write while in WD1_INIT state
WDTDELTA[6:0]
$19 $19
-
WD1 window delta value - WDTMAX=WDTMIN+WDTDELTA - resolution
according to WD1_MODE bit ($19 = 200µs in WD1 fast mode)
Updated by WSM_RESET or SPI write while in WD1_INIT state
68/202
DocID029274 Rev 1
L9678P, L9678P-S
5.1.16
WD1 timer control register (WD1T)
19
18
0
0
MOSI
MISO
SPI interface
17
16
0
0
-
W
Buffer:
$2B00
Reset:
$0056
WD1CTL[1:0]
X
X
X
12
11
10
9
8
7
6
5
4
3
2
X
X
X
X
X
X
X
X
X
X
X
WD1CTL[1:0]
0
0
0
0
0
0
WD1CTL[1:0]
WD1_TIMER
SSM
Type:
13
WSM
2B
14
POR
Address:
15
00
00
00 WD1 Control command
1
0
Updated by SSM_RESET or SPI write
00 NOP
01 Code 'A'
10 Code 'B'
11 NOP
WD1_TIMER
$00 $00 $00 WD1 Window timer value
Cleared by SSM_RESET or by WD1 refresh, incremented every 8µs or 64µs
while in WD1_RUN or WD1_TEST states
WD1 state register (WDSTATE)
18
MOSI
MISO
17
16
0
0
0
0
2C
Type:
R
Buffer:
$2C00
Reset:
POR
Address:
WD1_ERR_CNT[3:0] 000 000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
WD1_ERR_CNT[3:0]
WD_STATE[2:0]
SSM
19
WSM
5.1.17
-
Watchdog error counter
Updated according to Watchdog State Diagram
WD1_STATE[2:0] 000 000
-
Watchdog state
Updated according to Watchdog State Diagram
000 INITIAL
DocID029274 Rev 1
69/202
201
SPI interface
L9678P, L9678P-S
001 RUN
010 TEST
011 RESET
100 OVERRIDE
MISO
16
-
0
0
0
0
RW
Buffer:
$2D00
Reset:
$005A
AUX_SS_DIS
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
2D
14
POR
Address:
15
1
-
-
Auxiliary 3.75MHz oscillator Spread Spectrum disable
Updated by POR or SPI write while in INIT state
0 Spread Spectrum enabled
1 Spread Spectrum disabled
MAIN_SS_DIS
0
-
-
Main 16MHz oscillator Spread Spectrum disable
Updated by POR or SPI write while in INIT state
0 Spread Spectrum enabled
1 Spread Spectrum disabled
ERBST_F_SEL[1:0] 00
-
-
ER Boost switching frequency select
Updated by POR or SPI write while in INIT state
00 1.88 MHz
01 2.13 MHz
10 2.00 MHz
11 2.00 MHz
70/202
DocID029274 Rev 1
3
2
1
0
ERBST_F_SEL ERBST_F_SEL[1:0]
MOSI
17
MAIN_SS_DIS
18
MAIN_SS_DIS
19
AUX_SS_DIS
Clock configuration register (CLK_CONF)
AUX_SS_DIS
5.1.18
L9678P, L9678P-S
Scrap state entry command register (SCRAP_STATE)
19
18
0
0
MOSI
MISO
17
16
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
-
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
$3535
30
Type:
W
Buffer:
-
Reset:
$0060
POR
WSM
Address:
SSM
5.1.19
SPI interface
N/A N/A N/A
Non-latched Scrap State entry command
Enter Scrap state from DIAG state
Safing state entry command register (SAFING_STATE)
19
18
MISO
16
15
14
13
12
11
10
9
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
$ACAC
0
31
Type:
W
Buffer:
-
Reset:
$0062
POR
Address:
0
0
0
0
0
0
0
0
0
0
SSM
MOSI
17
WSM
5.1.20
N/A N/A N/A
Non-latched Safing State entry command
Enter safing state from DIAG state and clear arming pulse stretch counter (if
received in DIAG or SAFING state)
DocID029274 Rev 1
71/202
201
SPI interface
5.1.21
L9678P, L9678P-S
WD1 test command register (WD1_TEST)
19
18
0
0
16
15
14
13
12
0
0
0
0
0
0
-
MISO
11
10
9
8
0
0
0
0
$3C
35
Type:
W
Buffer:
-
Reset:
$006A
POR
WSM
Address:
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
SSM
MOSI
17
N/A N/A N/A
Non-latched WD1 Test Command
WD1_TEST SPI command as described in Figure 36: Watchdog state
diagram.
System diagnostic register (SYSDIAGREQ)
19
18
16
-
MISO
0
0
0
0
36
Type:
RW
Buffer:
$3601
Reset:
$006C
POR
Address:
WSM
MOSI
17
15
14
13
12
11
10
9
8
7
6
5
4
3
X
X
X
X
X
X
X
X
X
X
X
X
DSTEST[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
DSTEST[3:0]
SSM
5.1.22
DSTEST[3:0] 0000 0000 0000 Diagnostic State Test selection
Updated by SSM_RESET or SPI write while in DIAG state
0000 = all outputs inactive
0001 = ARM pin active
0010 = all outputs inactive
0011 = all outputs inactive
0100 = all outputs inactive
0101 = all outputs inactive
0110 = VSF regulator active
72/202
DocID029274 Rev 1
2
1
0
L9678P, L9678P-S
SPI interface
0111 = HS squib driver FET active
1000 = LS squib driver FET active
1001 = Output deployment timing pulses on ARM1 (separated by 8 ms)
1010 = ST reserved
1011 - 1111 = all outputs inactive
DocID029274 Rev 1
73/202
201
SPI interface
R
Buffer:
$3700
Reset:
-
DIAG_LEVEL
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STB
SQP
0
0
0 Diagnostic mode selector
Not present for low level diagnostic
Updated by SSM_RESET or SPI write to LPDIAGREQ
0 low level mode
1 high level mode
TIP
0
0
0 High level diagnostic test is running
Updated by SSM_RESET or Loops diagnostic state machine
0 High level
diagnostic
test is not running
1 High level
diagnostic
test is running
FP
0
0
0 Fault present before requested diagnostic
Updated by SSM_RESET
or Loops diagnostic state
machine
0 Fault not present
before requested
diagnostic
1 Fault present before
requested
diagnostic
FETON
74/202
0
0
0 FET activation during diagnostic
DocID029274 Rev 1
LEAK_CHSEL
10
SSM
Type:
11
WSM
37
12
POR
Address:
13
STG
FP
14
SBL
0
15
RES_MEAS_CHSEL/
HIGH_LEV_DIAG_SELECTED
TIP
MISO
16
-
DIAG_LEVEL
MOSI
17
HSR_LO
18
HSR_HI
19
ST_reserved
Diagnostic result register for deployment loops (LPDIAGSTAT)
FETON
5.1.23
L9678P, L9678P-S
L9678P, L9678P-S
SPI interface
Updated by SSM_RESET or Loops diagnostic state machine or when HS or
LS FET is activated during DIAG state
0 FET is off during
diagnostic
1 FET is on during
diagnostic
ST_reserved
0
0
0 ST_reserved
HSR_HI
0
0
0
HSR Diagnostic - HIGH Range
Updated by SSM_RESET or Loops diagnostic state machine or when squib
resistance test is run
0 HSR measurement
< HSR HIGH value
1 HSR measurement
> HSR HIGH value
HSR_LO
0
0
0 HSR Diagnostic - Low Range
Updated by SSM_RESET or Loops diagnostic state machine or when squib
resistance test is run
1 HSR measurement< HSR LOW value
0 HSR measurement > HSR LOW value
RES_MEAS_CHSEL 0000 0000 0000 Channel selected for resistance measurement
[3:0]
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib resistance channel selected
0000 = Ch 0
0001 = Ch 1
0010 = Ch 2
0011 = Ch 3
0100 - 1111 None Selected
HIGH_LEV_DIAG_ 0000 0000 0000
SELECTED[3:0]
0000 No diagnostic selected
0001 VRCM CHECK
0010 Leakage CHECK
0011 Short Between Loops CHECK
0100 Unused
0101Squib resistance range CHECK
0110 Squib resistance measurement
0111 FET test
1000 - 1111 Unused
DocID029274 Rev 1
75/202
201
SPI interface
L9678P, L9678P-S
SBL
0
0
0 Short between loop state
Updated by SSM_RESET or Loops diagnostic state machine
0 Short between squib loops is not present
1 Short between squib loops is present
STG
0
0
0 Short to Ground Test Status
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib leakage diagnostic
0 STG not detected
1 1 STG detected
STB
0
0
0 Short to Battery Test Status
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib leakage diagnostic
0 STB not detected
1 STB detected
SQP
0
0
0 Squib PIN where leakage test has been performed
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib leakage diagnostic
0 SRx
1 SFx
LEAK_CHSEL[3:0] 0000 0000 0000 Channel selected for leakage measurement
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib leakage diagnostic
0000 = Ch 0
0001 = Ch 1
0010 = Ch 2
0011 = Ch 3
0100 - 1111 None Selected
76/202
DocID029274 Rev 1
L9678P, L9678P-S
Loops diagnostic configuration command register for low level
diagnostic (LPDIAGREQ)
RW
Buffer:
$3800
Reset:
$0070
DIAG_LEVEL
SSM
Type:
WSM
38
POR
Address:
0
0
0
5
4
3
2
1
0
LEAK_CHSEL[3:0]
6
LEAK_CHSEL[3:0]
7
RES_MEAS_CHSEL[3:0]RES_MEAS_CHSEL[3:0]
8
VRCM[1:0]
9
VRCM[1:0]
10
ISINK
0
11
ISINK
0
12
ISRC [1:0]
0
13
ISRC [1:0]
0
-
MISO
14
PD_CURR
15
PD_CURR
16
ISRC_CURR_SEL
MOSI
17
ISRC_CURR_SEL
18
DIAG_LEVEL
19
DIAG_LEVEL
5.1.24
SPI interface
Diagnostic mode selector
Updated by SSM_RESET or SPI write
0 low level mode
1 N/A - see description below
ISRC_CURR_SEL
0
0
0
Selection of ISRC current value
0 40mA
1 8mA
PD_CURR
0
0
0
Pull down current control
Updated by SSM_RESET or SPI write
0 Request OFF only for channels connected to VRCM or ISINK or ISRC,
ON for all other channels
1 Request OFF for all channels
ISRC [1:0]
00
00
00 High side current source for channel selected in RES_MEAS_CHSEL[3:0]
Updated by SSM_RESET or SPI write
00 = OFF
01 = ON 40 mA current for channel selected in RES_MEAS_CHSEL, 
OFF on all other channels
DocID029274 Rev 1
77/202
201
SPI interface
L9678P, L9678P-S
10 = ON bypass current for channel selected in RES_MEAS_CHSEL, 
OFF ON all other channels
11 = OFF
ISINK
0
0
0
Low Side current sink control (max 50mA)
Updated by SSM_RESET or SPI write
0 All channels OFF
1 ON for channel selected by RES_MEAS_CHSEL[3:0], OFF on all other
channels
VRCM[1:0]
00
00
00 Voltage Regulator Current Monitor control
Updated by SSM_RESET or SPI write
00 VRCM not connected
01 VRCM connected to SFx of channel selected by LEAK_CHSEL[3:0]
01 VRCM connected to SFx of channel selected by LEAK_CHSEL[3:0]
and pull down current of the same channel disabled
10 VRCM connected to SRx of channel selected by LEAK_CHSEL[3:0]
and pull down current of the same channel enabled (ISINK and ISRC
must be switched
RES_MEAS_CHS 0000 0000 0000 Squib Resistance Measurement Channel select - selects the channel and
EL[3:0]
muxes for the resistance test, and the channel for HS driver test (full path fet
test) activation
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
LEAK_CHSEL[3:0] 0000 0000 0000 Squib Leakage Measurement Channel select - selects the channel and
muxes for the leakage test, and the channel for HS/LS FET test activation.
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
78/202
DocID029274 Rev 1
L9678P, L9678P-S
-
0
0
0
RW
Buffer:
$3800
Reset:
$0070
DIAG_LEVEL
12
11
10
9
8
X
X
X
X
X
X
X
0
0
0
0
0
0
0
SSM
Type:
13
WSM
38
14
POR
Address:
0
15
0
0
0
7
6
5
4
3
2
1
0
LOOP_DIAG_CHSEL[3:0] LOOP_DIAG_CHSEL[3:0]
MISO
16
SQP
MOSI
17
SQP
18
HIGH_LEVEL_DIAG_SEL HIGH_LEVEL_DIAG_SEL
19
DIAG_LEVEL
Loops diagnostic configuration command register for high level
diagnostic (LPDIAGREQ)
DIAG_LEVEL
5.1.25
SPI interface
Diagnostic mode selector
0 0 N/A - see description above
1 1 high level mode
HIGH_LEVEL_DIAG 000 000 000
Selection of high level squib diagnostic
_SEL
Updated by SSM_RESET or SPI write
000 No diagnostic selected
001 VRCM CHECK
010 Leakage CHECK
011 Short Between Loops CHECK
100 Unused
101 Squib resistance range CHECK
110 Squib resistance measurement
111 FET test
SQP
0
0
0
Squib pin select for all leakage diagnostic
Updated by SSM_RESET or SPI write
DocID029274 Rev 1
79/202
201
SPI interface
L9678P, L9678P-S
0 SRx
1 SFx
LOOP_DIAG_CHSE 0000 0000 0000 Channel select - selects the channel and muxes for all squib diagnostic.
L[3:0]
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
80/202
DocID029274 Rev 1
L9678P, L9678P-S
16
-
MISO
0
0
0
RW
Buffer:
$3900
Reset:
$0072
DCS_PDCURR
12
11
10
9
8
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
39
14
POR
Address:
0
15
0
0
0
7
6
5
4
X
X
CHID[3:0]
MOSI
17
0
0
CHID[3:0]
18
SWOEN
19
SWOEN
DC sensor diagnostic configuration command register (SWCTRL)
DCS_PDCURR DCS_PDCURR
5.1.26
SPI interface
3
2
1
0
Disable of all pull down current for DC sensor
Updated by SSM_RESET or SPI write
0 OFF for channel under voltage or current measurement, ON for all other
channels
1 OFF for all channels
SWOEN
0
0
0
Switch Output Enable
Updated by SSM_RESET or SPI write
0 OFF
1 ON (40mA)
CHID[3:0] 0000 0000 0000 Channel ID - selects DC sensor channel for output activation
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
DocID029274 Rev 1
81/202
201
SPI interface
5.1.27
L9678P, L9678P-S
ADC request and data registers (DIAGCTRL_x)
ADC A control command (DIAGCTRL_A)
19
18
MISO
17
16
NEWDATA_A
MOSI
0
15
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
0
6
3A
Type:
RW
Buffer:
$3A00
Reset:
$0074
4
3
2
1
0
1
0
1
0
ADCREQ_A[6:0]
ADCREQ_A[6:0]
Address:
5
ADCRES_A[9:0]
ADC B control command (DIAGCTRL_B)
19
18
MISO
16
NEWDATA_B
MOSI
17
0
15
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
0
6
3B
Type:
RW
Buffer:
$3B00
Reset:
$0076
4
3
2
ADCREQ_B[6:0]
ADCREQ_B[6:0]
Address:
5
ADCRES_B[9:0]
ADC C control command (DIAGCTRL_C)
19
18
MISO
17
16
NEWDATA_C
MOSI
0
0
Address:
3C
Type:
RW
Buffer:
$3C00
Reset:
$0078
82/202
15
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
ADCREQ_C[6:0]
DocID029274 Rev 1
6
5
4
3
2
ADCREQ_C[6:0]
ADCRES_C[9:0]
L9678P, L9678P-S
SPI interface
ADC D control command (DIAGCTRL_D)
19
18
MISO
17
16
NEWDATA_D
MOSI
0
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
0
RW
Buffer:
$3D00
Reset:
$007A
SSM
Type:
WSM
3D
6
ADCREQ_D[6:0]
POR
Address:
NEWDATA_x
15
0
0
0
5
4
3
2
1
0
ADCREQ_D[6:0]
ADCRES_D[9:0]
New data available from convertion
Updated by SSM_RESET or ADC state machine
0 cleared on read
1 convertion finished
ADCREQ_x[6:0]
$00 $00 $00 ADC Request select command
Updated by SSM_RESET or SPI write to DIAGCTRL_x
Measurement
$00 Unused
$01 Ground Ref
$02 Full scale Ref
$030 DCSx voltage
$04 DCSx current
$05 DCSx resistance
$06 Squib x resistance
$07 Internal BG reference voltage (BGR)
$080 Internal BG monitor voltage (BGM)
$09 Unused
$0A Temperature
$0B DCS 0 voltage
$0C DCS 1 voltage
$0D DCS 2 voltage
$0E DCS 3 voltage
$20 VBATMON pin voltage
$21 VIN pin voltage
$22 Internal analog supply voltage (VINT)
$23 Internal digital supply voltage (VDD)
DocID029274 Rev 1
83/202
201
SPI interface
L9678P, L9678P-S
$24 ERBOOST pin voltage
$25 Unused
$26 VER pin voltage
$27 VSUP voltage
$28 VDDQ voltage
$29 WAKEUP pin voltage
$2A VSF pin voltage
$2B WDTDIS pin voltage
$2C GPOD0 pin voltage
$2D GPOS0 pin voltage
$2E GPOD1 pin voltage
$2F GPOS1 pin voltage
$30 Unused
$31 Unused
$32 RSU0 pin Voltage
$33 RSU1 pin Voltage
$34 Unused
$35 Unused
$36 SS0 pin voltage
$37 SS1 pin voltage
$38 SS2 pin voltage
$39 SS3 pin voltage
$3A Unused
$3B Unused
$3C Unused
$3D Unused
$3E Unused
$3F Unused
$40 Unused
$41 Unused
$42 VRESDIAG voltage
$43 VDD5 voltage
$44 VDD3V3 voltage
$45 ISOK voltage
$46 SF0
$47 SF1
$48 SF2
$49 SF3
$4A - $7F Unused
ADCRES_x[9:0] $000 $000 $000 10-bit ADC result value corresponding to ADCREQ_x request
Updated by SSM_RESET or ADC state machine
84/202
DocID029274 Rev 1
L9678P, L9678P-S
GPO configuration register (GPOCR)
18
MOSI
MISO
17
16
-
0
0
0
RW
Buffer:
$4200
Reset:
$0084
GPOxLS
12
11
10
9
8
7
6
5
4
3
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
42
14
POR
Address:
0
15
0
0
0
1
0
GPO0LSGPO0LS
19
GPO1LSGPO1LS
5.1.28
SPI interface
GPO driver configuration bit
Updated by SSM_RESET or SPI write
0 High-side Driver configuration for GPOx (ER_BOOST_OK is required to
enable GPO as HS)
1 Low-side Driver configuration for GPOx (ER_BOOST_OK is not
required to enable GPO as LS)
DocID029274 Rev 1
85/202
201
SPI interface
5.1.29
L9678P, L9678P-S
GPO configuration register (GPOCTRLx)
Channel 0 (GPOCTRL0)
Channel 1 (GPOCTRL1)
19
18
MOSI
17
16
-
MISO
0
0
0
0
15
14
13
12
11
10
9
8
7
6
X
X
X
X
X
X
X
X
X
X
GPOxPWM[5:0]
0
0
0
0
0
0
0
0
0
0
GPOxPWM[5:0]
Address:
43 (GPOCTRL0)
44 (GPOCTRL1)
Type:
RW
Buffer:
$4300 (GPOCTRL0)
$4400 (GPOCTRL1)
Reset:
$0086 (GPOCTRL0)
$0088 (GPOCTRL1)
POR
GPOxPWM
WSM
5
3
2
SSM
000000 000000 000000 6 bit value for PWM% with scaling of 1.6% per count
Updated by SSM_RESET or SPI write
86/202
4
DocID029274 Rev 1
1
0
L9678P, L9678P-S
R
Buffer:
$4600
Reset:
-
GPO1DISABLE
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
GPO0OPN
0
0
SSM
Type:
12
WSM
46
13
POR
Address:
0
14
GPO0LIM
0
GPO0DISABLE
MISO
15
GPO0TEMP
16
GPO1DISABLE
MOSI
17
GPO1OPN
18
GPO1LIM
19
GPO1TEMP
GPO fault status register (GPOFLTSR)
GPO_NOT_CONF
5.1.30
SPI interface
1
1
1
GPO 1 disable state
0 GPO enable to work
1 GPO disabled due to thermal fault or configuration not received or
ERBOOST not OK (only HS mode)
GPO0DISABLE
1
1
1
GPO 0 disable state
0 GPO enable to work
1 GPO disabled due to thermal fault or configuration not received or
ERBOOST not OK (only HS mode)
GPO_NOT_CONF
1
1
1
GPO configuration status
0 GPO HS/LS configured (activation is permitted)
1 GPO not yet configured (activation is denied)
GPO1TEMP
0
0
0
GPO 1 Thermal Fault
Cleared by SSM_RESET or SPI read, set by detection circuit
0 Fault not detected
1 Fault detected
GPO1LIM
0
0
0
GPO 1 Current Limit Flag
Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
1 Fault detected
GPO1OPN
0
0
0
GPO 1 Open Detection
Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
DocID029274 Rev 1
87/202
201
SPI interface
L9678P, L9678P-S
1 Fault detected
GPO0TEMP
0
0
0
GPO 0 Thermal Fault
Cleared by SSM_RESET or SPI read, set by detection circuit
0 Fault not detected
1 Fault detected
GPO0LIM
0
0
0
GPO 0 Current Limit Flag
OK Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
1 Fault detected
GPO0OPN
0
0
0
GPO 0 Open Detection
OK Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
1 Fault detected
19
18
MOSI
17
16
-
MISO
0
0
0
R
Buffer:
$4700
Reset:
-
ISOTEMP
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
X
WSM
47
14
X
POR
Address:
0
15
ISOLIM
ISO fault status register (ISOFLTSR)
ISOTEMP
5.1.31
0
0
0
ISO Thermal Fault
Cleared by SSM_RESET or SPI read, set by detection circuit
0 Fault not detected
1 Fault detected
ISOLIM
0
0
0
ISO Current Limit Flag
Cleared by SSM_RESET or SPI read, set by detection circuit while ON (ISOK=0)
0 Fault not detected
1 Fault detected
88/202
DocID029274 Rev 1
L9678P, L9678P-S
5.1.32
SPI interface
Remote sensor configuration register (RSCRx)
Remote sensor configuration register 1 (RSCR1)
0
0
0
0
X
0
RW
Buffer:
$4A00 (RSCR1)
$4B00 (RSCR2)
Reset:
$0094 (RSCR1)
$0096 (RSCR2)
SLOWTRACK
SSM
Type:
WSM
4A (RSCR1)
4B (RSCR2)
POR
Address:
0
0
0
13
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
STSx[3:0]
MISO
14
0
0
0
0
0
0
0
0
STSx[3:0]
-
15
BLKTxSEL
16
BLKTxSEL
MOSI
17
STARTbitsMEAS_DISABLE STARTbitsMEAS_DISABLE
18
SLOWTRACK
19
SLOWTRACK
Remote sensor configuration register 2 (RSCR2)
3
2
1
0
Reduce frequency of base current tracking
0 8µs/1µs
1 16µs/2µs
STARTbitsMEAS_
DISABLE
0
0
0
Disable of start bits period measure to decode data bits
0 Period of start bits used to decode following data bits
1 Period of start bits not used to decode following data bits
BLKTxSEL
0
0
0
Current limiting blanking time select for channel x
Updated by SSM_RESET or SPI write
0 Blanking time = 5ms
1 Blanking time = 10ms
DocID029274 Rev 1
89/202
201
L9678P, L9678P-S
SSM
POR
WSM
SPI interface
STSx[3:0] 0000 0000 0000 Remote sensor type select
Updated by SSM_RESET or SPI write
0000 Async PSI5, parity, 8-bit, 125k (A8P-228/1L)
0001 Async PSI5, parity, 8-bit, 189k (A8P-228/1H)
0010 Async PSI5, parity, 10-bit, 125k (A10P-228/1L)
0011 Async PSI5, parity, 10-bit, 189k (A10P-228/1H)
0100-1111 Async PSI5, parity, 10-bit, 189k (A10P-228/1H)
Remote sensor control register (RSCTRL)
18
MOSI
MISO
17
16
0
0
0
0
R/W
Buffer:
$4E00
Reset:
$009C
CHxEN
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
4E
14
POR
Address:
15
0
0
0
Channel x Output enable
Updated by SSM_RESET or SPI write
0 Off
1 On
90/202
DocID029274 Rev 1
3
2
X
0
1
CH0EN CH0EN
19
CH1EN CH1EN
5.1.33
0
X
0
L9678P, L9678P-S
5.1.34
SPI interface
Remote sensor data/fault registers w/o fault (RSDRx)
Remote sensor 0 data and fault flag register (RSDR0)
Remote sensor 1 data and fault flag register (RSDR1)
Note:
The value in Bit15 (FLT) will re-define the use of the other bits, hence the information below
is divided into two groups.
Bit 15 = 0 NO FAULT condition
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R
Buffer:
$5000 (RSDR0)
$5100 (RSDR1)
Reset:
SSM
Type:
WSM
50 (RSDR0)
51 (RSDR1)
POR
Address:
DATA [9:0]
0
15
LCID [3:0]
MISO
16
CRC
MOSI
17
On/Off
18
FLT=0
19
CRC[2:0] 000 000 000 CRC based on bits [16:0]
Updated based on bits [16:0]
FLT
1
1
1
Fault Status - Depending on Fault Status, the DATA bits are defined differently
Cleared when all of the following bits are '0': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
Set when any of the following bits are '1': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
0 No fault
1 Fault
On/Off
0
0
0
Channel On/Off Status
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL or when the STG bit is set or the RSTEMP bit is set
Set when channel is commanded ON by SPI RSCTRL
0 Off
1 On
LCID[0:3] 0000 0000 0000 Logical Channel ID
DocID029274 Rev 1
91/202
201
SPI interface
L9678P, L9678P-S
Updated based on SPI read request
0000 RSU0
0100 RSU1
DATA[9:0] $000 $000 $000 10-bit data from Manchester decoder
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL
updated when a valid PSI5 frame is received
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STB
CURRENT_HI
OPENDET
RSTEMP
INVALID
NODATA
X
15
STG
MISO
16
-
CRC
MOSI
17
0
X
X
R
Buffer:
$5000 (RSDR0)
$5100 (RSDR1)
Reset:
SSM
Type:
WSM
50 (RSDR0)
51 (RSDR1)
POR
Address:
LCID [3:0]
18
On/Off
19
FLT=1
Bit 15 = 1 FAULTED condition
CRC[2:0] 000 000 000 CRC based on bits [16:0]
Updated based on bits [16:0]
FLT
1
1
1
Fault Status - Depending on Fault Status, the DATA bits are defined differently
Cleared when all of the following bits are '0': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
Set when any of the following bits are '1': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
0 No fault
1 Fault
On/Off
0
0
0
Channel On/Off Status
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL or when the STG bit is set or the RSTEMP bit is set
Set when channel is commanded ON by SPI RSCTRL
0 Off
92/202
DocID029274 Rev 1
L9678P, L9678P-S
SPI interface
1 On
LCID[0:3] 0000 0000 0000 Logical Channel ID
Updated based on SPI read request
0000 RSU0
0100 RSU1
STG
0
0
0
Short to Ground (in current limit condition)
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL
0 No fault
1 Fault
STB
0
0
0
Short to Battery
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL - not cleared by channel OFF caused by STG or RSTEMP
Set when channel voltage exceeds VSUP for a time greater than TSTBTH
0 No fault
1 Fault
CURRENT_HI
0
0
0
Current High
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL
Set when channel current exceeds ILKGG for a time determined by an
up/down counter
0 No fault
1 Fault
OPENDET
0
0
0
Open Sensor Detected
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL
Set when channel current exceeds ILKGB for a time determined by an
up/down counter
0 No fault
1 Fault
RSTEMP
0
0
0
Over temperature detected
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL
Set when over-temp condition is detected
0 No fault
1 Fault
DocID029274 Rev 1
93/202
201
SPI interface
INVALID
L9678P, L9678P-S
0
0
0
Invalid Data
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL or if one of the following is set: STG, STB, CURRENT_HI,
OPEN_DET, RSTEMP
Set when two valid start bits are received and a Manchester error (# of bits,
bit timing) or parity error is detected
0 No fault
1 Fault
NODATA
1
1
1
No Data in buffer
Cleared when a valid PSI frame is received or if one of the following is set:
STG, STB, CURRENT_HI, OPEN_DET, RSTEMP
Set upon SPI read of RSDRx if FIFO empty and none of the following bits are
set: STG, STB, CURRENT_HI, OPEN_DET, RSTEMP
0 No fault
1 Fault
94/202
DocID029274 Rev 1
L9678P, L9678P-S
Safing algorithm configuration register (SAF_ALGO_CONF)
-
MISO
0
0
0
0
R/W
Buffer:
$6600
Reset:
$00CC
NO_DATA
SSM
Type:
WSM
66
14
POR
Address:
15
0
0
0
X
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADD_VAL ADD_VAL
16
SUB_VAL SUB_VAL
MOSI
17
ARMP_TH ARMP_TH
18
ARMN_TH ARMN_TH
19
NO_DATA NO_DATA
5.1.35
SPI interface
Event counter no data select
Updated by SSM_RESET or SPI write while in DIAG state
0 Event counter reset to 0 if CC=0 when SPI read of SAF_CC bit is
performed (end of sample cycle)
1 Event counter decremented by SUB_VAL if CC=0 when SPI read of
SAF_CC bit is performed (end of sample cycle)
ARMN_TH 0011 0011 0011 Negative event counter threshold to assert arming
Updated by SSM_RESET or SPI write while in DIAG state
0000 Negative event counter disabled
ARMP_TH 0011 0011 0011 Positive event counter threshold to assert arming
Updated by SSM_RESET or SPI write while in DIAG state
0000 Positive event counter disabled
SUB_VAL
011 011 011 Decremental step size of the event counter
Updated by SSM_RESET or SPI write while in DIAG state
ADD_VAL
001 001 001 Incremental step size of the event counter
Updated by SSM_RESET or SPI write while in DIAG state
DocID029274 Rev 1
95/202
201
SPI interface
-
MISO
0
0
0
0
R
Buffer:
$6A00
Reset:
-
ACL_VALID
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
6A
14
POR
Address:
15
FENH
16
FENL
MOSI
17
ARMINT_1
18
ARMINT_2
19
ACL_VALID
Arming signals register (ARM_STATE)
ACL_PIN_STATE
5.1.36
L9678P, L9678P-S
0
0
0
Valid ACL detection
0 Cleared when ACL_BAD=2
1 Set when ACL_GOOD=3
ACL_PIN_STATE
-
-
-
Echo of ACL pin
ARMINT_x
0
0
0
State of armint signals
Updated per Safing Engine output logic diagram
FENH/FENL
-
-
-
State of external arming control signals
Updated based on pin state
96/202
DocID029274 Rev 1
L9678P, L9678P-S
5.1.37
SPI interface
ARMx assignment registers (LOOP_MATRIX_ARMx)
Assignment of ARM1 to specific loops (LOOP_MATRIX_ARM1)
16
-
MISO
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
RW
Buffer:
$6E00 (LOOP_MATRIX_ARM1)
$6F00 (LOOP_MATRIX_ARM2)
Reset:
$00DC (LOOP_MATRIX_ARM1)
$00DE (LOOP_MATRIX_ARM2)
ARMx_Ly
SSM
Type:
WSM
6E (LOOP_MATRIX_ARM1)
6F (LOOP_MATRIX_ARM2)
POR
Address:
0
0
0
3
2
1
0
ARMx_L0 ARMx_L0
MOSI
17
ARMx_L1 ARMx_L1
18
ARMx_L2 ARMx_L2
19
ARMx_L3 ARMx_L3
Assignment of ARM2 to specific loops (LOOP_MATRIX_ARM2)
Configures ARMx for Loop_y
Updated by SSM_RESET or SPI write while in DIAG state
0 ARMx signal is not associated with Loopy
1 ARMx signal is associated with Loopy
DocID029274 Rev 1
97/202
201
SPI interface
5.1.38
L9678P, L9678P-S
ARMx pulse stretch registers (AEPSTS_ARMx)
ARM1 enable pulse stretch timer status (AEPSTS_ARM1)
ARM2 enable pulse stretch timer status (AEPSTS_ARM2)
19
18
MOSI
MISO
17
16
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
RW
Buffer:
$7300 (AEPSTS_ARM1)
$7400 (AEPSTS_ARM2)
Reset:
- (AEPSTS_ARM1)
- (AEPSTS_ARM2)
SSM
Type:
WSM
73 (AEPSTS_ARM1)
74 (AEPSTS_ARM2)
POR
Address:
Timer Count[9:0]
Timer Count 0000 0000 0000 10-bit ARMing Enable Pulse Stretcher timer value
Cleared by SSM_RESET
Loaded with initial value based on ARMx bit and DWELL[1:0] of
SAF_CONTROL_y while safing is met for record y provided current value is <
DWELL[1:0] value
Decremented every 2ms while > 0
Contains remaining pulse stretcher timer value
98/202
DocID029274 Rev 1
L9678P, L9678P-S
MOSI
17
16
-
MISO
0
0
0
0
RW
Buffer:
$7F00
Reset:
$00FE
EN_SAFx
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
7F
14
POR
Address:
15
0
0
0
3
2
1
0
EN_SAF1 EN_SAF1
18
EN_SAF2 EN_SAF2
19
EN_SAF3 EN_SAF3
Safing records enable register (SAF_ENABLE)
EN_SAF4 EN_SAF4
5.1.39
SPI interface
Safing Record enable
Updated by SSM_RESET or SPI write
0 Disable
1 Enable
DocID029274 Rev 1
99/202
201
SPI interface
5.1.40
L9678P, L9678P-S
Safing records request mask registers (SAF_REQ_MASK_x)
Safing record request mask for record 1 (SAF_REQ_MASK_1)
Safing record request mask for record 2 (SAF_REQ_MASK_2)
Safing record request mask for record 3 (SAF_REQ_MASK_3)
Safing record request mask for record 4 (SAF_REQ_MASK_4)
19
18
MOSI
MISO
17
16
15
14
13
12
0
0
11
10
9
8
7
6
5
4
3
2
1
0
SAF_REQ_MASKx[15:0]
0
0
SAF_REQ_MASKx[15:0]
RW
Buffer:
$8000 (SAF_REQ_MASK_1)
$8100 (SAF_REQ_MASK_2)
$8200 (SAF_REQ_MASK_3)
$8300 (SAF_REQ_MASK_4)
Reset:
$8000 (SAF_REQ_MASK_1)
$8002 (SAF_REQ_MASK_2)
$8004 (SAF_REQ_MASK_3)
$8006 (SAF_REQ_MASK_4)
SSM
Type:
WSM
80 (SAF_REQ_MASK_1)
81 (SAF_REQ_MASK_2)
82 (SAF_REQ_MASK_3)
83 (SAF_REQ_MASK_4)
POR
Address:
SAF_REQ_MASKx 0000 0000 0000 Safing Request Mask for safing record x - 16-bit request mask that is bit-wise
[15:0]
ANDed with MOSI data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
100/202
DocID029274 Rev 1
L9678P, L9678P-S
5.1.41
SPI interface
Safing records request target registers (SAF_REQ_TARGET_x)
Safing record request mask for record 1 (SAF_REQ_TARGET_1)
Safing record request mask for record 2 (SAF_REQ_TARGET_2)
Safing record request mask for record 3 (SAF_REQ_TARGET_3)
Safing record request mask for record 4 (SAF_REQ_TARGET_4)
19
18
MOSI
MISO
17
16
15
14
13
12
11
0
0
10
9
8
7
6
5
4
3
2
1
0
SAF_REQ_TARGETx[15:0]
0
0
SAF_REQ_TARGETx[15:0]
RW
Buffer:
$9300 (SAF_REQ_TARGET_1)
$9400 (SAF_REQ_TARGET_2)
$9500 (SAF_REQ_TARGET_3)
$9600(SAF_REQ_TARGET_4)
Reset:
$8026 (SAF_REQ_TARGET_1)
$8028 (SAF_REQ_TARGET_2)
$802A (SAF_REQ_TARGET_3)
$802C (SAF_REQ_TARGET_4)
SSM
Type:
WSM
93 (SAF_REQ_TARGET_1)
94 (SAF_REQ_TARGET_2)
95 (SAF_REQ_TARGET_3)
96 (SAF_REQ_TARGET_4)
POR
Address:
SAF_REQ_TARGETx 0000 0000 0000 Safing Request target for safing record x - 16-bit request target that is
[15:0]
compared to the bit-wise AND result of the SAF_REQ_MASKx and MOSI
data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
DocID029274 Rev 1
101/202
201
SPI interface
5.1.42
L9678P, L9678P-S
Safing records response mask registers (SAF_RESP_MASK_x)
Safing record response mask for record 1 (SAF_RESP_MASK_1)
Safing record response mask for record 2 (SAF_RESP_MASK_2)
Safing record response mask for record 3 (SAF_RESP_MASK_3)
Safing record response mask for record 4 (SAF_RESP_MASK_4)
19
18
MOSI
MISO
17
16
15
14
13
12
11
0
0
10
9
8
7
6
5
4
3
2
1
0
SAF_RESP_MASKx[15:0]
0
0
SAF_RESP_MASKx[15:0]
RW
Buffer:
$A600 (SAF_RESP_MASK_1)
$A700 (SAF_RESP_MASK_2)
$A800 (SAF_RESP_MASK_3)
$A900 (SAF_RESP_MASK_4)
Reset:
$804C (SAF_RESP_MASK_1)
$804E (SAF_RESP_MASK_2)
$8050 (SAF_RESP_MASK_3)
$8052 (SAF_RESP_MASK_4)
SSM
Type:
WSM
A6 (SAF_RESP_MASK_1)
A7 (SAF_RESP_MASK_2)
A8 (SAF_RESP_MASK_3)
A9 (SAF_RESP_MASK_4)
POR
Address:
SAF_RESP_MASKx 0000 0000 0000 Safing Response Mask for safing record x - 16-bit response mask that is bit[15:0]
wise ANDed with MISO data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
102/202
DocID029274 Rev 1
L9678P, L9678P-S
5.1.43
SPI interface
Safing records response target registers (SAF_RESP_TARGET_x)
Safing record response target for record 1 (SAF_RESP_TARGET_1)
Safing record response mask for record 2 (SAF_RESP_TARGET_2)
Safing record response mask for record 3 (SAF_RESP_TARGET_3)
Safing record response mask for record 4 (SAF_RESP_TARGET_4)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
-
10
9
8
7
6
5
4
3
2
1
0
SAF_RESP_TARGETx[15:0]
SAF_RESP_TARGETx[15:0]
RW
Buffer:
$B900 (SAF_RESP_TARGET_1)
$BA00 (SAF_RESP_TARGET_2)
$BB00 (SAF_RESP_TARGET_3)
$BC00 (SAF_RESP_TARGET_4)
Reset:
$8072 (SAF_RESP_TARGET_1)
$8074 (SAF_RESP_TARGET_2)
$8076 (SAF_RESP_TARGET_3)
$8078 (SAF_RESP_TARGET_4)
SSM
Type:
WSM
B9 (SAF_RESP_TARGET_1)
BA (SAF_RESP_TARGET_2)
BB (SAF_RESP_TARGET_3)
BC (SAF_RESP_TARGET_4)
POR
Address:
SAF_RESP_TARGETx 0000 0000 0000 Safing Response target for safing record x - 16-bit response target that is
[15:0]
compared to the bit-wise AND result of the SAF_RESP_MASKx and MISO
data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
DocID029274 Rev 1
103/202
201
SPI interface
5.1.44
L9678P, L9678P-S
Safing records data mask registers (SAF_DATA_MASK_x)
Safing record data mask for record 1 (SAF_DATA_MASK_1)
Safing record data mask for record 2 (SAF_DATA_MASK_2)
Safing record data mask for record 3 (SAF_DATA_MASK_3)
Safing record data mask for record 4 (SAF_DATA_MASK_4)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
-
10
9
8
7
6
5
4
3
2
1
SAF_DATA_MASKx[15:0]
SAF_DATA_MASKx[15:0]
RW
Buffer:
$CC00 (SAF_DATA_MASK_1)
$CD00 (SAF_DATA_MASK_2)
$CE00 (SAF_DATA_MASK_3)
$CF00 (SAF_DATA_MASK_4)
Reset:
$8098 (SAF_DATA_MASK_1)
$809A (SAF_DATA_MASK_2)
$809C (SAF_DATA_MASK_3)
$809E (SAF_DATA_MASK_4)
SSM
Type:
WSM
CC (SAF_DATA_MASK_1)
CD (SAF_DATA_MASK_2)
CE (SAF_DATA_MASK_3)
CF (SAF_DATA_MASK_4)
POR
Address:
SAF_DATA_MASKx[ 0000 0000 0000 Safing Data Mask for safing record x - 16-bit data mask that is bit-wise
15:0]
ANDed with MISO data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
104/202
DocID029274 Rev 1
0
L9678P, L9678P-S
5.1.45
SPI interface
Safing records threshold registers (SAF_THRESHOLD_x)
Safing record threshold for record 1 (SAF_THRESHOLD_1)
Safing record threshold for record 2 (SAF_THRESHOLD_2)
Safing record threshold for record 3 (SAF_THRESHOLD_3)
Safing record threshold for record 4 (SAF_THRESHOLD_4)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
-
10
9
8
7
6
5
4
3
2
1
0
SAF_THRESHOLDx[15:0]
SAF_THRESHOLDx[15:0]
RW
Buffer:
$DF00 (SAF_THRESHOLD_1)
$E000 (SAF_THRESHOLD_2)
$E100 (SAF_THRESHOLD_3)
$E200 (SAF_THRESHOLD_4)
Reset:
$80BE (SAF_THRESHOLD_1)
$80C0 (SAF_THRESHOLD_2)
$80C2 (SAF_THRESHOLD_3)
$80C4 (SAF_THRESHOLD_4)
SSM
Type:
WSM
DF (SAF_THRESHOLD_1)
E0 (SAF_THRESHOLD_2)
E1 (SAF_THRESHOLD_3)
E2 (SAF_THRESHOLD_4)
POR
Address:
SAF_THRESHOLDx $FFFF$FFFF $FFFF Safing threshold for safing record x - 16-bit threshold used for safing data
[15:0]
comparison
Updated by SSM_RESET or SPI write while in DIAG state
DocID029274 Rev 1
105/202
201
SPI interface
5.1.46
L9678P, L9678P-S
Safing control registers (SAF_CONTROL_x)
Safing control register for record 1 (SAF_CONTROL_1)
Safing control register for record 2 (SAF_CONTROL_2)
Safing control register for record 3 (SAF_CONTROL_3)
RW
Buffer:
$EF00 (SAF_CONTROL_1)
$F000 (SAF_CONTROL_2)
$F100 (SAF_CONTROL_3)
$F200 (SAF_CONTROL_4)
Reset:
$80DE (SAF_CONTROL_1)
$80E0 (SAF_CONTROL_2)
$80E2 (SAF_CONTROL_3)
$80E4 (SAF_CONTROL_4)
ARMSELx
6
X
X
ARM2x
ARM1x
CSx[2:0]
IFx
0
0
ARM1x
CSx[2:0]
IFx
5
4
3
2
1
0
SSM
Type:
7
WSM
$EF (SAF_CONTROL_1)
$F0 (SAF_CONTROL_2)
$F1 (SAF_CONTROL_3)
$F2 (SAF_CONTROL_4)
8
POR
Address:
9
ARM2x
10
DWELLx[1:0] DWELLx[1:0]
0
11
COMBx
0
12
COMBx
0
13
LIM Enx
0
14
LIM Enx
-
MISO
15
LIM SELx
16
SPIFLDSELx SPIFLDSELx
MOSI
17
ARMSELx
18
ARMSELx
19
LIM SELx
Safing control register for record 4 (SAF_CONTROL_4)
00
00
00 ARMINT select for safing record x - correlates ARMINT 1 and ARMINT2 (as
determined by ARM1x and ARM2x bits) to ARMP and ARMN
Updated by SSM_RESET or SPI write while in DIAG state
00 ARMP OR ARMN
01 ARMP
10 ARMN
11 ARMP OR ARMN
SPIFLDSELx
106/202
0
0
0
SPI field select for safing record x - determines which 16-bit field in long SPI
messages (>31 bit) to use for response on MISO of SPI monitor. In case of
messages less than 32 bits this bit is don't care.
DocID029274 Rev 1
L9678P, L9678P-S
SPI interface
Updated by SSM_RESET or SPI write while in DIAG state
0 First 16 bits of SPI MISO frame used for Response Mask and Data
Mask bit-wise AND
1 Last 16 bits of SPI MISO frame used for Response Mask and Data
Mask bit-wise AND
LIM SELx
0
0
0
Data range limit select for safing record x - When enabled, determines the
range limit used for incoming sensor data
Updated by SSM_RESET or SPI write while in DIAG state
0 8-bit data range limit - incoming |data| >120d is not recognized as valid
data
1 10-bit data range limit - incoming |data| > 480d is not recognized as
valid data
LIM Enx
0
0
0
Data range limit enable for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
0 Data range limit disabled
1 Data range limit enabled
COMBx
0
0
0
Combine function enable for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
0 Combine function disabled
1 Combine function enabled
For record pairs = x,x+1, the comparison for record x uses |data(x) +
data(x+1)| and the comparison for record x+1 uses |data(x) - data(x+1)|
Record pairs are 1,2 and 6,7
DWELLx[1:0]
00
00
00 Safing dwell extension time select for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
00 2048 ms
01 256 ms
10 32 ms
11 0 ms
ARM2x
0
0
0
ARM2INT select for safing record x - correlates safing result to ARM2INT
Updated by SSM_RESET or SPI write while in DIAG state
0 Safing record x not assigned to ARM2INT
1 Safing record x assigned to ARM2INT
ARM1x
0
0
0
ARM1INT select for safing record x - correlates safing result to ARM1INT
Updated by SSM_RESET or SPI write while in DIAG state
DocID029274 Rev 1
107/202
201
SPI interface
L9678P, L9678P-S
0 Safing record x not assigned to ARM1INT
1 Safing record x assigned to ARM1INT
CSx[2:0]
000 000 000 SPI Monitor CS select for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
000 None selected for record x
001 SAF_CS0 selected for record x
010 SAF_CS1 selected for record x
011 None selected for record x
100 None selected for record x
101 SPI_CS selected for record x
110 None selected for record x
111 None selected for record x
IFx
0
0
0
SPI format select for safing record x - selects response protocol for SPI
monitor
Updated by SSM_RESET or SPI write while in DIAG state
0 Out of frame response for record x
1 In Frame response for record x
108/202
DocID029274 Rev 1
L9678P, L9678P-S
5.1.47
Safing record compare complete register (SAF_CC)
19
18
0
0
MOSI
MISO
SPI interface
17
16
0
0
-
R
Buffer:
$FF00
Reset:
-
CC_xx
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
FF
14
POR
Address:
15
0
0
0
3
2
1
0
X
X
X
X
CC_4 CC_3 CC_2 CC_1
Indicates compare complete status of each of the 4 safing records, and
defines the end of the sample cycle for safing
Cleared by SSM_RESET or SPI read, set by safing engine when request,
response mask and target registers match the incoming SPI frame
0 Compare not completed for record x
1 Compare completed for record x
DocID029274 Rev 1
109/202
201
Deployment drivers
6
L9678P, L9678P-S
Deployment drivers
The squib deployment block consists of 4 independent high side drivers and 4 independent
low side drivers. Squib deployment logic requires a deploy command received through SPI
communications and either an arming condition processed by safing logic or a proper FENH
and FENL input pin assessment, depending on whether the internal safing engine is used or
not. FENH signal is used to enable high side squib drivers and is active high, while FENL
enables low side drivers and is active low. Both conditions must exist in order for the
deployment to occur. Once a deployment is initiated, it can only be terminated by a RESET
event.
L9678P allows all 4 squib loops to be deployed at the very same time or in other possible
timing sequence. Deployment drivers are capable of granting a successful deployment also
in case of short to ground on low-side circuit (SRx pins). Firing voltage capability across high
side circuit is maximum 25 V. High side and low side drivers account for a maximum series
total resistance of 2 Ω. Each loop is granted for a minimum number of deployments of 50,
under all normal operating conditions and with a deployment repetition time higher than 10s.
6.1
Control logic
A block diagram representing the deployment driver logic is shown below. Deployment
driver logic features include:

Deploy command logic

Deployment current selection

Deployment current monitoring and deploy success feedback

Diagnostic control and feedback
Figure 20. Deployment driver control blocks
'&5
'HSOR\PHQW&RQILJXUDWLRQ
5HJLVWHU
'(3&20
'HSOR\PHQW
&RPPDQG5HJLVWHU
'HSOR\
5HTXHVW
9DOLGDWLRQ
)(1+ ;
+LJK
6LGH
)(7
; 6)[
'&076[
'HSOR\&XUUHQW
0RQLWRU6WDWXV
'HSOR\PHQW
&RQWURO
7LPLQJ
'&5
'HSOR\PHQW
&RQILJXUDWLRQ
5HJLVWHU
,QW([WVDILQJHQJLQH
LQWFON
,7+'(3/
&XUUHQW
0RQLWRU
'&5
'HSOR\PHQW
&RQILJXUDWLRQ
5HJLVWHU
'HSOR\PHQW6WDWXV
5HJLVWHU
'65[
/RZ
6LGH
)(7
)(1/ ;
; 65[
$50 ;
6DILQJ(QJLQH
3URJUDPPDEOH
/RRS
$VVLJQPHQWV
,QW([WVDILQJHQJLQH
'!0'03
110/202
DocID029274 Rev 1
L9678P, L9678P-S
Deployment drivers
Figure 21. Deployment driver control logic - Enable signal
$50,1*67$7(
$QDORJ
',$*67$7(
'HSOR\PHQW
/3',$*5(4/($.B&+6(/[
'67(67+6)(7B7(67
%ORFN
6$)(6(/
)(1+
(1$%/(B+6[
$50,17
$50B/[
$50,17
$50B/[
)(1/
6$),1*67$7(
$50B(1
(1$%/(B/6[
',$*67$7(
/3',$*5(4/($.B&+6(/[
'67(67/6)(7B7(67
'!0'03
Figure 22. Deployment driver control logic - Turn-on signals
$50,1*67$7(
([SLUDWLRQ
7LPHU
6$),1*67$7(
'(3B(1$%/('67$7(
6
63,B'(35(4[
5
6605(6(7
'(3B',6$%/('67$7(
8S&WU
(;3B7KUHVK
(1
&/5
&+['(3
&+[67$7
6
5
'(3B7KUHVK
8S&WU
(1$%/(B+6[
(1$%/(B/6[
6
',$*67$7 (
'67(6738/6(
5
(1
&/5
/6B29(5B&85[
*1'B/266[
'HSOR\
7LPHU
6605(6(7
6
6
5
5
&+['6
+6B21[
'67(67+6)(7B7(67
/3',$*5(4/($.B&+6(/[
/6B21[
'67(67/6)(7B7(67
$1$/2*
'HSOR\PHQW%/2&.
'!0'03
The high level block diagram for the deployment drivers is shown below:
DocID029274 Rev 1
111/202
201
Deployment drivers
L9678P, L9678P-S
Figure 23. Deployment driver block
66[\
5
P:
5
23ZLWKVZLWFKLQJ
2IIVHWFRPSHQVDWLRQ
(QDEOHB+6[
5
23SKDVH
23SKDVH
5
6)[
[,5()
2SHQWRVKRUWFRPS
Q)
7RGHSOR\
FXUUHQW !
FRXQWHU
5VTXLE
65[
9FODPS !9
,SXOOGRZQ
9
+6B2))
Q)
6DPHSRZHU
WUDQVLVWRU
/6B21
,5() P$
(1B,6,1.
,OLPLW !$W\S
(QDEOHB/6[
/6B2&B&RPS
,OLPLW
P$ W\S
6*[\
/RVVJURXQG
GLRGH
/6B/RVV B*QG
*1'68%
*$3*36
6.1.1
Deployment current selection
Deployment current is programmed for all channels using the Deploy Configuration Register
(DCRx) shown in “Deployment Configuration register (DCRx).
If 1.75 A deployment current is selected, the 2 ms deployment time cannot be chosen. If a
SPI command with 2 ms and 1.75 A selection is received, L9678P will discard it and switch
to a 500 µs and 1.2 A selection instead. This misuse is flagged with the CHxDD bit in the
Deploy Status Register (DSR).
6.1.2
Deploy command expiration timer
Deploy commands are received for all channels using SPI communications. Once a deploy
command is received, it will remain valid for a specified time period selected in the Deploy
Configuration Register (DCRx). The deploy status and deploy expiration timer can be read
through the Deploy Status Register (DSRx). The deploy expiration timer is 6 bits and the
maximum time is 500 ms nominal.
112/202
DocID029274 Rev 1
L9678P, L9678P-S
6.1.3
Deployment drivers
Deployment control flow
Deployment control logic requires the following conditions to be true to successfully operate
a deployment:

POR = 1

SSM to be either in Safing State or Arming State

a valid arming condition processed by safing logic or FENH and FENL signals to be set
(depending on selection of internal or external safing engine)

"channel-specific deploy command request bits to be set via SPI in the Deploy
command Register (DEPCOM)

a global deployment state has to be active, as described in the following figure.
Figure 24. Global SPI deployment enable state diagram
660B5HVHW
'(3B',6$%/('
63,B63,'(3(1'(3(1B:5
63,B63,'(3(1'(3(1B:5
81/2&.
/2&.
'(3B(1$%/('
'!0'03
In case a multiple deployment request would be needed, i.e. deploying the same channel in
sequence, a toggle on DEP_DISABLED has to be performed and a new DEPCOM
command on the same channel has to be sent.
The SPI DEPCOM command is ignored if the device is in the DEP_DISABLED state and the
deploy command is not set. While in DEP_ENABLED state, the following functionalities that
could be active are forced to their reset state:

All squib and DC sensor diagnostic current or voltage sources

All squib, DC sensor and ADC diagnostic mux settings, state machine, etc.
The SPI_LOCK and SPI_UNLOCK signals are available in the SPIDEPEN command:
High-side and Low-side enablers by internal/external safing are global and apply to all
channels. The Deploy commands in the Deploy Command Register (DEPCOM) are channel
specific.
Deployment requires a valid arming command from safing logic or the FENH and FENL
signals to be set any time before, during or after the specific sequence of deploy commands
is received. It is feasible for a deploy command to be received without a valid arming
command from safing logic or the FENH and FENL being set. In this case, the deploy
command will be terminated according to the Deploy Command Expiration Timer described
in Section 6.1.2. Likewise, a valid arming command or the FENH and FENL signals can be
set without receiving a Deploy Command. In this case, the enabling signals will remain
active according to the Arming Enable Pulse Stretch Timer or the FENx enabling state. The
Arming Enable Pulse Stretch Timers is available in the AEPSTS register.
DocID029274 Rev 1
113/202
201
Deployment drivers
6.1.4
L9678P, L9678P-S
Deployment success
Deploy success flag is set when the deploy timer elapses. This bit (CHxDS) is contained in
the Deploy Status Register. Within the Global Status Word register (GSW), a single bit
(DEPOK) is also set once any of the four deployment channels sets a deploy success flag.
6.2
Energy reserve - deployment voltage
One deployment voltage source pin is used for channels 0 and 1 (SS01) and one for
channels 2 and 3 (SS23). These pins are directly connected to the high side drivers for each
channel.
6.3
Deployment ground return
There are dedicated power ground connections for deployment current, SGx pins. One
ground connection is sufficient for two deployments occurring simultaneously.
6.4
Deployment driver protections
6.4.1
Delayed low-side deactivation
To control voltage spikes at the squib pins during drivers deactivation at the end of a
deployment, the low side driver is switched off after tDEL_SD_LS delay time with respect to
the high side deactivation.
6.4.2
Low-side voltage clamp
The low side driver is protected against overvoltage at the SRx pins by means of a clamping
structure as shown in Figure 23. When the Low side driver is turned off, voltage transients at
the SRx pin may be caused by squib inductance. In this case a low side FET drain to gate
clamp will reactivate the low side FET allowing for residual inductance current recirculation,
thus preventing potential low side FET damage by overvoltage.
6.4.3
Short to battery
The low side driver is equipped with current limitation and overcurrent protection circuitry. In
case of short to battery at the squib pins, the short circuit current is limited by the Low side
driver to ILIM_SR. If this condition lasts for longer than TFLT_ILIM_LS deglitch filter time then
the low and high-side drivers will be switched off and latched in this state until a new
deployment is commanded after SPI_DEPEN is re triggered.
6.4.4
Short to ground
The squib driver is designed to stand a short to ground at the squib pins during deployment.
In particular, the current flowing through the short circuit is limited by the high side driver
(deployment current) and the high-side FET is sized to handle the related energy.
In case the short to ground during deployment occurs after an open circuit, a protection
against damage is also available. The high side current regulator would have normally
reacted to the open circuit by increasing the Vgs of the high side FET. Thanks to a dedicated
114/202
DocID029274 Rev 1
L9678P, L9678P-S
Deployment drivers
fast comparator detecting the open condition, the driver is able to discharge the FET gate
quickly in order to reduce current overshoot and prevent potential driver damage when the
short to ground occurs.
6.4.5
Intermittent open squib
A dedicated protection is also available in case of intermittent open load during deployment.
In this case, if load is restored after an open circuit, due to slow reaction of the high-side
current regulation loop, the current through the squib is limited only to ILIMSRx by the low
side driver. If this condition lasts for longer than tLIMOS then the high side is turned off for
tHSOFFOS and then reactivated. By this feature, intermittent open squib and short to battery
faults may be distinguished and handled properly by the drivers.
6.5
Diagnostics
The L9678P provides the following diagnostic feedback for all deployment channels:

High voltage leakage test for oxide isolation check on SFx and SRx

Leakage to battery and ground on both SFx and SRx pins with or without a squib

Loop to loop short diagnostics

Squib resistance measurement with leakage cancellation

High squib resistance with range from 500 Ω to 2000 Ω

SSxy, SFx and VER voltage status

High and low side FET diagnostics

High side driver diagnostics

Loss of ground return diagnostics

High side safing FET diagnostics

Deployment Timer diagnostic
The above diagnostic results are processed through a 10 bit Analog to digital algorithmic
converter. These tests can be addressed in two different ways, with a high level approach or
a low-level one. The main difference between the two approaches is that with the low level
approach the user is allowed to precisely control the diagnostic circuitry, also deciding the
proper timings involved in the different tests. On the other hand, the high level approach is
an automatic way of getting diagnostic results for which an internal state machine is taking
care of instructions and timings.
The following is the block diagram of the squib diagnostics.
DocID029274 Rev 1
115/202
201
Deployment drivers
L9678P, L9678P-S
Figure 25. Deployment loop diagnostics
9(5SLQ
IURP(QHUJ\5HVHUYH
6DILQJ
WUDQVLVWRU
95(6',$*
,65&
P$
66[\
%\SDVV
Q)
6TXLEUHVLVWDQFHPHDVXUH
V\VWHPHUURU
9JQGRU
9%DW
6)[
5/HDN
9UHI Y
Q)
[1
$WR'
6TXLEORRS
GULYHUDQG
GLDJQRVWLF
EORFNV
5VTXLE
: WR: 9RXW
ELW
7RW HUU “/6%
/6% 9
9RIIVHW
+9DQDORJ08;
*DLQ 9JQGRU
9%DW
65[
6TXLEUHVLVWRU+,*+
,SXOOGRZQ
, P$
6TXLEUHVLVWRU/2:
6KRUWWR*1'
5OHDN !. : QRGHWHFWLRQ
5OHDN .: GHWHFWLRQ
5/HDN
Q)
6*[
9UHI Y
,6,1.
*1'$
,OLPLW P$
6KRUWWR%$7
5OHDN !. : QRGHWHFWLRQ
5OHDN .: GHWHFWLRQ
95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU
*$3*36
The leakage diagnostic includes short to battery, short to ground and shorts between loops.
The test is applied to each SFx and SRx pin so shorts can be detected regardless of the
resistance between the squib pins.
6.5.1
Low level diagnostic approach
In this approach, each of the test steps described in the sections below requires user
intervention by issuing the proper SPI command.
High voltage leakage test for oxide isolation check
This test is mandatory to address possible leakages that could not be experienced at low
voltages on SFx or SRx pins. The Isource current generator (ISRC) is enabled on the chosen
SFx pin. To confirm that the SFx pin has then reached a suitable voltage level, a dedicated
ADC measurement on the SFx pin can be requested. Once this test is performed, a leakage
test on SFx and SRx pins can be issued to double check possible leakages.
Leakage to battery/ground diagnostics
Prior to the real test, the Voltage Regulator Current Monitor block (VRCM) has to be tested
and validated. The validation of VRCM goes into verifying both the short to battery and short
to ground flags.
The Isource current generator (ISRC) is first connected to SFx pin to raise its voltage to
VRESDIAG. Then, the Voltage Regulator Current Monitor block (VRCM) is enabled and
connected to the selected SFx pin. The Isink current limited switch (ISNK) is turned off, as
116/202
DocID029274 Rev 1
L9678P, L9678P-S
Deployment drivers
well as the pull-down current generator. If the VRCM block works properly, the short to
battery flag would be asserted.
Then, the Isink current limited switch (ISNK) is connected to SRx pin, the Voltage Regulator
Current Monitor block (VRCM) is enabled and connected to the selected SRx pin. The
Isource current generator (ISRC) is turned off, as well as the pull-down current generator. If
the VRCM block works properly, the short to ground flag would be asserted.
Figure 26. SRx pull-down enable logic
/3',$*5(43'B&855
+6B21[
(1B3'B&855[
/6B21[
/3',$*5(4 ,65&
RU
/3',$*5(4 5(6B0($6B&+6(/[ /3',$*5(4,61.
/3',$*5(4 95&0
RU
/3',$*5(4 /($.B&+6(/[ /3',$*5(4 ',$*B/(9(/ /3',$*5(4 /223B',$*B&+6(/[ DQG /3',$*5(4+,*+B/(9(/ B',$*B6(/
*$3*36
Once the VRCM block is validated, the real leakage tests can be performed. ISRC and
ISNK currents have to be kept switched off. The VRCM shall be connected to the desired
pin (either SFx or SRx pins); by doing this, also the pull-down current on the selected SRx
pin is automatically deactivated. During the test, if no leakage is present the voltage on the
selected SFx or SRx pin will be forced by the VRCM to the VREF level and no current is
detected or sourced by the VRCM. If there is leakage to ground or battery, the VRCM will
sink or source current trying to maintain VREF. Two current comparators, ISTB and ISTG,
will detect the abnormal current flow and the relative flags will be given in the LPDIAGSTAT
(these flags are not latched and report the real time status of the relevant comparators in
case of low-level leakage diagnostic test). In LPDIAGSTAT register are also reported the
channel and the pin (SFx or SRx) under test, respectively with LEAK_CHSEL and SQP bit
fields.
The pull-down currents on the other SRx pins are still active. Therefore, the leakage test
that would show a leakage to ground may be depending on a real leakage on the pin under
test or on a short between loops.
Short between loops diagnostics
In case the previous test has reported a leakage to ground fault, the short between loops
diagnostics shall be run. The same procedure is followed as described for normal leakage
tests except the fact that in this case all the pull-down current generators have to be
deactivated (not only the one for the pin under test), by means of the PD_CURR bit in the
Diagnostic Request Register (LPDIAGREQ). If a leakage or ground fault is not present, then
the channel under test has a short to another squib loop.
DocID029274 Rev 1
117/202
201
Deployment drivers
L9678P, L9678P-S
Table 8. Short between loops diagnostics decoding
Channel leakage diagnostics with
PD_CURR on (for other channels
than the one under test
Channel leakage diagnostics
with PD_CURR off
(for all channels)
No fault
No fault
Short to battery
STB fault
STB fault
Short to ground
STG fault
STG fault
Short between loops
STG fault
No fault
Fault condition on
squib channel
No shorts
The condition of two open channels, i.e. without squib resistance connecting SFx to SRx,
that have a short between loops on SFx cannot be detected. If only one of the two shorted
SFx pins is open, the fault is indicated on the open channel.
Squib resistance measurement
During a resistance measurement, a two-step process is performed. At the first step, both
ISRC current generator and ISNK current limited switch are enabled and connected to the
selected SFx and SRx channel, through ISRC, ISNK and RES_MEAS_CHSEL bit fields in
the Loop Diagnostic Request Register (LPDIAGREQ). A differential voltage is created
between the SFx and SRx pin based in the ISRC current and squib resistance between the
pins. The SPI interface will provide the first resistance measurement voltage (Vout1) based
on the amplifying factor of the differential amplifier and a 10 bit internal ADC conversion.
The second measurement step (bypass measurement) is performed redirecting ISRC to the
selected SRx pin, while keeping ISNK on; this way, the differential amplifier and following
ADC will output the offset measurement through SPI (Vout2). Microcontroller is then allowed
to calculate the mathematical difference between first and second measurements to obtain
the real squib resistance value. The current sources ISRC and ISNK used for Squib
Resistance measurements are completely controlled by the user via SPI. Optionally, an
automatic control by the IC for current sources switch-off after ADC reading can be
activated by enabling the EN_AUTO_SWITCH_OFF bit in the SYS_CFG register.
R sq
 R leak  R sq
V out1 = G  I source   ------------------------------- + -------------------------------  V gnd – V refSQL  + G  V offset
 R leak + R sq R leak + R sq
G  R sq
V out2 = -------------------------------   V gnd – V refSQL  + G  V offset
R leak + R sq
V out
R sq = -------------------- (assuming Rleak >> Rsq)
G  I src
where:
G = differential amplifier gain.
The simplification in the calculation method reported above can result in some amount of
error that is already incorporated in the overall tolerance of the squib resistance
measurement reported in the electrical parameters table.
118/202
DocID029274 Rev 1
L9678P, L9678P-S
Deployment drivers
Values of each measurement step can be required addressing the proper ADCREQx code
in the Diagnostic Control command (DIAGCTRL) on Table 11: Diagnostics control register
(DIAGCTRLx) on page 159.
This calculation is tolerant to leakages and, thanks to a dedicated EMI low-pass filter, also to
high frequency noises on squib lines. Moreover, L9678P features a slew rate control on the
ISRC current generator to mitigate emissions.
High squib resistance diagnostics
With this test, the device is able to understand if the squib resistance value is below 200 Ω,
between 500 Ω and 2000 Ω or beyond 5000 Ω. During a high squib resistance diagnostics,
VRCM and ISNK are enabled and connected respectively to SFx and SRx on the selected
channel. VREF voltage level outputs on SFx. Current flowing on SFx is measured and
compared to ISRlow and ISRhigh thresholds to identify if the resistance is above or below
RSRlow or RSRhigh levels. The results are reported in the LPDIAGSTAT register. The relative
flags (HSR_HI and HSR_LO) are not latched and reflect the current status of the
comparators.
High and low side FET diagnostics
This couple of tests can only be run during the diagnostic mode of the power-up sequence
(Figure 9). Tests are performed individually for HS driver or LS driver, with two dedicated
commands. Prior to either the HS or LS FET diagnostics being run, the VRCM has to be first
enabled. Within the command to enable the VRCM, also the channel onto which the FET
test will be run has to be selected with the LEAK_CHSEL bit field. Running the leakage
diagnostics with the appropriate delay time prior to either the HS or LS FET diagnostics will
precondition the squib pin to the appropriate voltage level. When the FET diagnostic
command is issued with the Diagnostic Register SPI command (SYSDIAGREQ), the VRCM
flags will be cleared.
The device monitors the current through the VRCM. If the FET is working properly, this
current will exceed ISTB (HS test) or ISTG (LS test) and the driver under test is turned off
immediately. If the current does not exceed ISTB or ISTG then the test will be terminated and
the output is anyway turned off within TFETTIMEOUT. During TFETTIMEOUT period, the bit
stating that the FET is enabled will be set (FETON=1) and will be cleared as soon as the
FET is switched back off.
For all conditions the current on SFx/SRx will not exceed ILIM_VRCM_X, the VRCM block
current limitation value. There may be higher currents on the squib lines due to the presence
of filter capacitors. During these FET tests, energy available to the squib is limited to less
than EFETtest.
For high side FET diagnostics, if no faults were indicated in the preceding leakage
diagnostics then a normal result would be [STB=1, STG=0]. If the returned result for the
high side FET test is not as the previous then either the FET is not functional, a short to
ground occurred during the test, or there is a missing SSxy connection for that channel.
For low side FET diagnostics if no faults were indicated in the preceding leakage
diagnostics then a normal result would be [STB=0, STG=1]. If the returned result for the low
side FET test is not as the previous one then either the FET is not functional or a short to
battery occurred during the test. In case of SGx loss the low-side FET diagnostic would not
indicate a FETfault.
DocID029274 Rev 1
119/202
201
Deployment drivers
L9678P, L9678P-S
The VRCM flags will be given in the LPDIAGSTAT register. The status of the VRCM flags
after FET test is latched and can be cleared upon either LPDIAGREQ or SYSDIAGREQ SPI
commands.
Loss of ground return diagnostics
This diagnostics is available during a squib measurement or a high side driver diagnostics.
This test is based on the voltage drop across the ground return, if the voltage drop exceeds
VSGopen, ground connection is considered as lost. Should the ground connection on the
squib driver circuit be missing, the bit related to the channel under test by the two above
diagnostics will be activated in the LP_GNDLOSS register. The flag is latched after a proper
filter time tSGopen and cleared upon read.
High side safing FET diagnostics
This test has to be issued during the Diag state of the power-up sequence (Figure 9). Safing
FET has to be switched on with the proper code in DSTEST bit field of the SYSDIAGREQ.
Therefore, when the command is received, the device activates VSF regulator to supply the
external safing FET controller. The user can measure the voltage levels of both the VSF
regulator and the SSxy nodes. If the safing FET is properly switched on, the voltage on
SSxy is regulated.
The measurement request is done via Diagnostic Control command (DIAGCTRLx), while
results are reported through ADCRESx bit fields, as shown in Table 11.
Deployment timer diagnostic
This test allows verifying the correct functionality and duration of the timers used to control
the deployment times. This test can be executed only when the IC is in the Diag state by
setting the appropriate code in the DSTEST field of the SYSDIAGREQ register. When the
test is launched, the IC sequentially triggers the activation of the deployment timers of the
various channels (each of them separated by 8ms idle time) and outputs the relevant
waveform to the ARM output discrete pin. See the sequence detail in Figure 27. The MCU
can therefore test the deployment times by measuring the duration of the high pulses sent
by the IC on the ARM pin. The deployment time configuration used during this test is the
latest one programmed in the DCRx registers. In case the test is run on a channel with no
DCRx deployment time previously configured, a default 8us high pulse is output on ARM for
the relevant channel.
120/202
DocID029274 Rev 1
L9678P, L9678P-S
Deployment drivers
Figure 27. Deployment timer diagnostic sequence
)URPDQ\VWDWH
',$*VWDWH63,B6<65(4'67(67 38/6(
38/6(B7(67[ 37B705 PV
37B705 38/6(B7(67[ 38/6(B7(67 37B:$,7
660B5(6(7
38/6(B7(67[ 37
37B705 PV
37B705 38/6(B7(67[ 38/6(B7(67 37B2))
37
37B705 PV
38/6(B7(67[ 37B705 PV
37B705 38/6(B7(67[ 38/6(B7(67 37
37
37B705 PV
37B705 38/6(B7(67[ 38/6(B7(67 *$3*36
Loop diagnostics control and results registers
Diagnostic tests and channels for each test are controlled through the Loop Diagnostic
Request Register (LPDIAGREQ), diagnostic results are stored in the Loop Diagnostic
Status Register (LPDIAGSTAT).
6.5.2
High level diagnostic approach
In this approach, the test steps described in the sections below are coded into a dedicated
state machine that helps reducing the user intervention to a minimum.
The high-level diagnostic commands are contained in the LPDIAGREQ, LOOP_DIAG_SEL,
and LOOP_DIAG_CHSEL registers. These settings are described in the SPI Table for these
commands in Read/write register.
The high-level diagnostic response is available in the LPDIAGSTAT register. These are
described in the SPI Table for this command in Read/write register.
The concept is depicted in the following figures.
DocID029274 Rev 1
121/202
201
Deployment drivers
L9678P, L9678P-S
Figure 28. High level loop diagnostic flow1
,OWLEVELDIAGNOSTICISSELECTEDBIT
OF,0$)!'2%1ISLOW/2ANINVALID
HIGHLEVELDIAGNOSTICISSELECTED/2WE
AREIN$%0?%.!",%$STATE
4)0
,EAKAGETESTTIMEELAPSED
3",FLAGISASSERTEDIF34'
ISNOMOREPRESENT
,EAKAGEISDETECTEDDUETO
THEFACTTHAT&%4SWORK
PROPERLY/2&%4TEST
TIMEOUTELAPSED
$)!'?/&&
.EWHIGHLEVELDIAGNOSTICREQUEST
BITOF,0$)!'2%1ISHIGH
62#-CHECKTIMEELAPSED
!.$62#-#(%#+TEST
ISSELECTED/262#-FAILS
4)0
7AITENAUGHTIMETO
BESURETHATALL
CURRENTSANDVOLTAGES
SUPPLIESSTARTIN/&&STATE
7!)4?/&&
/FFTIME—S
,ATCH34"34'FLAGS
&0IF,%!+!'%OR
&%44TESTSARESELECTED
/FFTIMEELAPSED!.$NEW
DIAGNOSTICREQUESTIS
62#-?#(%#+/2
,%!+!'%/23",/2
&%4TESTS
62#-?#(%#+
&%44%34
4)0
&%4TESTTIMEOUT—S
%NABLE62#$ISABLE)32#AND)3).+
%NABLE(3OR,3&%4IFALSO
$34%34OR
,EAKAGETESTTIMEELAPSED
!.$&%4TESTISSELECTED
!.$./LEAKAGEISPRESENT
,EAKAGETESTTIMEELAPSED
!.$,%!+!'%TEST/2
3",ANDNOLEAKAGEIS
PRESENT/2&%4TESTAND
LEAKAGEISPRESENT
,ATCH34"34'FLAGS
&0IF&%4TESTISSELECTED
4)0
,%!+!'%?4%34?
%NABLE62#$ISABLE)32#AND ,EAKAGETESTTIME—S
)3).+
$ISABLE!,,PULL
DOWNCURRENTS
62#-CHECKTIME—S—S
4)0
%NABLE62#$ISABLE)32#AND)3).+
,EAKAGETESTTIMEELAPSED
!.$3",ISSELECTED
!.$LEAKAGEISPRESENT
,%!+!'%?4%34?
,EAKAGETESTTIME—S
4)0
%NABLE62#$ISABLE)32#AND)3).+
'!0'03
122/202
DocID029274 Rev 1
L9678P, L9678P-S
Deployment drivers
Figure 29. High level loop diagnostic flow2
,OWLEVELDIAGNOSTICISSELECTEDBIT
OF,0$)!'2%1ISLOW/2ANINVALID
HIGHLEVELDIAGNOSTICISSELECTED/2WE
AREIN$%0?%.!",%$STATE
%NDOFCONVERSION
3TORERESULTIN!$#2%3"
$)!'?/&&
4)0
2ESISTANCERANGETESTTIMEELAPSED
,ATCH(32?()(32?,/FLAGS
315)"2%32!.'%
4%34
.EWHIGHLEVELDIAGNOSTICREQUEST
BITOF,0$)!'2%1ISHIGH
/FFTIMEELAPSED!.$NEW
DIAGNOSTICREQUESTIS315)"
2%3)34!.#%2!.'%TEST
4)0
7AITENOUGHTIMETO
BESURETHATALL
CURRENTSANDVOLTAGES
SUPPLIESSTARTIN/&&STATE
7!)4?/&&
2ESISTANCERANGETEST
SETTINGTIME—S—S
4)0
%NABLE62#%NABLE)3).+
/FFTIME—S
/FFTIMEELAPSED!.$NEW
DIAGNOSTICREQUESTIS
315)"2%3)34!.#%MEASURETEST
%NDOFSETTINGTIME
315)"2%3-%!3
#/.6
315)"2%3-%!3
#/.6
%NDOFCONVERSION
3TORERESULTIN!$#2%3!
%NDOFSETTINGTIME
315)"2%3-%!3
3%44,%
4)0
%NABLE)32#ON3&X
%NABLE)3).+
2ESISTANCETEST
SETTINGTIME—S—S
315)"2%3-%!3
3%44,%
4)0
2ESISTANCETEST
%NABLE)3).+
SETTINGTIME—S—S
%NABLE)32#
"90!33)32#ON32X
'!0'03
DocID029274 Rev 1
123/202
201
Remote sensor interface
7
L9678P, L9678P-S
Remote sensor interface
The L9678P-S contains 2 remote sensor interfaces, capable of supporting PSI-5 protocol
(standard voltage range). A block diagram of the interface is shown below. The circuitry
consists of a power interface that demodulates current flowing in the external sensor and
transmits these current states to the decoder, which produces a digital value for each
satellite channel. Data are then output through the Remote Sensor Data Registers
(RSDRx). The power interface also contains error detection circuitry. When a fault is
detected, the error code is stored in a global SPI data buffer in the Remote Sensor Data
Registers (RSDRx).
Figure 30. Remote sensor interface logic blocks
5HPRWH6HQVRU&RQILJXUDWLRQ5HJ56&5
5HPRWH6HQVRU'DWD5HJ;56'5[
0DQFKHVWHU
'HFRGHU
)DXOW
'HWHFWLRQ
3RZHU
,QSXW
3URWHFWLRQ
;
568[
5HPRWH6HQVRU)DXOW6WDWXV5HJ56)65
)DXOW6WDWXV5HJ)/765
'!0'03
The Remote Sensor Configuration Registers (RSCRx) allow for configuration of the
particular PSI5 protocol adopted by the sensor and the transceiver current limit blanking
time.
The Remote Sensor Control Register (RSCTRL) allows for interface channels to be
switched on and off via SPI.
RSU interface has 2 registers per channel, which can report either data or fault information,
that can be readout by sending 2 consecutive Read commands of the Remote Sensor Data
Register (RSDRx). It is a FIFO, so the first SPI reading contains the oldest received data
and the next SPI reading contains the most recent one. SPI accesses both from the same
address, i.e. the MCU should do 2 reads of the same RID to get both data samples. The
couple of registers will retain only the last two received messages, regardless they have
been qualified as valid or invalid data. In case of driver fault (Short to Ground, Short to
Battery, Over-current, Open detection, Over-temperature) any message is lost. To re-start a
correct reception of messages, it is needed to have no more fault present and fault flag read
by MCU.
If the device detects an error on the sensor interface, the fault bit in RSDRx (FLTBIT) will be
set to '1' and the following bits will be used to report the detected errors. Otherwise, the
register will contain only data information. Detailed information on data and fault reporting
are explained in the following sections.
When a fault condition is detected, the RSFLT bit of the global status word (GSW) is set to
1, except in the case the register is empty for which NODATA fault bit will be set instead.
Data are cleared upon reading the RSDRx register.
RSU interface is supplied by VSUP regulator as showed in Figure 31. To avoid a too low
RSU output voltage in case of battery loss, the upper VINGOOD and VBATMOND
124/202
DocID029274 Rev 1
L9678P, L9678P-S
Remote sensor interface
thresholds must be selected. In this way the device will detect the battery loss condition in
time to guarantee the minimum RSU output voltage required.
Figure 31. Remote sensor interface block diagram
9683
95()
568B2&
568B67%
6KRUWWR
9%$7
FRPS
6KRUWWR
*1'
FRPS
P9
568B(QDEOH
(0,ILOWHU
,6$7
568[
,6$7
:
Q )
Q)
5;6$76<1&
RU
&203%$6(287
,EDVH
IVDPSOH
6$7
8S'RZQ
FRXQWHU
'LJLWDOZRUG 6DWHOOLWH
%DVHFXUUHQW
ELWV
,WKUHVKROG
36,FXUUHQWFRPSDUDWRU
7.1
*$3*36
PSI-5 protocol
All channels are compliant to the PSI-5 v1.3 specification as described below:

Two-wire current interface

Manchester coded digital data transmission

High data transmission speeds of 125 kbps and 189 kbps

Variable data word length (8 & 10 bit only)

1-bit parity

Asynchronous operation mode
DocID029274 Rev 1
125/202
201
Remote sensor interface
L9678P, L9678P-S
An example of the data format for one possible PSI-5 protocol configuration is shown below.
Data size may vary, but the presence of 2 sync start bits (referenced below as sync bits) and
TGap time is consistent regardless the data size.
Figure 32. PSI-5 remote sensor protocol (10-bit, 1-bit parity)
$ATA4RANSMISSION
4'!0
FRAMEDURATION
3 3 $ $ $ $ $ $ $ $ $ $ 0
-ANCHESTER#ODE
4RANSMISSIONOFX%
X%B
4")4
7.1.1
'!0'03
Functional description - remote sensor modes
The Remote sensor Interface block provides a hardware connection between the
microcontroller and up to two remote sensors. Each channel is independent of the other,
and is not influenced by fault conditions, such as short circuits to ground or vehicle battery,
on the other channel. Each channel supplies an independently current limited DC voltage to
its remote sensor derived from VSUP, and monitors the current draw to extract encoded
data. The remote sensors modulate the current draw to transmit Manchester-encoded data
back to the receiver. The current level detection threshold for all channels is automatically
set by the integrated current adjust feature in order to adapt to the quiescent current draw of
the sensors.
All channels can be enabled or disabled independently via SPI commands. The operational
status of all channels can also be read via SPI command.
The message bits are encoded using a Manchester format, in which logic values are
determined by a current transition in the middle of the bit time. The interface supports
Manchester 2 encoding as shown in Figure 33.
Figure 33. Manchester bit encoding
%LWWLPH
3TARTBITS
,OGICgg
&XUUHQW
µ¶
,OGICgg
µ¶
µ¶
µ¶
µ¶
-ANCHESTER
03)
'!0'03
The received message data are stored in input data registers that are read out by the
microcontroller via the SPI interface. All bits of these registers are simultaneously updated
upon reception of the remote sensor message to prevent partial frame data from being
sampled via the SPI interface. After the data for a given channel is read via the SPI
126/202
DocID029274 Rev 1
L9678P, L9678P-S
Remote sensor interface
interface, subsequent requests for data from this channel will result in an error response
(NODATA fault).
The remote sensor interface is also able to detect faults occurring on the sensor interface.
The Remote Sensor Data Register (RSDRx) will report multiple fault flags.
When the number of bits decoded is incorrect (either too many or too few), a bit error is
indicated. When any bit error is detected (bit time, too many bits or too few bits), the
message is discarded.
Error bit INVALID is an OR-ed combination of the following errors:

Data length error or stop bit error

Parity Error of received Remote sensor Message

Bit time error (a data bit edge is not received inside the expected time window)
Should one or more of the channel faults (STG, STB, CURRENT_HI, OPENDET and
RSTEMP) be set, the INVALID and NODATA bits are cleared.
7.1.2
RSU data fields and CRC
The remote sensor interface reports both data information and fault information in the
Remote Sensor Data Register (RSDRx). Independent data registers are defined for each
remote sensor interface and the data contained therein is formatted differently based on
whether a fault is detected. See SPI command in Remote sensor data/fault registers w/o
fault (RSDRx) on page 91.
The data available in the RSDRx register is separated into several bit fields. The Logical
Channel ID is a 4-bit field to identify the satellite sensor. The DATA bits are appended to the
LCID at the output of the Manchester decoder. The 3-bit CRC bit field is computed on the
entire data packet of fields, bits[16:0], which also includes the CHxON and FLTBIT. To
satisfy safety requirements, the LCID, DATA and CRC bit fields propagate through the same
data path as a single item to the SPI output.
The polynomial calculation implemented for PSI5 data is described as in PSI5 specification
g(x)=1+x+x^3 with the initialization value equal to "111".
Below are the equations to calculate the CRC in combinatorial way:
CRC[2] = CRCext[0]+D[0]+D[1]+D[3]+D[6]+D[7]+D[8]+D[10]+D[13]+D[14]+D[15]
CRC[1] = CRCext[2]+D[0]+D[1]+D[2]+D[4]+D[7]+D[8]+D[9]+D[11]+D[14]+D[15]+D[16]
CRC[0] = CRCext[1]+CRCext[0]+D[0]+D[2]+D[5]+D[6]+D[7]+D[9]+D[12]+D[13]+D[14]+D[16]
where D[16:0]= RSDR[16:0] and CRCext[n] are the starting seed values (all '1').
7.1.3
Detailed description
Manchester decoding
The Manchester decoder will support remote sensor communication as per PSI
specification rev 1.3 for the modes configurable via the STS bits in the RSCRx registers.
The Manchester Decoder checks the duty-cycle and period of the start bits to determine
their validity, depending on the configuration of the PERIOD_MEAS_DISABLE bit in the
RSCRx registers. The expected time windows for the mid bit transitions of each subsequent
bit within the received frame is determined by means of the internal oscillator time base.
Glitches shorter than 25% of the minimum bit time duration are rejected.
DocID029274 Rev 1
127/202
201
Remote sensor interface
L9678P, L9678P-S
Figure 34. Manchester decoder state diagram
5(6(7B'(&2'(5Æ
6WUREH 5(6(7B&17
,'/(
7
3(5,2'BB
6WUREH5(&B(1'
6WUREH 5(6(7B&17
FKHFN3$5,7<B(55
7
7
5,6,1*B('*(Æ
3(5,2'BB
6WUREH 5(6(7B&17
6WUREH5(6(7B&17
7
$1<DQG3(5,2'BB
6WUREH 5(6(7B&17
7D
7
$1<DQG
3(5,2'BBRUQRW ),567
:$,7
7*$3
%
%
6WUREH 0$1<%,76
6WUREH 5(6(7B&17
3HULRGBB
DQG$1<B('*(Æ
6WUREH5(6(7B&17
$
7E
(5525
3HULRGBBDQGQRW$1<B('*(
$
%
67$57%,7
'(7
(
&
7
'
ILUVWSXOVHGXW\F\FOHFKHFN
)$//,1*B('*(EHIRUHSHULRGBB Æ
6WUREH5(6(7B&17
7
7D
5,6,1*B('*(3HULRGBBÆ
3(5,2'BB DQG$1<
VWUREH&+(&.B7,0(
6WUREH5(6(7B&17
6WUREH5(6(7B&17
7E
3(5,2'BB DQGQRW$1<
VWUREH &+(&.B7,0(
7
$1<DQG
QRW 3(5,2'BB DQG
QRW ),567B('*(
6WUREH 5(6(7B&17
6WUREH &+(&.B7,0(
$
%
(
'$7$5(&
7
'
7
$1<DQG
3(5,2'BBDQG 67$7( &B1%
6WUREH 5(6(7B&17
6WUREH 1(;7%,7
'DWD)LOW
5,6,1*B('*(
)$//,1*B('*(
$1<
&B1%
67$7(
%LW&RXQWHU
3HULRGBB
3HULRGBB
3HULRGBB
),567B('*(
5,6,1*DQG3(5,2'BB
6WUREH5(6(7B&17
&
7
$1<DQG QRW3(5,2'BB DQG
3(5,2'BBDQGQRW 67$7( &B1%
6WUREH 5(6(7B&17
6WUREH1(;7%,7
)LOWHUHG5DZ'DWD 5;6$7IURP&XUUHQW'HPRGXODWRU DIWHUGHJOLWFKHU 'DWD)LOWQQ ³´
'DWD)LOWQQ ³´
5,6,1*B('*(RU)$//,1*B('*(
ELWIUDPHFRQILJXUDWHG "
^#,'/(#67$7%,7'(7#767$7(#7[( #:$,7[)#(5525`
5(6(7B&17"%LW&RXQWHU
%LW&RXQWHU! %LW3HULRG
%LW&RXQWHU! %LW3HULRG
%LW&RXQWHU! %LW3HULRG
3HULRGBB"$1<" ),567B('*(DIWHUDGHOD\RI7FN 5HPDUNQRWDFRPELQDWRULDOVLJQDO (QGRIPHVVDJHGHILQLWLRQIRUXVHLQWLPHVORWFRQWURO(20 7777D7E
*$3*36
128/202
DocID029274 Rev 1
L9678P, L9678P-S
Remote sensor interface
A Manchester Decoder Error occurs if one or more of the following conditions are true:

Two valid start bits are detected, and at least one of the expected 13 mid-bit transitions
are not detected

Two valid start bits are detected, and more than 13 mid-bit transitions are detected

When the number of bits decoded is incorrect (either too many or too few), a bit error is
indicated. When any bit error is detected (bit time, too many bits, too few bits), the
decoder will revert to the minimum bit time of the selected range and the message is
discarded.
All errors are readable through the Sensor Fault Status Register and the RSFLT bit in the
Global Status Word Register.
When a valid message is correctly decoded, the 10/8 data bits are stored into the
appropriate RSDRx register together with the related LCID. The RSDRx register contains
the 10/8 bits data as they are received from the sensor (no data range check/mask is done
at this stage). The 8-bit data word is right-justified inside the 10-bit data field in the RSDRx
registers.
Current sensor with auto-adjust trip current
The current sensor is responsible for translating the current drawn by the sensor into a
digital state (refer to Figure 35). Each satellite channel has a dedicated current sensor with
hysteresis.
Figure 35. Remote sensor current sensing auto adjust
2X3AT
)TRIP
)SAT
EGM!
M!
)BASE
M!
COUNT
—S
—S
'!0'03
The auto adjust feature uses a 7 bit D/A to converter to step up and down the threshold level
for detecting the base current through the remote sensor before start bits are transmitted.
Once start bits are received, the counter stops and the D/A value remains fixed until the
remote sensor message is received. This procedure is repeated for each cycle of the
remote sensor. The auto adjust circuit uses the following equation:
Ibase = Ioffset + (D/A counts) * 300 µA where Ioffset is fixed to 2.5 mA
DocID029274 Rev 1
129/202
201
Remote sensor interface
L9678P, L9678P-S
The converter default count value is 42, therefore,
Ibase = 2.5 mA + 42 * 300 µA
Ibase = 15 mA
Itrip = Ibase + threshold where threshold is a fixed at 12 mA
Thanks to this implementation, Ibase can span from 2.5 mA up to 41 mA covering PSI-5
specification range. As an example, for a remote sensor that operates at 10 mA base
current, Itrip = 23 mA.
7.2
Remote sensor interface fault protection
7.2.1
Short to ground, current limit
Each output is short circuit protected by an independent current limit circuit. Should the
output current level reach or exceed the ILIMTH for a time period greater than TILIMTH the
output stage is disabled and an internal up-down counter will count in 25 µs increment up to
TILIMTH. The filter time is chosen in order to avoid false current limit detection for in-rush
current that may happen at interface switch-on. When the output is turned off due to current
limit, the appropriate fault code STG is set in the Remote Sensor Data Register (RSDR).
The fault timer latch is cleared when the sensor channel is first disabled and then reenabled through the Remote Sensor Configuration Register (RSCR). This fault condition
does not interfere with the normal operation of the IC, nor with the operation of the other
channels. When a sensor fault is detected, the RSFLT bit of the GSW is set indicating a fault
occurred and can be decoded by addressing the RSFSR register.
In order to fulfil the blanking time requirement at channel activation as per PSI-5
specification, a dedicated masking time is applied to the current limitation fault detection
each time a channel is activated.
7.2.2
Short to battery
All outputs are independently protected against a short to battery condition. Short to battery
protection disconnects the channel from its supply rail to guarantee that no adverse
condition occurs within the IC. The short-to-battery detection circuit has input offset voltage
(10 mV, minimum) to prevent disconnecting of the output under an open circuit condition. A
short to battery is detected when the output RSUx pin voltage increases above VSUP
supply pin voltage for a TSTBTH time. An internal up-counter will count in 1.5 µs increment
up to TSTBTH. The counter will be cleared if the short condition is not present for at least
1.5 µs. Short to battery protection blocks the battery condition to guarantee that no adverse
condition occurs within the IC. The channel in short to battery is not shut down by this
condition. Other channels are not affected in case of short of one output pin. As in the case
previously described, the STB fault code can be read from RSDR bits and any fault will set
the RSFLT bit of the global status word register (GSW). The STB bit is cleared upon read.
7.2.3
Cross link
The device provides also the capability of a cross link check between outputs, in order to
reveal conditions where two output channels are in short. This functionality is allowed by
enabling one output channel, while asking for voltage measurement on any of the other
ones.
130/202
DocID029274 Rev 1
L9678P, L9678P-S
7.2.4
Remote sensor interface
Leakage to battery, open condition
The remote sensor interface offers detection of an open sensor condition. The autoadjusting counter for remote sensor current sensing will drop to 0 in case the current flowing
through RSUx pin is lower than 3 mA. The OPENDET fault flag is asserted when the fault
condition lasts for longer than TRSUOP_FILT deglitch filter time. This fault flag can be read
from RSDR bits and any fault will set the RSFLT bit of the global status word register
(GSW). The channel in this condition is not shutdown.
7.2.5
Leakage to ground
The sensor interface offers as well the detection of a leakage to ground condition, that will
possibly raise the sensor current higher than 36 mA. The CURRENT_HI fault flag is
asserted when the fault condition lasts for longer than TRSUCH_FILT deglitch filter time. This
fault flag can be read from RSDR bits and any fault will set the RSFLT bit of the global status
word register (GSW). The channel in this condition is not shutdown.
7.2.6
Thermal shutdown
Each output is protected by an independent over-temperature detection circuit. Should the
remote sensor interface thermal protection be triggered the output stage is disabled and a
corresponding thermal fault is latched and reported through the RSTEMP flag in the Remote
Sensor Data Register (RSDRx). The thermal fault flag is cleared when the sensor channel is
first disabled and then re-enabled through the Remote Sensor Configuration Register
(RSCRx).
DocID029274 Rev 1
131/202
201
Watchdog timer
8
L9678P, L9678P-S
Watchdog timer
This device offers a watchdog implementation by means of a temporal WD. Window times
are SPI programmable and a couple of specific codes has to be written within this window in
order to serve the WD control.
8.1
Temporal watchdog
The temporal watchdog ensures the system software is operating correctly by requiring
periodic service from the microcontroller at a programmable rate. This service (watchdog
refresh) must occur within a time window, and if serviced too early or too late will enter an
error state (WD1_ERROR) reported via the WD1_WDR bit of the FLTSR register.
The overall WD1 functionality is described in the state diagram reported in Figure 36.
Figure 36. Watchdog state diagram
:60B5HVHW
)URPDQ\VWDWH
:'B/2&.287 :'B:'5 :'B(55B&17 :'B(55B7+B:( :'770!9:'B29(55,'( $1'
63,:'B7(67
:'B/2&.287 PV
:'B:'5 PV$1'
:'B7295 :'B/2&.287 :'B(55B&17
:'5(6(7
:'B(5525
:'B/2&.287 :'B(55B&17
:'
29(55,'(
:',1,7,$/
:'581
:'UHIUHVK2. :'UHIUHVK2. :'B:'5 :'B(55B7+B:( ,I:'B(55B&17:'B(55B7+
:'B/2&.287 63,:'B7(67
:'7(67
:'B(5525
'!0'03
132/202
DocID029274 Rev 1
L9678P, L9678P-S
Watchdog timer
Following the description of the above states:
Table 9. Watchdog timer status description
State/Signal
WD1 INITIAL
Description
Default state entered from startup. While in this state, no watchdog service is
required, and the IC may stay in this state indefinitely. For system safety, all
arming signals are disabled during this state to prevent deployment.
WD1 RUN
Normal run-time state where WD1 service is required.
WD1 TEST
A special state used to test the watchdog function. Normally, this state will only
be checked once per power cycle by the software, but there is no inherent
restriction in the watchdog logic preventing periodic testing. This state allows
testing of the watchdog refresh function without setting WD1_LOCKOUT=1,
which can only be cleared via WSM reset. Deployment is inhibited when the
WD state machine is in this state.
WD1 RESET
State entered when a WD1_ERROR occurs. This is a timed-duration state that
is automatically exited after 1ms.
WD1 OVERRIDE
A special state used to disable watchdog functionality for development
purposes. Other logic within the IC can use this state to emulate the WD1 RUN
state without the need to service WD1.
WSM_RESET
Signal used to reset the WD1 state machine to the WD1 INITIAL state and all
signals to their inactive values
WD1_refresh OK
Signal that is asserted only if the watchdog is refreshed ('A' - 'B' or 'B' - 'A' seq.)
within the WD1 time window
WD1_ERROR
WD1_WDR
Signal that is asserted if the watchdog refresh fails to occur during the WD1
time window.
Watchdog Reset – latched signal that is activated whenever a watchdog error
is qualified. For WD1, this occurs when WD1 service is required, but not
received. This signal is SPI-readable.
WD1_TM
Test Mode – a signal that indicates that WD1 is being tested. This signal is
SPI-readable.
WD1_LOCKOUT
A latched signal activated if an unexpected WD1 error occurs. This signal is
permanently latched when set (until WSM_RESET). When set, all arming
signals are disabled, preventing deployment. This signal is SPI-readable.
SPI_WD1_TEST
SPI command used to enter WD1 TEST state from WD1 RUN state, or to enter
WD1 OVERRIDE state from INITIAL state if WDT/TM pin voltage is greater
than the threshold. This command has no effect in other states.
WD1_ERR_CNT
Retry counter to let the microcontroller fails multiple times before set
LOCKOUT and prevent deployment.
WD1_ERR_TH
SPI configurable threshold for the retry counter.
WD1_ERR_TH_WE Signal to lock the writing of WD1_ERR_TH when watchdog entered RUN state.
A single SPI command (WD_TEST) is used to activate test states for the watchdog circuitry.
DocID029274 Rev 1
133/202
201
Watchdog timer
8.1.1
L9678P, L9678P-S
Watchdog timer configuration
The watchdog timer can be configured on two different frequency modes:

Fast watchdog with maximum range of 2 ms and a resolution of 8 µs;

Slow watchdog with maximum range of 16.3 ms and a resolution of 64 µs.
The watchdog window times are SPI programmable. The configuration of watchdog timer
frequency and window times can be done by setting the Watchdog Timer Configuration
Register (WDTCR) with the appropriate values. However, this configuration is accepted only
when the device is in the Init operating state, as shown in Figure 9. As soon as the Diag
state is entered, the watchdog control is enabled and the watchdog configuration is fixed
and cannot be changed anymore.
8.1.2
Watchdog timer operation
While in the WD1_INITIAL state, watchdog service must begin or a SPI command with
WD1_TOVR=1 must be received within the first 500 ms. If the WD1 timer override bit is set,
the device can stay in the WD1_INITIAL state indefinitely without watchdog service.
To refresh WD1, the logic must receive a Watchdog Timer Register (WD1T) SPI command
containing the expected key value within the WD1 time window (WDTMIN+WDTDELTA). If it
is received too early or too late the WD1_ERROR signal will be asserted. The
WD1_ERROR will not be asserted in case a SPI command containing the Watchdog Timer
Register (WD1T) with an incorrect key value is received at any time relative to the window
(WDTMIN+WDTDELTA). This allows the system software to repeatedly transmit the key
value until it needs to change to the correct key value.
Upon reception of the correct key value within the window, the logic will reset the watchdog
timer to create a new window.
The timer is cleared upon writing code 'A' and code 'B' (either in 'A' - 'B' or 'B' - 'A'
sequences) to the WD1CTL[1:0] bits, in the WD1T register. The watchdog timer value can
be read via the WD1T register.
134/202
DocID029274 Rev 1
L9678P, L9678P-S
Watchdog timer
Figure 37. Watchdog timer refresh diagram
660B5(6(7
:',1,7
63,B:'B%
63,B:'B$
:'$
:'%
:'%
705!0,1
63,B:'B$
705 6WUREH:'UHIUHVK2.
:'$
705!0,1
63,B:'B%
705 6WUREH:'UHIUHVK2.
705!0$;25
>7050,163,B:'B$@
705!0$;25
>7050,163,B:'B%@
:'B(5525
'!0'03
8.2
Watchdog reset assertion timer
Upon a watchdog reset, the watchdog logic will momentarily assert the RESET pin for time
duration twdrst. When the RESET pin has been asserted through the watchdog reset
assertion timer, stored faults are maintained and can be read by the microcontroller via SPI
following the RESET period.
8.3
Watchdog timer disable input (WDT/TM)
This input pin has a passive pull-down and is used to disable the watchdog timer. The state
of this pin can be read by SPI through the WDTDIS_S bit in the GSW register. When
WDT/TM pin is asserted, the watchdog timer is disabled, the timer is reset to its starting
value and no faults are generated.
DocID029274 Rev 1
135/202
201
DC sensor interface
9
L9678P, L9678P-S
DC sensor interface
L9678P implements a circuitry able to interface with a variety of positioning sensors. The
sensors that can be connected to the device are Hall-effect, resistive or simple switches.
Range of measurements is:

Resistive sensor: 65 Ω to 3 kΩ

Hall-effect sensor: 2 mA to 20 mA.
Within the above ranges, accuracy of ±15% is granted. A reduced accuracy is given in the
range 1 mA to 2 mA.
Hall sensor and switch interface block diagram is shown below.
Figure 38. Switch sensor interface block diagram
95(6',$*
%ORFNVVKDUHG PXOWLSOH[HG
DPRQJWKHWKHGLIIHUHQWFKDQQHOV
9%*
5
,'&6
$[5
,OLP
5
9,179
5
,'&6
5
'&6[
5
,UHI
Q)·Q)
/9DQDORJPX[
9*1' ц9
9LQ
ELWV
9UHI
9UHI Y
'LJLWDOZRUG '&[YROWDJHSLQ RU,6$7
2SHQORDGLI,RXW '&[ORZHUWKDQP$
'!0'03
The global SPI contains several bits to control and configure the interface. The SWOEN bit
is used to enable the output voltage on DCSx pins. The channel to be activated can be
chosen by setting CHID bits accordingly. The interface activation is completely controlled by
user SPI command. The interface could be optionally configured for "automatic switch-off"
immediately after the current or resistance measurement completion by setting the
EN_AUTO_SWITCH_OFF bit in the SYS_CFG register.
136/202
DocID029274 Rev 1
L9678P, L9678P-S
DC sensor interface
The voltage and current for the selected channel are made available to the main ADC by
selecting the proper channel and enabling the measurement process by dedicated
DIAGCTRLx commands.
The device offers the capability to actively keep all the DCSx lines discharged by means of a
weak pull down. The pull down is active by default on all channels and it comes to be
deactivated in either of the following cases:
1.
when the voltage source is active on the relevant channel
2.
when a voltage measurement is requested on the relevant channel
3.
if SPI bit SWCTRL(DCS_PD_CURR) is set (global pull-down disable for all channels)
In case of Hall-effect sensors, a single current measurement is processed. The current load
needed for regulating the pin is internally reflected to a reference resistance, whose voltage
drop is then measured through the internal ADC converter.
When resistive or switch sensors are used, a more complex measurement is performed. In
a first step the current information as above described is provided. Then, also the
information on the voltage level achieved on the output pin is provided via ADC. By
processing these two values, the micro-controller can understand the resistive value. The
DCSx voltage is internally rescaled by a voltage divider into the ADC converter voltage
range as shown in Figure 38. Additionally a positive voltage offset is internally applied to the
scaled voltage in order to allow voltage measurement capability for DCSx down to -1V.
In order to have accurate resistive information even in case of an external ground voltage
shift on the sensor of up to ±1V, the voltage measurement step actually needs two DCSx
voltage measurements. A first voltage measurement has to be done with selection of 6.25 V
on the output channel and a second one with the regulator switched off. The difference
between the two measurements will cancel out the offsets (both external ground shift and
internal offset).
The DCSx current and voltage can be retrieved from ADC readings according to the
following formulas and related parameters specified in Section 15.19: DC sensor interface
and Section 15.23: Voltage diagnostics (analog Mux):
ADC REF_hi
1
I DCSx = ------------------------------------  -------------------------------  DIAGCTRLn  ADCRESn  
ADC RES
R REF1_IDCSx

2

@DIAGCTRL(ADCREQn) = $04
 ADC REF_hi

V DCSx = RATIO VDCSx   -------------------------------  DIAGCTRLn  ADCRESn  – V OFF_DCSx 
ADC
RES
 2



@DIAGCTRL(ADCREQn = $03
The DCSx sensor resistance can be calculated according to the following formula:
V DCSx @(SWCTRL(SWOEN)=1 – V DCSx @(SWCTRL(SWOEN)=0
V DCSx
R sensor = ---------------------- = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 
I DCSx
I DCSx
x


@SWCTRL(CHID) = x
DocID029274 Rev 1
137/202
201
DC sensor interface
L9678P, L9678P-S
The device provides also the capability of a cross link check between outputs, in order to
reveal conditions where two output channels are in short. This functionality is allowed by
enabling one output channel, while asking for voltage measurement on any of the other
ones.
All parametric requirements for this block can be found in specification tables.
Each output is protected against
138/202

Overload conditions by current limit

Ground offset between the ECU and the loads of up to ±1 V.

Loss of ECU battery

Loss of ground

Shorts to ground
DocID029274 Rev 1
L9678P, L9678P-S
Safing logic
10
Safing logic
10.1
Safing logic overview
The integrated safing logic uses data from on-board and remote locations by decoding the
various SPI communications between the interfaces and the main microcontroller. The
safing logic has several programmable features enabling its ability to decode SPI
transmissions and can process data from up to 4 sensors. The operating mode involves
simple symmetrical data threshold comparisons, with the use of symmetrical or
asymmetrical counters. A high level diagram is shown in the figure below. Please note that
this top-level diagram is simplified, and references to more detailed flowcharts to show a)
message decoding, b) valid data limits, c) effects of the 'combine' function, d) comparison to
thresholds and arming, and e) the setting of the 'compare complete bit. Two independent
arming outputs, ARM1INT and ARM2INT, are also mapped internally to any of the
integrated squib drivers.
Figure 39. Top level safing engine flow chart
'&8,&6DILQJ/RJLF
7RS/HYHO
67$57
1
63,B06*
5HFHLYHG"
<
&6B*
63,B6$)B&&
5HDG"
<
1
&KHFNVZKHWKHUUHTXHVWDQGUHVSRQVH
DUHJRRGIRUHDFKELWVDILQJUHFRUG
WDNLQJLQWRDFFRXQW,)ELW'HWHUPLQHV
'$7$WDNLQJLQWRDFFRXQW63,)/'6(/
ELW
&KHFNVZKHWKHUUHTXHVWDQGUHVSRQVH
DUHJRRGIRUHDFKELWVDILQJUHFRUG
WDNLQJLQWRDFFRXQW,)ELW
8SGDWHVHYHQWFRXQWHUV
LIQRGDWDUHFHLYHG
FOHDUV&&ELWV
$
*
06*'(&
&&B5($'
%
+
%
VHW$50,17DQG
$50,17PDQDJHGZHOO
WLPHUV
$50,1*
06*'(&
&
&KHFNVZKHWKHUGDWDLVZLWKLQUDQJHLI
FRQILJXUHG
&
9$/'$7
'
&RQYHUWVGDWDWREHFRPSDUHGLQWR
FRPELQHGGDWDVXPDQGGLIIHUHQFHLI
FRQILJXUHG
'
&20%,1(
(
(
&RPSDUH'$7$WRWKUHVKROGV XSGDWH
HYHQWFRXQWHUV
&203$5(
)
'!0'03
DocID029274 Rev 1
139/202
201
Safing logic
10.2
L9678P, L9678P-S
SPI sensor data decoding
Sensor data is regularly communicated with the main microcontroller through multiple SPI
messages. Since not all communications between sensors and the microcontroller contain
data, it is important for the decoder to properly sort the communications and extract only the
targeted data. The solution involves defining specific masking functions, contained within
independent safing records, programmed by the user. The following figures detail the SPI
message decoding methodology and the ensuing comparisons of valid sensor data to the
programmed thresholds.
Figure 40. Safing engine - 16-bit message decoding flow chart
06*'(&
$
L 6DILQJ5HFRUGLQGH[
65
65
65
65
L (1B6$)L
"
1
<
1
&&>L@ "
<
&6>L@ FVBDFWLYH"
1
<
,)>L@ "
1
UHTBRN>L@
"
<
1
<
63,)/'6(/>L@"
QG
63,)/'6(/>L@"
VW
VW
1
QG
5(637$5*>L@
VW>0,62@
5(630$6.>L@
5(637$5*>L@
QG>0,62@
5(630$6.>L@
PDWFK>L@ UHTBRN>L@ <
<
GDWDUHVXOW>L@ VW>0,62@
'$7$0$6. >L@
1
1
5(637$5*>L@
QG>0,62@
5(630$6.>L@
<
<
GDWDUHVXOW>L@ VW>0,62@
'$7$0$6. >L@
GDWDUHVXOW>L@ QG>0,62@
'$7$0$6. >L@
PDWFK>L@ 5(637$5*>L@
VW>0,62@
5(630$6.>L@
1
PDWFK>L@ UHTBRN>L@ GDWDUHVXOW>L@ QG>0,62@
'$7$0$6. >L@
PDWFK>L@ 5(47$5*>L@
06>026,@
5(40$6.>L@"
PDWFK>L@ PDWFK&&>L@ UHTBRN>L@ 1
<
PDWFK>L@ PDWFK&&>L@ 5(47$5*>L@
06>026,@
5(40$6.>L@"
PDWFK>L@ 1
<
L
1
L 1"
<
140/202
UHTBRN>L@ UHTBRN>L@ 1 /
1 /
1 /
%
2XWSXWVWR9$/'$7IXQFWLRQ GDWDUHVXOW>L@
UHTBRN>L@
PDWFK>L@
DocID029274 Rev 1
'!0'03
L9678P, L9678P-S
Safing logic
Figure 41. Safing engine - 32-bit message decoding flow chart
06*'(&
%
L "
<
1
L 1"
L UHFRUGV
1 /
1 //
<
1
(1B6$)L
"
L 6DILQJ5HFRUGLQGH[
65
65
65
65
/VNLSVELW
&
1
2XWSXWVWR9$/'$7IXQFWLRQ GDWDUHVXOW>L@
PDWFK>L@
<
1
&&>L@ "
<
&6>L@ FVBDFWLYH"
1
<
,)>L@ "
1
1
<
UHTBRN>L@
"
<
UHTBRN>L@ 5(637$5*>L@
0,62
5(630$6.>L@
5(637$5*>L@
0,62
5(630$6.>L@
1
<
<
GDWDUHVXOW>L@ 0,62
'$7$0$6. >L@
0DWFK>L@ GDWDUHVXOW>L@ 0,62
'$7$0$6. >L@
5(47$5*>L@
026,
5(40$6.>L@"
5(47$5*>L@
026,
5(40$6.>L@"
1
<
PDWFK>L@ 1
PDWFK>L@ 1
<
PDWFK>L@ PDWFK>L@ UHTBRN>L@ UHTBRN>L@ L
*$3*36
DocID029274 Rev 1
141/202
201
Safing logic
L9678P, L9678P-S
Figure 42. Safing engine - validate data flow chart
9$/'$7
&
L 6DILQJ5HFRUGLQGH[
65
65
65
65
L 0DWFK>L@ &20%>L@ <
1
1
&KHFNVIRUFRPELQDEOH
UHFRUGV
= /
= /
= /
L=
&20%>L@ <
&KHFNVIRURGGLQGLFHV
1
0RGL
<
1
0DWFK>L@ 0DWFK&&>L@ <
1
0DWFK>L@ 0DWFK&&>L@ <
&&>L@ 1
&&>L@ "
<
<
/,0(1>L@ "
1
/,06(/>L@ "
<
1
$EV
GDWDUHVXOW>L@
G"
$EV
GDWDUHVXOW>L@
G"
1
1
<
<
YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ L L
<
1
L 1
142/202
L /"
L 1"
1 /
1 /
1 /
<
'
DocID029274 Rev 1
2XWSXWVWR&20%,1(IXQFWLRQ
&&>L@
YDOGDW>L@
YDO&&>L@
*$3*36
L9678P, L9678P-S
Safing logic
Figure 43. Safing engine - combine function flow chart
'
&20%,1(
L 6DILQJ5HFRUGLQGH[
65
65
65
65
L 9DO&&>L@
YDO&&>L@
"
1
<
&20%>L@ "
1
<
WHPS GDWDUHVXOW>L@
GDWDUHVXOW>L@ WHPSGDWDUHVXOW>L@
1
&20%>L@ "
<
WHPS GDWDUHVXOW>L@
GDWDUHVXOW>L@ WHPS
GDWDUHVXOW>L@
L L
1
L 1"
1 /
1 /
1 /
<
(
2XWSXWVWR&203$5(IXQFWLRQ
GDWDUHVXOW>L@
&&>L@
FRPS>L@
DocID029274 Rev 1
'!0'03
143/202
201
Safing logic
L9678P, L9678P-S
Figure 44. Safing engine threshold comparison
(
&203$5(
L 1
9DOGDW>L@
"
1RPDWFKFDVH
<
1
PDWFK>L@ "
1
GDWDUHVXOW>[email protected]
6$)B7+5(6+>L@
GDWDUHVXOW>[email protected]
6$)B7+5(6+>L@
<
1
'DWDRXWRI
UDQJHFDVH
326B&2817>L@
326B&2817>L@
68%B9$/
326B&2817>L@
"
1(*B&2817>L@
1(*B&2817>L@
$''B9$/
1
1(*B&2817>L@
1(*B&2817>L@
68%B9$/
1(*B&2817>L@
"
<
<
326B&2817>L@ 1
12B'$7$ >L@
"
<
326B&2817>L@
326B&2817>L@
$''B9$/
<
<
1
326B&2817>L@
326B&2817>L@
68%B9$/
1(*B&2817>L@
1(*B&2817>L@
68%B9$/
1(*B&2817>L@ 1(*B&2817>L@
"
326B&2817>L@!
$503B7+"
1
1(*B&2817>L@!
$501B7+"
<
1
1
1(*B&2817>L@ $501B7+
326B&2817>L@
"
1
<
1(*B&2817>L@ <
326B&2817>L@ $503B7+
1(*B&2817>L@ 326B&2817>L@ <
326B&2817>L@ 0DWFK>L@ YDOGDW>L@ L L
<
L /"
1
L 1
L 1"
1 /
1 /
1 /
<
)
'!0'03
144/202
DocID029274 Rev 1
L9678P, L9678P-S
Safing logic
Figure 45. Safing engine - compare complete
*
&&B5($'
L <
&&>L@ "
1
1
12B'$7$ >L@
"
<
326B&2817>L@
326B&2817>L@
68%B9$/
1(*B&2817>L@
1(*B&2817>L@
68%B9$/
1(*B&2817>L@
"
1
1(*B&2817>L@ 326B&2817>L@
"
1
<
1(*B&2817>L@ <
326B&2817>L@ 326B&2817>L@ &&>L@ YDO&&>L@ PDWFK&&>L@ L
<
L 1
L /"
<
1
L 1"
1 /
1 /
1 /
<
+
2XWSXWV
&&>L@
PDWFK>L@
PDWFK&&>L@
326B&2817>L@
1(*B&2817>L@
DocID029274 Rev 1
'!0'03
145/202
201
Safing logic
L9678P, L9678P-S
Each safing record has SPI accessible registers defined in the SPI command tables and
summarized below:

Request Mask and Request Target - to understand what sensor the microcontroller is
addressing

Response Mask and Response Target - to identify the sensor response
–
Data Mask - to extract relevant sensor data from the response. Sensor data is
extracted as a bit-wise AND result of the SAF_DATA_MASKx and monitored
SPI_MISO data
–
The extracted data is then right-justified into a 16-bit register for 16-bit safing
records, respectively, prior to further processing steps which assume data is
signed - two-s complement represented

Safing Threshold - specific value that sets the comparator limit for successful arming

Control:
–
IF, In Frame - to indicate serial data response is "in frame". There are two types of
potential serial data responses, "in-frame" and "out of frame"
–
CS - to align safing record with a specific SPI CS. The device contains 2 SPI CS
inputs for the safing function (SAF_CS0 and SAF_CS1)
–
ARM - there are two internal arming signals, each active record is assigned or
mapped to any arming signal. Several safing records can be mapped to a single
arming output
–
Dwell - Once an arming condition is detected, the safing record remains armed for
the specified dwell time
–
Comb (Combined Data) - specific solution for dual axis high-g sensors specifically
oriented off-axis
–
Lim En (Limit Enable) - to enable PSI5 out-of-range control
–
Lim Sel (Limit Select) - to select PSI5 out-of-range thresholds between 8-bit and
10-bit protocol
–
SPIFLDSEL (Spi Field Select) – to determine which 16-bit field in long SPI
messages (>31 bit) to use for response on MISO of SPI monitor. If the
SPIFLDSEL bit is set to 0 the message bits from 0 (first bit received) to 15 are
processed, while if set to 1 the message bits from 16 to 31 are processed.
SPIFLDSEL bit will not help L9678P device to work with sensor that places data
across this boundary or has response and data in separate 'fields'.
In case of message less than 32-bit, always the first 16bits received will be
processed regardless of the SPIFLDSEL value.
If input packet matches multiple safing records, the safing engine should process all of them
and treat them independently.
Safing record can only be evaluated on the first matching input packet. Any further data
packet matches are ignored (i.e. once CC is set, record can't be processed until is cleared).
The En (Record Enable) bit for any record is programmable as on or off at any time and will
enable/disable the record itself upon the following sensor sampling period.
All CC bits are available in one register (SAF_CC) for access in one single SPI read.
Safing Engine must not process sensor data in any state but Safing state (refer to Figure 9).
All safing records are cleared on SSM RESET.
146/202
DocID029274 Rev 1
L9678P, L9678P-S
Safing logic
Comb (Combined Data) bit allows combining X and Y for off-axis oriented sensors. In this
case, it is typical for such orientations to add or subtract the sensor response to translate the
sensor signal to an on-axis response. Only couples of 16-bit long records have this feature
(i.e. 1&2, 3&4).
Records are added and subtracted and results compare against two thresholds. Safing
engine will process data as follows:

Use record (n) and record (n+1), where n = 1, 3.

The matching inputs used for math combinations are processed only after both records
are captured.

The sum of the two matching inputs will be compared to the threshold of record (n).

The difference of the two records will be compared to the threshold of record (n+1).

If the Comb feature was enabled on only one of the two records in a couple, math
would be performed only on it as shown in Figure 43.
Example:
Table 10. Records results comparison against two threshold
Combine Bit
Data
Resulting
Value
Record
Threshold
(assume ARMP)
ARMing Result
Record 1
0
12
12
48
0
Record 2
0
50
50
48
1
Record 3
0
12
12
48
0
Record 4
1
50
50 – 12 = 38
48
0
Record 1
1
12
12 + 50 = 62
48
1
Record 2
0
50
50
48
1
Record 3
1
12
12 + 50 = 62
48
1
Record 4
1
50
50 – 12 = 38
48
0
In this example the ARM and dwell assignments for record1 only would be asserted.
All items in the safing records, except En(Record Enable) bit, can be configured only in Diag
state (refer to Figure 9). Additionally, the global bit to select internal or external safing
engine is set in Diag state.
DocID029274 Rev 1
147/202
201
Safing logic
10.3
L9678P, L9678P-S
In-frame and out-of-frame responses
Some sensors will communicate data within the current communication frame while others
will send data on the next communication frame. Sometimes this is sensor specific and
sometimes this is due to the amount of data to be transmitted. A simplified diagram shows
the basic communication differences of in and out of frame responses.
Figure 46. In-frame example
-/3)
2EQUESTN
-)3/
3TATUS
5NUSED
2ESPONSEN
'!0'03
Figure 47. Out of frame example
-/3)
2EQUESTN
2EQUESTN
-)3/
2EQUESTN
2ESPONSEN
'!0'03
Synchronization between clock domains relies upon inter-frame gap.
10.4
Safing state machine operation
State machine operation is disabled when the safing state machine reset signal is active as
described in the power supply diagnostics and controls section of this document. The
outputs of the state machine are ARM1INT and ARM2INT. As previously stated, there is a
maximum of 4 safing records available to the state machine. Inputs to the safety state
machine are programmed safing records and sensor data. The configuration of the state
machine is common to all sensors.
10.4.1
Simple threshold comparison operation
In this mode, sensor data received through the sensor SPI interface and validated by the
safing record is passed to the safing algorithm. The simple threshold comparison algorithm
compares the received data to two thresholds, SAF_TH (positive threshold) and (-SAF_TH)
(negative threshold). If the sensor data is greater than SAF_TH or is less than (-SAF_TH)
then and event is flagged and the event counter is incremented based on the programmed
value of ADD_VAL. If sensor data does not trigger the SAF_TH comparators, the counter is
decremented by SUB_VAL. SUB_VAL is programmed by the user and can be the same as
or different from ADD_VAL. This feature allows for an asymmetrical counter function making
the system either more or less sensitive to sensor data. Since sensor data can indicate a
positive or negative event, the algorithm maintains separate event counters, POS_COUNT
and NEG_COUNT. The ADD_VAL and SUB_VAL programmed values are the same for all
safing sources.
On each sensor sample, the event counters, both POS_COUNT and NEG_COUNT, are
updated. Each event counter is then compared with a corresponding arming threshold. In
this case, POS_COUNT value is compared to ARMP_TH and NEG_COUNT to ARMN_TH.
ARMP_TH and ARMN_TH are programmable thresholds set by the user. The compared
result will set ARMP and ARMN to either "1" or "0" depending on the comparison status. If
148/202
DocID029274 Rev 1
L9678P, L9678P-S
Safing logic
ARMP_TH or ARMN_TH are set to 0, the arming will be activated immediately entering in
safing state.
POS_COUNT and NEG_COUNT are not updated if microcontroller stops reading SAF_CC
bits (this must be avoided otherwise ARMING set and reset will not be possible).
By way of the assignment of the ADD_VAL, SUB_VAL, ARMP_TH and ARMN_TH settings,
the safing engine can be configured to assert arming for either a simple accumulation of
COUNTs in a non-consecutive manner, or it could be set to require some number of
consecutive samples.
10.5
Safing engine output logic (ARMxINT)
SPI messages are monitored and mapped to specific safing records. Each safing record is
configured with its own threshold, dwell time and the appropriate ARMxINT internal signal to
activate if safing criteria are met.
Any enabled safing record can be programmed to an arming signal. All safing records
arming status is logically "OR'd" to its programmed arming signal. For example, if safing
records 1, 2, 4 are programmed to ARMINT1 and the records are enabled, any of the
records can set the ARMINT1 signal. Configuration of safing record mapping to ARMxINT
signals is specified in the SAF_CONTROL_x register (refer to Safing control registers
(SAF_CONTROL_x) on page 106).
While in Diag state, L9678P allows diagnostics of the squib driver HS and LS FETs, ARM
pin, VSF output and firing timers. The ARM and VSF output tests are mutually exclusive.
For safety purposes, the safing logic circuitry is physically separated from the circuitry that
contains the deployment logic.
DocID029274 Rev 1
149/202
201
Safing logic
L9678P, L9678P-S
Figure 48. Safing Engine Arming flow diagram
67$57
L 1
326B&2817>L@
! $503B7+"
1(*B&2817>L@
! $501B7+"
<
$503 1
<
$503 $501 $506(/>L@
RU"
$506(/>L@
RU"
<
$501 1
<
1
7,0(5B&17[LVDELW
GRZQFRXQWHUDOZD\V
UXQQLQJDWPV
1
$50>L@ 7,0(5B&17
':(//>L@
$50>L@ 7,0(5B&17
':(//>L@
<
1
7,0(5B&17[FRQWURO
H[WHQGVWRIRUKLJKPLG
<
7,0(5B&17
':(//>L@
7,0(5B&17
':(//>L@
L
7,0(5B&17
!"
1
L 1"
7,0(5B&17
!"
<
1
$50[,17FRQWUROH[WHQGV
WRIRUKLJKPLG
<
$50,17 1 /
1 /
1 /
1
$50,17 $50,17 $50,17 <
*$3*36
150/202
DocID029274 Rev 1
L9678P, L9678P-S
Safing logic
Figure 49. Safing engine diagnostic logic
6&/.B*
026,B*
0,62B*
&6B*
6$)B&6
6$)B&6
63,'HFRGH
7KUHVKROG
&RPSDUH
3XOVH
6WUHWFK
'67(6796)
',$*67$7(
$50,17
'67(67$50
'67(6738/6(
&+38/6(
&+38/6(
&+38/6(
&+38/6(
$50,17
$50,1*67$7(
'!0'03
A configurable mask for each internal ARMxINT signal is available for all of the integrated
deployment loops (refer to ARMx assignment registers (LOOP_MATRIX_ARMx) on
page 97). The un-masked ARMxINT signal for each loop will enable the respective loop
drivers (refer to Figure 21).
Activation of VSF (regulation rail for High Side Safing FET) occurs upon ARMxINT or
FENH/FENL, depending on SPI configuration (refer to Figure 17). Actual High Side Safing
FET activation still requires microcontroller signal.
L9678P is able to provide arming signals to external deployment loops by means of the
discrete output ARM pin. The ARM pin can either output an arming signal generated by the
integrated safing engine or an arming signal made by the combination of FENH and FENL
input signals, coming from external safing logic.
Figure 50. ARM output control logic
:'B581
:'B/2&.287
660B5(6(7
$50B(1
:'B29(55,'(
$50,17
6DILQJ
(QJLQH
$50,17
$50
)(1/
)(1+
6$)(6(/
'!0'03
DocID029274 Rev 1
151/202
201
Safing logic
10.6
L9678P, L9678P-S
Arming pulse stretch
Upon a valid command processed by the safing logic, the Dwell bits to stretch the arming
time assertion (dwell time) apply to each safing record and is used to help safe the
deployment sequence to avoid undesired behaviour.
Once dwell time has started, it will continue, regardless of the En (Record Enable) bit. Dwell
will be truncated in case of SSM reset. Dwell values in the safing records are transferred to
the ARM signal. A dedicated counter is designed for ARM output pin. If different dwell
values are assigned to ARM, the longer value is used. Dwell times can only be extended,
not reduced. If the remaining dwell time is less than the new dwell extension setting, the
new setting will be loaded into the dwell counter.
Dwell times are user programmable.
The behavior of the pulse stretch timer is shown in Figure 51.
Figure 51. Pulse stretch timer example
$UPLQJ6DILQJ/RJLF
3URFHVVHGUHVXOW
$UPLQJ(QDEOH
3XOVH6WUHWFK
3XOVH6WUHWFK7LPH
/HVV7KDQ3XOVH
6WUHWFK7LPH
3XOVH6WUHWFK
7LPH
'!0'03
10.7
Additional communication line
The ACL pin is the Additional Communication Line input that provides a means of safely
activating the arming outputs (ARM and VSF) for disposal of restraints devices at the end of
vehicle life.
A valid ACL detection (as described below) allows L9678P to transition from Scrap state to
Arming state. To remain in Arming state L9678P must receive the correct ACL signal; this
must occur before the scrap time-out timer expires (TdisEOL).
While the System Operating State Machine is in Arming state, the arming outputs are
asserted (ARM=1, VSF on). If the ACL is not correctly received before the time-out expires,
the System Operating State Machine reverts back to the Scrap state, and the arming
outputs are deactivated.
152/202
DocID029274 Rev 1
L9678P, L9678P-S
Safing logic
Figure 52. Scrap ACL state diagram
660B5
(6(725
1276&5$3VWDWH$1'127$50,1*VWDWH
$&/*22' $&/%$' $&/705 5LVLQJHGJH
$&/705 $&/*22' $&/%$'
$&/705!SHULRGPLQ
ULVLQJHGJH
$&/*22'
$&/%$' $&/705 $&/+,*+
)DOOLQJHGJH
$&/705!KLJKPLQ
$&/705!KLJKPD[25
)DOOLQJHGJH$&/7,0(5
KLJKPLQ
$&//2:
$&/705!SHULRGPD[
$&/*22' $&/%$'
$&/705 5LVLQJHGJH25
$&/705!SHULRGPD[
$&/705 $&/*22' $&/%$'
$&/(5525
'!0'03
A specific waveform needs to be present on this input in order to instruct L9678P to arm all
deployment loops. L9678P is designed to support the Additional Communication Line (ACL)
aspect of the ISO-26021 standard, which requires an independent hardwired signal (ACL) to
implement the scrapping feature. The disposal signal may come from either the vehicle's
service connector, or the systems main microcontroller, depending on the end customer's
requirements.
The arming function monitors the disposal PWM input (ACL pin) for a command to arm all
loops for vehicle end-of-life airbag disposal. The disposal signal characteristic is shown in
Figure 53. To remain in Arming state, at least three cycles of the ACL signal must be
qualified. For the device to qualify the periodic ACL signal, the period and duty cycle are
checked. Two consecutive cycles of invalid disposal signal are to be received to disqualify
the ACL signal.
Figure 53. Disposal PWM signal
&\FOHWLPH
2QWLPH
'!0'03
The disposal PWM signal cycle time and on time parameters can be found in the electrical
parameters tables.
DocID029274 Rev 1
153/202
201
General purpose output (GPO) drivers
11
L9678P, L9678P-S
General purpose output (GPO) drivers
The L9678P contains two GPO drivers configurable either as high-side or low-side modes,
controlled in ON-OFF mode or in PWM mode setting the desired duty cycle value through
the GPO Control Register (GPOCTRLx).
For low side driver configuration, the GPODx pin is the equivalent drain connection of the
internal MOSFET and it is the current sink for the output driver. The GPOSx pin is the
source connection of the GPO driver and is externally connected to ground.
Figure 54. GPO driver block diagram - LS configuration
9%DWW
6HO*32'[
ELWV
9LQ
*32)/765 *32[',6$%/( 9UHI
63,:,' ¶*32&5¶ 6
660B5(6(7
5
6(7
&/ 5
/2$'
9
*32'[
4
(5%2267
4
*32&5*32[/6 (5%2267B2.
287
(1
21
3:0
C
&7/
3:0B&/.XV *32&75/[ > @
&7/
'ULYHUZLWK
6OHZ5DWH
&RQWURO
Q)
7HPSHUDWXUH
VHQVRU
&XUUHQW
VHQVH
*32)/765 *32[7(03 4
6(7
6
4
4
&/ 5
6(7
6
5
4
&/ 5
7MVG
&XUUHQWOLPLWDWLRQ
5
*326[
*32&75/[ >@ K
660B5(6(7
*32)/765 *32[231 4
4
*32)/765 *32[/,0 4
4
6(7
&/ 5
6(7
&/ 5
6
5
6
5
,RSHQORDG
,OLP
63,5,' ¶*32)/765¶ 660B5(6(7
*$3*36
For high side driver configuration, the GPODx pin will be connected to battery and GPOSx
pin will be connected to the load high side.
154/202
DocID029274 Rev 1
L9678P, L9678P-S
General purpose output (GPO) drivers
Figure 55. GPO driver block diagram - HS configuration
6HO*32'[
9LQ
ELWV
9LQ
*32)/765 *32[',6$%/( 9UHI
63,:,' ¶*32&5¶ 6
660B5(6(7
5
6(7
&/ 5
9
*32'[
4
(5%2267
4
*32&5*32[/6 (5%2267B2.
287
(1
21
3:0
C
&7/
3:0B&/.XV *32&75/[ > @
'ULYHUZLWK
6OHZ5DWH
&RQWURO
7HPSHUDWXUH
VHQVRU
&7/
&XUUHQW
VHQVH
*32)/765 *32[7(03 4
6
6(7
4
4
&/ 5
6(7
6
5
4
&/ 5
7MVG
&XUUHQWOLPLWDWLRQ
5
*326[
/2$'
*32&75/[ >@ K
660B5(6(7
*32)/765 *32[231 4
4
*32)/765 *32[/,0 4
4
6(7
&/ 5
6(7
&/ 5
6
Q)
,RSHQORDG
5
6
5
,OLP
63,5,' ¶*32)/765¶ 660B5(6(7
*$3*36
The drivers have to be configured in one of the two modes through the GPO Configuration
Register (GPOCR) register before being activated. This hardware configuration is only
allowed during the Init and Diag states.
When configured as high-side, the drivers need ER Boost voltage to be above the
VERBST_OK threshold to be enabled.
The default state of both drivers is off. The drivers can be independently activated via SPI
control bits on GPO Control Register (GPOCTRLx). In addition, a set point on the
GPOCTRLx will control the output drivers in PWM with a 125Hz frequency. If PWM control is
desired, user should set the needed set point in the GPOxPWM bits of the GPOCTRLx
while activating the interface. When all bits are set to '0', the GPOx output will be disabled.
PWM control is based on a 125 Hz frequency. 6 bits of GPOCTRLx are reserved to this
mode, in order to control the drivers with 64 total levels from a 0% to a full 100% duty cycle.
When both GPO channels are used in PWM Mode at the same frequency they are
synchronized to provide parallel configuration capability.
PWM control is implemented through a careful slew rate control to mitigate EMC emissions
while operating the interface. The driver output structure is designed to stand -1V on its
terminals and a +1V reverse voltage across source and drain.
The GPO driver is protected against short circuits and thermal overload conditions. The
output driver contains diagnostics available in the GPO Fault Status Register (GPOFLTSR).
All faults except for thermal overload will be latched until the GPOFLTSR register is read.
DocID029274 Rev 1
155/202
201
General purpose output (GPO) drivers
L9678P, L9678P-S
Thermal overload faults will remain active after reading the GPOFLTSR register should the
temperature remain above the thermal fault condition. For current limit faults, the output
driver will operate in a linear mode (ILIM) until a thermal fault condition is detected.
The device also offers an open load diagnostics while in ON state. The diagnostics is run
comparing the current through the output stage with a reference threshold IOpenLoad: should
the output current be lower than the threshold, the open detection flag is asserted.
156/202
DocID029274 Rev 1
L9678P, L9678P-S
12
ISO9141 transceiver
ISO9141 transceiver
A block diagram of the function is shown below. Data transmitted by the main
microcontroller is sent via the ISOTX pin and data is received via the ISORX pin. The bus
output is ISOK.
Figure 56. ISO9141 block diagram
9%$7
9,1
:
,625;
,62.
YGGT
9,+
*DWH
&RQWURO
,627;
)/765,/,0;&95
7KHUPDO
6KXWGRZQ
)LOWHU
WG
,OLQ
)/765 27;&95
'!0'03
When the ISOTX pin is asserted, logic high, the ISOK output will be disabled (pulled high by
an external resistor). When the ISOTX pin is deasserted, logic low, the ISOK output will be
enabled (pulled low by the internal driver). This input pin contains an internal pull-up to
command the output to the disabled state in the event of an open circuit condition.
The ISORX pin has a push-pull output stage referenced to VDDQ voltage. This output is
asserted high when the voltage on the ISOK pin is above the ISOK input receiver threshold,
VBATMON, as defined in the electrical tables. This output is deasserted low when the
voltage on the ISOK pin is below the ISOK input receiver threshold with hysteresis.
ISOK output is a low side driver compatible with ISO9141 physical layer.
The output stage is protected against short circuits and diagnostics provide feedback for
current limit and thermal shutdown. While in current limit, the output stage will continue to
function until thermal limit is reached. Should thermal limit occur, the output stage will shut
down until the temperature decreases below the limit threshold with hysteresis. The fault
status is reported in the ISO9141 Fault Status Register (ISOFLTSR).
DocID029274 Rev 1
157/202
201
System voltage diagnostics
13
L9678P, L9678P-S
System voltage diagnostics
L9678P has an integrated dedicated circuitry to provide diagnostic feedback and processing
of several inputs. These inputs are addressed with an internal analog multiplexer and made
available through the SPI digital interface with the Diagnostic Data commands. In order to
avoid saturation of high voltage internal signals, an internal voltage divider is used. The
diagnostics circuitry is activated by four SPI Diagnostics Control commands (DIAGCTRLx);
each of them can address all the available nodes to be monitored, except for what
mentioned in Table 11: Diagnostics control register (DIAGCTRLx) on page 159.
DIAGCTRLx SPI command bit fields are structured in the following way:
DIAGCTRL_A (ADDRESS HEX 3A)
19
18 17 16 15 14 13 12 11 10 9 8 7
MOSI
x
MISO NEWDATA_A
0
0
x
x
x
x
x
x
x
6
5
x
4
3
2
1
0
1
0
1
0
1
0
ADCREQ_A[6:0]
ADCREQ_A[6:0]
ADCRES_A[9:0]
DIAGCTRL_B (ADDRESS HEX 3B)
19
18 17 16 15 14 13 12 11 10 9 8 7
MOSI
MISO
x
NEWDATA_B
0
0
x
x
x
x
x
x
x
6
5
x
4
3
2
ADCREQ_B [6:0]
ADCREQ_B [6:0]
ADCRES_B [9:0]
DIAGCTRL_C (ADDRESS HEX 3C)
19
18 17 16 15 14 13 12 11 10 9 8 7
MOSI
x
MISO NEWDATA_C
0
0
x
x
x
x
x
x
x
6
5
x
4
3
2
ADCREQ_C [6:0]
ADCREQ_C [6:0]
ADCRES_C [9:0]
DIAGCTRL_D (ADDRESS HEX 3D)
19
18 17 16 15 14 13 12 11 10 9 8 7
x
MOSI
MISO NEWDATA_D
0
0
x
x
x
x
x
x
ADCREQ_D [6:0]
x
x
6
5
4
3
2
ADCREQ_D [6:0]
ADCRES_D [9:0]
ADCREQ[A-D] bit fields, used to address the different measurements offered, are listed in
Table 11: Diagnostics control register (DIAGCTRLx) on page 159 for reference.
L9678P diagnostics are structured to take four automatic conversions at a time. In order to
get four measurements, four different SPI commands have to be sent (DIAGCTRL_A,
DIAGCTRL_B, DIAGCTRL_C and DIAGCTRL_D), in no particular order.
158/202
DocID029274 Rev 1
L9678P, L9678P-S
System voltage diagnostics
In case the voltage to be measured is not immediately available, the desired inputs for
conversion have to be programmed by SPI in advance, to allow them to attain a stable
voltage value. This case applies to the squib resistance measurement and diagnostics (refer
to Loop diagnostics control and results registers) and to the switch sensor measurement
(refer to Section 9: DC sensor interface).
CONVRDY_0 bit in GSW is equal to (NEWDATA_A or NEWDATA_B), while CONVRDY_1
bit in GSW corresponds to (NEWDATA_C or NEWDATA_D).
Each NEWDATAx flag is asserted when conversion is finished and cleared when result is
read out. However result is cleared only when new result for that register is available.
When a new request is received it is queued if other conversions are ongoing. The
conversions are executed in the same order as their request arrived. The queue is 4
measures long so it's possible to send all 4 requests at the same time and then wait for the
results. If a DIAGCTLRx command is received twice, the second conversion request will
overwrite the previous one.
Requests are sent to the L9678P IC via the ADC measurement Registers (ADCREQx) as
shown in Table 11: Diagnostics control register (DIAGCTRLx) on page 159. All diagnostics
results are available on the ADCRESx registers, when addressed by the related ADCREQx
register (e.g. data requested by ADCREQA would be written to ADCRESA).
Table 11. Diagnostics control register (DIAGCTRLx)
ADC Request (ADCREQx)
ADC Results (ADCRESx)
Voltage measurement selection
Bit [6:0]
Hex
Bit [9:0]
0
0
0
0
0
0
0
0
$00
Unused
0
0
0
0
0
0
1
1
$01
ADC Test Pattern 1
Ground reference
0
0
0
0
0
1
0
2
$02
ADC Test Pattern 2
Full scale reference
0
0
0
0
0
1
1
3
$03
DC Sensor ch. selected, Voltage
0
0
0
0
1
0
0
4
$04
DC Sensor ch. selected, Current
DCSV_selected
DCSI_selected
(1)
DCSV and DCSI selected
0
0
0
0
1
0
1
5
$05
DC Sensor ch. selected, Resistance
0
0
0
0
1
1
0
6
$06
Squib measurement loop selected
Voutx
0
0
0
0
1
1
1
7
$07
Bandgap reference Voltage
VBGR
0
0
0
1
0
0
0
8
$08
Bandgap reference monitor Voltage
VBGM
0
0
0
1
0
0
1
9
$09
Unused
0
0
0
1
0
1
0
10
$0A
Temperature Measurement
0
0
0
1
0
1
1
11
$0B
DC Sensor ch 0, Voltage
DCSV_0
0
0
0
1
1
0
0
12
$0C
DC Sensor ch 1, Voltage
DCSV_1
0
0
0
1
1
0
1
13
$0D
DC Sensor ch 2, Voltage
DCSV_2
0
0
0
1
1
1
0
14
$0E
DC Sensor ch 3, Voltage
DCSV_3
0
0
0
1
1
1
1
15
$0F
Unused
0
0
1
0
0
0
0
16
$10
Unused
0
0
1
0
0
0
1
17
$11
Unused
0
0
1
0
0
1
0
18
$12
Unused
DocID029274 Rev 1
TEMP
159/202
201
System voltage diagnostics
L9678P, L9678P-S
Table 11. Diagnostics control register (DIAGCTRLx) (continued)
ADC Request (ADCREQx)
ADC Results (ADCRESx)
Voltage measurement selection
Bit [6:0]
Hex
Bit [9:0]
0
0
1
0
0
1
1
19
$13
Unused
0
0
1
0
1
0
0
20
$14
Unused
0
0
1
0
1
0
1
21
$15
Unused
0
0
1
0
1
1
0
22
$16
Unused
0
0
1
0
1
1
1
23
$17
Unused
0
0
1
1
0
0
0
24
$18
Unused
0
0
1
1
0
0
1
25
$19
Unused
0
0
1
1
0
1
0
26
$1A
Unused
0
0
1
1
0
1
1
27
$1B
Unused
0
0
1
1
1
0
0
28
$1C
Unused
0
0
1
1
1
0
1
29
$1D
Unused
0
0
1
1
1
1
0
30
$1E
Unused
0
0
1
1
1
1
1
31
$1F
Unused
0
1
0
0
0
0
0
32
$20
Battery monitor Voltage
VBATMON
0
1
0
0
0
0
1
33
$21
Device battery Voltage
VIN
0
1
0
0
0
1
0
34
$22
Analog internal supply Voltage
VINT3V3
0
1
0
0
0
1
1
35
$23
Digital internal supply Voltage
CVDD
0
1
0
0
1
0
0
36
$24
ERBOOST voltage
0
1
0
0
1
0
1
37
$25
Unused
0
1
0
0
1
1
0
38
$26
VER Voltage
0
1
0
0
1
1
1
39
$27
VSUP Voltage
VSUP
0
1
0
1
0
0
0
40
$28
VDDQ Voltage
VDDQ
0
1
0
1
0
0
1
41
$29
WAKEUP Voltage
0
1
0
1
0
1
0
42
$2A
VSF Regulator Voltage
0
1
0
1
0
1
1
43
$2B
WDT/TM Voltage
WDTDIS
0
1
0
1
1
0
0
44
$2C
GPO Driver 0 drain Voltage
GPOD0
0
1
0
1
1
0
1
45
$2D
GPO Driver 0 source Voltage
GPOS0
0
1
0
1
1
1
0
46
$2E
GPO Driver 1 drain Voltage
GPOD1
0
1
0
1
1
1
1
47
$2F
GPO Driver 1 source Voltage
GPOS1
0
1
1
0
0
0
0
48
$30
Unused
0
1
1
0
0
0
1
49
$31
Unused
0
1
1
0
0
1
0
50
$32
Remote sensor Interface Voltages ch. 0
RSU0
0
1
1
0
0
1
1
51
$33
Remote sensor Interface Voltages ch. 1
RSU1
160/202
DocID029274 Rev 1
ERBOOST
VER
WAKEUP
VSF
L9678P, L9678P-S
System voltage diagnostics
Table 11. Diagnostics control register (DIAGCTRLx) (continued)
ADC Request (ADCREQx)
ADC Results (ADCRESx)
Voltage measurement selection
Bit [6:0]
Hex
Bit [9:0]
0
1
1
0
1
0
0
52
$34
Unused
0
1
1
0
1
0
1
53
$35
Unused
0
1
1
0
1
1
0
54
$36
SSxy Voltage ch. 0
SS01
0
1
1
0
1
1
1
55
$37
SSxy Voltage ch. 1
SS01
0
1
1
1
0
0
0
56
$38
SSxy Voltage ch. 2
SS23
0
1
1
1
0
0
1
57
$39
SSxy Voltage ch. 3
SS23
0
1
1
1
0
1
0
58
$3A
Unused
0
1
1
1
0
1
1
59
$3B
Unused
0
1
1
1
1
0
0
60
$3C
Unused
0
1
1
1
1
0
1
61
$3D
Unused
0
1
1
1
1
1
0
61
$3E
Unused
0
1
1
1
1
1
1
63
$3F
Unused
1
0
0
0
0
0
0
64
$40
Unused
1
0
0
0
0
0
1
65
$41
Unused
1
0
0
0
0
1
0
66
$42
VRESDIAG
1
0
0
0
0
1
1
67
$43
VDD5
1
0
0
0
1
0
0
68
$44
VDD3V3
1
0
0
0
1
0
1
69
$45
ISOK output voltage
ISOK
1
0
0
0
1
1
0
70
$46
SF0 voltage
SF0
1
0
0
0
1
1
1
71
$47
SF1 voltage
SF1
1
0
0
1
0
0
0
72
$48
SF2 voltage
SF2
1
0
0
1
0
0
1
73
$49
SF3 voltage
SF3
VRESDIAG
VDD5
VDD3V3
1. The DC sensor resistance measurement can only be addressed through DIAGCRTL_A command. Results are available
through DIAGCTRL_A and DIAGCTRL_B, where ADCRES_A will contain DCSI and ADCRES_B will contain DCSV.
Proper scaling is necessary for various voltage measurements. The divider ratios vary by
measurement and are summarized by function in the table below.
Table 12. Diagnostics divider ratios
Divider Ratio
Measurements
15:1
VER
X
ERBOOST
X
VSF
X
SSxy
X
10:1
DocID029274 Rev 1
7.125:1
7:1
4:1
1:1
161/202
201
System voltage diagnostics
L9678P, L9678P-S
Table 12. Diagnostics divider ratios (continued)
Divider Ratio
Measurements
15:1
SFx
X
VRESDIAG
X
10:1
GPODx
X
GPOSx
X
VIN
X
VBATMON
X
WAKEUP
X
7.125:1
7:1
ISOK
X
VSUP
X
WDTDIS
X
RSUx
4:1
1:1
X
DCSx
X
VDDQ
X
VDD5
X
VDD3V3
X
VINT3V3
X
Bandgap (BGR/BGM)
X
TEMP
X
For measurements other than voltage (current, resistance, temperature etc.) the ranges are
specified in the electrical parameters section of the relevant block.
13.1
Analog to digital algorithmic converter
The device hosts an integrated 10 bit Analog to Digital converter, running at a clock
frequency of 16MHz. The ADC output is processed by a D to D converter with the following
functions:

Use of trimming bits to recover ADC offset and gain errors;

Digital low-pass filtering;

Conversion from 12 to 10 bits.
10 bits data are filtered inside the digital section. The number of samples that are filtered
varies depending on the chosen conversion. As per Section 5.1.2: System configuration
register (SYS_CFG), the number of used samples in converting DC sensor, squib or
temperature measurements defaults to 8. The number of samples for all other
measurements defaults to 4. The sample number can be configured by accessing the
SYS_CFG register. After low pass filter, the residual total error is ±4 LSB. This error figure
162/202
DocID029274 Rev 1
L9678P, L9678P-S
System voltage diagnostics
applies to the case of a precise reference voltage: the spread of reference voltage causes a
proportional error in the conversion output. The reference voltage of the ADC is set to 2.5 V.
The conversion time is comprised of several factors: the number of measurements loaded
into the queue, the number of samples taken for any measurement, and the various settling
times. An example of conversion time calculation for a full ADC request queue is reported in
Figure 57. The timings reported in Figure 57 are nominal ones, min/max values can be
obtained by considering the internal oscillator frequency variation reported in the DC
characteristics section.
Figure 57. ADC conversion time
',$*&75/B$
3UH
$'&
67B6&
',$*&75/B&
',$*&75/B%
,4
67B6&
,4
67B6&
',$*&75/B'
,4
67B6&
3RVW
$'&
3UH$'& ,QLWLDO$'&6HWWOLQJ7LPH —V
6 RI6DPSOHVGHIDXOW IRUYROWDJHRQO\PHDVXUHPHQWV
7B6& 6LQJOH6DPSOH&RQYHUVLRQ7LPH —V
,4 ,QWUD4XHXH6HWWOLQJ7LPH —V
3RVW$'& )LQDO$'&6HWWOLQJ7LPH —V
'!0'03
DocID029274 Rev 1
163/202
201
Temperature sensor
14
L9678P, L9678P-S
Temperature sensor
The L9678P provides an internal analog temperature sensor. The sensor is aimed to have a
reference for the average junction temperature on silicon surface. The sensor is placed far
away from power dissipating stages and squib deployment drivers. The output of the
temperature sensor is available via SPI through ADC conversion, as shown in Table 11. The
formula to calculate temperature from ADC reading is the following one:
 ADC REF_hi

 220

T  C  = 180 –   ---------------   -------------------------------  DIAGCTRLn  ADCRESn  – 0.739  
 1.652  ADC RES




2

@ DIAGCTRLn(ADCREQn) = 0Ahex
All parametric requirements for this block can be found in specification tables.
164/202
DocID029274 Rev 1
L9678P, L9678P-S
15
Electrical characteristics
Electrical characteristics
Every parameter in this chapter is fulfilled down to VINGOOD(max).
No device damage is granted to occur down to VINBAD(min).
GNDA pin is used as ground reference for the voltage measurements performed within the
device, unless otherwise stated.
All table or parameter declared "Design Info" are not tested during production testing
15.1
Configuration and control
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD(max)  VIN  35 V.
Table 13. Configuration and control DC specifications
N°
Symbol
Parameter
Min
Typ
Max
Unit
1
VNOV
Normal operating
voltage
Design Info
Depending on power supply
configuration
6
13
18
V
2
VJSV
Jump start voltage
Design Info -40 °C ≤ Ta ≤ 50 °C
18.00
-
26.50
V
3
VLDV
Load dump voltage
Transient
Design Info
26.50
-
40
V
4
WU_mon
WAKEUP monitor
threshold
-
-
-
1.5
V
5
WU_off
WAKEUP Off threshold -
2
2.5
3
V
6
WU_on
WAKEUP On threshold -
4
4.5
5
V
7
WURPD
WAKEUP pull-down
resistor
-
120
300
480
kΩ
8
VBGOOD1
SYS_CTL(VBATMON_TH_SEL)=0
0
5.5
-
6
V
9
VBBAD1
SYS_CTL(VBATMON_TH_SEL)=0
0
5
-
5.5
V
10
VBGOOD2
SYS_CTL(VBATMON_TH_SEL)=0
1
6.3
-
6.8
V
11
VBBAD2
SYS_CTL(VBATMON_TH_SEL)=0
1
5.8
-
6.3
V
12
VBGOOD3
SYS_CTL(VBATMON_TH_SEL)=1
0
7.5
-
8
V
13
VBBAD3
SYS_CTL(VBATMON_TH_SEL)=1
0
7
-
7.5
V
14
VBGOOD4
SYS_CTL(VBATMON_TH_SEL)=11
8.3
-
8.8
V
15
VBBAD4
SYS_CTL(VBATMON_TH_SEL)=11
7.8
-
8.3
V
VBATMON input
voltage thresholds
Condition
DocID029274 Rev 1
165/202
201
Electrical characteristics
L9678P, L9678P-S
Table 13. Configuration and control DC specifications (continued)
N°
Symbol
16 ILKG_VBATMON_OFF
17 ILKG_VBATMON_ON
Parameter
Condition
VBATMON input
leakage
Min
Typ
Max
Unit
5
µA
Device OFF
-5
Device ON
Design Info
20
24
30
µA
18 RPD_VBATMON
VBATMON pull-down
resistance
Device ON
VBATMON < 10V
Design Info
125
250
375
kΩ
19 ILKG_VBATMON_TOT
VBATMON total input
leakage
ILKG_VBATMON_ON + RPD_VBATMO
VBATMON = 18V
35
70
105
µA
SYS_CTL(VIN_TH_SEL)=0
5
-
5.5
V
SYS_CTL(VIN_TH_SEL)=0
4.5
-
5
V
SYS_CTL(VIN_TH_SEL)=1
7
-
7.5
V
SYS_CTL(VIN_TH_SEL)=1
6.5
-
7
V
VIN Thresholds used to
25 VINFASTSLOPE_L change boost regulator transition time
26 VINFASTSLOPE_HYS
9.3
9.8
10.3
V
9
9.5
10
V
0.2
0.3
0.4
V
27
ILKG_VIN_OFF
Device OFF, VIN = 40V
-10
-
10
µA
28
ILKG_VIN_ON
Device ON, VIN = 12V
-
-
30
mA
29
CVIN
-
1
-
-
-
30
ILKG_VER_OFF
Device OFF, VER = 40 V
-5
-
5
µA
31
ILKG_VER_ON_L
Device ON
ERBOOST > VER
-5
-
5
µA
32
ILKG_VER_ON_H
Device ON
ERBOOST < VER
-
-
200
µA
33
VWD_OVERRIDE_th
WDT/TM threshold
-
10
12
14
V
34
VWDTDIS_HYST
WDT/TM hysteresis
-
0.2
0.4
0.5
V
35
IPD_WDTDIS
WDT/TM pull-down
Current
VWDTDIS ≤ 5 V
20
45
70
µA
Battery line Input
Leakage
Total leakage at RT from VIN,
VBATMON, ERBSTSW, ERBOOST,
BVDD5, VDD5, VDDQ, BVSUP,
VSUP
VBAT = 12 V
Guaranteed by design
-
-
100
µA
Junction temperature
Design Info
-
-
150
°C
20
VINGOOD1
21
VINBAD1
22
VINGOOD2
23
VINBAD2
24
VINFASTSLOPE_H
VIN input voltage
thresholds
VIN input leakage
36
ILKG_BAT
37
Tj
166/202
External VIN capacitor
VER input leakage
DocID029274 Rev 1
L9678P, L9678P-S
Electrical characteristics
Table 14. Configuration and control AC specifications
No
Symbol
1
TFLT_VBATMONTH
2
TFLT_VINTH
3
TFLT_WAKEUP
4
TLATCH_WAKEUP
5
tdon
Parameter
Condition
Min
Typ
Max
Units
VBATMON thresholds
deglitch filter time
-
26
30
34
µs
VIN thresholds deglitch filter
time
-
3
3.5
4
µs
Wakeup deglitch filter time
-
0.95
1.05
1.15
ms
Wakeup latch time
-
9.7
10.8
11.9
ms
-
-
10
ms
Min
Typ
Max
Unit
Power-up delay time – 
Wake-up to RESET released
Table 15. Open ground detection DC specifications
N°
Symbol
Parameter
Condition
1
GNDAOPEN
GNDA threshold
GNDSUBx=0
100
200
300
mV
2
GNDDOPEN
GNDD threshold
GNDSUBx=0
100
200
300
mV
3
BSTGNDOPEN
BSTGND threshold
GNDSUBx=0
100
200
300
mV
4
IPU_BSTGND
BSTGND pull-up
current
-
80
120
160
µA
Min
Typ
Max
Unit
-
7
11
16
µs
-
1.9
2.3
2.7
µs
Table 16. Open ground detection AC specifications
N°
Symbol
Parameter
1
GNDA and GNDD
TFLT_GNDREFOPEN Open Deglitch Filter
Time
2
TFLT_BSTGNDOPEN
15.2
Condition
BSTGND Latch Filter
Time
Internal analog reference
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V.
Table 17. Internal analog reference
N°
Symbol
1
VBG1
Bandgap reference
2
VBG2
3
VADC_GROUND
4
Parameter
Condition
Min
Typ
Max
Unit
-
-1%
1.2
+1%
V
Bandgap monitor
-
-1%
1.2
+1%
V
ADC Ground reference
-
-3%
103
+3%
mV
-1.5%
2.5
+1.5%
V
VADC_FULLSCALE ADC Full scale reference -
DocID029274 Rev 1
167/202
201
Electrical characteristics
15.3
L9678P, L9678P-S
Internal regulators
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V.
Table 18. Internal regulators DC specifications
N°
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1
VOUT_VINT3V3
VINT3V3 output voltage
-
3.14
3.3
3.46
V
2
VOV_VINT3V3
VINT3V3 over voltage
-
3.47
-
3.7
V
3
VUV_VINT3V3
VINT3V3 under voltage
-
2.97
-
3.13
V
4
VOUT_VDD
VDD output voltage
-
3.14
3.3
3.46
V
5
IOUT_VDD
VDD current capability
External Load is not allowed
-
-
50
mA
6
ILIM_VDD
VDD current limit
-
80
-
-
mA
7
VOV_VDD
VDD over voltage
-
3.47
-
3.7
V
8
VUV_VDD
VDD under voltage
-
2.7
-
2.9
V
9
CVDD
VDD output capacitance
Design Info
60
100
140
nF
Table 19. Internal regulators AC specifications
N°
Symbol
1
TFLT_ VINT_VDD_OV
Internal regulator OV
Deglitch filter time
2
TFLT_ VINT_VDD_UV
Internal regulator UV
Deglitch filter time
15.4
Parameter
Condition
Min
Typ.
Max
Unit
-
7
11
16
µs
-
7
11
16
V
Oscillators
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, 3.14  CVDD  3.46.
Table 20. Oscillators AC specifications
No
Symbol
Parameter
Min
Typ
1
fOSC
Main oscillator average
frequency
-
15.2
16
2
fMOD_OSC
Main oscillator
modulation frequency
SPI_CLK_CNF(MAIN_SS_DIS=0)
Design Info
-
ƒ OSC
--------------128
-
MHz
3
IMOD_OSC
Main oscillator
modulation index
SPI_CLK_CNF(MAIN_SS_DIS=0)
3
4
5
%
4
fAUX
Aux oscillator average
frequency
-
7.125
7.5
5
fMOD_AUX
Aux oscillator
modulation frequency
SPI_CLK_CNF(AUX_SS_DIS=0)
Design Info
-
ƒ OSC_AUX
---------------------------128
168/202
Conditions / Comments
DocID029274 Rev 1
Max
Unit
16.8 MHz
7.87
MHz
5
-
MHz
L9678P, L9678P-S
Electrical characteristics
Table 20. Oscillators AC specifications (continued)
No
Symbol
6
IMOD_AUX
7
Parameter
Aux oscillator
modulation index
Main oscillator Low
fOSC_LOW_TH Frequency Detection
Threshold
15.5
Conditions / Comments
Min
Typ
Max
Unit
SPI_CLK_CNF(AUX_SS_DIS=0)
3
4
5
%
-
-
128
----------  ƒ AUX
174
-
MHz
Watchdog
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C  Ta  +95 °C,VINGOOD1(max)  VIN  35 V
Table 21. Temporal watchdog timer AC specifications
N°
Symbol
1
TWDT1_TIMEOUT
Temporal watchdog
timeout
-
2
TWDT1_RST
Temporal Watchdog
Reset Time
-
15.6
Parameter
Condition
Min
Typ
Max
Unit
-
-
2.00
ms
-
-
16.3
ms
0.9
-
1.1
ms
Reset
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C  Ta  +95 °C; VINGOOD1(max)  VIN  35 V, VDDx(min)  VDDx  VDDx(max),
VDDQ = VDD5 or VDD3V3
Table 22. Reset DC specifications
N°
Symbol
1
VOH_RESET
2
VOL_RESET
3
RPD_RESET
Parameter
RESET output voltage
RESET pull down
resistance
Condition
Min
Typ
Max
Unit
ILOAD = -0.5 mA
VDDQ
-0.6
-
VDDQ
V
ILOAD = 2.0 mA
0
-
0.4
V
RESET=VDDQ, Device OFF
65
100
135
kΩ
Table 23. Reset AC specifications
N°
Symbol
Parameter
1
TRISE_RESET
Rise Time
2
TFALL_RESET
3
THOLD_RESET
Condition
Min
Typ
Max
Unit
80pF load, 20%-80%
-
-
1.00
µs
Fall Time
80pF load, 20%-80%
-
-
1.00
µs
Reset Hold Time
-
0.45
0.5
0.55
ms
DocID029274 Rev 1
169/202
201
Electrical characteristics
15.7
L9678P, L9678P-S
SPI interface
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V, VDDx(min)  VDDx  VDDx(max)
VDDQ = VDD5 or VDD3V3.
Table 24. SPI DC specifications
N°
Symbol
Parameter
Min
Typ
Max
Unit
1
VIH_CS
SPI_CS high level input
voltage
-
2
-
-
V
2
VIL_CS
SPI_CS low level input
voltage
-
-
-
0.8
V
3
IPU_CS
SPI_CS pull up current
SPI_CS = 0V
-70
-45
-20
µA
4
VIH_MOSI
MOSI high level input
voltage
-
2
-
-
V
5
VIL_MOSI
MOSI low level input
voltage
-
-
-
0.8
V
6
IPD_MOSI
SPI_MOSI pull down
current
SPI_MOSI = VDDQ
20
45
70
µA
7
VIH_SCK
SCK high level input
voltage
-
2
-
-
V
8
VIL_SCK
SCK low level input
voltage
-
-
-
0.8
V
9
IPD_SCK
SPI_SCK pull down
current
SPI_SCK = VDDQ
20
45
70
µA
10
VOH_MISO
SPI_MISO high level
output voltage
ILOAD = -800µA
VDDQ
-0.5
-
VDDQ
V
11
VOL_MISO
SPI_MISO low level
output voltage
ILOAD = 2.0mA
-
-
0.4
V
12
VIH_MISO
SPI_MISO high level
input voltage
-
2
-
-
V
13
VIL_MISO
SPI_MISO low level
input voltage
-
-
-
0.8
V
14
ILKG_MISO
SPI_MISO tri-state
leakage
SPI_MISO= VDDQ or 0V
-10
-
10
µA
170/202
Condition
DocID029274 Rev 1
L9678P, L9678P-S
Electrical characteristics
Table 25. SPI AC specifications
N°
Symbol
Min
Typ
Max
Unit
1
FSCLK
SPI Transfer frequency
-
-
8
8.08
MHz
2
TSCLK
SPI_SCK period
-
123.8
-
-
ns
3
TLEAD
Enable lead time
-
250
-
-
ns
4
TLAG
Enable lag time
-
50
-
-
ns
5
THIGH_SCLK
SPI_SCK high time
-
50
-
-
ns
6
TLOW_SCLK
SPI_SCK low time
-
50
-
-
ns
7
TSETUP_MOSI
SPI_MOSI input setup
time
-
20
-
-
ns
8
THOLD_MOSI
SPI_MOSI input hold
time
-
20
-
-
ns
9
TACC_MISO
SPI_MISO access time
80pF load
-
-
60
ns
10
TDIS_MISO
SPI_MISO disable time
80pF load
-
-
100
ns
11
TVALID_MISO_OUT
SPI_MISO output valid
time
80pF load
-
-
30
ns
12
THOLD_MISO_OUT
SPI_MISO output hold
time
80pF load
0
-
-
ns
13
TSETUP_MISO_IN
SPI_MISO Input Setup
Time
20
ns
14
THOLD_MISO_IN
SPI_MISO Input Hold
Time
20
ns
15
THOLD_SCLK
SPI_SCK hold time
-
20
-
-
ns
16
TFLT_CS
SPI_CS noise glitch
rejection time
-
50
-
300
ns
17
TNODATA
SPI interframe time
-
400
-
-
ns
Note:
Parameter
Condition
All timing is shown with respect to 10% and 90% of the actual delivered VDDQ voltage.
Figure 58. SPI timing diagram
63,B&6
63,B6&/.
06%287
63,B0,62
63,B026,
'$7$
/6%287
'21¶7
&$5(
06%,1
'$7$
/6%,1
'!0'03
DocID029274 Rev 1
171/202
201
Electrical characteristics
15.8
L9678P, L9678P-S
ER boost
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  18 V.
Table 26. ER Boost converter DC specifications
N°
Symbol
Parameter
1
VO_ERBST
Boost output voltage
2
3
Condition
Min
Typ
Max
Unit
Across all line and IO_BST load
(steady state)
ERBST33V=0
Test conditions: IO_BST = 0.1 &
40mA
22.4
23.8
25
V
Across all line and IO_BST load
(steady state)
ERBST33V=1
Test conditions: IO_BST = 0.1 &
20mA
31.4
33
35
V
BST33V = 0
0.1
-
60
mA
BST33V = 1
0.1
-
40
mA
IO_ERBST
Boost output current
dVSR_ac
Line transient response
All line, load; dt=100us;
BST33V = 0/1
Design Info
-8%
-
8%
%
6
dVLR_ac
All line, load; dt=100us;
Load transient response BST33V = 0/1
Design Info
-8%
-
8%
%
7
RDSON_ERBST
-
-
1
Ω
8
IOC_ERBST
Over current detection
-
550
-
800
mA
9
ILKG_ERBST
ERBOOST leakage
current
ERBOOST=40V
Device off
-
-
5
µA
VERBST_OK
ERBOOST voltage
threshold
BST33V = 0
18
20
22
V
BST33V = 1
26
28
30
V
VERBST_OV
ERBOOST Over Voltage BST33V = 0
threshold
BST33V = 1
22.6
25
V
31.65
35
V
4
5
10
11
12
13
Power switch resistance -
14
Voltage difference
between VIN and
VERBST_DIS_TH
VIN – ERBOOST
ERBOOST to deactivate
the ER Boost regulator
1.6
2.2
2.5
V
15
Voltage difference
between ERBSTSW and
VCLAMP_EN_TH
ERBSTSW – ERBOOST
ERBOOST to activate
the ER Boost CLAMP
1.6
2.2
2.5
V
-
150
175
190
°C
-
5
10
15
°C
16
TJSD_ERBST
17 THYS_TSDERBST
172/202
Thermal shutdown
DocID029274 Rev 1
L9678P, L9678P-S
Electrical characteristics
Table 27. ER boost converter AC specifications
N°
Symbol
1
FSW_ERBST
Min
Typ
Max
Unit
-
1.8
1.882
2.0
MHz
10% to 90% voltage on
ERBSTSW
VIN ≥ VINFASTSLOPE_L =
10.3 V
Iload = 60mA
ERboost settings 23 V
Guaranteed by design
10
15
-
25
35
ns
TRISE_ERBSTSW_FAST
TFALL_ERBSTSW_FAST
10% to 90% voltage on
ERBSTSW
VIN ≤ VINFASTSLOPE_H=
9V
Iload=60mA
ERboost settings 23 V
Guaranteed by design
10
-
25
ns
4
TON_ERBST
CERBOOST = 2.2µF,
Vin =12V, IO_ERBST=
5mA
BST33V = 1
Measured from CS edge
to VO_ERBST(min)
-
-
5
ms
5
TFLT_TSD_ERBST
-
10
µs
Min
Typ
Max
Unit
2
Parameter
Condition
ERBOOST switching
frequency
TRISE_ERBSTSW_SLOW
TFALL_ERBSTSW_SLOW
ERBSTSW transition time
3
ERBOOST charge-up time
Thermal shutdown filter time -
Table 28. ER boost converter external components (Design Info)
N°
Symbol
1
LERBST
2
ESLERBST
3
CBLK_ERBST
4
Parameter
Condition
Inductance
-
8
10
-
µH
Inductance resistance
-
-
-
0.1
Ω
Output bulk capacitance
to ensure regulator
stability
Min capacitance value including
derating factors
1
2.2
-
-
-
0.1

ESRCBLK_ERBST Bulk capacitor ESR
µF
5
VFSTR_ERBST
Steering diode forward
voltage
IF=100 mA
-
-
0.85
V
6
ILKGSTR_ERBST
Steering diode reverse
leakage
Ta = 95 °C
-
-
100
µA
DocID029274 Rev 1
173/202
201
Electrical characteristics
15.9
L9678P, L9678P-S
ER charge
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V, 8 V  ERBOOST.
Table 29. ER current generator DC specifications
N°
Symbol
Parameter
Condition
1
IER_CHARGE
ER charge current
ERBOOST – VER  3 V
2
RDSON_ERCHARGE
ER charge power
resistance
(VERBOOST - VVER) / IVER
IVER = 10mA
Min
Typ
Max
Unit
-33
-30
-27
mA
-
-
22
Ω
Min
Typ
Max
Unit
-
-
6
s
Table 30. ER current generator AC specifications
N°
Symbol
1
TON_ERCAP
15.10
Parameter
Condition
Energy reserve capacitor
charge-up time
CVER  4.7mF nominal,
BST33V = 0; Design Info
ER switch
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V.
Table 31. ER switch DC specifications
N°
Symbol
1
RDSON ERSW
2
ILIM,ERSW
3
TJSD_ERSW
4
THYS_TSDERSW
Parameter
Condition
Min
Typ
Max
Unit
Power switch resistance
ILIM,ERSW(min)
0.5
-
3
Ω
ER switch current limit
-
400
-
600
mA
-
150
175
190
°C
-
5
10
15
°C
Min
Typ
Max
Unit
CVIN = 10µF
-
-
5
µs
-
-
-
10
µs
ER switch activation blanking
time after thermal shutdown
-
1
-
ms
Thermal shutdown
Table 32. ER switch AC specifications
N°
Symbol
Parameter
1
TON_ERSW
ER turn-on time (time to
reach either RDSON_ERSW or
ILIM_ERSW)
2
Condition
TFLT_TSD_ERSW Thermal shutdown filter time
3
174/202
TBLK_ERSW
DocID029274 Rev 1
L9678P, L9678P-S
15.11
Electrical characteristics
COVRACT
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V, VDDx(min)  VDDx  VDDx(max),
VDDQ = VDD5 or VDD3V3
Table 33. COVRACT DC Specifications
N°
Symbol
1
VOH_COVRACT
2
VOL_COVRACT
Parameter
Condition
COVRACT output voltage
Min
Typ
Max
Unit
ILOAD = -0.5 mA
VDDQ
-0.6
-
VDDQ
V
ILOAD = 2.0 mA
0
-
0.4
V
Table 34. COVRACT AC specifications
N°
Symbol
1
TRISE_COVRACT
Rise time
2
TFALL_COVRACT
Fall time
15.12
Parameter
Condition
Min
Typ
Max
Unit
80pF load, 20%-80%
-
-
0.5
µs
80pF load, 20%-80%
-
-
0.5
µs
VDD5 regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V.
Table 35. VDD5 regulator DC specifications
N°
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1
VO_VDD5
Output voltage
Across all line and load,
steady state
4.85
5
5.15
V
2
IO_BVDD5
Base driver current limit
VDD5 > VDD5UVL
4
7
10
mA
3
IO_BVDD5_LOW
Base driver current limit
Low level
VDD5 < VDD5UVL
2
-
5
mA
4
IO_VDD5
Output load current
-
0.5
-
200
mA
5
dVSR_ac
Line transient response
All load IO_VDD5;
VIN=6V to 18V @ dt = 1 µs;
Design Info
4.5
-
5.5
V
4.5
-
5.5
V
6
dVLR_ac
Load transient response
All line;
IO_VDD5= 1mA to 100mA
@dt = 1 µs;
Design Info
7
IOF_VDD5
Open feedback current on
VDD5
Active only during
VDD5_rampup state
55
80
105
µA
8
VDD5OV
Over voltage detection
-
5.2
-
5.50
V
DocID029274 Rev 1
175/202
201
Electrical characteristics
L9678P, L9678P-S
Table 35. VDD5 regulator DC specifications (continued)
N°
Symbol
Parameter
9
VDD5UV
Under voltage detection
10
VDD5UVL
Condition
Min
Typ
Max
Unit
-
4.5
-
4.8
V
Under voltage detection low
level
1.8
2
2.2
V
Min
Typ
Max
Unit
Table 36. VDD5 regulator AC specifications
N°
Symbol
1
TSOFTST_VDD5
2
Parameter
Condition
Soft start time
From 10% to 90%
1
2
3
ms
TFLT_VDD5OV
Over voltage
detection deglitch filter time
-
27
30
33
µs
3
TFLT_VDD5UV
Under voltage
detection deglitch filter time
-
27
30
33
µs
4
TFLT_VDD5UVL
Under voltage low
detection deglitch filter time
-
1.5
2
2.5
µs
Min
Typ
Max
Unit
Table 37. VDD5 regulator external components (Design Info)
N°
Symbol
1
hFE_PNP
2
Parameter
Condition
Output transistor gain
-
50
250
500
A/A
Ft_PNP
Output transistor transit
frequency
-
30
-
-
MHz
3
RVDD5BE
Output transistor baseemitter
Pull-up resistance
-
-
3
-
k
4
CBLK_VDD5
Output bulk capacitance
Min 4.7µF nominal
3
-
30
µF
-
-
-
50
mΩ
5
ESRCBLK_VDD5 Bulk capacitor ESR
176/202
DocID029274 Rev 1
L9678P, L9678P-S
15.13
Electrical characteristics
VDD3V3 regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VDD5(min)  VDD5.
Table 38. VDD3V3 regulator DC specifications
N°
Symbol
1
VO_VDD3V3
2
IO_VDD3V3
3
Parameter
Condition
Min
Typ
Max
Unit
Output voltage
Across all line and load, steady
state
3.2
3.3
3.4
V
Output load current
capability
-
0.5
-
125
mA
-
150
-
-
mA
3
-
3.6
V
3
-
3.6
V
IO_LIM_VDD3V3 Output load current limit
All load IO_VDD3V3;
VIN = 6 V to 18 V @ dt = 1 µs;
Guaranteed by design
dVSR_ac
Line transient response
7
dVLR_ac
All line; IO_VDD3V3= 1mA to
100mA
Load transient response
@dt = 1 µs;
Guaranteed by design
4
VDD3V3OV
Over-voltage threshold
-
3.43
-
3.6
V
5
VDD3V3UV
Under voltage reset
threshold
-
3
-
3.17
V
Min
Typ
Max
Unit
6
Table 39. VDD3V3 regulator AC specifications
N°
Symbol
Parameter
1
TSOFTST_VDD3
2
3
Condition
Soft start time
From 10% to 90%
1
2
3
ms
TFLT_VDD3OV
Over voltage
detection deglitch filter time
-
27
30
33
µs
TFLT_VDD3UV
Under voltage
detection deglitch filter time
-
27
30
33
µs
Min
Typ
Max
Unit
Min 4.7µF nominal
3
-
30
µF
-
-
-
50
mΩ
Table 40. VDD3V3 regulator external components (design info)
N°
Symbol
1
CBLK_VDD3
2
Parameter
Condition
Output bulk capacitance
ESRCBLK_VDD3 Bulk capacitor ESR
DocID029274 Rev 1
177/202
201
Electrical characteristics
15.14
L9678P, L9678P-S
VSUP regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD2(max)  VIN  35 V.
Table 41. VSUP regulator DC specifications
N°
Symbol
1
VO_VSUP
2
Parameter
Condition
Min
Typ
Max
Unit
Output voltage
Across all line and load,
steady state
6.5
6.8
7.1
V
IO_BVSUP
Base driver current limit
-
4
7
10
mA
3
IO_VSUP
Output load current
-
0.5
200
mA
4
dVSR_ac
Line transient response
All load IO_VDD5;
VIN = 6 V to 18 V @ dt = 1 µs;
Design Info
6.2
7.4
V
6.2
7.4
V
8
V
5
dVLR_ac
Load transient response
All line;
IO_VDD5= 1mA to 100mA @dt = 1µs;
Design Info
6
VSUPOV
Over voltage detection
-
7.6
7
VSUPUV
Under voltage detection
-
1.8
2
2.2
V
Min
Typ
Max
Unit
From 10% to 90%
1
2
3
ms
Table 42. VSUP AC specifications
N°
1
Symbol
Parameter
Condition
TSOFTST_VSUP Soft start time
2
TFLT_VSUPOV
Over voltage
deglitch filter time
-
27
30
33
µs
3
TFLT_VSUPUV
Under voltage
deglitch filter time
-
27
30
33
µs
Min
Typ
Max
Unit
Table 43. VSUP regulator external components (Design Info)
N°
Symbol
1
hFE_PNP
2
Ft_PNP
3
RVSUPBE
4
CBLK_VSUP
5
Component
Output transistor gain
-
50
250
500
A/A
Output transistor
transit frequency
-
30
-
-
MHz
Output transistor BaseEmitter
Pull-up Resistance
-
-
3
-
kΩ
Output Bulk Capacitance
Min 4.7µF nominal
3
-
30
µF
-
-
-
50
mΩ
ESRCBLK_VSUP Bulk Capacitor ESR
178/202
Conditions
DocID029274 Rev 1
L9678P, L9678P-S
15.15
Electrical characteristics
VSF regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V, VSF + 2V  ERBOOST
Table 44. VSF regulator DC specifications
N°
Symbol
Parameter
1
VSF
Output voltage
2
Condition
Min
Typ
Max
Unit
All line, load, IO_VSF up to 6 mA
SYS_CFG(VSF_V)= 0
18
20
22
V
All line, load, IO_VSF up to 6 mA
BST33V = 1, SYS_CFG(VSF_V)= 1
23
25
27
V
3
ILIM_VSF
Output load current limit
Test conditions: VSF = 0
7
10
13
mA
4
VDO_VSF
Drop-out voltage
V(ERBOOST-VSF)
-
-
2
V
5
CVSF
Output capacitance
Design Info.
2.9
-
14
nF
Device OFF
-5
5
µA
60
125
188
kΩ
6
ILKG_VSF_OFF VSF input leakage
7
RPD_VSF
VSF pull-down resistance
Device ON
VSF regulator OFF or ON
1.5V<VSF<25V
Test condition: VSF = 25V
8
IPD_VSF
VSF pull-down current
Device ON
VSF regulator ON
Design Info
34
40
46
µA
VSF total pull-down
current
IPD_VSF_TOT = IPD_VSF +
RPD_VSF
Device ON
VSF regulator ON
Test conditions:
– VSF = 25V
– SYS_CGF(VSF_V)= 0
166
230
462
µA
9
IPD_VSF_TOT
Table 45. VSF regulator AC specifications
N°
Symbol
1
TON,VSF
Parameter
VSF turn on time
Condition
CVSF = 14 nF and IO_VSF=0
Measured from VSF_EN = 1 to
VSF inside regulation limits
DocID029274 Rev 1
Min
Typ
Max
Unit
-
-
100
µs
179/202
201
Electrical characteristics
15.16
L9678P, L9678P-S
Deployment drivers
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V, 6 V  SSxy  35 V, SSxy - SFx  25 V.
Table 46. Deployment drivers - DC specifications
N°
Symbol
1
Parameter
IDEPL_LO
Deployment
current
Condition
Min
Typ
Max
Unit
R = 2 ohms
Considering 9mA as not
detected leakage with a 1kOhm
equivalent resistance from SFx
to GND
1.33
1.4
1.55
A
R = 2 ohms, 9 V  SSxy
Considering 13.5 mA as not
detected leakage with a 1 kΩ
equivalent resistance from SFx
to GND, Not available with tdepl
= 2 ms selection
1.94
1.99
2.2
A
2
IDEPL_HI
3
IOC_SR
Low side over
current detection
2.2
3.1
4
A
4
ILIM_SR
Low side current
limitation
2.2
3.1
4
A
0.1
-
-
A
-
-
2
Ω
-
-
-100
mA
-10
-
10
µA
5
ILIM_OC_SR
6
RDSONT
7
IRV_SF
-
Difference
between current
-I
I
limitation and OC LIM_SR OC_SR
threshold
Total high and
low side MOS on Ta = 95 °C
resistance
Reverse current
on SFx
Without device malfunction (1)
Not to be tested in series
production
8
ILKG_SS_OFF
Device OFF
SSxy ≤ 35V
SFx = SFy = 0
9
ILKG_SS_ON
Device ON
SSxy ≤ 35V
SFx = 0
46
66
86
µA
Device ON
One channel armed
SSxy ≤ 35V
SFx = 0
410
490
570
µA
10
ILKG_SS_CH_ARMED
180/202
SSxy leakage
current
DocID029274 Rev 1
L9678P, L9678P-S
Electrical characteristics
Table 46. Deployment drivers - DC specifications (continued)
N°
Symbol
11
ILKG_SF_ON
Parameter
SF leakage
current
Condition
Min
Typ
Max
Unit
Device ON,
VRESDIAG = VSSxy = 35 V,
SFx = 0V-35 V
-50
-
50
µA
-50
-
50
µA
12
ILKG_SF_OFF
Device OFF,
VRESDIAG = open, VSSxy =
open but all SSxy pins
connected, SEx = 0 V - 35 V
13
ILKG_SR_ON
Device ON,
VRESDIAG = VSSxy = 35 V,
SFx = 0V-35 V
-
-
50
µA
Device OFF,
VRESDIAG = open,
VSSxy = open but all SSxy pins
connected, SEx = 0 V - 35 V
-
-
50
µA
0
-
60
µH
13
-
455
nF
13
-
455
nF
-
-
10
nF
-
-
6.5
Ω
1
-
10
m
SR leakage
current
14
ILKG_SR_OFF
15
LDEPL
Load Inductance
Maximum load inductance
Design Information(2)
16
CSFx
17
CSRx
Load
capacitance
Maximum capacitance to GND
Design Information
18
CSSxy
SSxy
capacitance
Maximum capacitance to GND
connected directly to SSxy pin
Design Information
19
RSFLx
Load Impedance Design Information
20
-
21
Wire Length
Squib Loops containing a
clockspring shall be limited to a
maximum length of 3m
RWirex
Wire resistance
Design information
16.8
-
63.4
mΩ/m
22
LWirex
Wire Inductance
Design Information
0.6
-
1.8
µH/m
23
RCSx
Clock spring
resistance
Maximum number of clock
springs is 3 for any IC
Design Information
0
-
0.7
Ω
24
LCSx
Clock spring
inductance
Design Information
0
-
42.9
µH
25
kL_CS1 – L_CS2
Clocks pring
coupling
Design Information
0.739
-
0.903
-
26
LEMI
Squib EMI
protection
Design Information
0
-
7.7
µH
1. In case of an unsupplied device and shorted deployment pins (e.g. to battery voltage), the dynamic reverse current through
the high side power stage depends on CSSxy.
2. LDEPL could be calculated in the following way:
- Non-ClockSpring Loops
LDEPL(max) = LWire(10m*2) + LEMI = (3.6 µH/m * 10m) + 7.7 µH = 43.7 µH
- ClockSpring Loops
LDEPL(max) = LWire(3m*2) + LCSx + LEMI = (3.6µH/m * 3m) + [42.9 µH * (1 - 0.739)] + 7.7 µH = 29.7 µH
- ClockSpring Loops with short to ground
LDEPL(max) = LWire(3m) + LCSx + LEMI = (1.8µH/m * 3m) + 42.9µH + 7.7µH = 56 µH.
DocID029274 Rev 1
181/202
201
Electrical characteristics
L9678P, L9678P-S
Figure 59. Deployment drivers diagram
%3$%-)0ROTECTION
3YSTEM7IRING)MPEDANCE
3QUIB%-)
0ROTECTION
#LOCK3PRING
)MPEDANCE
2?#3
3QUIB,OAD
,?#3
3&X
2?7IRE
#?3&X
,?%-)
,?7IRE
2?3QUIB
K,?#38
7IRE,ENGHTM
32X
2?7IRE
,?7IRE
2?#3
#?32X
,?#3
'!0'03
Table 47. Deployment drivers - AC specifications
N°
Symbol
1
TDEPL_LO
Parameter
Condition
1.209 A rising to 1.209 A
falling
Deployment time
2
1.764 A rising to 1.764 A
falling
TDEPL_HI
3
Deployment current counter
resolution
Min
Typ
Max
Unit
2
-
2.268
ms
0.7
-
0.832
ms
0.5
-
0.613
ms
0
-
16
µs
-
-
32
µs
-
-
65
µs
-
-
32
µs
4
TDEP_RES
5
TRISE_IDEPL
6
TDEL_IDEP
7
TFALL_IDEPL
8
Low-side shutdown delay time
TDEL_SD-LS (with respect to high-side
deactivation)
-
50
-
-
µs
9
Low-side overcurrent to low-side
TFLT_LIM_LS deactivation deglitch time in short
to battery condition
-
80
100
120
µs
10
Low-side overcurrent to high-side
deactivation deglitch time in case
TOFF_OS_HS
of intermittent open squib
condition
-
-
-
20
µs
11
TOFF_OS_HS
-
4
-
12
µs
182/202
-
Rise time
10% - 90% of IDEPL
Delay time
SPI_CS to 90% IDEPL
SSxy = 25 V; RSQ = 2.2 Ω, 
C = 22 nF, L = 44 µH
Fall time
90% - 10% IDEPL
High-side off time in case of
intermittent open squib condition
DocID029274 Rev 1
L9678P, L9678P-S
Electrical characteristics
15.17
Squib diagnostic
15.17.1
Squib resistance measurement
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V, 6 V  SSxy  35 V; 7V  VRESDIAG 
35V.
Table 48. Deployment drivers diagnostics (Squib resistance)
N°
Symbol
1
RSQ_RANGE_1
2
RSQ_RANGE_2
Condition
Min
Typ
Max
Unit
Squib Resistance
Range 1
LPDIAGREQ(ISRC_CURR_SEL)= 0
0
-
10
Ω
Squib Resistance
Range 2
LPDIAGREQ(ISRC_CURR_SEL)= 1
0
-
50
Ω
GRSQ
Squib resistance
measurement
differential amplifier
gain
-
-2%
5.2
+2%
V/V
4
VOFF_RSQ
Squib Resistance
Measurement
Differential Amplifier
Output Offset
VOUT_RSQ = GRSQ x (VSF – VSR) +
Voff_RSQ
200
-
400
mV
5
ISRC_HI_SF
ISRC_HI_SR
Squib resistance
measurement high
current source
RSQ_RANGE = 1 Ωto 10 Ω
LPDIAGREQ(ISRC_CURR_SEL) = 0
LPDIAGREQ(ISRC) = "01" or "10"
-5%
40
+5%
mA
6
ISRC_LO_SF
ISRC_LO_SR
Squib resistance
measurement low
current source
RSQ_RANGE = 1 Ωto 50 Ω
LPDIAGREQ(ISRC_CURR_SEL) = 1 -10%
LPDIAGREQ(ISRC) = "01" or "10"
8
+10%
mA
7
ISRC_DELTA
Squib Resistance
Measurement
Delta Current Source
-
-5%
32
+5%
mA
8
SRISRC
Squib resistance
measurement
current source slewrate
-
4
7.5
11
mA/µs
9
VSRx_RM
SRx voltage during
Resistance
Measurement
LPDIAGREQ(ISRC) = ”01” or “10”
LPDIAGREQ(ISINK) = 1
0.5
0.7
1
V
10
ISINK_HI_SR
SRx current sink limit
high level
LPDIAGREQ(ISRC_CURR_SEL) = 0
LPDIAGREQ(ISINK) = 1
50
70
90
mA
11
ISINK_LO_SR
SRx current sink limit
low level
LPDIAGREQ(ISRC_CURR_SEL) = 1
LPDIAGREQ(ISINK) = 1
10
17.5
25
mA
12
IPD_SR
SRx current pull down
-
0.7
1
1.3
mA
13
RLKG_SF
Leakage resistance on
SFx
Leakage to GND ±1 V or to Battery
from 6 V to 18 V. Design info
1
-
-
kΩ
3
Parameter
DocID029274 Rev 1
183/202
201
Electrical characteristics
L9678P, L9678P-S
Table 48. Deployment drivers diagnostics (Squib resistance) (continued)
N°
Symbol
14
RSQ_ACC
15
-
15.17.2
Parameter
Condition
Min
Typ
Max
Unit
Accuracy of digital
resistance
measurement
After software calculation
All errors included
RSQ between 1.0 Ω and 10.0 Ω
With High Current Source (40mA)
-8
-
+8
%
EMI Input Low-pass
filter
Design Info
50
-
100
kHz
Squib leakage test (VRCM)
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V,
VDD3V3(min)  VDD3V3  VDD3V3(max).
Table 49. Squib leakage test (VRCM)
N°
Symbol
1
VOUT_VRCM
2
Parameter
Condition
Min
Typ
Max
Unit
Output Voltage on SF or
SR pins during Leakage
test
IOUT = 0 mA
-10%
2.5
+10%
V
IOUT = 6.6 mA
-8.7%
2.3
+8.7%
V
Detection threshold,
leakage to GND
Leakage detected if
RLKG_GSQ  1 kΩ and not
detected if RLKG_GSQ  10 kΩ
Design Info
1
-
10
kΩ
-15%
450
+15%
µA
1
-
10
kΩ
-15%
1.8
+15%
mA
3
RLKG_GSQ_TH
4
ILKG_GSQ_TH
Equivalent to resistance
range
5
RLKG_BSQ_TH
Leakage detected if LKG_BSQ
 1 kΩ and not detected if
RLKG_BSQ  10 kΩ
Design Info
6
ILKG_BSQ_TH
Detection threshold,
leakage to BATTERY
Equivalent to resistance
range
7
ILIM_VRCM_SRC VRCM current limitation
-
-20
-
-10
mA
8
ILIM_VRCM_SINK
-
10
-
20
mA
9
VSHIFT
Design Info
-1
-
1
V
10
RSQ_LOW_TH
Design Info
200
-
500
Ω
11
IRSQ_LOW_TH
-12%
6
+12%
mA
12
RSQ_HIGH_TH
2
-
5
kΩ
13
IRSQ_HIGH_TH
-15%
700
+15%
µA
14
TFLT_LKG
184/202
External ground or battery
shift
Detection Threshold for
“resistance too low”
Detection threshold for
“resistance too high”
Equivalent to resistance
range
Design Info
Equivalent to resistance
range
Leakage test deglitch filter
time
DocID029274 Rev 1
8
µs
L9678P, L9678P-S
15.17.3
Electrical characteristics
High/low side FET test
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V, 6 V  SSxy  35 V, 7V  VRESDIAG 
35V.
Table 50. High/low side FET test
N°
Symbol
1
IHS_FET_TH
Detection threshold
(HS FET test)
2
ILS_FET_TH
3
EFET_TESt
4
Parameter
Condition
Min
Typ
Max
Unit
-
-10%
1.8
+10%
mA
Detection threshold low
side FET test
-
-10%
450
+10%
µA
Energy transferred to
squib during HS/LS FET
tests
Design Info
-
-
170
µJ
-
1.3
1.5
1.7
µs
TFLT_HS_FET_TH FET Test deglitch filter
TFLT_LS_FET_TH time
5
TFETTIMEOUT
HS/LS FET test time-out
-
190
200
210
µs
6
SGxy_OPEN
Squib open ground
detection
GNDSUBx as ground
reference
300
450
600
mV
7
TFLT_SGOPEN
Squib open ground
detection filter time
-
46
50
54
µs
15.17.4
Deployment timer test
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35 V
Table 51. Deployment timer test
No
Symbol
1
tPULSE_IDLE
2
IPULSE_HIGH_00
3
IPULSE_HIGH_01
4
IPULSE_HIGH_10
5
IPULSE_HIGH_11
Parameter
Comments / Conditions
Deployment timer pulse
SYSDIAGREQ(DSTEST)=PULSE
Test Idle Time
SYSDIAGREQ(DSTEST)=PULSE
DCR_x(Deploy_Time) = 00
SYSDIAGREQ(DSTEST)=PULSE
Deployment timer pulse DCR_x(Deploy_Time) = 01
Test High Time
SYSDIAGREQ(DSTEST)=PULSE
DCR_x(Deploy_Time) = 10
SYSDIAGREQ(DSTEST)=PULSE
DCR_x(Deploy_Time) = 11
DocID029274 Rev 1
Min
Typ
Max
Unit
7
8
9
ms
-5%
8
+5%
µs
-5%
584
+5%
µs
-5%
792
+5%
µs
-5%
2160
+5%
µs
185/202
201
Electrical characteristics
15.18
L9678P, L9678P-S
Remote sensor interface
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD2(max)  VIN  35V, VSUP(min)  VSUP  VSUP(max).
Table 52. Remote sensor I/F DC parameters
N°
Symbol
1
IS_LOW
Is
2
3
VLIM_RSU
Parameter
Condition
Min
Typ
Max
Unit
Interface quiescent
current (low signal
current level)
According to PSI-5 v1.3,
section 5.1.2 - parameter #4
Design info
-19
-
-4
mA
Delta signal current
IS_HIGH - IS_LOW
According to PSI-5 v1.3,
section 5.4 - parameter #6
Design Info
22
-
30
mA
Output voltage
limitation
VSUP = VIN
According to PSI-5 v1.3,
section 5.1.1 - parameter #1
-
-
11
V
RSU power switch
resistance
(VVSUP – VRSU) / IRSU
IRSUx = 4-50 mA
According to PSI-5 v1.3,
section 6.2 - parameter #3
-
-
12.5
Ω
10
50
100
mV
-
-
5
mA
4
RDSON_RSU
5
VSTB_RSU
Output short to
battery threshold
-
6
ISTB_RSU
Static reverse
current into RSU pin
VRSU > VVSUP + VSTB_RSU
7
IOC_RSU
Over current
detection threshold
Interface disabled after
TFLT_STD_RSU
According to PSI-5 v1.3,
section 5.1.2 - parameter #8-9
-105
-
-50
mA
8
ILIM_RSU
Current limitation
RSU = 0
According to PSI-5 v1.3,
section 5.1.2, parameter #8-9
-105
-
-65
mA
9
∆ILIM_OC_RSU
Difference between
current limitation and ILIM_RSU - IOC_RSU
OC threshold
0.1
-
-
mA
10
IB0_RSU
Internal base current Default value of internal 7 bit
starting value
counter
-18
-15
-13
mA
11
IS_TH_RSU
12
ILKGG_RSU
13
ILKGB_RSU
14
IOL_RSU
186/202
Trigger point for
signal current
threshold
IRSU = ILOW_RSU = -19mA to
-4mA
Leakage to GND; detected by IB
Trigger point for fault
Leakage to BATTERY;
current detection
detected by IB
Output open load
detection threshold
RSU open
DocID029274 Rev 1
IB_RSU
+
(12-11%)
IB_RSU
IB_RSU
+
+
(12+11%)
12
mA
-48
-
-36
mA
-3.5
-
-1.5
mA
ILKGB(min)
-
ILKGB(max)
-
L9678P, L9678P-S
Electrical characteristics
Table 52. Remote sensor I/F DC parameters (continued)
N°
Symbol
15
DACRES
16
ILSB
17
CRSU
18
TJSD_ERBST
Parameter
19 THYS_TSDERBST
Condition
Min
Typ
Max
Unit
-
7
-
Bit
DAC resolution
Design info
LSB current
-
270
-
330
µA
EMC capacitor
22nF nominal
Design Info
13
-
-
nF
-
150
175
190
°C
-
5
10
15
°C
Thermal shutdown
Table 53. PSI-5 remote sensor transceiver - AC specifications
N°
Symbol
Parameter
1
TFLT_STD_RSU
Over Current
Shutdown Filter Time
2
TBLK_OC_RSU
Over current
shutdown filter time
3
Condition
Min
Typ
Max
Unit
Normal operation
500
-
600
µs
At interface power on
(BLKTxSEL = 0)
According to PSI-5 v1.3,
section 5.2 - parameter #1
4.6
-
5.4
ms
At interface power on
(BLKTxSEL = 1)
According to PSI-5 v1.3,
section 5.2 - parameter #2
9.4
-
10.8
ms
-
-
200
ns
12
-
16
µs
-
10
µs
Short to battery
comparator response
time
Guaranteed by design
TSTB_REC_RSU
Short to battery
recovery time
-
6
TFLT_TSD_RSU
Thermal shutdown
filter time
-
7
TFLT_OPEN_RSU
Open detection
deglitch filter time
-
10
-
15
µs
8
TFLT_LKG_RSU
Leakage deglitch filter
time
10
-
15
µs
4
TSTB_RSU
5
DocID029274 Rev 1
187/202
201
Electrical characteristics
15.19
L9678P, L9678P-S
DC sensor interface
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD2(max)  VIN  35V, 8.5 V  VRESDIAG  35 V.
Table 54. DC sensor interface specifications
N°
Symbol
Parameter
1
VOUT_DCSREG
Output voltage
regulation mode
2
ILIM_DCSREG
Current limitation
regulation mode
Condition
DCS Regulator enabled
Min
Typ
Max
Unit
-10%
6.25
+10%
V
24
27
30
mA
-1
-
1.4
V
DCS Regulator enabled
DCS = 0
3
VDCS_RANGE1
Voltage measurement
range1
First voltage
measurement
(VDCS_MEAS1) to
compensate external
ground shift and internal
offset
4
VDCS_ACC1
Voltage measurement
accuracy 1
VDCS = VDCS_RANGE1
Included ADC error
-15
-
15
%
5
VDCS_RANGE2
Voltage measurement
range 2
-
1.5
-
10
V
6
VDCS_ACC2
Voltage measurement
accuracy 2
VDCS = VDCS_RANGE2
Included ADC error
-8
-
+8
%
7
IDCS_RANGE1
Current measurement
range 1
-
1
-
2
mA
8
IDCS_ACC1
Current measurement
accuracy 1
IDCS = IDCS_RANGE1
Included ADC error
-30
-
+30
%
9
IDCS_RANGE2
Current measurement
range 2
-
2
-
22
mA
10
IDCS_ACC2
Current measurement
accuracy 2
IDCS = IDCS_RANGE2
Included ADC error
-12
-
+12
%
11
IDCS_RANGE3
Current measurement
range 3
Regulator in current
limitation
-
ILIM_DCSREG
-
mA
12
IDCS_ACC3
Current measurement
Accuracy 3
DCS = 0
Included ADC error
-12
-
+12
%
13
RDCS_RANGE
Design info
65
-
3000
Ω
15
%
14
188/202
RDCS_ACC
Resistance
Measurement
Range
Accuracy of digital
resistance
measurement
Performing both voltage
measurements 1 and 2
-15
After Software calculation
All errors included
DocID029274 Rev 1
L9678P, L9678P-S
Electrical characteristics
Table 54. DC sensor interface specifications (continued)
N°
Symbol
Parameter
15
IPD_DCS
Pull down current
16
RPD_DCS
17
ITOT_PD_DCS
18
CDCS
19
Min
Typ
Max
Unit
VDCS = 1.5V
70
100
130
µA
Pull down resistance
Device ON,
DCS Pull Down Current
disabled
90
150
210
kΩ
Total pull down current
ITOT_PD_DCS = IPD_DCS +
RPD_DCS
VDCS = 6.5V
100
140
200
µA
Output capacitance
Design Info
10
-
nF
IREF_IDCS
Internal current
reference for DCS
current measurement
-
-5%
300
+5%
µA
20
Ratio_VDCS
Divider ratio for DCS
voltage measurement
-
-3%
7.125
+3%
V/V
21
VOFF_DCS
Internal offset during
voltage measurement
-
-4%
0.375
+4%
V
15.20
Condition
Safing engine
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35V, VDDx(min)  VDDx  VDDx(max),
VDDQ = VDD5 or VDD3V3.
Table 55. Arming interface - DC specifications
N°
Symbol
1
VTH_H_ACL
2
Parameter
Condition
Min
Typ
Max
Unit
-
2.33
-
2.42
V
VTH_L_ACL
ACL input voltage
thresholds
-
1.58
-
1.67
V
3
VHYS_ACL
ACL hysteresis
-
0.6
0.75
0.9
V
4
RPD_ACL
ACL pull down resistance VACL = 3.3V
120
200
280
kΩ
5
VOH_ARM
ARM output high voltage
ILOAD = -0.5 mA
Internal safing selected
VDDQ
-0.60
-
VDDQ
V
6
VOL_ARM
ARM output low voltage
ILOAD = 2.0 mA
Internal safing selected
0
-
0.4
V
7
RPD_ARM
ARM pull down resistance -
65
100
135
kΩ
14
VIH_ FENH
FENH high level
input voltage
-
2
-
-
V
15
VIL_ FENH
FENH low level
input voltage
-
-
-
0.8
-
16
IPU_ FENH
FENH pull down current
FENH = VDDQ
20
45
70
µA
14
VIH_ FENL
FENL high level
input voltage
-
2
-
-
V
DocID029274 Rev 1
189/202
201
Electrical characteristics
L9678P, L9678P-S
Table 55. Arming interface - DC specifications (continued)
N°
Symbol
Parameter
Condition
Min
Typ
Max
15
VIL_ FENL
FENL low level
input voltage
-
16
IPU_ FENL
FENL pull up current
FENL = 0
14
VIH_SAF_CSx
SAF_CSx high level
input voltage
15
VIL_SAF_CSx
16
IPU_SAF_CSx
Unit
-
-
0.8
-70
-45
-20
µA
-
2
-
-
V
SAF_CSx low level
input voltage
-
-
-
0.8
-
SAF_CSx pull up current
SAF_CSx = 0V
-70
-45
-20
µA
Table 56. Arming interface - AC specifications
N°
Symbol
1
TARM
2
TACL_HI
3
TACL_LO
4
TON_ACL_HI
5
TON_ACL_LO
6
TVALID_EOL
7
TDIS_EOL
Parameter
Min
Typ
Max
Unit
-
475
500
525
µs
-
213
-
237
ms
-
168
-
187
ms
-
154
-
171
ms
-
114
-
126
ms
Scrap validation
TACL and TON_ACL valid
-
3
-
-
cycles
Scrap timeout
-
2 * TACL
-
-
-
0
ms
-
30
32
34
ms
-
242
270
ms
-
1934
2162
ms
Sensor sampling period
ACL period
ACL on-time
8
9
10
TPULSE_STRECH
Condition
Arming enable
pulse stretch time
11
ms
12
TRISE_ARM
ARM rise time
80pF load, 20% to 80%
Internal Safing Selected
-
-
1.00
µs
13
TFALL_ARM
ARM fall time
80pF load, 20% to 80%
Internal Safing Selected
-
-
1.00
µs
190/202
DocID029274 Rev 1
L9678P, L9678P-S
15.21
Electrical characteristics
General purpose output drivers
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD1(max)  VIN  35V; GPODx + 5V  ERBOOST.
Table 57. GPO interface DC specifications
N°
Symbol
Min
Typ
Max
Unit
1
VSAT_GPO
Output saturation
voltage
VGPOD – VGPOS
ILOAD = 70 mA
-
-
0.5
V
2
ILIM_GPO
Current limitation
VGPOD – VGPOS = 1.5 V
73
110
155
mA
3
IOC_GPO
Over current detection
threshold
-
73
110
155
mA
4
∆ILIM_OC_GPO
Difference between
current limitation and
OC threshold
ILIM_GPO - IOC_GPO
0.1
-
-
mA
5
IOL_GPO
Open load current
threshold
GPO ON condition; LS and HS
configuration
0.1
1
3
mA
Diagnostic current on
load
Voltage measurement in progress
through Analog MUX
Increased leakage for a short
specified time (32 µs)
-
-
130
µA
VGPOD = 18V
VGPOS = 0V
Power-off or sleep mode
-5
-
5
µA
ILKG_GPOD_ON
VGPOD = 18V
VGPOS = 0V
Active or passive mode
Driver off
-
-
100
µA
ILKG_GPOS_OFF
VGPOD = 18V
VGPOS = 0V
Power-Off or Sleep Mode or
ERBOOST = ERBOOST_OK
Driver OFF
-5
-
5
µA
VGPOD = 18V
VGPOS = 0V
(Active or Passive Mode) and
ERBOOST = ERBOOST_OK
Driver OFF
-
-
100
µA
VGPOS = VGPOD + 1V
Driver OFF
-
1
mA
6
IDIAG_GPO
7
ILKG_GPOD_OFF
Parameter
Condition
GPOD output leakage
current
8
9
GPOS output leakage
current
10
ILKG_GPOS_ON
11
IREV_GPO
12
TJSD_GPO
13
THYS_TSD_GPO
14
CGPO
Reverse current
Thermal Shutdown
Load capacitor
-
150
175
190
°C
-
5
10
15
°C
Min 10nF nominal
Design Info
6
-
-
nF
DocID029274 Rev 1
191/202
201
Electrical characteristics
L9678P, L9678P-S
Table 58. GPO Driver Interface - AC specifications
N°
Symbol
Parameter
Min
Typ
Max
Unit
1
SRGPO
Output voltage slew rate
30% - 70%;
RLOAD = 273Ω, CLOAD = 100nF
0.1
0.25
0.4
V/µs
2
TFLT_OC_GPO
Over current detection
filter time
-
10
12
14
µs
3
TFLT_OL_GPO
Open load detection filter
time
8
10
12
µs
4
TMASK_ON_GPO
Diagnostic mask delay
after switch ON
CGPO = 100nF typ
40
50
60
µs
5
TFLT_TSD
Thermal shutdown filter
time
-
-
-
10
µs
6
FPWM_GPO
PWM frequency
-
-
125
-
Hz
7
DCPWM_GPO
PWM duty cycle
Increment Step = 1.6%
0
-
100
%
192/202
Condition
DocID029274 Rev 1
L9678P, L9678P-S
15.22
Electrical characteristics
ISO9141 interface (K-LINE)
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD(max)  VIN  35V.
Table 59. ISO9141 interface DC specifications
N°
Symbol
Parameter
1
VIH_ISOTX
ISOTX high level
input voltage
2
VIL_ISOTX
3
VHYS_ISOTX
4
Condition
Min
Typ
Max
Unit
-
2
-
-
V
ISOTX low level
input voltage
-
-
-
0.8
V
ISOTX hysteresis
input voltage
-
150
-
500
mV
IPU_ISOTX
ISOTX pull up current
ISOTX = 0
-70
-45
-20
µA
5
CIN_ISOTX
ISOTX input
capacitance
Design Info
-
-
5
pF
6
VTH_DOM_ISOK
7
VTH_REC_ISOK
8
VHYS_ISOK
9
VO_DOM_ISOK
10
ISOK input receiver
threshold
ISOTX = 0V
VIN * VIN * VIN *
0.4
0.45
0.5
V
ISOTX = VDDQ
VIN * VIN * VIN *
0.5
0.55
0.6
V
-
VIN * VIN * VIN *
0.1
0.13
0.07
V
ISOK output voltage
ISOTX = 0V,
IISOK = 40mA
IOC_ISOK
ISOK over current
detection
11
ILIM_ISOK
12
∆ILIM_OC_ISOK
13
ISINK_ISOK
ISOK sink current
capability
14
ILKG_ISOK
ISOK input leakage
current
VIN < 18V, Driver Off (device is
supplied)
15
VOH_ISORX
ISORX output high
voltage
ILOAD = -0.5 mA
16
VOL_ISORX
ISORX output low
voltage
17
CIN
ISOK Input
Capacitance
18
TJSD_ISOK
19
THYS_TSD_ISOK
-
-
1.2
V
-
50
-
100
mA
ISOK current limitation
-
50
-
100
mA
Difference between
current limitation and
OC threshold
ILIM_ISOK - IOC_ISOK
0.1
-
-
mA
40
-
-
mA
-10
-
10
µA
VDD
Q
-0.60
-
VDD
Q
V
ILOAD = 2 mA
0
-
0.4
V
Design info
-
-
10
pF
-
150
175
190
°C
-
5
10
15
°C
Thermal shutdown
Design Info
DocID029274 Rev 1
193/202
201
Electrical characteristics
L9678P, L9678P-S
Table 60. ISO9141 interface transceiver AC specifications
N°
Symbol
Parameter
1
TFLT_TSD
Thermal shutdown filter
time
2
TBLK_ISOK
3
Min
Typ
Max
Unit
-
-
-
10
µs
Current limit fault
blanking time
-
8
-
12
µs
TRISE_ISORX
ISORX rise time
80pF load, 20%-80%
-
-
0.5
µs
4
TFALL_ISORX
ISORX fall time
80pF load, 20%-80%
-
-
0.5
µs
5
-
Baud rate
Design Info
-
62.5
-
kBd
6
TPD_ILTX
ISOTX High to Low to ISOK = 70%
* VO_REC_ISOK
RISOK=510Ω, CISOK=470pF
-
-
1
µs
Propagation delay
transmitter
Condition
7
TPD_IHTX
ISOTX Low to High to ISOK = 30%
* VO_DOM_ISOK
RISOK=510Ω, CISOK=470pF
-
-
1.5
µs
8
TPD_ILRX
ISOK = VTH_DOM_ISOK to ISORX
High to Low
RISOK=510Ω, CISOK=470pF
-
-
1.5
µs
ISOK = VTH_REC_ISOK to ISORX
Low to High
RISOK=510Ω, CISOK=470pF
-
-
1.5
µs
Propagation delay
receiver
9
TPD_IHRX
10
TRISE_ISOK
ISOK rise time
30% to 70%
RISOK=510Ω, CISOK=470pF
-
-
1.5
µs
11
TFALL_ISOK
ISOK fall time
70% to 30%
RISOK=510Ω, CISOK=470pF
-
-
1.5
µs
12
TPDW_RX
Receiver pulse width
symmetry
TPD_ILRX - TPD_IHRX
-
-
1
µs
13
TPDW_TX
Transmitter pulse width
symmetry
(TPD_ILTX + TFALL_ISOK) – (TPD_IHTX
+ TRISE_ISOK)
-
-
1
µs
194/202
DocID029274 Rev 1
L9678P, L9678P-S
15.22.1
Electrical characteristics
Analog to digital converter
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD(max)  VIN  35V.
Table 61. Analog to digital converter
N°
Symbol
Min
Typ
Max
Unit
1
VADC_RANGE
0.1
-
2.5
V
2
VADC_REF
ADC reference voltage
-
-1.5%
2.5
+1.5%
V
3
ADC_RES
ADC resolution(1)
Design Info
-
10
-
bit
DNL
Differential non linearity
error (DNL)
Separation between adjacent
levels, measured bit to bit of
actual and an ideal output step.
No missing codes
-1
-
+1
LSB
5
INL
Integral non linearity
error (INL)
Maximum difference between
the actual analog value at the
transition between 2 adjacent
steps and its ideal value
-3
-
+3
LSB
6
EQUANT
Quantization Error
Design Info
-0.5
-
0.5
LSB
7
TotErr
Total error
Includes INL, DNL, ADC
Reference voltage tolerance
and quantization error
-15
-
+15
LSB
8
TotErr_0v1
ADC total error for 0.1V
input voltage
-
-5
-
+5
LSB
9
TotErr_2v4
ADC total error for 2.4V
input voltage
-
-15
-
+15
LSB
10
-
Pre-ADC settling time
-
-
4.81
-
µs
11
-
Single conversion time
-
-
2.25
-
µs
12
-
Intra-queue settling time -
-
3.5
-
µs
13
-
Post- ADC settling time
-
-
3.44
-
µs
14
-
ADC conversion time voltage
4x sampling for each of the 4
conversions in the queue
Design Info
-
54.75
-
µs
ADC conversion time –
current and voltage
8x sampling for DCS,
temperature and squib loop
resistance measurements + 4x
sampling for remaining 2
conversions in the queue
Design Info
-
51.25
-
µs
4
15
-
Parameter
Condition
ADC input voltage range -
1. LSB = (2.5 V / 1024) = 2.44 mV
DocID029274 Rev 1
195/202
201
Electrical characteristics
15.23
L9678P, L9678P-S
Voltage diagnostics (analog Mux)
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD(max)  VIN  35V.
Table 62. Voltage diagnostics (Analog MUX) DC specifications
N°
Symbol
1
Ratio_1
VIN_RANGE1 = 0.1V … 2.5V
2
Ratio_4
3
Ratio_7
4
5
6
Parameter
Condition
Min
Typ
Max
Units
-
1
-
V/V
VINPUT_RANGE2 = 1V … 10V
(where applicable)
-3%
4
+3%
V/V
VINPUT_RANGE_3 = 1.5V … 17.5V
(where applicable)
-3%
7
+3%
V/V
Ratio_10
VINPUT_RANGE_4 = 2V … 25V
(where applicable)
-3%
10
+3%
V/V
Ratio_15
VINPUT_RANGE_5 = 3V … 35V
(where applicable)
-3%
15
+3%
V/V
High impedance
-10
-
10
mV
Multiplexer input to GNDA
80
-
-
kΩ
Multiplexer input to GNDA
120
-
-
kΩ
Multiplexer input to GNDA
160
-
-
kΩ
Multiplexer input to GNDA
200
-
-
kΩ
-
-
60
µA
-12
-
+12
%
Divider ratios
VOFFSET_RATIO_X Divider offset
7
RRATIO_4
8
RRATIO_7
9
RRATIO_10
10
RRATIO_15
11
ILEAK_RATIO_X
12
VMEAS_ACC
15.24
Multiplexer input
resistance
Additional multiplexer
on-state input
For All Divider Ratio expect Ratio_1
leakage current
Voltage
measurement
accuracy
All range
All errors included
Temperature sensor
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C  Ta  +95 °C, VINGOOD(max)  VIN  35V.
Table 63. Temperature sensor specifications
N°
Symbol
1
TMON_RANGE
2
TMON_ACC
196/202
Parameter
Condition
Min
Typ
Max
Units
Monitoring temperature
range
-40
-
150
°C
Monitoring temperature
accuracy
-15
-
15
°C
DocID029274 Rev 1
L9678P, L9678P-S
Quality information
16
Quality information
16.1
OTP trim bits
The device has 43 fuse programmable bits which are used to tune and refine performance
characteristics of the device and also provide detailed identification of each component.
These bits are only available during production testing and require activation of a special
test mode. These bit values are confirmed every transition from POR, and reported in
Section 5.1.1: Fault status register (FLTSR) if an error is found.
The OTP CRC is implemented using the polynomial calculation (g(x)=1+x+x^3 with
initialization value equal to "111").
Equivalent equations are:
CRC[2] =
C0in + C1in + C2in + d1 + d11 + d12 + d13 + d15 + d18 + d19 + d20 + d22 + d25 + d26
+ d27 + d29 + d32 + d33 + d34 + d36 + d39 + d4 + d40 + d41 + d5 + d6 + d8
CRC[1] =
C0in + C1in + d0 + d12 + d13 + d14 + d16 + d19 + d2 + d20 + d21 + d23 + d26 + d27 +
d28 + d30 + d33 + d34 + d35 + d37 + d40 + d41 + d42 + d5 + d6 + d7 + d9
CRC[0] =
C1in + C2in + d0 + d10 + d11 + d12 + d14 + d17 + d18 + d19 + d21 + d24 + d25 + d26
+ d28 + d3 + d31 + d32 + d33 + d35 + d38 + d39 + d4 + d40 + d42 + d5 + d7
where d[42:0] are the 43 OTP bits and Cxin are the starting seed values (all '1').
DocID029274 Rev 1
197/202
201
Package information
17
L9678P, L9678P-S
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
17.1
LQFP64 (10x10x1.4 mm) package information
Figure 60. LQFP64 (10x10x1.4 mm) package outline
6($7,1*
3/$1(
F
$
$
$
&
E
FFF
PP
*$*(3/$1(
&
$
.
/
'
/
'
'
3,1
,'(17,),&$7,21
(
(
(
H
*$3*36
B+B:
198/202
DocID029274 Rev 1
L9678P, L9678P-S
Package information
Table 64. LQFP64 (10x10x1.4 mm) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.60
-
-
0.0630
A1
0.05
-
0.15
0.0020
-
0.0059
A2
1.350
1.40
1.45
0.0531
0.0551
0.0571
b
0.17
0.22
0.27
0.0067
0.0087
0.0106
c
0.09
-
0.20
0.0035
-
0.0079
D
11.80
12.00
12.20
0.4646
0.4724
0.4803
D1
9.80
10.00
10.20
0.3858
0.3937
0.4016
D3
-
7.50
-
-
0.2953
-
E
11.80
12.00
12.20
0.4646
0.4724
0.4803
E1
9.80
10.00
10.20
0.3858
0.3937
0.4016
E3
-
7.50
-
-
0.2953
-
e
-
0.50
-
-
0.0197
-
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
-
1.00
-
-
0.0394
-
-
0.0031
K
ccc
0° (min.), 3.5° (typ.) 7° (max.)
-
-
0.08
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID029274 Rev 1
199/202
201
Package information
17.2
L9678P, L9678P-S
LQFP64 (10x10x1.4) marking information
Figure 61. LQFP64 (10x10x1.4) marking information
0DUNLQJDUHD$
0DUNLQJDUHD%
/DVWWZRGLJLWV
(6(QJLQHHULQJVDPSOH
EODQN!&RPPHUFLDOVDPSOH
3LQ5HI
/4)374)37239,(:
QRWLQVFDOH
*$3*36B(6
Parts marked as ‘ES’ are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted to run a qualification activity prior to any decision to use
these engineering samples.
200/202
DocID029274 Rev 1
L9678P, L9678P-S
18
Revision history
Revision history
Table 65. Document revision history
Date
Revision
05-May-2016
1
Changes
Initial release.
DocID029274 Rev 1
201/202
201
L9678P, L9678P-S
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
202/202
DocID029274 Rev 1
Similar pages