CLRC663 Quickstart Guide

AN11022
CLRC663 Quickstart Guide
Rev. 1.2 — 14 January 2015
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Document information
Info
Content
Keywords
RC663, Reader IC, Power Supply, Interfacing RC663, RC663 Quick start
up, Functional description, Register settings
Abstract
This document describes the required basic circuitry to operate the
RC663 and it also describes how to set up first communication using the
RC663 Design-In Board (Demo Board V 3_0)
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CLRC663 Quickstart Guide
Revision history
Rev
Date
Description
1.2
20150114
Fig 8 RC663 Schematic updated
1.1
20120712
Some Figures updated because of quality reasons, Section Licenses updated
1.0
20120216
Initial release
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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1. Introduction
This document describes the basic requirements to power up the reader IC. This
application note does not replace the CLRC663 datasheet. Please refer to the datasheet
to read more information on each chapter. This document also gives an overview of the
RC663 evaluation reader board and describes the function and first steps of using the
board and the RC663. For this Application Note Version 3.0 of the 663 reader board is
used.
2. General description of the RC663
The RC663’s overall functionality can be separated into three functions:
1. Generate the RF field: The generated magnetic field has to be maximized within the
limits of the transmitter supply current, general emission limits and requirements to
protocol standards.
2. Transmit data: The coded and modulated data signal has to be transmitted in a way,
that all supported card standards are able to receive it. The signal shape and timing
according to relevant standards has to be considered.
3. Receive data: The response of a card or NFC passive device has to be transferred
to the differential or single sided receive input of the RC663 considering various
limits, e.g. maximum voltage and receiver sensitivity.
In the following chapters the general wiring just like the power supply concept, interface
selection and so on is described.
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2.1 Basic wiring
The basic wiring diagram can be found in Fig 1. The matching procedure of the antenna
can be found in the application note AN11019 (Ref. 2).
470 nF
470 nF
Fig 1.
Basic wiring diagram
It is recommended that Input pins which are not used be tied to a defined electrical
potential.
Output pins can be floating.
2.2 Power supply concept
The CLRC663 is supplied by VDD - Supply voltage, PVDD- pad supply and TVDD- Tx
power supply. These three voltages are independent and can have different as well as
the same supply voltage values. e.g. to operate with a 3.3 V supplied Microcontroller,
PVDD and VDD shall be 3.3 V, to guarantee maximum field strength TVDD shall be 5V.
Voltages between 3 V to 5.5 V can be applied to VDD, PVDD and TVDD.
Independent of the voltage it is recommended to buffer these supplies with blocking
capacitors. VDD and PVDD min 100 nF; TVDD min 100 nF parallel to 1 uF
NOTE: AVDD and DVDD are not Voltage inputs! Buffer them with blocking
capacitances of 470 nF each.
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VDD
HPD
Control
PD
PDOWN
AVDD
DVDD
V-Regulators 1.8V
PMU
TVDD
TX1
TX
TX2
TVSS
Fig 2.
Power supply diagram
2.3 Interface selection
The CLRC663 supports direct interfacing of various hosts as the SPI, I2C, I2CL and serial
UART interface type. The CLRC663 resets its interface and checks the current host
interface type automatically having performed a Power-On or Hard Reset. The CLRC663
identifies the host interface by the means of the logic levels on the control pins after the
Reset Phase. This is done by a combination of fixed pin connections IF1SEL0 and
IF1SEL1. The following table shows the different configurations:
Table 1.
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Connection Scheme for detecting the different Interface Types
UART
SPI
I2C
IF0
I/O
Rx
IF1(SCL)
I/O
IF2
I/O
IF3-SDA
SDA
IFSEL0
IFSEL1
I2C-L
MOSI
ADR1
ADR1
SCK
SCL
SCL
Tx
MISO
ADR2
SDA
Trigger
NSS
SDA
ADR2
I
0
0
1
1
I
0
1
0
1
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2.4 Crystal oscillator
The clock applied to the CLRC663 acts as a time basis for generation of the carrier sent
out at TX, for the quadrature mixer I and Q clock generation, and for the coder and
decoder of the synchronous system. Therefore, stability of the clock frequency is an
important factor for proper performance. To obtain highest performance, clock jitter has
to be as small as possible. This is best achieved by using the internal oscillator buffer
with the recommended circuitry.
Fig 3.
Table 2.
Symbol
Crystal connection
Crystal requirements recommendations
Parameter
min
Typ
fxtal
Crystal frequency
∆fxtal
Crystal frequency accuracy
ESR
Equivalent series resistant
50
CL
Load capacitance
10
Pxtal
Crystal power dissipation
50
max
27.12
-250
Unit
MHz
+250
ppm
100
Ω
pF
100
uW
2.5 Receiver circuit
The Receiver is a fully differential circuit and can be used double ended or single
ended:
 For single ended use (Quasi- Differential) of the receiver circuit it is strongly
recommended to connect RxN and RxP to each other or to connect them by
using the Rcv_Reg register (address 38h).But if the Rcv_Rx_single bit in the
Rcv_Reg register is set to 1 -> Quasi-Differential, the unused Rx pin has to
be open and not connected to Ground.
 For double ended use connect RxN and RxP, as recommended, to the
transmitter circuit, directly after the EMC filter.
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3. Hardware design of the RC663 evaluation board (“red board”)
3.1 Scope
This part describes the functionality of the evaluation reader based on the RC663. It
includes the functional and electrical specifications and gives the needed details to use
this reader as a reference design.
This reader implementation is based on the HVQFN33 package (body 5 x 5 x 0.85 mm).
The RC663 itself is described in the corresponding data sheet (see reference [1]).
3.2 Features
• Single 7.5 V external power supply
• RS232 DSUB9 connector for easy connection to a host PC
• RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage
supply
• Supports transfer speed communication up to 848 kbit/s with credentials
• I/O pins (GPIO0/SIGIN; SIGOUT)
• Hard Power Down
• Standby mode
• Programmable and cascadable timers
• FiFo buffer handles 512 byte send and receive
• IntegerN PLL providing clock for standard microcontroller used frequencies
• Low power card detection
• Integrated Free-Running Low Power Oscillator
• Digital test signal pins CLKOUT,SIGOUT,TCK,TDI,TDO,TMS
• versatile quadrature receiver architecture with fully differential receiver
• Antenna size: 113 mm x 77 mm
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3.3 Functional description
The RC663 evaluation reader is a contactless smartcard reader based on the RC663
reader IC.
The Reader PCB is divided into 2 Parts, the general reader part and The Antenna and
matching part:
Table 3.
PCB sections
PCB Section
Description
General reader part
(Fig 5 lower figure)
Includes Power supply, Rs232 Interface and
RC663 related part also EMC filter for TX circuit
Antenna and matching part
(Fig 5 lower figure)
Antenna matching (without EMC filter) with fully
differential receiver circuit and PCB antenna coil
The reader has one drawn cutline between EMC filter and matching circuit. This is to cut
the antenna and the antenna related matching from the reader (Fig 4). Seven vias have
been added to connect another Antenna with matching to the evaluation reader.
Fig 4.
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RC663 board version 3.0
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3.4 PCB Marking and major improvements to older version
There are two versions of the RC663 board version 2.0 and version 3.0
The latest version is:
NXP
RC663 Board V3.0
The difference is shown below (Fig 5)
Improvements form V 2.0 to V 3.0:
 Adding a Cutline to separate the general reader part from the Antenna and
matching part
 Analog debug pins are outlined
 Adding pins for current measurement on TVDD
 Prepared for adding another antenna with matching
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NXP RC663 Board V2.0
NXP RC663 Board V3.0
Fig 5.
NXP RC663 Board V2.0 and 3.0
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3.5 Schematic description
The following parts describe the RC663 evaluation reader board schematic, the part list,
and the layout of the PCB completely in order to give the user the possibility to take the
evaluation reader as a reference design for contactless smartcard reader integration.
3.6 Interface section
3.6.1 Power supply
Fig 6.
Power supply circuit
The power supply can be connected with a 2.5 mm dc plug. The polarity of the plug is
managed automatically on the PCB. The supplied voltage should be in a range of 7.5 V
to 12.0 V and can be unregulated. The power supply should be able to provide at least
250 mA.
The main supply voltage at TVDD and PVDD is 5 V.
The Core supply Voltage at AVDD and DVDD is 1.8 V.
After plugging the voltage supply, the LED on the PCB should light up.
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3.6.2 RS232 Host interface
Fig 7.
RS232 interface and transceiver
The DSUB-9 socket is used for a standard RS232 connection to the PC.
For this interface the following values are assembled:
Table 4.
Device
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Used devices for RS232 interface
Value
C1
1 μF
C6
1 μF
C7
220 nF
C8
1 μF
C9
1 μF
R3
Not assembled
R9
0Ω
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Table 5.
Pin
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DSUB-9 Pinning for RS232
Signal
D
Voltage
1
DCD (Data Carrier Detect)
O
± 3 – 12 V
2
RD (Receive Data)
O
± 3 – 12 V
3
TD (Transmit Data)
I
± 3 – 12 V
4
DTR (Data Terminal Ready)
I
± 3 – 12 V
5
GND
Pwr
6
DSR (Data Set Ready)
O
± 3 – 12 V
7
RTS (Ready To Send)
I
± 3 – 12 V
8
RTS (Ready To Send)
O
± 3 – 12 V
9
RI (IRQ)
O
± 3 – 12 V
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3.6.3 Microcontroller interface type
The CLRC663 supports direct interfacing of various hosts as the SPI, I2C, I2CL and
serial
UART interface type. The CLRC663 resets its interface and checks the current host
interface type automatically having performed a Power-On or Hard Reset. The CLRC663
identifies the host interface by the means of the logic levels on the control pins after the
Reset Phase. This is done by a combination of fixed pin connections. The Table 1 on
page 5 shows the different configurations.
3.6.4 USB-RS232 adapter
The development boards make use of a serial RS232 interface which is connected to a
PC to execute scripts or other PC based software to control the functionality of the
contactless reader IC.
More and more it is found that modern PC’s are not equipped by default with the RS232
interface.
A standard interface available on most PCs is the USB interface. USB to serial
converters convert the signals of a USB interface to RS232 signals are available in the
market.
In practice we have found that not all USB /RS232 converters are working without
problems. The reason for this problem could be that the designers of this interface need
to find a compromise to fit most applications, so that it does not fit very well to the use
case of transferring contactless data.
To avoid this problem more information’s about RS232 to USB converter and the right
configuration can be found in AN11116 (“Using the RS232 serial evaluation boards on a
USB port”) on CLRC 663 web page.
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3.6.5 RC663 schematic
This part shows a short overview of the RC336 schematic with all connections and also
the oscillator part of the evaluation reader.
Fig 8.
Table 6.
Device
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RC663 Schematic
Used devices for RC663 Schematic including oscillator
Value
R1 / R2
47 kΩ
Crystal
EPSON TOYOCOM - FA-128, 27.120000 MHZ, +-15PPM CRYSTAL ,FA-128,27.120000 MHZ,+-15PPM
C12
12 pF
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3.6.6 Antenna circuit
The Transceiver circuit is divided into 3 Parts: the Antenna, Matching Circuit, and EMC
Filter. The matching part of the transceiver circuit is responsible for the matching
resistance of the whole Tx circuit. To tune your Antenna to the target resistance C1 and
C2 have to be adjusted. For more information’s about Antenna design and Tuning see
AN11019 (“CLRC Antenna Design Guide”) and AN78010 (“13.56 MHz RFID Proximity
Antennas”).
Fig 9.
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Antenna and transceiver circuit
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Fig 10. Schematic of the Antenna and Transceiver circuit
Table 7.
Used devices for RC663 Schematic including oscillator
Device
Value
R7 / R8
Rq
Damping Resistors for Q limitation
C2
C1
4,7 Ω
C25
12 pF
C26
12 pF
C35
150 pF
C36
150 pF
C2
10 pF
C18
10 pF
C21
22 pF
C30
18 pF
C45
18 pF
C46
22 pF
470 nH
L1
EMC
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L2
WE-MK 0.47uH 200mA, manufacturer Würth Elektronik;
manufacturer. part-nr. 74479032
470 nH
WE-MK 0.47uH 200mA, manufacturer Würth Elektronik;
manufacturer. part-nr. 74479032
C24
56 pF
C27
68 pF
C47
56 pF
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Device
Value
C48
68 pF
R12
15 kΩ
R13
15 kΩ
R17
n.A.
R20
Receiver
C19
circuit
C20
n.A.
C41
1 nF
R10
1 kΩ
R18
1 kΩ
100 nF
1 nF
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3.7 PCB description and functionality
3.7.1 Top layer and placing
Fig 11. Top layer RC663 board
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Fig 12. Parameter Selection Placement Top Layer
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3.7.2 Bottom, middle layer and placing
Fig 13. Bottom layer RC663 board
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Fig 14. Placement bottom Layer
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Fig 15. Middle layer RC663 board
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3.7.3 PCB antenna section
Refer to section 0
Receiver RxN
EMC Filter
Damping
Matching resistors
circuit
Receiver RxP
Fig 16. PCB antenna section
The matching circuit and the antenna with damping resistor part of the RC663 board can
be separated by cutting the board along the white dashed line on the top side of the
board. This line is shown in black in Fig 16. The EMC filter is left on the board. After
cutting the antenna and matching circuit the receiver resistor, for the voltage divider, R12
and R13 (these resistors are also on the antenna and matching side) can be replaced by
using R17 and R20. Both resistors are not assembled, they are only for the case that the
antenna section is cut from the reader part.
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To connect a different antenna, J1-J7 can be used (after cutting the board).
Table 8.
Antenna section connector
Connector via
Signal
J1
Tx2
J2
Tx1
J3
GND
J4
RxP
J5
RxN
J6
GND
J7
GND
4. Register Settings for different modes and features
4.1 EMD suppression
The EMD suppression feature is only for ISO 14443 use cases.
If an error occurs within the first three bytes or the frame is < 3 bytes, this frame is
seen as EMD and ignored. If RxForceCRCWrite is set, the FIFO should not be read out
before three bytes are written into. The FIFO is cleared automatically in case of an EMD
error. A collision is treated as error.
To activate the EMD suppression the EMD_SUP Bit in the RxCtrl Register has to be set.
(Table 9)
Table 9.
Bit
RxCtrl_Reg register (address 35h); reset value: 04h
7
6
5
4
Symbol
Access rights
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3
0-2
Baud rate
RxAllow
Rx
RxEOF
EGT_
EMD_
Bits
Multiple
Type
Check
Sup
r/w
r/w
r/w
r/w
r/w
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4.2 Load Protocol command
The Load Protocol command reads data from the internal EEPROM and initializes the
CLRC663 registers needed for a Protocol change.
The command reads out the EEPROM (RX and TX protected area) and copies the
values from the RX- and TX protected area into the Registers.
The RX and TX protected area is a special area in the EEPROM with read access only.
The load protocol command loads only the values for the registers 0x48 and 0x4A –
0x5F. The command loads only these registers because they are only related to the type
of protocol that is used and not hardware or software related. From this it follows that the
rest of the registers, for the chosen protocol have to be set in addition (see chapter 4.3
and following).
The Parameter for the command is:
Protocol Number RX (1 byte, 0x00 - 0xFF) + Protocol Number TX (1 byte, 0x00 - 0xFF)
The following table (Table 10) is an overview over the predefined protocols that can be
loaded.
Note: The predefined Values for the RX and TX Protected area are shown in the
ID2 antenna charts in Chapters 4.3 and following (marked in blue
).
Table 10.
Protocol
Number
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
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Predefined protocol overview
Protocol
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
FeliCa
FeliCa
ISO/IEC15693
ISO/IEC15693
ISO/IEC15693
EPC/UID
ISO/IEC18000-3
Mode 3
Transmitter
speed [kbits/s]
106
212
424
848
106
212
424
848
212
424
Modulation
Miller
Miller
Miller
Miller
NRZ
NRZ
NRZ
NRZ
Manchester
Manchester
¼
¼
1/256
Unitray
Tari, ASK,PIE
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Receiver
speed
[kbits/s]
106
212
424
848
106
212
424
848
212
424
Modulation
Manchester SubC
BPSK
BPSK
BPSK
BPSK
BPSK
BPSK
BPSK
Manchester
Manchester
SSC
DSC
SSC
SSC
2/424
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Example for using the load protocol with the CLRC663 PcSerial.3.6.exe.:
CLL
CHB 115200
Terminate any running command. Flush_FiFo
SR 00 00
SR 02 b0
// Clear all IRQ 0,1 flags
SR 06 7f
SR 07 7f
//> Write in Fifo: Tx and Rx protocol numbers(0,0)
GR 04
SR 05 04 // Rx protocol=0
SR 05 04
// Tx prot=0
// Enable IRQ0 interrupt sources
//
// Idle interrupt(Command terminated), RC663_BIT_IDLEIRQ=0x10
GR 08
SR 08 10
// Enable Global IRQ propagation.
GR 09
SR 09 40
//> Start RC663 command "Load Protocol"=0x0d
SR 00 0D
::: L_LoadProtocol
GR 07
JNM IOR 40 40 L_LoadProtocol
// Disable Irq 0,1 sources
SR 08 00
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SR 09 00
//> Flush Fifo. Read Error Reg
SR 02 B0
GR 0A
4.3 ISO/IEC 14443 Type A recommended register settings
The following section gives an overview of the recommended register settings for
ISO/IEC 14443 Type A communication, with different Antenna sizes (ID1, ID2, ID3).
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4.3.1 ISO/IEC 14443 Type A for 77x113 mm 2-turn sized antenna
Table 11.
TX_Protected
RX_Protected
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Register settings Type A ID2 sized antenna
Reg
Reg descr
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8A
0x08
0x21
0x1A
0x18
0x18
0x0F
0x27
0x00
0xC0
0x12
0xCF
0x00
0x04
0x90
0x32
0x12
0x0A
0x20
0x04
0x50
0x40
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x50
0x02
0x00
0x00
0x01
0x00
0x08
0x80
0xF0
0x8E
0x12
0x11
0x06
0x18
0x18
0x0F
0x10
0x00
0xC0
0x12
0xCF
0x00
0x05
0x90
0x3F
0x12
0x02
0x20
0x05
0x50
0x50
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x50
0x22
0x00
0x00
0x00
0x00
0x0D
0x80
0xB2
0x8E
0x12
0x11
0x06
0x18
0x18
0x0F
0x08
0x00
0xC0
0x12
0xCF
0x00
0x06
0x90
0x3F
0x12
0x0A
0x20
0x06
0x50
0x60
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x50
0x22
0x00
0x00
0x00
0x00
0x0D
0x80
0xB2
0x8F
0xDB
0x11
0x06
0x18
0x18
0x0F
0x02
0x00
0xC0
0x12
0xCF
0x00
0x07
0x90
0x3F
0x12
0x02
0x20
0x07
0x50
0x70
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x50
0x22
0x00
0x00
0x00
0x00
0x0D
0x80
0xB2
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
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AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
ISO/IEC 14443 Type B recommended register settings
The following section gives an overview of the recommended register settings for
ISO/IEC 14443 Type B communication, with different Antenna sizes (ID1, ID2, ID3).
4.3.2 Type B for 77x113 mm 2-turn sized antenna
Table 12.
TX_Protected
RX_Protected
AN11022
Application note
COMPANY PUBLIC
Register settings Type B ID2 sized antenna
Reg
Reg descr
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0xCC
0x01
0x06
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x34
0x90
0x3F
0x12
0x0a
0x09
0x04
0x08
0x04
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xB2
0x8F
0xCC
0x01
0x06
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x35
0x90
0x3F
0x12
0x02
0x09
0x05
0x08
0x05
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xB2
0x8F
0xCC
0x01
0x06
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x36
0x90
0x3F
0x12
0x09
0x09
0x06
0x08
0x06
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xB2
0x8F
0xCC
0x01
0x06
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x37
0x90
0x3F
0x12
0x02
0x09
0x07
0x08
0x07
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xB2
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205912
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AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.3.3 Type B for ID3 sized antenna
Table 13.
AN11022
Application note
COMPANY PUBLIC
Register settings Type B ID3 sized antenna
Reg
Reg descr
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0x0C
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x34
0x90
0x66
0x12
0x0A
0x09
0x04
0x08
0x04
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xF0
0x8F
0x0C
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x35
0x90
0x66
0x12
0x02
0x09
0x05
0x08
0x05
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xF0
0x8F
0x0C
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x36
0x90
0x66
0x12
0x02
0x09
0x06
0x08
0x06
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xF0
0x8F
0x0C
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x01
0x00
0x05
0x00
0x37
0x90
0x66
0x12
0x02
0x09
0x07
0x08
0x07
0x00
0x03
0x00
0x01
0x00
0x00
0xAB
0x00
0x00
0x08
0x00
0x04
0x00
0x00
0x00
0x02
0x0D
0x80
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
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AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.4 FeliCa recommended register settings
The following section gives an overview of the recommended register settings for FeliCa
communication, with different antenna sizes (ID1, ID2, ID3).
4.4.1 FeliCa for ID1 sized antenna
Table 14.
AN11022
Application note
COMPANY PUBLIC
Register settings FeliCa ID1 sized antenna
Reg
Reg descr
212 kbit/s
424 kbit/s
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0x4F
0x01
0x0A
0x09
0x09
0x08
0x00
0x03
0x80
0x12
0x01
0x00
0x05
0x10
0x3C
0x12
0x02
0x80
0x05
0x01
0x05
0xB2
0x4D
0x00
0x00
0x00
0x00
0x0F
0x00
0x01
0x01
0x00
0x18
0x00
0xB2
0x4D
0xF0
0x19
0x20
0xF0
0x8F
0x4F
0x01
0x0A
0x09
0x09
0x08
0x00
0x03
0x80
0x12
0x01
0x00
0x06
0x40
0x3C
0x12
0x02
0x80
0x06
0x01
0x06
0xB2
0x4D
0x00
0x00
0x00
0x00
0x0F
0x00
0x01
0x01
0x00
0x18
0x00
0xB2
0x4D
0xF0
0x19
0x50
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
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AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.4.2 FeliCa for ID2 sized antenna
Table 15.
TX_Protected
RX_Protected
AN11022
Application note
COMPANY PUBLIC
Register settings FeliCa ID2 sized antenna
Reg
Reg descr
212 kbit/s
424 kbit/s
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0x17
0x01
0x06
0x09
0x09
0x08
0x00
0x03
0x80
0x12
0x01
0x00
0x05
0x10
0x3F
0x12
0x02
0x80
0x05
0x01
0x05
0xB2
0x4D
0x00
0x00
0x00
0x00
0x0F
0x00
0x01
0x01
0x00
0x18
0x00
0xB2
0x4D
0xF0
0x19
0x20
0xF0
0x8F
0x17
0x01
0x06
0x09
0x09
0x08
0x00
0x03
0x80
0x12
0x01
0x00
0x06
0x40
0x3F
0x12
0x02
0x80
0x06
0x01
0x06
0xB2
0x4D
0x00
0x00
0x00
0x00
0x0F
0x00
0x01
0x01
0x00
0x18
0x00
0xB2
0x4D
0xF0
0x19
0x50
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
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AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.4.3 FeliCa for ID3 sized antenna
Table 16.
AN11022
Application note
COMPANY PUBLIC
Register settings FeliCa ID3 sized antenna
Reg
Reg descr
212 kbit/s
424 kbit/s
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0x17
0x01
0x0A
0x09
0x09
0x08
0x00
0x03
0x80
0x12
0x01
0x00
0x05
0x10
0x3C
0x12
0x02
0x80
0x05
0x01
0x05
0xB2
0x4D
0x00
0x00
0x00
0x00
0x0F
0x00
0x01
0x01
0x00
0x18
0x00
0xB2
0x4D
0xF0
0x19
0x20
0xF0
0x8F
0x17
0x01
0x0A
0x09
0x09
0x08
0x00
0x03
0x80
0x12
0x01
0x00
0x06
0x40
0x3C
0x12
0x02
0x80
0x06
0x01
0x06
0xB2
0x4D
0x00
0x00
0x00
0x00
0x0F
0x00
0x01
0x01
0x00
0x18
0x00
0xB2
0x4D
0xF0
0x19
0x50
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
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34 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.5 ISO/IEC 15693 recommended register settings
The following section gives an overview of the recommended register settings for
ISO/IEC 15693 communication, with different Antenna sizes (ID1, ID2, ID3).
4.5.1 ISO/IEC 15693 for ID1 sized antenna
Table 17.
AN11022
Application note
COMPANY PUBLIC
Register settings I-Code ID1 sized antenna
Reg
Reg descr
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
SLI ¼
SLI ¼
SSC26
SSC52
DSC
0x8F
0x4F
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x02
0x10
0x44
0x12
0x06
0x00
0x83
0x04
0x40
0x00
0x00
0x00
0x00
0x84
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x24
0x60
0xF0
0x8F
0x4F
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x03
0x10
0x44
0x12
0x06
0x00
0x83
0x04
0x40
0x00
0x00
0x00
0x00
0x84
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x24
0x40
0xF0
0x8E
0x4F
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x02
0x10
0x44
0x12
0x06
0x00
0x93
0x04
0x40
0x00
0x00
0x00
0x00
0x81
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x26
0x60
0xF0
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Rev. 1.2 — 14 January 2015
205912
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AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.5.2 ISO/IEC 15693 for ID2 sized antenna
Table 18.
TX_Protected
RX_Protected
AN11022
Application note
COMPANY PUBLIC
Register settings I-Code ID2 sized antenna
Reg
Reg descr
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
SLI ¼
SLI ¼
SSC26
SSC52
DSC
0x8F
0x10
0x01
0x06
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x02
0x10
0x44
0x12
0x06
0x00
0x83
0x04
0x40
0x00
0x00
0x00
0x00
0x84
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x24
0x60
0xF0
0x8F
0x10
0x01
0x06
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x03
0x10
0x44
0x12
0x06
0x00
0x83
0x04
0x40
0x00
0x00
0x00
0x00
0x84
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x24
0x40
0xF0
0x8E
0x10
0x01
0x06
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x02
0x10
0x44
0x12
0x06
0x00
0x93
0x04
0x40
0x00
0x00
0x00
0x00
0x81
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x26
0x60
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
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AN11022
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CLRC663 Quickstart Guide
4.5.3 ISO/IEC 15693 for ID3 sized antenna
Table 19.
AN11022
Application note
COMPANY PUBLIC
Register settings I-Code ID3 sized antenna
Reg
Reg descr
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
SLI ¼
SLI ¼
SSC26
SSC52
DSC
0x8F
0x17
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x02
0x10
0x44
0x12
0x06
0x00
0x83
0x04
0x40
0x00
0x00
0x00
0x00
0x84
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x24
0x60
0xF0
0x8F
0x17
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x03
0x10
0x44
0x12
0x06
0x00
0x83
0x04
0x40
0x00
0x00
0x00
0x00
0x84
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x24
0x40
0xF0
0x8E
0x17
0x01
0x0A
0x7B
0x7B
0x08
0x00
0x00
0x88
0xA9
0x0F
0x00
0x02
0x10
0x44
0x12
0x06
0x00
0x93
0x04
0x40
0x00
0x00
0x00
0x00
0x81
0x02
0x00
0x37
0x00
0x00
0x00
0x00
0x1D
0x00
0x01
0x00
0x26
0x60
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
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© NXP B.V. 2015. All rights reserved.
37 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.6 ISO18000-3 Mode3 recommended register settings
4.6.1 ISO18000-3 Mode3 ID1 sized antenna
Table 20.
AN11022
Application note
COMPANY PUBLIC
ISO18000-3 Mode3 ID1 sized antenna
Reg
Reg descr
EPC V2
2/424
EPC V2
4/424
EPC V2
2/848
EPC V2
4/848
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0x4F
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x04
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x40
0xF0
0x8F
0x4F
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x03
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x50
0xF0
0x8F
0x4F
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x05
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x88
0xF0
0x8F
0x4F
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x04
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x80
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
© NXP B.V. 2015. All rights reserved.
38 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.6.2 ISO18000-3 Mode3 ID2 sized antenna
Table 21.
TX_Protected
RX_Protected
AN11022
Application note
COMPANY PUBLIC
ISO18000-3 Mode3 ID2 sized antenna
Reg
Reg descr
EPC V2
2/424
EPC V2
4/424
EPC V2
2/848
EPC V2
4/848
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0x10
0x01
0x06
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x04
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x40
0xF0
0x8F
0x10
0x01
0x06
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x03
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x50
0xF0
0x8F
0x10
0x01
0x06
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x05
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x88
0xF0
0x8F
0x10
0x01
0x06
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x04
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x80
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
© NXP B.V. 2015. All rights reserved.
39 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
4.6.3 ISO18000-3 Mode3 ID3 sized antenna
Table 22.
AN11022
Application note
COMPANY PUBLIC
ISO18000-3 Mode3 ID3 sized antenna
Reg
Reg descr
EPC V2
2/424
EPC V2
4/424
EPC V2
2/848
EPC V2
4/848
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
48
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
DrvMode_Reg
TxAmp_Reg
DrvCon_Reg
TxI_Reg
TXCrcCon
RxCrcCon
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RXSOFD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
TxBitMod
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
RxSvette_Reg
0x8F
0x17
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x04
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x40
0xF0
0x8F
0x17
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x03
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x50
0xF0
0x8F
0x17
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x05
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0b
0x00
0x01
0x04
0x0C
0x88
0xF0
0x8F
0x17
0x01
0x0A
0x11
0x91
0x09
0x00
0x00
0x80
0x12
0x01
0x00
0x04
0x00
0x36
0x12
0x0A
0x80
0xC5
0x00
0x05
0x68
0x41
0x01
0xA1
0x00
0x00
0x8E
0x00
0x00
0x00
0x00
0x08
0x0B
0x00
0x01
0x04
0x0C
0x80
0xF0
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
© NXP B.V. 2015. All rights reserved.
40 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
5. References
[1] Product Data Sheet; CLRC663 Contactless reader IC (Doc. Nr.:1711xx)
[2] Application note; AN11019 CLRC663 Antenna Design Guide (Doc. Nr.:2058xx)
[3] Application note; AN11116 (“Using the RS232 serial evaluation boards on a USB
port”), (Doc. Nr.:2151xx)
AN11022
Application note
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
© NXP B.V. 2015. All rights reserved.
41 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
6. Legal information
6.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
6.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
AN11022
Application note
COMPANY PUBLIC
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express,
implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire
risk as to the quality, or arising out of the use or performance, of this product
remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be
liable to customer for any special, indirect, consequential, punitive or
incidental damages (including without limitation damages for loss of
business, business interruption, loss of use, loss of data or information, and
the like) arising out the use of or inability to use the product, whether or not
based on tort (including negligence), strict liability, breach of contract, breach
of warranty or any other theory, even if advised of the possibility of such
damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by
customer for the product or five dollars (US$5.00). The foregoing limitations,
exclusions and disclaimers shall apply to the maximum extent permitted by
applicable law, even if any remedy fails of its essential purpose.
6.3 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC 14443 Type
B software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the Near
Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481
does not convey an implied license under any patent right infringed by
implementation of any of those standards.
6.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are property of their respective owners.
MIFARE — is a trademark of NXP B.V.
I²C-bus — is a trademark of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
© NXP B.V. 2015. All rights reserved.
42 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
7. List of figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Basic wiring diagram ......................................... 4
Power supply diagram ...................................... 5
Crystal connection ............................................ 6
RC663 board version 3.0 .................................. 8
NXP RC663 Board V2.0 and 3.0..................... 10
Power supply circuit ........................................ 11
RS232 interface and transceiver ..................... 12
RC663 Schematic ........................................... 15
Antenna and transceiver circuit ....................... 16
Schematic of the Antenna and Transceiver
circuit .............................................................. 17
Top layer RC663 board ................................... 19
Parameter Selection Placement Top Layer..... 20
Bottom layer RC663 board.............................. 21
Placement bottom Layer ................................. 22
Middle layer RC663 board .............................. 23
PCB antenna section ...................................... 24
AN11022
Application note
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
© NXP B.V. 2015. All rights reserved.
43 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
8. List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Connection Scheme for detecting the different
Interface Types ................................................. 5
Crystal requirements recommendations ........... 6
PCB sections .................................................... 8
Used devices for RS232 interface................... 12
DSUB-9 Pinning for RS232 ............................. 13
Used devices for RC663 Schematic including
oscillator .......................................................... 15
Used devices for RC663 Schematic including
oscillator .......................................................... 17
Antenna section connector.............................. 25
RxCtrl_Reg register (address 35h); reset value:
04h .................................................................. 25
Predefined protocol overview .......................... 26
Register settings Type A ID2 sized antenna ... 29
Register settings Type B ID2 sized antenna ... 30
Register settings Type B ID3 sized antenna ... 31
Register settings FeliCa ID1 sized antenna .... 32
Register settings FeliCa ID2 sized antenna .... 33
Register settings FeliCa ID3 sized antenna .... 34
Register settings I-Code ID1 sized antenna .... 35
Register settings I-Code ID2 sized antenna .... 36
Register settings I-Code ID3 sized antenna .... 37
ISO18000-3 Mode3 ID1 sized antenna ........... 38
ISO18000-3 Mode3 ID2 sized antenna ........... 39
ISO18000-3 Mode3 ID3 sized antenna ........... 40
AN11022
Application note
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 January 2015
205912
© NXP B.V. 2015. All rights reserved.
44 of 45
AN11022
NXP Semiconductors
CLRC663 Quickstart Guide
9. Contents
1.
2.
2.1
2.2
2.3
2.4
2.5
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.7
3.7.1
3.7.2
3.7.3
4.
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.5
4.5.1
4.5.2
4.5.3
4.6
Introduction ......................................................... 3
General description of the RC663 ...................... 3
Basic wiring ........................................................ 4
Power supply concept ........................................ 4
Interface selection .............................................. 5
Crystal oscillator ................................................. 6
Receiver circuit................................................... 6
Hardware design of the RC663 evaluation
board (“red board”) ............................................. 7
Scope ................................................................. 7
Features ............................................................. 7
Functional description ........................................ 8
PCB Marking and major improvements to older
version ............................................................... 9
Schematic description ...................................... 11
Interface section ............................................... 11
Power supply.................................................... 11
RS232 Host interface ....................................... 12
Microcontroller interface type ........................... 14
USB-RS232 adapter ........................................ 14
RC663 schematic ............................................. 15
Antenna circuit ................................................. 16
PCB description and functionality..................... 19
Top layer and placing ....................................... 19
Bottom, middle layer and placing ..................... 21
PCB antenna section ....................................... 24
Register Settings for different modes and
features .............................................................. 25
EMD suppression ............................................. 25
Load Protocol command .................................. 26
ISO/IEC 14443 Type A recommended register
settings ............................................................. 28
ISO/IEC 14443 Type A for 77x113 mm 2-turn
sized antenna ................................................... 29
Type B for 77x113 mm 2-turn sized antenna ... 30
Type B for ID3 sized antenna ........................... 31
FeliCa recommended register settings ............. 32
FeliCa for ID1 sized antenna ............................ 32
FeliCa for ID2 sized antenna ............................ 33
FeliCa for ID3 sized antenna ............................ 34
ISO/IEC 15693 recommended register
settings ............................................................. 35
ISO/IEC 15693 for ID1 sized antenna .............. 35
ISO/IEC 15693 for ID2 sized antenna .............. 36
ISO/IEC 15693 for ID3 sized antenna .............. 37
ISO18000-3 Mode3 recommended register
4.6.1
4.6.2
4.6.3
5.
6.
6.1
6.2
6.3
6.4
7.
8.
9.
settings .............................................................38
ISO18000-3 Mode3 ID1 sized antenna ............38
ISO18000-3 Mode3 ID2 sized antenna ............39
ISO18000-3 Mode3 ID3 sized antenna ............40
References .........................................................41
Legal information ..............................................42
Definitions.........................................................42
Disclaimers .......................................................42
Licenses ...........................................................42
Trademarks ......................................................42
List of figures .....................................................43
List of tables ......................................................44
Contents .............................................................45
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2015.
All rights reserved.
For more information, visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 January 2015
205912
Document identifier: AN11022
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