Si4708/Si4709-C Broadcast FM Radio Tuner for Portable Applications—Ideal for space-constrained mobile devices such as handsets

Si4708/09-C
B R O A DC A S T F M R A D I O TU N E R F O R P O R TA BL E A P P LI C A T I O N S
Features



Integrated LDO regulator allows
direct connection to battery
 2.5 x 2.5 mm 16-pin QFN
package
Pb-free/RoHS

Cellular handsets
 MP3 players
 Portable radios
Portable navigation 
 Consumer electronics 
 Mobile Internet

devices

USB FM radio
PDAs
Notebook PCs
Net PCs
Description
The Si4708/09 is the world's smallest FM broadcast receiver, integrating
the complete tuner function from antenna input to stereo audio output with
RDS (Si4709).
Functional Block Diagram
PGA
DSP
Q
ADC
AGC
0 / 90
LOUT
DAC
LOW-IF
GPIO
32.768 kHz
ROUT
GPO
TUNE
AFC
RDS
(Si4709)
VA
VD
Rev. 1.2 10/10
REG
RSSI
CONTROL
INTERFACE
VIO
RCLK
RST
SDIO
SCLK
SEN
CONTROLLER
RFGND
LNA
DAC
AMPLIFIER
Si4708/09
I
ADC
FMI
Si4708/09-GM
RDS/RBDS Processor (Si4709)

Headphone
Cable
Pin Assignments
(Top View)
compliant
Applications

Ordering Information:
See page 34.
Copyright © 2010 by Silicon Laboratories
1
16
15
14
FMI
2
RFGND
3
RST
4
SEN
5
GND
PAD
6
7
8
13
LOUT
12
ROUT
11
GND
10
VD
9
RCLK

2.7 to 5.5 VA supply voltage

VA



VIO



GPO


SDIO

Adjustable soft mute
Volume control
Line-level analog output
32.768 kHz reference clock
2-wire and 3-wire control
interface
2.7 to 5.5 VD supply voltage
NC


SCLK

Worldwide FM band support
(76–108 MHz)
Digital low-IF receiver
Frequency synthesizer with
integrated VCO
Adjustable seek tuning
Automatic frequency control
(AFC)
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
Programmable de-emphasis
(50/75 µs)
Adaptive noise suppression
NC

This product, its features, and/or its
architecture is covered by one or
more of the following patents, as well
as other patents, pending and
issued, both foreign and domestic:
7,127,217; 7,272,373; 7,272,375;
7,321,324; 7,355,476; 7,426,376;
7,471,940; 7,339,503; 7,339,504.
Notes:
1. To ensure proper operation and FM
receiver performance, follow the
guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and
Design Guidelines" and “AN383:
Si47xx Antenna Selection and
Universal Layout Guidelines.” Silicon
Laboratories will evaluate schematics
and layouts for qualified customers.
2. Place Si4708/09 as close as possible
to antenna jack and keep the FMI
trace as short as possible.
Si4708/09-C
Si4708/09-C
2
Rev. 1.2
Si4708/09-C
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3. General Purpose Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Pin Descriptions: Si4708/09-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.1. Si4708 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2. Si4709 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10. Package Outline: Si4708/09-GM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11. PCB Land Pattern: Si4708/09-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.2
3
Si4708/09-C
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Digital Supply Voltage
VD
2.7
—
5.5
V
Analog Supply Voltage
VA
2.7
—
5.5
V
Interface Supply Voltage
VIO
1.62
—
3.6
V
Ambient Temperature
TA
–20
25
85
°C
Digital Power Supply Power-Up Rise Time
VDRISE
10
—
—
µs
Analog Power Supply Power-Up Rise Time
VARISE
10
—
—
µs
Interface Power Supply Power-Up Rise Time
VIRISE
10
—
—
µs
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VD = VA = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
Unit
Digital Supply Voltage
VD
–0.5 to 5.8
V
Analog Supply Voltage
VA
–0.5 to 5.8
V
Interface Supply Voltage
VIO
–0.5 to 3.9
V
Input Current3
IIN
±10
mA
Voltage3
VIN
–0.3 to (VIO + 0.3)
V
Operating Temperature
TOP
–40 to 95
°C
Storage Temperature
TSTG
–55 to 150
°C
0.4
VpK
Input
RF Input Level4
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4708/09 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling and
assembly of this device should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, and GPO.
4. At RF input pins.
4
Rev. 1.2
Si4708/09-C
Table 3. DC Characteristics
(VD = VA = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
16.4
19.3
mA
—
18.2
21.1
mA
IFM
—
17
19.8
mA
IIO
—
300
—
µA
Digital Powerdown Current
IDDPD
—
2.6
—
µA
Analog Powerdown Current
IAPD
Enable = 0
—
4.4
—
µA
VIO Powerdown Current
IIOPD
SCLK, RCLK inactive
—
4.0
—
µA
FM Receiver to Line Output
VDD Supply Current
IFM
VDD Supply Current1
IFM
VDD RDS Supply
Current2
Low SNR level
Supplies and Interface
Interface Supply Current
Voltage3
VIH
0.7 x VIO
—
VIO + 0.3
V
Low Level Input Voltage3
VIL
–0.3
—
0.3 x VIO
V
Current3
IIH
VIN = VIO = 3.6 V
–10
—
10
µA
Low Level Input Current3
IIL
VIN = 0 V,
VIO = 3.6 V
–10
—
10
µA
High Level Output Voltage4
VOH
IOUT = 500 µA
0.8 x VIO
—
—
V
Low Level Output Voltage4
VOL
IOUT = –500 µA
—
—
0.2 x VIO
V
High Level Input
High Level Input
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.2
5
Si4708/09-C
Table 4. Reset Timing Characteristics (Busmode Select Method)1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
SEN Input to RSTSetup
tSRST1
30
—
—
ns
SEN Input to RSTHold
tHRST1
30
—
—
ns
Notes:
1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
tSRST
tHRST
70%
RST
30%
70%
SEN
30%
Figure 1. Reset Timing Parameters
6
Rev. 1.2
Si4708/09-C
Table 5. 3-Wire Control Interface Characteristics
(VD = VA = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLKHold
tHSDIO
10
—
—
ns
SEN Input to SCLKHold
tHSEN1
10
—
—
ns
SEN Input to SCLKHold
tHSEN2
10
—
—
ns
SDIO Input, SEN to SCLKSetup
SCLKto SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLKto SDIO Output High Z
tCDZ
Read
2
—
25
ns
Note: When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
SEN
70%
SDIO
70%
30%
tHSDIO
tS
tHIGH
tLOW
tHSEN1
tS
tHSEN2
30%
A7
30%
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
Address In
D0
Data In
Figure 2. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
SEN
70%
30%
tHSDIO
tS
tCDV
tHSEN1
tS
tCDZ
tHSEN2
30%
80%
SDIO
A7
20%
A6-A5,
R/W,
A4-A1
Address In
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 3. 3-Wire Control Interface Read Timing Parameters
Rev. 1.2
7
Si4708/09-C
Table 6. 2-Wire Control Interface Characteristics1,2,3
(VD = VA = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO Hold (START)
tHD:STA
0.6
—
—
µs
SDIO Input to SCLK Setup
tSU:DAT
100
—
—
ns
SDIO Input to SCLK Hold
tHD:DAT
0
—
900
ns
tSU:STO
0.6
—
—
µs
STOP to START Time
tBUF
1.3
—
—
µs
SDIO Output Fall Time
tf:OUT
20 + 0.1 Cb
—
250
ns
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
20 + 0.1 Cb
—
300
ns
SCLK, SDIO Capacitive Loading
Cb
—
—
50
pF
Input Filter Pulse Suppression
tSP
—
—
50
ns
4,5
SCLK input to SDIO Setup (STOP)
Notes:
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the 1st start condition.
3. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
4. As a 2-wire transmitter, the Si4708/09-C delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to
comply with the 0 ns tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated
so long as all other timing parameters are met.
8
Rev. 1.2
Si4708/09-C
SCLK
70%
SDIO
70%
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
30%
30%
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
STOP
START
Figure 4. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
SDIO
START
ADDRESS + R/W
D7-D0
ACK
DATA
D7-D0
ACK
DATA
ACK
STOP
Figure 5. 2-Wire Control Interface Read and Write Timing Diagram
Rev. 1.2
9
Si4708/09-C
Table 7. FM Receiver Characteristics1,2
(VD = VA = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
76
—
108
MHz
(S+N)/N = 26 dB
—
1.7
3.5
µVEMF
Sensitivity (50  matching
network)3,4,5,6,8
(S+N)/N = 26 dB
—
1.1
—
µVEMF
RDS Sensitivity8
f = 2 kHz,
RDS BLER < 5%
—
15
—
µVEMF
3
4
5
k
4
5
6
pF
103
106
—
dBµVEMF
m = 0.3
40
55
—
dB
Adjacent Channel Selectivity
±200 kHz
35
50
—
dB
Alternate Channel Selectivity
±400 kHz
60
70
—
dB
In-band
35
—
—
dB
—
32.768
—
kHz
SPACE[1:0] = 00 or 01
–200
—
200
ppm
SPACE[1:0] = 10
–50
—
50
72
80
90
mVRMS
—
—
1
dB
Input Frequency
Sensitivity
Test Condition
fRF
3,4,5,6,7
LNA Input Resistance8,9
LNA Input
Capacitance8,9
Input IP38,10
AM Suppression3,4,5,8,9
Spurious Response
Rejection8
RCLK Frequency
RCLK Frequency
Audio Output
Tolerance11
Voltage3,4,5,9
Audio Output L/R
Imbalance3,4,9,12
8
–3 dB
—
—
30
Hz
Audio Frequency Response High8
–3 dB
15
—
—
kHz
25
—
—
dB
Audio Frequency Response Low
Audio Stereo Separation
3,9,12
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. BAF = 300 Hz to 15 kHz, A-weighted.
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. VEMF = 1 mV.
10. |f2 – f1| > 1 MHz, f0 = 2 x f1 – f2. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page
20.
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 20. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing. ±50 ppm PCLK tolerance required for 50 kHz channel
spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 20.
14. At LOUT and ROUT pins.
15. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN349: Si4708/09 Programming Guide" for more information.
16. Minimum and maximum at room temperature (25 °C).
10
Rev. 1.2
Si4708/09-C
Table 7. FM Receiver Characteristics1,2 (Continued)
(VD = VA = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Mono/Stereo Switching Level3,8,12
Test Condition
Min
Typ
Max
Unit
BLNDADJ = 10
10 dB stereo separation
—
34
—
dBµVEMF
55
60
—
dB
—
58
—
dB
—
0.1
0.5
%
DE = 0
70
75
80
µs
Audio Mono S/N3,4,5,6,9
Audio Stereo S/N
3,5,6,8
BLNDADJ = 10
3,4,9,12
Audio THD
13
De-emphasis Time Constant
DE = 1
45
50
54
µs
14
Audio Common Mode Voltage
ENABLE = 1
0.65
0.8
0.9
V
Audio Common Mode Voltage14
ENABLE = 0
AHIZEN = 1
—
0.5 x VIO
—
V
RL
Single-ended
10
—
—
k
CL
Single-ended
—
—
50
pF
SPACE[1:0] = 0x,
RCLK
tolerance = 200 ppm,
(x = 0 or 1)
—
—
60
ms/
channel
From powerdown
(Write ENABLE bit to 1)
—
—
110
ms
Input levels of 8 and
60 dBµV at RF input
–3
—
3
dB
Audio Output Load Resistance8,14
8,14
Audio Output Load Capacitance
Seek/Tune Time
8,11
Powerup Time15
RSSI Offset16
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. BAF = 300 Hz to 15 kHz, A-weighted.
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. VEMF = 1 mV.
10. |f2 – f1| > 1 MHz, f0 = 2 x f1 – f2. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page
20.
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 20. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing. ±50 ppm PCLK tolerance required for 50 kHz channel
spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 20.
14. At LOUT and ROUT pins.
15. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN349: Si4708/09 Programming Guide" for more information.
16. Minimum and maximum at room temperature (25 °C).
Rev. 1.2
11
Si4708/09-C
2. Typical Application Schematic
1
16
NC
15
GPO
14
VA
13
LOUT
R1
NC
2
FMIP
3
RFGND
4
RST
FMI
5
SEN
6
SCLK
7
SDIO
8
VIO
RFGND
12
ROUT
11
GND
10
VD
9
RCLK
GPO
LOUT
ROUT
VBATTERY
2.7 to 5.5 V
C1
RST
RCLK
SEN
SCLK
SDIO
VIO
1.62 to 3.6 V
Notes:
1. Place C1 close to VD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 16 are no connects, leave floating.
4. Important Note: FM Receiver performance is subject to adherence to antenna design guidelines in “AN350: Si4708/09
Antenna, Schematic, Layout, and Design Guidelines.” Failure to use these guidelines may negatively affect the
performance of the Si4708/09, particularly in weak signal and noisy environments. Silicon Laboratories will evaluate
schematics and layouts for qualified customers.
5. Pin 2 connects to the antenna interface, refer to “AN350: Si4708/09 Antenna, Schematic, Layout, and Design
Guidelines” and "AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines."
6. RFGND should be locally isolated from GND, refer to “AN350: Si4708/09 Antenna, Schematic, Layout, and Design
Guidelines.”
7. Place Si4708/09 as close as possible to antenna jack and keep the FMI trace as short as possible.
8. VA and VD may be supplied from the same VBAT or may be supplied by independent power supplies.
9. Place R1 on the opposite side of the PCB as the tuner (as close to pin 15 as possible), and route the GPO trace to the
system controller on this layer.
3. Bill of Materials
Component(s)
Value/Description
Supplier(s)
C1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Murata
R1
GPO resistor, 1 k
Venkel
U1
Si4708/09 FM Radio Tuner
Silicon Laboratories
12
Rev. 1.2
Si4708/09-C
4. Functional Description
RFGND
LNA
PGA
DAC
DSP
Q
ADC
AGC
LOUT
0 / 90
DAC
LOW-IF
GPIO
32.768 kHz
ROUT
GPO
TUNE
RDS
(Si4709)
AFC
VA
VD
REG
RSSI
CONTROL
INTERFACE
VIO
RCLK
RST
SDIO
SCLK
SEN
CONTROLLER
I
ADC
FMI
AMPLIFIER
Si4708/09
Headphone
Cable
Figure 6. Si4708/09 FM Receiver Block Diagram
4.1. Overview
The Si4708/09 extends Silicon Laboratories Si4700 FM
tuner family, and further increases the ease and
attractiveness of adding FM radio reception to mobile
devices through small size and board area, minimum
component count, flexible programmability, and
superior, proven performance. Si4708/09 software is
backwards compatible to existing Si4700/01/02/03 FM
Tuner designs and leverages Silicon Laboratories'
highly successful and patented Si4700/01/02/03 FM
tuner. The Si4708/09 benefits from proven digital
integration and 100% CMOS process technology,
resulting in a completely integrated solution. It is the
industry's smallest footprint FM tuner IC requiring only
6.25 mm2 board space and one external bypass
capacitor.
The device offers significant programmability, catering
to the subjective nature of FM listeners’ audio
preferences and variable FM broadcast environments
worldwide.
RDS status, data, and block errors. Si4709 RDS
software is backwards compatible to the proven
Si4701/03, adopted by leading cell-phone and MP3
manufacturers world-wide.
The Si4708/09 is based on the superior, proven
performance of Silicon Laboratories' Si4700/01/02/03
architecture offering unmatched interference rejection
and leading sensitivity. The device uses the same
programming interface as the Si4700/01/02/03 and
supports multiple bus modes. Power management is
simplified with an integrated regulator allowing direct
connection to a 2.7 to 5.5 V battery for VD and 2.7 to 5.5
V battery for VA.
The Si4708/09 device’s high level of integration and
complete FM system production testing increases
quality to manufacturers, improves device yields, and
simplifies device manufacturing and final testing.
*Note: RDS/RBDS is referred to as RDS throughout the
remainder of this document.
The Si4709 incorporates a digital processor for the
European Radio Data System (RDS) and the US Radio
Broadcast Data System (RBDS) including all required
symbol decoding, block synchronization, error
detection, and error correction functions.
RDS/RDBS* enables data such as station identification
and song name to be displayed to the user. The Si4709
offers a detailed RDS view and a standard view,
allowing adopters to selectively choose granularity of
Rev. 1.2
13
Si4708/09-C
4.2. FM Receiver
4.4. RDS/RBDS Processor and
Functionality
The Si4708/09 architecture and antenna design
increases system performance. To ensure proper
performance and operation, designers should refer to
the guidelines in "AN350: Si4708/09 Antenna,
Schematic,
Layout,
and
Design
Guidelines".
Conformance to these guidelines will help to ensure
excellent performance in weak signal, noisy, and
crowded signal environments where many strong
channels are present.
The Si4709 implements an RDS/RBDS processor for
symbol decoding, block synchronization, error
detection, and error correction. RDS functionality is
enabled by setting the RDS bit. The device offers two
RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS
block-error levels and synchronization status with
verbose mode.
The Si4708/09’s patented digital low-IF architecture
reduces external components and eliminates the need
for factory adjustments. The receive (RX) section
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (76 to 108 MHz). An
automatic gain control (AGC) circuit controls the gain of
the LNA to optimize sensitivity and rejection of strong
interferers.
Setting the RDS mode (RDSM) bit low places the
device in standard RDS mode (default). The device will
set the RDS ready (RDSR) bit for a minimum of 40 ms
when a valid RDS group has been received. Setting the
RDS interrupt enable (RDSIEN) bit and GPO[1:0] = 01
will configure GPO to pulse low for a minimum of 5 ms
when a valid RDS group has been received. If an invalid
group is received, RDSR will not be set and GPO will
not pulse low. In standard mode RDS synchronization
(RDSS) and block error rate A, B, C and D (BLERA,
BLERB, BLERC, and BLERD) are unused and will read
0. This mode is backward compatible with earlier
firmware revisions.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered,
and
digitized
with
high
resolution
analog-to-digital converters (ADCs). This advanced
architecture achieves superior performance by using
digital signal processing (DSP) to perform channel
selection, FM demodulation, and stereo audio
processing
compared
to
traditional
analog
architectures.
4.3. General Purpose Output
The GPO pin can serve multiple functions. After
powerup of the device, the GPO pin can be used as a
general purpose input/output, and can be used as an
interrupt request pin for the seek/tune or RDS ready
functions. See register 04h, bits [3:2] in Section “6.
Register Descriptions” for information on GPO control. It
is recommended that the GPO pin not be used as an
interrupt request output until the powerup time has
completed (see Section “4.9. Reset, Powerup, and
Powerdown”). The GPO pin is powered from the VIO
supply; therefore, general purpose input/output
functionality is available regardless of the state of the VA
and VD supplies, or the ENABLE and DISABLE bits.
14
Setting the RDS mode bit high places the device in RDS
verbose mode. The device sets RDSS high when
synchronized and low when synchronization is lost. If
the device is synchronized, RDS ready (RDSR) will be
set for a minimum of 40 ms when a RDS group has
been received. Setting the RDS interrupt enable
(RDSIEN) bit and GPO[1:0] = 01 will configure GPO to
pulse low for a minimum of 5 ms if the device is
synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide
block-error levels for the RDS group. The number of bit
errors in each block within the group is encoded as
follows: 00 = no errors, 01 = one to two errors, 10 =
three to five errors, 11 = six or more errors. Six or more
errors in a block indicate the block is uncorrectable and
should not be used.
Rev. 1.2
Si4708/09-C
4.5. Stereo Audio Processing
Modulation Level
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961 and is used worldwide. Today's MPX
signal format consists of left + right (L+R) audio, left –
right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS
data as shown in Figure 7.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted with the DMUTE
bit. Volume can be adjusted digitally with the
VOLUME[3:0] bits. The volume dynamic range can be
set to either –28 dBFS (default) or –58 dBFS by setting
VOLEXT=1.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The soft mute attack and decay rate can be
adjusted with the SMUTER[1:0] bits where 00 is the
fastest setting. The soft mute attenuation level can be
adjusted with the SMUTEA[1:0] bits where 00 is the
most attenuated. The soft mute disable (DSMUTE) bit
may be set high to disable this feature.
4.6. Tuning
0
15 19 23
38
53
57
Frequency (kHz)
Figure 7. MPX Signal Spectrum
The
Si4708/09's
integrated
stereo
decoder
automatically decodes the MPX signal. The 0 to 15 kHz
(L+R) signal is the mono output of the FM tuner. Stereo
is generated from the (L+R), (L-R), and a 19 kHz pilot
tone. The pilot tone is used as a reference to recover
the (L-R) signal. Separate left and right channels are
obtained by adding and subtracting the (L+R) and (L-R)
signals, respectively. The Si4709 uses frequency
information from the 19 kHz stereo pilot to recover the
57 kHz RDS/RBDS signal.
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. The signal level range over which
the stereo to mono blending occurs can be adjusted by
setting the BLNDADJ[1:0] register. Stereo/mono status
can be monitored with the ST register bit and mono
operation can be forced with the MONO register bit.
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. All FM receivers
incorporate a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants, 50 or 75 µs, are used in various regions.
The de-emphasis time constant is programmable with
the DE bit.
The Si4708/09 uses Silicon Laboratories’ patented and
proven frequency synthesizer technology including a
completely integrated VCO. The frequency synthesizer
generates the quadrature local oscillator signal used to
downconvert the RF input to a low intermediate
frequency. The VCO frequency is locked to the
reference clock and adjusted with an automatic
frequency control (AFC) servo loop during reception.
The tuning frequency is defined as:
Freq (MHz) = Spacing (kHz)  Channel + Bottom of Band (MHz)
Channel spacing of 50, 100 or 200 KHz is selected with
bits SPACE[1:0]. The channel is selected with bits
CHAN[9:0]. The bottom of the band is set to 76 MHz or
87.5 MHz with the bits BAND[1:0]. The tuning operation
begins by setting the TUNE bit. After tuning completes,
the seek/tune complete (STC) bit will be set and the
RSSI level is available by reading bits RSSI[7:0]. The
TUNE bit must be set low after the STC bit is set high in
order to complete the tune operation and clear the STC
bit.
Seek tuning searches up or down for a channel with an
RSSI greater than or equal to the seek threshold set
with the SEEKTH[7:0] bits. In addition, an optional SNR
and/or impulse noise detector may be used to qualify
valid stations. The SKSNR[3:0] bits set the SNR
threshold required. The SKCNT[3:0] bits set the impulse
noise threshold. Using the extra seek qualifiers can
reduce false stops and, in combination with lowering the
RSSI seek threshold, increase the number of found
stations. The SNR and impulse noise detectors are
disabled by default.
Two seek modes are available. When the seek mode
(SKMODE) bit is low and a seek is initiated, the device
seeks through the band, wraps from one band edge to
the other, and continues seeking. If the seek operation
Rev. 1.2
15
Si4708/09-C
was unable to find a channel, the seek failure/band limit
(SF/BL) bit will be set high and the device will return to
the channel selected before the seek operation began.
When the SKMODE bit is high and a seek is initiated,
the device seeks through the band until the band limit is
reached and the SF/BL bit will be set high. A seek
operation is initiated by setting the SEEK and SEEKUP
bits. After the seek operation completes, the STC bit will
be set, and the RSSI level and tuned channel are
available by reading bits RSSI[7:0] and bits
READCHAN[9:0].
During
a
seek
operation
READCHAN[9:0] is also updated and may be read to
determine seek progress. The STC bit will be set after
the seek operation completes. The channel is valid if the
seek operation completes and the SF/BL bit is set low.
At other times, such as before a seek operation or after
a seek completes and the SF/BL bit is set high, the
channel is valid if the AFC Rail (AFCRL) bit is set low
and the value of RSSI[7:0] is greater than or equal to
SEEKTH[7:0]. Note that if the AFCRL bit is set, the
audio output is muted as in the softmute case discussed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
must be set low after the STC bit is set high in order to
complete the seek operation and clear the STC and
SF/BL bits. The seek operation may be aborted by
setting the SEEK bit low at any time.
The device can be configured to generate an interrupt
on GPO when a tune or seek operation completes.
Setting the seek/tune complete (STCIEN) bit and
GPO[1:0] = 01 will configure GPO for a 5 ms low
interrupt when the STC bit is set by the device.
For additional recommendations on optimizing the seek
function, consult "AN349: Si4708/09 Programming
Guide."
4.7. Reference Clock
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the VIO supply
is applied regardless of the state of the VD or VA
supplies. RCLK is not required for proper register
operation.
4.8.1. 3-Wire Control Interface
For three-wire operation, a transfer begins when the
SEN pin is sampled low by the device on a rising SCLK
edge. The control word is latched internally on rising
SCLK edges and is nine bits in length, comprised of a
four bit chip address A7:A4 = 0110b, a read/write bit
(write = 0 and read = 1), and a four bit register address,
A3:A0. The ordering of the control word is A7:A5, R/W,
A4:A0. Refer to Section 5. "Register Summary" on page
19 for a list of all registers and their addresses.
For write operations, the serial control word is followed
by a 16-bit data word and is latched internally on rising
SCLK edges.
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
For details on timing specifications and diagrams, refer
to Table 5, “3-Wire Control Interface Characteristics,” on
page 7, Figure 2, “3-Wire Control Interface Write Timing
Parameters,” on page 7, and Figure 3, “3-Wire Control
Interface Read Timing Parameters,” on page 7.
The Si4708/09-C accepts a 32.768 kHz reference clock
to the RCLK pin. The reference clock is required
whenever the ENABLE bit is set high. Refer to Table 3,
“DC Characteristics,” on page 5 for input switching
voltage
levels
and
Table 7,
"FM
Receiver
Characteristics," on page 10 for frequency tolerance
information.
16
Rev. 1.2
Si4708/09-C
4.8.2. 2-Wire Control Interface
4.9. Reset, Powerup, and Powerdown
For two-wire operation, the SCLK and SDIO pins
function in open-drain mode (pull-down only) and must
be pulled up by an external device. A transfer begins
with the START condition (falling edge of SDIO while
SCLK is high). The control word is latched internally on
rising SCLK edges and is eight bits in length, comprised
of a seven bit device address equal to 0010000b and a
read/write bit (write = 0 and read = 1).
Driving the RST pin low will disable the Si4708/09 and
its control bus interface, and reset the registers to their
default settings. Driving the RST pin high will bring the
device out of reset. As the part is brought out of reset,
the SEN pin is used to select between 2-wire and 3-wire
control interface operation.
The device acknowledges the address by driving SDIO
low after the next falling SCLK edge, for 1 cycle. For
write operations, the device acknowledge is followed by
an eight bit data word latched internally on rising edges
of SCLK. The device acknowledges each byte of data
written by driving SDIO low after the next falling SCLK
edge, for 1 cycle. An internal address counter
automatically increments to allow continuous data byte
writes, starting with the upper byte of register 02h,
followed by the lower byte of register 02h, and onward
until the lower byte of the last register is reached. The
internal address counter then automatically wraps
around to the upper byte of register 00h and proceeds
from there until continuous writes end. Data transfer
ends with the STOP condition (rising edge of SDIO
while SCLK is high). After every STOP condition, the
internal address counter is reset.
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
the controller IC must drive an acknowledge (SDIO = 0)
if an additional byte of data will be requested. Data
transfer ends with the STOP condition. After every
STOP condition, the internal address counter is reset.
Table 8. Selecting 2-Wire or 3-Wire Control
Interface Busmode Operation
Bus Mode
SEN
3-wire
0
2-wire
1
Note: All parameters applied on rising edge of RST.
The bus mode selection method requires the use of the
SEN pin. To select 2-wire operation, the SEN pin must
be sampled high by the device on the rising edge of
RST. To select 3-wire operation, the SEN pin must be
sampled low by the device on the rising edge of RST.
When proper voltages are applied to the Si4708/09, the
ENABLE and DISABLE bits in register 02h can be used
to select between powerup and powerdown modes.
When voltage is first applied to the device, ENABLE =
DISABLE = 0. Setting ENABLE = 1 and DISABLE = 0
puts the device in powerup mode. To power down the
device, disable RDS (Si4709 only), set Reg4(5:4),
Reg4(3:2), and Reg4(1:0) to 0b10. then write 1 to the
ENABLE and DISABLE bits. After being written to 1,
both bits will get cleared as part of the internal device
powerdown sequence. To put the device back into
powerup mode, set ENABLE = 1 and DISABLE = 0 as
described above. The ENABLE bit should never be
written to a 0.
For details on timing specifications and diagrams, refer
to
Table 6,
“2-Wire
Control
Interface
Characteristics1,2,3,” on page 8, Figure 4, “2-Wire
Control Interface Read and Write Timing Parameters,”
on page 9 and Figure 5, “2-Wire Control Interface Read
and Write Timing Diagram,” on page 9.
Rev. 1.2
17
Si4708/09-C
4.10. Audio Output Summation
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
0.5 x VIO on the LOUT and ROUT pins to prevent the
ESD diodes from clamping to the VIO or GND rail in
response to the output swing of the other device. The
bias point is set with a 370 k resistor to VIO and GND.
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and VIO is supplied. In
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 7, “FM
Receiver Characteristics1,2,” on page 10, regardless of
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
4.11. Initialization Sequence
1. Note that VIO is still supplied in this scenario. If VIO is
not supplied, refer to device initialization procedure
above.
2. (Optional) Set the AHIZEN bit low to disable the dc
bias of 0.5 x VIO volts at the LOUT and ROUT pins,
but preserve the states of the other bits in Register
07h. Note that in powerup the LOUT and ROUT pins
are set to the common mode voltage specified in
Table 7 on page 10, regardless of the state of
AHIZEN.
3. Supply VA and VD.
4. Provide RCLK. Steps 3 and 4 may be reversed when
using an external oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
Characteristics1,2,” on page 10) before continuing
with normal part operation.
Refer to Figure 8, “Initialization Sequence,” on page 18.
To initialize the device:
1. Supply VA and VD.
VA,VD Supply
2. Supply VIO while keeping the RST pin low. Note that
steps 1 and 2 may be reversed. Power supplies may
be sequenced in any order.
3. Select 2-wire or 3-wire control interface bus mode
operation as described in Section 4.9. "Reset,
Powerup, and Powerdown" on page 17.
VIO Supply
RST Pin
RCLK Pin
ENABLE Bit
4. Provide RCLK. Steps 3 and 4 may be reversed when
using an external oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
Characteristics1,2,” on page 10) before continuing
with normal part operation.
To power down the device:
1
3
4
5
Figure 8. Initialization Sequence
4.12. Programming Guide
Refer to "AN349: Si4708/09 Programming Guide" for
control interface programming information.
1. (Optional) Set the AHIZEN bit high to maintain a dc
bias of 0.5 x VIO volts at the LOUT and ROUT pins
while in powerdown, but preserve the states of the
other bits in Register 07h. Note that in powerup the
LOUT and ROUT pins are set to the common mode
voltage specified in Table 7 on page 10, regardless
of the state of AHIZEN.
2. Set the ENABLE bit high and the DISABLE bit high
to place the device in powerdown mode. Note that all
register states are maintained so long as VIO is
supplied and the RST pin is high.
3. (Optional) Remove RCLK.
4. Remove VA and VD supplies as needed.
To power up the device (after power down):
18
2
Rev. 1.2
CHIPID
01h
Rev. 1.2
RDSA
RDSB
RDSC
RDSD
0Ch
0Dh
0Eh
0Fh
STC
AHIZEN
BLERB[1:0]2,3
RDSR2
0
AFCRL
BLERC[1:0]2,3
SF/BL
DE
0
RDSM2
D9
0
0
BLERA[1:0]2,3
AGCD
0
SKMODE SEEKUP
D10
BLERD[1:0]2,3
RDSS2,3
SEEKTH[7:0]
RDS2
0
0
SMUTEA[1:0]
0
0
MONO
D11
D7
0
DISABLE
RDSD[15:0]2
RDSC[15:0]2
RDSB[15:0]2
0
READCHAN[9:0]
D2
0
1
0
D1
SKCNT[3:0]
VOLUME[3:0]
GPO[1:0]
0
FIRMWARE[5:0]
D3
RSSI[7:0]
SPACE[1:0]
SKSNR[3:0]
BAND[1:0]
1
0
D4
CHAN[9:0]
0
D5
MFGID[11:0]
D6
BLNDADJ[1:0]
RDSA[15:0]2
ST
VOLEXT
0
SEEK
DEV[3:0]
D8
Notes:
1. Any register not listed is reserved and should not be written. Writing to reserved registers may result in unpredictable behavior.
2. Si4709 only.
3. Available in RDS verbose mode only.
READCHAN
BOOTCONFIG
09h
0Bh
TEST2
08h
STATUSRSSI
TEST1
07h
0Ah
SYSCONFIG3
06h
SMUTER[1:0]
SYSCONFIG2
0
05h
TUNE
SYSCONFIG1 RDSIEN2 STCIEN
CHANNEL
D12
REV[5:0]
D13
PN[3:0]
D14
04h
03h
D15
POWERCFG DSMUTE DMUTE
DEVICEID
00h
02h
Name
Reg1
5. Register Summary
0
ENABLE
D0
Si4708/09-C
19
Si4708/09-C
6. Register Descriptions
Register 00h. Device ID
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Name
PN[3:0]
MFGID[11:0]
Type
R
R
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
Reset value = 0x1242
Bit
Name
Function
15:12
PN[3:0]
Part Number.
0x01 = Si4708/09
11:0
MFGID[11:0]
Manufacturer ID.
0x242
Register 01h. Chip ID
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Name
REV[5:0]
DEV[3:0]
FIRMWARE[5:0]
Type
R
R
R
Si4708C Reset value = 0x1093 or 0x109E if ENABLE = 1
Si4708C Reset value = 0x1000 or 0x101E if ENABLE = 0
Si4709C Reset value = 0x1293 or 0x0129E if ENABLE = 1
Si4709C Reset value = 0x1200 or 0x121E if ENABLE = 0
Bit
Name
15:10
REV[5:0]
Chip Version.
0x04 = Rev C
9:6
DEV[3:0]
Device.
0000 before powerup = Si4708.
1000 before powerup = Si4709.
0010 after powerup = Si4708.
1010 after powerup = Si4709.
5:0
20
Function
FIRMWARE[5:0] Firmware Version.
0 before powerup.
Firmware version after powerup = 010011 or 011110.
Rev. 1.2
Si4708/09-C
Register 02h. Power Configuration
Bit
D15
D14
D13 D12 D11
Name DSMUTE DMUTE MONO
Type
R/W
R/W
R/W
0
R/W
D10
D9
D8
RDSM SKMODE SEEKUP SEEK
R/W
R/W
R/W
R/W
D7
D6
0
DISABLE
R/W
R/W
D5 D4 D3 D2 D1
0
0
0
0
0
R/W R/W R/W R/W R/W
D0
ENABLE
R/W
Reset value = 0x0000
Bit
Name
Function
15
DSMUTE
14
DMUTE
Mute Disable.
0 = Mute enable (default).
1 = Mute disable.
13
MONO
Mono Select.
0 = Stereo (default).
1 = Force mono.
12
Reserved
11
RDSM
10
SKMODE
Seek Mode.
0 = Wrap at the upper or lower band limit and continue seeking (default).
1 = Stop seeking at the upper or lower band limit.
9
SEEKUP
Seek Direction.
0 = Seek down (default).
1 = Seek up.
8
SEEK
Softmute Disable.
0 = Softmute enable (default).
1 = Softmute disable.
Reserved.
Always write to 0.
RDS Mode (Si4709 only).
0 = Standard (default).
1 = Verbose.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
Seek.
0 = Disable (default).
1 = Enable.
Notes:
1. Seek begins at the current channel, and goes in the direction specified with the SEEKUP
bit. Seek operation stops when a channel is qualified as valid according to the seek
parameters, the entire band has been searched (SKMODE = 0), or the upper or lower
band limit has been reached (SKMODE = 1).
2. The STC bit is set high when the seek operation completes and/or the SF/BL bit is set
high if the seek operation was unable to find a channel qualified as valid according to the
seek parameters. The STC and SF/BL bits must be set low by setting the SEEK bit low
before the next seek or tune may begin.
3. Seek performance for 50 kHz channel spacing varies according to RCLK tolerance.
Silicon Laboratories recommends ±50 ppm RCLK crystal tolerance for 50 kHz seek
performance.
4. A seek operation may be aborted by setting SEEK = 0.
7
Reserved
Always write to 0.
Rev. 1.2
21
Si4708/09-C
Bit
Name
Function
6
DISABLE
Powerup Disable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
5:1
Reserved
Always write to 0.
0
ENABLE
Powerup Enable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
Register 03h. Channel
Bit
D15
Name TUNE
Type
R/W
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
0
0
CHANNEL[9:0]
R/W
R/W
R/W
R/W
R/W
R/W
D3
D2
D1
D0
Reset value = 0x0000
Bit
Name
Function
15
TUNE
Tune.
0 = Disable (default).
1 = Enable.
The tune operation begins when the TUNE bit is set high. The STC bit is set high
when the tune operation completes. The STC bit must be set low by setting the TUNE
bit low before the next tune or seek may begin.
14:10
Reserved
Always write to 0.
9:0
CHAN[9:0]
Channel Select.
Channel value for tune operation.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (kHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (kHz) x Channel + 76 MHz.
CHAN[9:0] is not updated during a seek operation. READCHAN[9:0] provides the
current tuned channel and is updated during a seek operation and after a seek or
tune operation completes. Channel spacing is set with the bits SPACE 05h[5:4].
22
Rev. 1.2
Si4708/09-C
Register 04h. System Configuration 1
Bit
D15
D14
Name RDSIEN STCIEN
Type
R/W
R/W
D13
D12
D11
D10
D9
D8
0
RDS
DE
AGCD
0
0
R/W
R/W
R/W
R/W
R/W
R/W
D7
D6
D5
D4
BLNDADJ[1:0]
0
0
R/W
R/W
R/W
D3
D2
D1
D0
GPO[1:0]
0
0
R/W
R/W
R/W
Reset value = 0x0000
Bit
Name
Function
15
RDSIEN
RDS Interrupt Enable (Si4709 only).
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting RDSIEN = 1 and GPO[1:0] = 01 will generate a 5 ms low pulse on GPO when the
RDSR 0Ah[15] bit is set.
14
STCIEN
Seek/Tune Complete Interrupt Enable.
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting STCIEN = 1 and GPO[1:0] = 01 will generate a 5 ms low pulse on GPO when the
STC 0Ah[14] bit is set.
13
Reserved
12
RDS
11
DE
10
AGCD
9:8
Reserved
7:6
5:4
Always write to 0.
RDS Enable (Si4709 only).
0 = Disable (default).
1 = Enable.
De-emphasis.
0 = 75 µs. Used in USA (default).
1 = 50 µs. Used in Europe, Australia, Japan.
AGC Disable.
0 = AGC enable (default).
1 = AGC disable.
Always write to 0.
BLNDADJ[1:0] Stereo/Mono Blend Level Adjustment.
Sets the RSSI range for stereo/mono blend.
00 = 31–49 RSSI dBµV (default).
01 = 37–55 RSSI dBµV (+6 dB).
10 = 19–37 RSSI dBµV (–12 dB).
11 = 25–43 RSSI dBµV (–6 dB).
ST bit set for RSSI values greater than low end of range.
Reserved
Always write to 10.
Rev. 1.2
23
Si4708/09-C
Bit
Name
Function
3:2
GPO[1:0]
General Purpose I/O.
00 = High impedance (default).
01 = STC/RDS interrupt. A logic high will be output unless an interrupt occurs as
described below.
10 = Low.
11 = High.
Setting STCIEN = 1 will generate a 5 ms low pulse on GPO when the STC 0Ah[14] bit is
set. Setting RDSIEN = 1 will generate a 5 ms low pulse on GPO when the RDSR 0Ah[15]
bit is set.
1:0
Reserved
Always write to 10.
24
Rev. 1.2
Si4708/09-C
Register 05h. System Configuration 2
Bit
D15
D14
D13
D12
D11
Name
SEEKTH[7:0]
Type
R/W
D10
D9
D8
D7
D6
D5
D4
BAND[1:0] SPACE[1:0]
R/W
R/W
D3
D2
D1
D0
VOLUME[3:0]
R/W
Reset value = 0x0000
Bit
Name
Function
15:8
SEEKTH[7:0]
RSSI Seek Threshold.
0x00 = min RSSI (default).
0x7F = max RSSI.
SEEKTH presents the logarithmic RSSI threshold for the seek operation. The
Si4708/09 will not validate channels with RSSI below the SEEKTH value. SEEKTH is
one of multiple parameters that can be used to validate channels. For more information, see "AN349: Si4708/09 Programming Guide."
7:6
BAND[1:0]
Band Select.
00 = 87.5–108 MHz (US/Europe, Default).
01 = 76–108 MHz (Japan wide band).
10 = 76–90 MHz (Japan).
11 = Reserved.
5:4
SPACE[1:0]
Channel Spacing.
00 = 200 kHz (USA, Australia) (default).
01 = 100 kHz (Europe, Japan).
10 = 50 kHz.
3:0
VOLUME[3:0]
Volume.
Relative value of volume is shifted –30 dBFS with the VOLEXT 06h[8] bit.
VOLEXT = 0 (default).
0000 = mute (default).
0001 = –28 dBFS.
:
:
1110 = –2 dBFS.
1111 = 0 dBFS.
VOLEXT = 1.
0000 = mute.
0001 = –58 dBFS.
:
:
1110 = –32 dBFS.
1111 = –30 dBFS.
FS = full scale.
Volume scale is logarithmic.
Rev. 1.2
25
Si4708/09-C
Register 06h. System Configuration 3
Bit
D15
D14
D13
D12
Name SMUTER[1:0] SMUTEA[1:0]
Type
R/W
R/W
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
VOLEXT
SKSNR[3:0]
SKCNT[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
D0
Reset value = 0x0000
Bit
Name
15:14
SMUTER[1:0]
Softmute Attack/Recover Rate.
00 = fastest (default).
01 = fast.
10 = slow.
11 = slowest.
13:12
SMUTEA[1:0]
Softmute Attenuation.
00 = 16 dB (default).
01 = 14 dB.
10 = 12 dB.
11 = 10 dB.
11:9
Reserved
Always write to zero.
8
VOLEXT
Extended Volume Range.
0 = disabled (default).
1 = enabled.
This bit attenuates the output by 30 dB. With the bit set to 0, the 15 volume settings
adjust the volume between 0 and –28 dBFS. With the bit set to 1, the 15 volume settings adjust the volume between –30 and –58 dBFS.
Refer to 4.5. "Stereo Audio Processing" on page 15.
7:4
SKSNR[3:0]
Seek SNR Threshold.
0000 = disabled (default).
0001 = min (most stops).
1111 = max (fewest stops).
Required channel SNR for a valid seek channel.
3:0
SKCNT[3:0]
Seek FM Impulse Detection Threshold.
0000 = disabled (default).
0001 = max (most stops).
1111 = min (fewest stops).
Allowable number of FM impulses for a valid seek channel.
26
Function
Rev. 1.2
Si4708/09-C
Register 07h. Test 1
Bit
D15
D14
D13
D12
D11 D10
D9
D8
Name Reserved AHIZEN
Type
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
R/W
R/W
Reset value = 0x0100
Bit
Name
Function
15
Reserved
14
AHIZEN
Audio High-Z Enable.
0 = Disable (default).
1 = Enable.
Setting AHIZEN maintains a dc bias of 0.5 x VIO on the LOUT and ROUT pins to prevent the ESD diodes from clamping to the VIO or GND rail in response to the output
swing of another device. Register 07h containing the AHIZEN bit must not be written
during the powerup sequence and high-Z only takes effect when in powerdown and
VIO is supplied. Bits 13:0 of register 07h must be preserved as 0x0100 while in powerdown and as 0x3C04 while in powerup.
13:0
Reserved
If written, these bits should be read first and then written with their pre-existing values.
Do not write during powerup.
Always write to zero.
Register 08h. Test 2
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Type
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Reset value = 0x0000
Bit
Name
Function
15:0
Reserved
If written, these bits should be read first and then written with their pre-existing values.
Do not write during powerup.
Rev. 1.2
27
Si4708/09-C
Register 09h. Boot Configuration
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
Name
Reserved
Type
R/W
D6
D5
D4
D3
D2
D1
D0
Reset value = 0x0000
Bit
Name
Function
15:0
Reserved
If written, these bits should be read first and then written with their pre-existing values.
Do not write during powerup.
Register 0Ah. Status RSSI
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
Name RDSR STC SF/BL AFCRL RDSS BLERA[1:0]
ST
RSSI[7:0]
Type
R
R
R
R
R
R
R
R
D2
D1
D0
Reset value = 0x0000
28
Bit
Name
Function
15
RDSR
14
STC
Seek/Tune Complete.
0 = Not complete (default).
1 = Complete.
The seek/tune complete flag is set when the seek or tune operation completes. Setting
the SEEK 02h[8] or TUNE 03h[15] bit low will clear STC.
13
SF/BL
Seek Fail/Band Limit.
0 = Seek successful.
1 = Seek failure/Band limit reached.
The SF/BL flag is set high when SKMODE 02h[10] = 0 and the seek operation fails to
find a channel qualified as valid according to the seek parameters.
The SF/BL flag is set high when SKMODE 02h[10] = 1 and the upper or lower band limit
has been reached.
The SEEK 02h[8] bit must be set low to clear SF/BL.
12
AFCRL
AFC Rail.
0 = AFC not railed.
1 = AFC railed, indicating an invalid channel. Audio output is softmuted when set.
AFCRL is updated after a tune or seek operation completes and indicates a valid or
invalid channel. During normal operation, AFCRL is updated to reflect changing RF environments.
RDS Ready (Si4709 only).
0 = No RDS group ready (default).
1 = New RDS group ready.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
Rev. 1.2
Si4708/09-C
Bit
Name
11
RDSS
10:9
BLERA[1:0]
8
ST
7:0
RSSI[7:0]
Function
RDS Synchronized (Si4709 only).
0 = RDS decoder not synchronized (default).
1 = RDS decoder synchronized.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
RDS Block A Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
Stereo Indicator.
0 = Mono.
1 = Stereo.
RSSI (Received Signal Strength Indicator).
RSSI is measured units of dBµV in 1 dB increments with a maximum of approximately
75 dBµV. Si4708/09-C does not report RSSI levels greater than 75 dBuV.
Rev. 1.2
29
Si4708/09-C
Register 0Bh. Read Channel
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name BLERB[1:0] BLERC[1:0] BLERD[1:0]
Type
R
R
D7
D6
D5
D4
D3
D2
D1
D0
READCHAN[9:0]
R
R
Reset value = 0x0000
Bit
Name
15:14
BLERB[1:0]
RDS Block B Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
13:12
BLERC[1:0]
RDS Block C Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
11:10
BLERD[1:0]
RDS Block D Errors (Si4709 only).
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
9:0
30
Function
READCHAN[9:0] Read Channel.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (kHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (kHz) x Channel + 76 MHz.
READCHAN[9:0] provides the current tuned channel and is updated during a seek
operation and after a seek or tune operation completes. Spacing and channel are set
with the bits SPACE 05h[5:4] and CHAN 03h[9:0].
Rev. 1.2
Si4708/09-C
Register 0Ch. RDSA
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
Name
RDSA[15:0]
Type
R
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
Reset value = 0x0000
Bit
Name
15:0
RDSA
Function
RDS Block A Data (Si4709 only).
Register 0Dh. RDSB
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
Name
RDSB[15:0]
Type
R
D6
Reset value = 0x0000
Bit
Name
15:0
RDSB
Function
RDS Block B Data (Si4709 only).
Rev. 1.2
31
Si4708/09-C
Register 0Eh. RDSC
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
Name
RDSC[15:0]
Type
R
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
Reset value = 0x0000
Bit
Name
15:0
RDSC
Function
RDS Block C Data (Si4709 only).
Register 0Fh. RDSD
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
Name
RDSD[15:0]
Type
R
D6
Reset value = 0x0000
Bit
Name
15:0
RDSD
32
Function
RDS Block D Data (Si4709 only).
Rev. 1.2
Si4708/09-C
NC
NC
GPO
VA
7. Pin Descriptions: Si4708/09-GM
1
16
15
14
RST
4
SEN
5
GND
PAD
6
ROUT
11
GND
10
VD
7
8
9
RCLK
3
12
VIO
RFGND
LOUT
SDIO
2
SCLK
FMI
13
Top View
Pin Number(s)
Name
Description
1, 16
NC
No Connect. Leave floating.
2
FMI
FM RF inputs.
3
RFGND
4
RST
Device reset input (active low).
5
SEN
Serial enable input (active low).
6
SCLK
Serial clock input.
7
SDIO
Serial data input/output.
8
VIO
9
RCLK
10
VD
11, PAD
GND
12
ROUT
Right audio output.
13
LOUT
Left audio output.
14
VA
15
GPO
RF ground. Connect to ground plane on PCB.
I/O supply voltage.
External reference oscillator input.
Digital supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Analog supply voltage. May be connected directly to battery.
General purpose input/output.
Rev. 1.2
33
Si4708/09-C
8. Ordering Guide
Part
Number*
Description
Package
Type
Operating
Temperature
Si4708-C-GM
Portable Broadcast Radio Tuner
FM Stereo
QFN
Pb-free
–20 to 85 °C
Si4709-C-GM
Portable Broadcast Radio Tuner
FM Stereo with RDS
QFN
Pb-free
–20 to 85 °C
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.
34
Rev. 1.2
Si4708/09-C
9. Package Markings (Top Marks)
9.1. Si4708 Top Mark
9.2. Si4709 Top Mark
9.3. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Device Number
4708 = Si4708
4709 = Si4709
Line 2 Marking:
TTTT = Mfg Code
Line 2 from the "Markings" section of the Assembly Purchase Order form.
Line 3 Marking:
Pin 1 Identifier.
Circle = 0.3 mm Diameter
YWW = Date Code
Assigned by the Assembly House. Corresponds
to the last digit of the current year (Y) and the
workweek (WW) of the assembly release.
Rev. 1.2
35
Si4708/09-C
10. Package Outline: Si4708/09-GM
Figure 9 illustrates the package details for the Si4708/09-GM. Table 9 lists the values for the dimensions shown in
the illustration.
Figure 9. 16-Pin Quad Flat No-Lead (QFN)
Table 9. Package Dimensions
Symbol
Millimeters
Symbol
Min
Nom
Max
A
0.50
0.55
0.60
E2
A1
0.00
0.02
0.05
f
b
0.18
0.23
0.28
L
0.25
0.30
0.35
c
0.25
0.30
0.35
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
D
D2
2.50 BSC
1.35
1.40
1.45
Min
Nom
Max
1.35
1.40
1.45
2.00 BSC
e
0.50 BSC
ddd
—
—
0.10
E
2.50 BSC
eee
—
—
0.10
Notes:
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
36
Millimeters
Rev. 1.2
Si4708/09-C
11. PCB Land Pattern: Si4708/09-GM
Figure 10 illustrates the PCB land pattern details for the Si4708/09-GM. Table 10 lists the values for the dimensions
shown in the illustration.
Figure 10. PCB Land Pattern
Table 10. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
D
D2
Symbol
Max
2.60 REF
Max
GE
1.95
—
W
—
0.30
0.50 BSC
X
—
0.30
E
2.60 REF
Y
1.35
f
GD
1.45
Min
e
E2
1.35
Millimeters
1.45
2.00 BSC
1.95
0.65 REF
ZE
—
3.25
ZD
—
3.25
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based
on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.18x1.18 mm square aperture should be used for the center pad. This provides approximately 70%
solder paste coverage on the pad, which is optimum to assure correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.2
37
Si4708/09-C
12. Additional Reference Resources

AN230: Si4700/01/02/03 Programming Guide
 AN235: Si4700/01/02/03/08/09 EVB Quick Start Guide
 AN243: Using RDS/RBDS with the Si4701/03/09






38
AN316: AM/FM Tuner Field Test ProcedureSi4700/01/02/03
AN349: Si4708/09 Programming Guide
AN350: Si4708/09 Antenna, Schematic, Layout, and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
Si4708/09 EVB User’s Guide
Customer Support Site: http://www.silabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to fminfo@silabs.com. Silicon Labs
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Rev. 1.2
Si4708/09-C
DOCUMENT CHANGE LIST
Revision 0.6 to Revision 1.0

Updated patent list on cover page
Updated Table 3 with full production values
 Updated Table 4
 Updated Table 7 to reflect specifications from 76–
108 MHz
 Added Table 7 to reflect specifications from 64–
75.9 MHz

Revision 1.0 to Revision 1.1

FM frequency range 64-76.9 MHz no longer
supported
 Chip ID register values changed
 Typical VDD Supply Current values changed in
Table 3
 Minimum VIO value changed in Table 2
Revision 1.1 to Revision 1.2

Min VIO value changed in Table 1, Table 5, Table 6,
and Table 7
 Chip ID register value changed
Rev. 1.2
39
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