Datasheet TH8065 DownloadLink 5055

TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Features
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Compatible to LIN Specification 2.0 and SAE J2602
Operating voltage VS = 6 ... 18 V
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Low standby current consumption of typ. 15 μA in sleep mode
ƒ “noload” current < 200µA
Linear low drop voltage regulator 5V/70mA ±2%
ƒ Output current limitation
LIN-Bus Transceiver
ƒ Compatible to ISO9141 functions
ƒ Baud rate up to 20 kBaud
ƒ Slew rate control for best EME behavior
ƒ Low slew mode for optimized SAE J2602 transmission
ƒ High EMI immunity
ƒ High signal symmetry for using in RC – based slave nodes up to 2% clock tolerance
ƒ Current limitation
Wake-up via LIN bus traffic
Reset output (default 8ms/4.65V)
ƒ Reset time adjustable to 4ms, 15ms and 30ms during IC final test
Analogue Watchdog with programmable time constant via external capacity
Over temperature shutdown
Automotive temperature range of –40°C to 125°C
CMOS compatible interface to microcontroller
Load dump protected (40V)
Small SOIC14 package with fused lead frame for low Rth value
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o
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o
o
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Ordering Information
Part No.
Temperature Range
Package
Version
POR time
TH8065 KDC AA
K (-40 to 125 °C)
DC (SOIC14NB)
A
A (8ms)
On Request
TH8065 KDC AB
TH8065 KDC AC
TH8065 KDC AD
K (-40 to 125 °C)
K (-40 to 125 °C)
K (-40 to 125 °C)
DC (SOIC14NB)
DC (SOIC14NB)
DC (SOIC14NB)
A
A
A
B (4ms)
C (30ms)
D (15ms)
General Description
The TH8065 consists of a low-drop voltage regulator 5V/70mA combined with a Reset/Watchdog unit and a
LIN bus transceiver. The LIN transceiver is suitable for LIN bus systems conform to LIN specification revision
2.0 and SAE J2602.
The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful
and cheap slave nodes in LIN Bus systems.
TH8065 – Datasheet
3901008065
Page 1 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Contents
1.
Functional Diagram ............................................................................................................................... 4
2.
Electrical Specification.......................................................................................................................... 5
2.1
Operating Conditions ....................................................................................................................................... 5
2.2
Absolute Maximum Ratings ............................................................................................................................. 5
2.3
Static Characteristics ....................................................................................................................................... 6
2.3.1.
Voltage Regulator and Reset Unit .......................................................................................................... 6
2.3.2.
LIN Bus Interface.................................................................................................................................... 8
2.4
Dynamic Characteristics .................................................................................................................................. 9
2.5
Timing Diagrams ............................................................................................................................................ 11
3.
Functional Description ........................................................................................................................ 13
3.1
Operating Modes............................................................................................................................................ 13
3.2
Initialization .................................................................................................................................................... 15
3.3
Wake-Up ........................................................................................................................................................ 15
3.4
VSUP under voltage reset.............................................................................................................................. 16
3.5
Overtemperature Shutdown ........................................................................................................................... 16
3.6
LIN BUS Transceiver ..................................................................................................................................... 17
3.7
Linear Regulator............................................................................................................................................. 20
3.8
RESET and Watchdog ................................................................................................................................... 21
3.8.1.
RESET.................................................................................................................................................. 21
3.8.2.
Watchdog ............................................................................................................................................. 22
3.9
Mode Input EN ............................................................................................................................................... 24
4.
Application Hints ................................................................................................................................. 26
4.1
4.2
4.3
4.4
4.5
5.
Safe Operating Area ...................................................................................................................................... 26
Low Dropout Regulator .................................................................................................................................. 27
Application Circuitry ....................................................................................................................................... 29
EMI Supressing.............................................................................................................................................. 29
Connection to Flash-MCU .............................................................................................................................. 30
Operating during Disturbance............................................................................................................ 31
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
Operating without VSUP or GND ................................................................................................................... 31
Short Circuit BUS against VBAT .................................................................................................................... 31
Short Circuit BUS against GND...................................................................................................................... 31
Short Circuit TxD against GND ...................................................................................................................... 31
TxD open ....................................................................................................................................................... 31
Short Circuit VCC against GND ..................................................................................................................... 31
Overload of VCC ............................................................................................................................................ 31
Undervoltage VCC ......................................................................................................................................... 31
Undervoltage VSUP ....................................................................................................................................... 32
Short circuit RxD, RESET against GND or VCC ............................................................................................ 32
Short circuit CWD against GND or VCC ........................................................................................................ 32
6.
PIN Description .................................................................................................................................... 33
7.
Mechanical Specification .................................................................................................................... 34
8.
Tape and Reel Specification ............................................................................................................... 35
8.1
8.2
9.
Tape Specification.......................................................................................................................................... 35
Reel Specification .......................................................................................................................................... 36
ESD/EMC Remarks .............................................................................................................................. 37
9.1
9.2
9.3
General Remarks ........................................................................................................................................... 37
ESD-Test ....................................................................................................................................................... 37
EMC ............................................................................................................................................................... 37
10.
Revision History................................................................................................................................... 38
11.
Assembly Information ......................................................................................................................... 39
12.
Disclaimer............................................................................................................................................. 40
TH8065 – Datasheet
3901008065
Page 2 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
List of Figures
Figure 1 - Block diagram.......................................................................................................................... 4
Figure 2 - Timing diagram for propagation delays................................................................................. 11
Figure 3 - Timing diagram for duty cycle acc. to LIN 2.0 and J2602..................................................... 11
Figure 4 - Timing Diagram for EN mode selection ................................................................................ 12
Figure 5 - State diagram of operating modes........................................................................................ 13
Figure 6 - Operating of power-on and under-voltage reset ................................................................... 15
Figure 7 - Receive mode impulse diagram............................................................................................ 17
Figure 8 - TxD input circuitry ................................................................................................................. 18
Figure 9 - RxD output circuitry............................................................................................................... 19
Figure 10 - Characteristic of current limitation VCC = f (IVCC) ............................................................... 20
Figure 11 - Reset and Watchdog behaviour.......................................................................................... 21
Figure 12 - Reset behaviour .................................................................................................................. 22
Figure 13 - Output current of reset output vs. VCC voltage .................................................................. 22
Figure 14 - Watchdog timing ................................................................................................................. 23
Figure 15 - EN input circuitry ................................................................................................................. 24
Figure 16 - EN controlled via MCU........................................................................................................ 24
Figure 17 - Permanent normal mode..................................................................................................... 25
Figure 18 - Power dissipation LIN transceiver @ 20kbit ....................................................................... 26
Figure 19 - Save operating area............................................................................................................ 27
Figure 20 - ESR Curves for 6.8μF ≤ CL ≤ 100μF and Frequency of 100 kHz ....................................... 28
Figure 21 - Application circuit (slave node) ........................................................................................... 29
Figure 22 – Example circuitry for connection of RxD to MCU for flash programming........................... 30
TH8065 – Datasheet
3901008065
Page 3 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
1. Functional Diagram
VSUP
VCC
Vaux
control
amplifier
Aux.
Supply
Adjust
ment
EN
⎠ μs
SBY
MR
Mode
Control
Reset
PORTimer
Osc
VCC
POR
4.65 V
VBAT_Res
Vaux
Wake-up
Control
RESETBuffer
WDI_sig
RESET
WD
logic
VBAT_Res
WDI_sig
VBATReset
Vaux
Wake-Filter
50k
Receiver
VSUP
MR
4,8,15,30ms
VCC
CWD
comp
POR
4.65 V
Temp.
Protection
SBY
TSHD
Vaux
WDI
Reset
Generator
VBG
BG
CWD
GND
current
limitation
VSUP
70μs
RxDBuffer
Vaux
VCC
RxD
Rec-Filter
30k
Transmitter
BUS
GND
VCC
SBY
Driver
control
15k
Filter
TxD
MR
Figure 1 - Block diagram
TH8065 – Datasheet
3901008065
Page 4 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
2. Electrical Specification
All voltages are referenced to ground (GND). Positive currents flow into the IC.
The absolute maximum ratings (in accordance with IEC 134) given in the table below are limiting values that
do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term
exposure to limiting values may affect the reliability of the device. Correct operating of the device cannot be
guaranteed if any of these limits are exceeded.
2.1 Operating Conditions
Parameter
Symbol
Min
Max
Unit
Supply voltage
VSUP
6
18
V
Output voltage
VCC
4.85
5.15
V
Operating ambient temperature
TA
-40
+125
°C
Junction temperature
TJ
+150
°C
2.2 Absolute Maximum Ratings
Parameter
Supply voltage at VSUP
Input voltage at pin BUS
Symbol
Condition
VSUP
VBUS
Min
Max
-1.0
18
T ≤ 300 s
-
30
T ≤ 500 ms
-
40
-24
30
-
40
T ≤ 500 ms
Unit
V
V
Difference VSUP-VCC
VSUP-VCC
-0.3
40
V
Input voltage at pin EN
VINEN
-0.3
VSUP+0.3
V
Input voltage at pin TxD, RxD, RESET, WDI, CWD
VIN
-0.3
VCC+0.3
V
Input current at pin EN, TxD, RxD, RESET, WDI,
CWD
IIN
-25
25
mA
IINSH
-500
500
mA
Input current for short circuit of pin VSUP and VCC
ESD Capability on pin BUS, VBAT, GND
ESDBUSHB
Human body Model, 100pF
via 1.5kΩ
-4
4
kV
ESD Capability on pin TxD, RxD, EN, RESET, WDI,
CWD, VCC
ESDBUSHB
Human body Model, 100pF
via 1.5kΩ
-2
2
kV
Power dissipation
Thermal resistance from junction to ambient
(SOIC14fused) [2]
Junction temperature [3]
Storage temperature
[1]
[2]
[3]
P0
Internal limited [1]
RTHJA
70
K/W
TJ
150
°C
150
°C
TSTG
-55
See chapter 4.1 Safe Operating Area
SOIC14 with fused lead frame and an active copper area of >150sqmm
See chapter 3.5 Overtemperature Shutdown
TH8065 – Datasheet
3901008065
Page 5 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
2.3 Static Characteristics
Unless otherwise specified all values in the following tables are valid for VSUP = 6 to 18V and
TAMB = -40 to 125oC. All voltages are referenced to ground (GND), positive currents flow into the IC.
2.3.1. Voltage Regulator and Reset Unit
Parameter
Symbol
Condition
Min
Typ
Max
Unit T[1]
6
12
18
V
B
VEN = VSUP = 13V,
CWD=1nF,
BUS: 1k to VSUP,
Pins TxD, RxD, WDI and
RESET open, EN = VCC
200
300
μA
A
VSUP = 13V, VEN = 0V,
BUS: 1k to VSUP
15
30
μA
A
VSUP
Operating voltage
Supply current, VCC „noload“ [2]
VSUP
ISnl
Supply current, „sleep mode“
ISsleep
VSUP under voltage reset “off”
threshold
VSUVR_OFF
VSUP ramp up
3.2
3.7
4.2
V
A
VSUP under voltage reset “on”
threshold
VSUVR_ON
VSUP ramp down
2.7
3.1
3.5
V
A
VSUP under voltage reset hysteresis
VSUVR_HYS
V
A
V
A
5.25
V
A
0.2
VCC
VCCn
6V ≤ VSUP ≤ 18V
1mA ≤ ILOAD ≤ 70mA
TA = 25°C
TA = -40°C to 125°C
Output voltage VCC
4.90
4.85
5.0
5.10
5.15
VCCh
18V ≤ VSUP ≤ 40V
ILOAD = 10mA
VD10
IVCC = 10mA
75
120
mV
A
VD30
IVCC = 30mA
220
350
mV
A
VD70
IVCC = 70mA
500
800
mV
A
VLNR
6V ≤ VSUP ≤ 18V
20
mV
A
VLDR10
ILOAD = 1mA Æ 10mA
50
mV
A
VLDR30
ILOAD = 1mA Æ 30mA
90
mV
A
VLDR70
ILOAD = 1mA Æ 70mA
150
mV
A
Output current limitation
IVCC_max
VSUP > 0V
200
mA
A
Ripple Rejection on VSUP
PSRR
VSUP = 12V, fi = 120Hz, ViP-P =
1V, ILOAD = 10mA
Drop-out voltage [3]
Line regulation
Load regulation
TH8065 – Datasheet
3901008065
Page 6 of 40
4.80
80
130
t.b.d
dB
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Parameter
Symbol
Reset threshold - POR
VRES(ON)
Reset threshold – low voltage reset
VRES(OFF)
Vres Hysteresis
VRESHYS = |VRES(ON) – VRES(OFF)|
VRESHYS
Master reset threshold
Condition
Min
Typ
Max
VCC ramp up, t > trr
4.4
4.6
4.8
V
A
VCC ramp down, t > trr
4.4
4.6
4.8
V
A
150
mV
A
3.3
V
D
VMRES
3.0
3.15
Unit T[1]
Enable Input EN
Input voltage low
VENL
-0.3
0.8
V
A
Input voltage high
VENH
2.0
VSUP +0.3
V
A
Hysteresis
VENHYS
50
300
mV
A
Pull-down resistor EN low
RpdENL
0V ≤ VEN ≤ 0.8V
14
25
35
kΩ
A
Pull-down current EN high
IpdENH
VEN ≥ VENL
0.5
2
10
µA
A
0.8
V
A
Output RESET
Output voltage low
Pull-up current
VOL1_RESET IOUT = 1 mA, VSUP ≥ 6 V
Ipu
-500
-375
-250
μA
A
Input CWD
Input threshold low
VCWDL
0.076
0.08
0.084
VCC
A
Input threshold high
VCWDH
0.342
0.36
0.378
VCC
A
Pull up current (charge current)
ICWD_pu
VIN = 1V
7.6
13.9
20.2
µA
A
Pull down current (discharge current)
ICWD_pd
VIN = 1V
0.76
1.39
2.02
µA
A
35
50
73
kΩ
A
0.3
VCC
A
VCC
A
°C
D
°C
D
Input WDI
Pull down resistor
Rpd_WDI
Input voltage low
VIL_WDI
Input voltage high
VIH_WDI
VIN = VCC
0.7
Thermal Protection
Thermal shutdown
TJSHD
155
Thermal recovery
TJREC
126
[1]
[2]
[3]
180
A = 100% serial test, B = Operating parameter, C = Only used for data characterization (cpk), D = Value guaranteed by design
No active watchdog reset
The nominal VCC voltage is measured at VSUP =12V. If the VCC voltage is 100mV below its nominal value then the voltage drop is
VD = VSUP – VCC.
TH8065 – Datasheet
3901008065
Page 7 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
2.3.2. LIN Bus Interface
Parameter
Symbol
Condition
Min
Typ
Max
Unit T[1]
General
20
μA
A
47
kΩ
A
mA
A
20
µA
A
-1
1
mA
A
0.4
0.6
Pull up current BUS (recessive)
IINBUSpu
VBUS = 18 V, VSUP = 6V
Pull up resistor BUS
RBUSpu
VSUP = 12V, VBUS = 0V
20
Reverse current BUS (recessive)
-IINBUSrev VSUP = 12V, VBUS = 0V
-1
Reverse current BUS (loss of battery)
IINBUS_lob VSUP = 0V, 0V ≤ VBUS ≤ 18V
Reverse current BUS (loss of ground)
IINBUS_log VSUP= 12V, 0V ≤ VBUS ≤ 18V
30
Receiver
Receive threshold
Vthr_rec,
Vthr_dom
Centre point of receive threshold
Vthr_cnt = (Vthr_rec+Vthr_dom)/2
Vthr_cnt
Hysteresis of receive threshold
Vthr_hys = Vthr_rec-Vthr_dom
Vthr_hys
7.0 V ≤ VSUP ≤ 18 V
0.475
A
0.5
0.525
VSUP A
0.15
0.175
A
Transmitter
Output voltage BUS (dominant)
Current limitation BUS
VBUSdom_1
ILIM
IBUS = 40mA
VBUS = VSUP, TxD = 0V
1.2
V
A
41
120
200
mA
A
9.5
15
21
kΩ
A
0.3
VCC A
Input TxD
Pull-up resistor
Rpu_TxD
Input voltage low TxD
VIL
Input voltage high TxD
VIH
VIN = 0V
VCC A
0.7
Output RxD
Output voltage Low RxD
VOL
IOUT = 1 mA
Output voltage High RxD
VOH
IOUT = -1 mA
[1]
0.8
VCC - 0.8
V
A
V
A
A = 100% serial test, B = Operating parameter, C = only used for data characterization (cpk), D = Value guaranteed by design
TH8065 – Datasheet
3901008065
Page 8 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
2.4 Dynamic Characteristics
6V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C, unless otherwise specified
Min
Typ
Max
Unit
T[1]
VSUP = 12V,Vers. “A”
5.6
8
10.4
ms
A
VSUP = 12V,Vers. “B”
2.8
4
5.2
ms
A
VSUP = 12V,Vers. “C”
21
30
39
ms
A
VSUP = 12V,Vers. “D”
10.5
15
19.5
ms
A
trr
VSUP = 12V
3.0
6.5
12
μs
A
Discharge time CWD-capacity
tfCWD
CWD = 10nF,
ΔVCWD = 1V
5
µs
C
Watchdog period
tWD_per
CWD = 1nF ±1%
0.63
1.1
1.54
ms
A
Watchdog reset time
tWD_R
CWD = 1 nF ±1%
60
100
140
µs
A
twake_BUS
30
70
150
μs
A
tdeb_EN
2
6
15
µs
D
Parameter
Symbol
Condition
RESET and Watchdog
Reset time
Reset rising time
tRes
Wake-up and Mode Select
Wake up time
Debouncing time EN
Propagation delay EN to sleep mode
tpd_EN_sleep EN = High to Low
400
µs
A
Propagation delay EN to normal mode
tpd_EN_norm EN = Low to High
400
µs
A
Setup time TxD to EN for low slew mode
tset_TxD_LS
TxD = Low before
EN = L/H
5
µs
B
Hold time TxD after EN for low slew mode
thold_TxD_LS
TxD = Low after
EN = L/H
20
µs
B
General LIN Parameter
Slew rate rising edge BUS
dV/dTrise
Normal Mode
0.8
1.5
2.5
V/µs
C
Slew rate falling edge BUS
dV/dTfall
BUS-Load:
1kOhm/1nF
-2.5
-1.5
-0.8
V/µs
C
Slew rate rising edge BUS
dV/dTrise
0.3
0.8
1.3
V/µs
C
Slew rate falling edge BUS
dV/dTfall
-1.3
-0.8
-0.3
V/µs
C
Receiver debouncing time
tdeb_BUS
1.5
2.8
4.0
µs
C
6
µs
A
2
µs
A
35
pF
D
Receiver propagation delay BUS->RxD
Symmetry propagation delay BUS->RxD
Internal capacity
TH8065 – Datasheet
3901008065
tdr_RxD
tdf_RxD
tdsym_RxD
CBUS
Low Slew Mode
BUS-Load:
1kOhm/1nF
CL(RXD) = 50 pF
tdr_RXD - tdf_RXD
Pulse at BUS via
10kOhm with 0/10 V;
VSUP = open
Page 9 of 40
-2
25
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Parameter
Symbol
Condition
Min
Typ
Max
Unit
T[1]
LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (20kbit/s)
Conditions:
Normal slew mode; VSUP =7.0V to 18V; BUS loads: 1kΩ/1nF; 660Ω/6.8nF; 500Ω/10nF
TxD signal: tBit = 50µs, twH = TwL = tBit; trise = tfall < 100ns
Minimal recessive bit time [2]
trec(min)
40
50
58
µs
Maximum recessive bit time [2]
trec(max)
40
50
58
µs
Duty cycle 1
D1
D1 = trec(min) / (2*tBit)
Duty cycle 2
D2
D2 = trec(max) / (2*tBit)
0.396
A
0.581
A
LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (10.4kbit/s)
Conditions:
Low slew mode; VSUP =7.0V to 18V; BUS loads: 1kΩ/1nF; 660Ω/6.8nF; 500Ω/10nF
TxD signal: tBit = 96µs, twH = TwL = tBit; trise = tfall < 100ns
Minimal recessive bit time [2]
Maximum recessive bit
time [2]
trec(min)
80
96
113
µs
trec(max)
80
96
113
µs
Duty cycle 1
D1
D1 = trec(min) / (2*tBit)
Duty cycle 2
D2
D2 = trec(max) / (2*tBit)
0.417
A
0.590
A
LIN transceiver parameter according to SAE J2602 (10.4kbit/s)
Conditions:
Low slew mode; VSUP =7.0V to 18V; BUS loads: 1kΩ/1nF;660Ω/6.8nF;500Ω/10nF
TxD signal: tBit = 96µs, twH = TwL = tBit; trise = tfall < 100ns
Minimal recessive delay TxD -> BUS
[2]
Maximum recessive delay TxD -> BUS
Minimal dominant delay TxD -> BUS
[2]
[2]
Maximum dominant delay TxD -> BUS
[2]
tx_rec_min
48
µs
tx_rec_max
48
µs
tx_dom_min
48
µs
tx_dom_max
48
µs
Maximum rec. to dom. delay
Tr_d_max
tx_rec_max - tx_dom_min
15.9
µs
A
Maximum dom. to rec. delay
Td_r_max
tx_dom_max - tx_rec_min
17.2
µs
A
[1]
[2]
A = 100% serial test, B = Operating parameter, C = only used for data characterization (cpk), D = Value guaranteed by design
See chapter 2.5 Timing Diagrams
TH8065 – Datasheet
3901008065
Page 10 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
2.5 Timing Diagrams
50%
TxD
tdf_TXD
tdr_TXD
VBUS
100%
95%
BUS
50%
50%
5%
0%
tdr_RXD
tdf_RXD
RxD
50%
Figure 2 - Timing diagram for propagation delays
tBit
tBit
TxD
tx_rec_max
tx_dom_max
tx_dom_min
VSUP
100%
tdom(max)
74.4%
(77.8%)
tdom(min)
58.1%
(61.6%)
BUS
58.1%
(61.6%)
42.2%
(38.9%)
28.4%
(25.1%)
VSS
trec(min)
tx_rec_min
trec(max)
28.4%
(25.1%)
0%
Remark:
The levels for low slope mode are shown in brackets
Figure 3 - Timing diagram for duty cycle acc. to LIN 2.0 and J2602
TH8065 – Datasheet
3901008065
Page 11 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Normal Mode
Sleep Mode
Normal Mode
Ini-Phase
Low Slew
tpdEN_sleep
5V
4.5V
VCC
0.5V
0V
tset_TxD_LS
tpdEN_norm
EN
2V
2.0V
0.8V
thold_TxD_LS
TxD
50%
Figure 4 - Timing Diagram for EN mode selection
TH8065 – Datasheet
3901008065
Page 12 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
3. Functional Description
The TH8065 consists of a low drop voltage regulator 5V/70mA and a LIN bus transceiver, which is a bidirectional bus interface for data transfer between LIN bus and the LIN protocol controller.
Additionally integrated is a RESET unit with a power-on-reset delay of 8ms (optional 4,15 or 30ms).
and a programmable watchdog time which will be defined by an external capacity.
3.1 Operating Modes
The TH8065 provides three main operating modes “normal”, “sleep” and “low slew” and the intermediate
states “Ini-state” and “thermal shutdown”. The main modes are fixed states defined by basic actions (VSUP
start, EN or wake-up). The intermediate states are soft states. They aren’t defined by logical actions but by
changes of voltage (VSUP, VCC) or junction temperature.
VSUP power on
Set Slew_State = L
UVR / POR
VSUP > UVR_OFF
Regulator on
RESET = L / after tres RESET=H
and Watchdog activated
Wake-up disabled
LIN-Transceiver on/ normal slew mode
clear Reset-Timer
Start Regulator -> VCC ramp up
RESET = L
Wake-up disabled
VCC > Vres (4.65V) &
Slew_State=L
VSUP < UVR_ON
Ini-state
EN= L/H edge & TxD=H
NormalMode
VCC < Vres
Tj > Tjshd
VCC > Vres (4.65V) &
Slew_State=H
VSUP < UVR_ON
thermal
shutdown
EN= L/H edge & TxD=L
VSUP > UVR_ON &
BUS Wake-up
Tj > Tjshd
Tj < Tjrec
Tj > Tjshd
VCC < Vres
Regulator off
Wake-up disabled
LIN-Transceiver off
EN= H/L
EN=L
Low Slew
Mode
SleepMode
EN= H/L
Regulator off
Thermal shutdown off
Wake-up enabled (LIN-Receiver on)
LIN-Transmitter off
Regulator on
RESET = L / after tres RESET=H
and Watchdog activated
Wake-up disabled
Set Slew State = H
LIN-Transceiver on/ low slew mode
Figure 5 - State diagram of operating modes
TH8065 – Datasheet
3901008065
Page 13 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Normal Mode
This mode is the base mode. The bus transceiver is able to send with a max baud rate of 20kbit/s.
The whole TH8065 is active. Switching to normal mode can be done via the following actions:
- Start of VSUP or after under voltage reset
- Rising edge at EN (EN=high) and TxD=high
(local wake-up)
- Activity on the LIN bus
(remote wake-up)
Sleep Mode
Sleep mode is most current saving. With a falling edge on EN (EN=low) the TH8065 is switched from normal
mode into sleep mode. The voltage regulator and the reset/watchdog unit will be switched off and the LIN
transceiver is in recessive state.
Switching into sleep mode can be done independently from the current transceiver state. That means if the
transmitter is in dominant state this state will be cancelled and it will be switched to recessive state.
Low Slew Mode
In this mode the slew rate is switched from the normal value of typ. 1.6V/µs to a low value of typ. 0.8V/µs.
This mode is optimized to send with a maximum baud rate of 10.4kbit/s (SAE J2602). Because of this
reduction of the slew rate the EME behaviour is improved especially in the frequency range of 100 kHz to
10MHz.
Switching to this mode is possible with a combination of rising edge on EN together with a low level on TxD.
POR-state
This is the power-on-reset state of the TH8065, while Vsup < VSUVR_OFF. If the prior state was sleep mode,
the TH8065 switches via the ini-state to normal mode.
Ini-state
This is an intermediate state, which will pass through after switching on of VSUP or VCC. The TH8065
remains in this state if VCC is below VRES (Reset output = L) and Vsup > VSUVR_ON.
Thermal Shutdown
If the junction temperature TJ is higher than TJSHD (>155°C), the TH8065 will be switched into the thermal
shutdown mode. The behaviour within this mode is comparable with the sleep mode except for LIN
transceiver operating. The transceiver is completely disabled; no wake-up functionality is available.
If TJ falls below the thermal recovery temperature TJREC (typ. 140°C) the TH8065 will be recover to the
previous state (normal, sleep or low slew).
TH8065 – Datasheet
3901008065
Page 14 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
3.2 Initialization
Initialization starts if the power supply is switched on as well as every rising edge on of the TH8065 via the
EN pin.
VSUP- Power-ON
If VSUP is switched on the TH8065 starts to normal mode via the POR- and Ini-state. A combination of
dynamic POR and under voltage reset circuitry generates a POR signal, which switches the TH8065 into
normal mode. This power on behaviour is independent from the status of the EN-pin.
Power-on reset and under-voltage reset operates independent from each other, which secures the
independence from the rise time of VSUP. During fast VSUP edges the power-on reset will be active. If the
increasing of VSUP is very slow (> 1ms/V) and VSUP > VSUVR_OFF (typ. 3.5V) the under voltage reset unit
initializes the voltage regulator.
The effects of both POR circuits at different VSUP slopes will show in Figure 6.
VSUP
VSUVR_OFF
VSUVR_ON
UVR
POR
POR
UVR
EN=H/L
VCC
normal mode
sleep mode
normal mode
Figure 6 - Operating of power-on and under-voltage reset
After POR the voltage regulator starts and the VCC voltage will be output. If VCC>VMRes the bus interface will
be activated. If the VCC voltage level is higher than VRES, the reset time tRes is started. After tRes the RESET
output switches from low to high (see Figure 12).
The Initialization procedure operates after POR independent from the EN voltage.
Start of Linear Regulator via Wake-up
The initialization is only being done for the VCC circuitry parts. This procedure begins with leaving the master
reset state (VCC > VMRes) and runs in the same manner as the VSUP-Power-On.
3.3 Wake-Up
If the regulator is put into sleep mode it can be woken up with the BUS interface. Every pulse on the BUS
(high pulse or low pulse) with a pulse width of min. 70μs switches on the regulator.
The low slew mode has to be selected again if necessary.
After the BUS has woken up the regulator, it can only be switched off with a high level followed by a low level
on the EN pin.
TH8065 – Datasheet
3901008065
Page 15 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
3.4 VSUP under voltage reset
The under voltage detection unit inhibits an undefined behaviour of the TH8062 under low voltage condition
(VSUP < 4V). If VSUP drops below VSUVR_ON (typ. 3.1V) the under voltage detection becomes active and the
IC will be switched to POR state. The following increasing of VSUP above VSUVR_OFF (typ. 3.7V) cancels this
POR state and the voltage regulator starts with the initialization sequence.
VSUP under voltage in Normal Mode
Supply Voltages below VSUVR_OFF do not influence the voltage regulator. The output voltage Vcc follows
VSUP.
VSUP under voltage in Sleep Mode
No exit from the sleep mode will take place if the VSUP voltage drops down to VSUVR_ON (typ. 3.5V). The
under voltage reset becomes active (POR-state) if the voltage drops below 2.7V. As a result of this
functioning, the sleep mode is left to the normal mode. If VSUP rises again above VSUVR_OFF (typ. 4.2V) the IC
initializes the voltage regulator and continues to work with the normal mode.
The under voltage reset unit secures stable functioning in the under voltage range of VSUP down to GND
level. The dynamic Power-On-Reset secures a defined internal state independent from the duration of the
VSUP drop, which guarantees a stable restart.
VSUP under voltage in Low Slew Mode
The behaviour of TH8062 at low VSUP voltages is equal to the sleep mode. The low slew mode will be
cancelled, if VSUP drops below VSUVR_ON in this mode. The TH8062 enters the normal mode, if VSUP rises
again above VSUVR_OFF.
3.5 Overtemperature Shutdown
If the junction temperature is 155°C < TJ < 175°C the over-temperature recognition will be activated and the
regulator voltage will be switched off. The VCC voltage drops down, the reset state is entered and the bustransceiver is switched off (recessive state).
After TJ falls below 140°C the TH8065 will be initialized again (see Figure 12). This initialisation starts
independently from the voltage levels on EN and BUS. Within the thermal shutdown mode the transceiver
can not switch to the normal mode neither with local nor with remote wake-up.
The operation of the TH8065 is possible between TAmax (125°C) and the switch off temperature, but small
parameter differences can appear.
After over-temperature switch-off the IC behaves as described in chapter 3.8 RESET and Watchdog.
TH8065 – Datasheet
3901008065
Page 16 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
3.6 LIN BUS Transceiver
The TH8065 has an integrated bi-directional bus interface device for data transfer between LIN bus and the
LIN protocol controller.
The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver
with high voltage comparator followed by a debouncing unit.
Transmit Mode
During transmission the data at the pin TxD will be transferred to the BUS driver to generate a bus signal. To
minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control
and wave shaping unit.
Transmitting will be interrupted in the following cases:
- Sleep mode
- Thermal Shutdown active
- Master Reset (VCC < 3.15V)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode
This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS
(VBUS>VSUP).
No additional termination resistor is necessary to use the TH8065 in LIN slave nodes. If this IC is used for
LIN master nodes it is necessary that the BUS pin is terminated via an external 1kΩ resistor in series with a
diode to VBAT.
Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus
signal are suppressed by the implemented debouncing circuit (τ = 2.8µs).
VSUP
Vthr_max
60%
BUS
Vthr_hys
50%
40%
Vthr_cnt
Vthr_min
t < tdeb_BUS
t < tdeb_BUS
RxD
Figure 7 - Receive mode impulse diagram
The receive threshold values Vthr_max and Vthr_min are symmetrical to the centre voltage of 0.5*VSUP with a
hysteresis of 0.150*VSUP. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and
0.6*VSUP will be securely observed.
TH8065 – Datasheet
3901008065
Page 17 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Slew Modes and Data rates
The TH8065 is a constant slew rate transceiver which means that the bus driver works with a mode
depended slew rate. In normal mode the slew rate is typical 1.6 V/µs and in low slew mode typical 0.8 V/µs.
The lower slew rate in low slew mode associated with a baud rate of 10.4kbit/s improves the EME behaviour.
The LIN transceiver of TH8065 is compatible to the physical layer specification according to LIN 2.0
specification for data rates up to 20kbit/s and the SAE specification J2602 for data rates up to 10.4kbit/s.
The constant slew rate principle is very robust against voltage drops and can operate with RC- oscillator
systems with a clock tolerance up to ±2% between 2 nodes.
Low Slew Mode
In this mode the slew rate is switched from the normal value of typ. 1.6V/µs to a low value of typ. 0.8V/µs.
This mode is optimized to send with a maximum baud rate of 10.4kbit/s (acc. to SAE J2602). Because of this
reduction of the slew rate the EME behaviour is improved especially in the frequency range of 100 kHz to
10MHz.
Input TxD
The 5V input TxD controls directly the BUS level:
TxD = low
TxD = high
->
->
BUS = low (dominant level)
BUS = high (recessive level)
The TxD pin has an internal pull up resistor connected to VCC. This guarantees that an open TxD pin
generates a recessive BUS level.
MCU
VCC
VCC
RPU_TXD
IPU_TXD
TH8065
Typ.
15k
TxD
RC-Filter
(10ns)
Figure 8 - TxD input circuitry
TH8065 – Datasheet
3901008065
Page 18 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Output RxD
The received BUS signal will be output to the RxD pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys
BUS > Vthr_cnt + 0.5 * Vthr_hys
->
->
RxD = low
RxD = high
This output is a push-pull driver between VCC and GND with an output current of 1mA.
TH8065
MCU
VCC
RxD
Figure 9 - RxD output circuitry
TH8065 – Datasheet
3901008065
Page 19 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
3.7 Linear Regulator
The TH8065 has an integrated low drop linear regulator with a p-channel-MOSFET as driving transistor. This
regulator outputs a voltage of 5V ±3% and a current of ≤70mA within an input voltage range of
6V ≤ VSUP ≤ 18V. The current limitation unit limits the output current for short circuits or overload to 130mA
respectively drop-down of the VCC voltage.
6
VCC [V]
5
4
3
2
1
0
0
20
40
60
80
100
120
140
Iload [mA]
Figure 10 - Characteristic of current limitation VCC = f (IVCC)
TH8065 – Datasheet
3901008065
Page 20 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
3.8 RESET and Watchdog
The TH8065 contains a combined reset- and watchdog-unit which secures the correct initialization and
generation of the reset signal.
VSUP,
VCC
VRES
int.
POR
signal
trr
tRes
RESET
Start-up
ON delay
Watchdog
Power-off
WDI
CWD
VCWDH
tWDL
tWDH
VCWDL
Figure 11 - Reset and Watchdog behaviour
The RESET pin outputs the reset state and the watchdog state of the TH8065. The POR timer will be started
if VSUP is switched on and VCC> POR threshold (4.65V). The Watchdog is inactive. After the time tRes the
RESET output is switched from low to high and the watchdog becomes active. The charging of the watchdog
capacity starts and dependent from the trigger pulse on the WDI input the Reset outputs the status of the
watchdog.
The watchdog is only active if VCC > VRES. If VCC drops below VRES the watchdog will be switched off and the
watchdog capacity will be discharged.
3.8.1. RESET
The RESET unit combines a VCC low voltage detection unit with fixed POR timer This output is switched
from low to high if VSUP is switched on and VCC>VRES (4.65V) after the time tRes .
All conditions which cause a drop of the VCC voltage will be detected from the low voltage reset unit which
generates a reset signal. The TH8065 will be reinitialized if the VCC voltage rises above the low voltage limit.
If the voltage VCC drops below VRES then the RESET output is switched from high to low after the time trr has been
reached. For this reason short breaks of the VCC voltage and uncontrolled reset generations will be inhibited.
The circuitry of the RESET output driver guarantees, that the reset low level during decreasing of the VCC
voltage will be secure kept (see Figure 13).
TH8065 – Datasheet
3901008065
Page 21 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
VSUP
T>Tj
T<Tj
t<trr
VCC
t<trr
VRES
tRes
trr
tRes
tRes
tRes
RESET
Initialisation
Thermal
shutdown
Spike VSUP
Current limitation
Low voltage
active
VSUP
Spike VCC
Figure 12 - Reset behaviour
Figure 13 - Output current of reset output vs. VCC voltage
3.8.2. Watchdog
The Watchdog can be used for observation of the connected microcontroller. It has to be triggered via the
WDI input and the time is defined via the capacity connected to the CWD input. The watchdog status will be
output via the reset pin.
With rising edges on WDI the watchdog time will be reset. If the WDI input isn’t triggered the internal circuitry
generates low pulses at the RESET pin with a time tWD_R and a period of tWD-per.
The CWD capacitor provides a wide adjustment range for the watchdog time.
With every rising edge on WDI the capacitor CWD will be charged up to the threshold VCWDL. If there is no new
trigger pulse on WDI, the following discharging of CWD within the time tWDL will be done up to the lower
threshold VCWDL.
TH8065 – Datasheet
3901008065
Page 22 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
WDI
WDI = High or Low
tWDt_R
CWD
tWD_per
VCWDH
VCWDM
VCWDL
tWD_R
RESET
Figure 14 - Watchdog timing
The reset output will be switched from high to low (watchdog reset), if the voltage on pin CWD reaches
VCWDL. The reset output stays at low level until the voltage at CWD has reached the level of VCWDH.
The RESET pin generates a periodic signal with low pulse width of tWD_R and a period of tWD_per, if no
retrigger of WDI takes place.
Calculation of Watchdog time
Watchdog reset time:
tWD _ R =
(VCWDH
− VCWDL ) ∗ CWD
I CWD _ pu
CWD
Watchdog capacity connected to pin CWD
VCWDH Upper watchdog threshold
VCWDL Lower watchdog threshold
Max. watchdog reset trigger time
tWDt _ R =
(VCWDH − VCWDL ) ∗ CWD
ICWD _ pd
ICWD_pu CWD charge current
ICWD_pd CWD discharge current
With the valid charge and discharge currents of CWD of the TH8065 is a simple calculation of the capacity
values for a defined watchdog trigger time and reset time possible:
tWDt _ R [ms ] = CWD [nF ]
tWD _ R [ms ] = 0.1 ∗ CWD [nF ]
Example:
C WD = 10nF → t WDt _ R = 10ms and t WD _ R = 1ms
Within a timeframe of 10ms the MCU has to reset the watchdog to prevent a reset generation. The
complete watchdog period tWD_per = 11ms.
If the watchdog has to be deactivated for e.g. firmware development, the pin CWD has to be directly
connected to GND. The reset signal is in this case only determined by the reset thresholds.
TH8065 – Datasheet
3901008065
Page 23 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
3.9 Mode Input EN
The TH8065 is switched into the sleep mode with a falling edge and into normal mode with a rising edge at
the EN pin. The normal mode will be kept as long as EN = high.
The deactivation of TH8065 with a falling edge at EN can be done independently from the state of the bustransceiver.
Filter
6μs
23k
ESD
enable
1.5M
voltage
limiter
EN
Figure 15 - EN input circuitry
The maximum input voltage is VSUP. The threshold is typ. 1.4V and therefore also 5V and 3.3V CMOS
levels can be used as input signal. Figure 15 shows the internal circuitry of the EN pin.
The EN input has an internal pull down resistor of typ. 23k to secure that if this pin is not connected a low
level will be generated. An input debouncing filter of 6µs suppresses effectively disturbance couplings via the
EN pin
It will use different pull down resistors for normal and sleep mode to minimize the sleep mode current.
The wide input voltage range allows different EN control possibilities. If the EN input is connected to a CMOS
output of the MCU, a falling edge switches the TH8065 into sleep mode (the regulator is also switched off).
The wake up is only possible via the bus line.
TH8065
VBAT
GND
GND
VSUP
VCC
EN
CIN
LIN
220p
Cload
MCU
+5V
RESET
GND
TxD
BUS
RxD
CWD
WDI
GND
GND
Figure 16 - EN controlled via MCU
TH8065 – Datasheet
3901008065
Page 24 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
If the application doesn’t need the wake up capability of the TH8065 a direct connection EN to VSUP is
possible. In this case the TH8065 operates in permanent normal mode. Also possible is the external (outside
of the module) control of the EN line via a VBAT signal. If this is a direct VBAT signal an external reverse
battery protection has to be added to the circuitry.
TH8065
VBAT
CIN
10k
LIN
220p
GND
GND
VSUP
VCC
EN
Cload
MCU
+5V
RESET
GND
TxD
BUS
RxD
CWD
WDI
GND
GND
Figure 17 - Permanent normal mode
TH8065 – Datasheet
3901008065
Page 25 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
4.
Application Hints
4.1 Safe Operating Area
The maximum power dissipation depends on the thermal resistance of the package and the PCB, the
temperature difference between Junction and Ambient as well as the airflow.
The power dissipation can be calculated with:
PD = (VSUP – VCC) * IVCC + PD_TX
The power dissipation of the transmitter PD_TX depends on the transceiver configuration and its parameters
as well as on the bus voltage VBUS=VBAT-VD, the resulting termination resistance RL, the capacitive bus load
CL and the bit rate. Figure 18 shows the dependence of power dissipation of the transmitter as function of
VSUP. The conditions for calculation of the power dissipation is RL=500Ω, CL=10nF, bit rate=20kbit and duty
cycle on TxD of 50%
50
45
40
PD [mW]
35
30
25
20
15
10
5
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VSUP [V]
Figure 18 - Power dissipation LIN transceiver @ 20kbit
The permitted package power dissipation can be calculated:
PDmax =
T j − TA
RTHJ − A
If we consider that PD_TX_max= f (VSUP) the max output current IVCC on VCC can be calculated:
T j − TA
I VCCmax =
RTHJ − A
− PD _ TX
_ max @ VSUP
VSUP − VCC
TJ -TA is the temperature difference between junction and ambient and Rth is the thermal resistance of the
package. The thermal energy is transferred via the package and the pins to the ambient. This transfer can be
improved with additional ground areas on the PCB as well as ground areas under the IC.
TH8065 – Datasheet
3901008065
Page 26 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
80
maximum current
70
TA=85°C
TA=125°C
50
max. supply voltage
IVCC_max [mA]
60
40
30
20
10
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VSUP [V]
Figure 19 - Save operating area
The linear regulator of the TH8065 operates with input voltages up to 18V and can output a current of 70mA.
The maximum power dissipation limits the maximum output current at high input voltages and high ambient
temperatures. The output current of 70mA at an ambient temperature of TA = 125°C is only possible with
small voltage differences between VSUP and VCC. See Figure 19 for safe operating areas for different ambient
temperatures. The TH8065 is able to output 70mA over the whole voltage range if the max ambient
temperature is limited to 85°C.
4.2 Low Dropout Regulator
The voltage regulator of theTH8065 is a low dropout regulator (LDO) with a p-MOSFET as driving transistor.
This kind of regulator has a standard pole, generated from the internal frequency compensation and an
additional pole, which is dependent from the load and the load capacitance. This additional pole can cause
an instable behaviour of the regulator! It is required a zero point to compensate this additional pole. It can be
realised via an additional load resistor in series with a load capacitor. It is used for this compensation the
equivalent series resistance (ESR) of the load capacitor. Every real capacitor is characterized with an ESR
value. With the help of this ESR value an additional zero point is implemented into the amplification loop and
therefore the result of the negative phase shift is compensated.
Because of this correlation the regulator has a stable operating area which is defined by the load resistance
RL, the load capacitor CL and the corresponding ESR value. The load resistance resp. load current is defined
by the application itself and therefore the compensation of the pole can only be done via variation of the load
capacitance and ESR value.
Input Capacitor on VSUP CIN
An input capacitance is necessary of CIN ≥ 4.7µF. Higher capacitance values improves the line transient
response and the supply noise rejection behaviour. The combination of electrolytic capacitor (e.g.100µF) in
parallel with a ceramic RF-capacitor (e.g.100nF) archives good disturbance suppressing.
The input capacitor should be placed as close as possible (< 1cm) to the VSUP pin.
TH8065 – Datasheet
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Page 27 of 40
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Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Load Capacitor on VCC CL
The regulator is stabilized by the output capacitor CL. The TH8065 requires a minimum of 4.7µF capacitor
connected to the 5V output to insure stability. This capacitor should maintain its ESR in the stable region of
the ESR curve (See Figure 20) over the full operating temperature range of the application. It has to be taken
into account that the capacitance value and the ESR of a capacitor changes with temperature. The minimal
capacitance value must also be kept within the whole operating temperature range.
[email protected] [Ohm]
100
10
1
Stable Area
0,1
0,01
0
10
20
30
40
50
load current [mA]
Figure 20 - ESR Curves for 6.8μF ≤ CL ≤ 100μF and Frequency of 100 kHz
The value and type of the output capacitor can be selected using the diagram shown in Figure 20. The load
capacitor should be placed as close as possible (< 1cm) to the VCC pin.
Capacitance Value
The capacitance value of an electrolytic capacitor is dependent from the voltage, temperature and the
frequency. The temperature coefficient of the capacitor value is positive, that means that the value increases
with increasing of the temperature. The capacitance value decreases with increasing of the frequency. This
behaviour of a capacitor can cause that at TA=-40°C the capacitance value falls below the minimum required
capacitance for the regulator. In this case the regulator becomes instable, which means the regulator starts
oscillation. The nominal value of the capacitor at TA=25°C has to be chosen with enough margin under
consideration of the capacitor specification. The instable behaviour will be amplified because of the
decreasing of the capacitance with this oscillation.
ESR
The equivalent serial resistance is the resistor part of the equivalent circuit diagram of a capacitor. The ESR
value is dependent from the temperature and frequency. Normally the specified ESR values for a capacitor is
valid at a temperature of TA=25°C and a frequency of f=100 kHz.
The temperature coefficient is negative, which means with increasing of the temperature the ESR value
decreases. In the choice of the capacitance has to be taken into account that the ESR can decrease at TA=40°C dramatically that the valid operating area can be left, which causes that the regulator will be instable.
TH8065 – Datasheet
3901008065
Page 28 of 40
May 2006
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TH8065
Voltage Regulator with LIN Transceiver and Watchdog
Tantalum Capacitors
This type of capacitor has a low dependence of the capacitance and the ESR from the temperature and is
therefore well suited as VCC load capacitor.
Aluminium Capacitors
These capacitors show a strong influence of the capacitance and the ESR from the temperature. This
characteristic restrains the usability as load capacitor for the low drop regulator of TH8065.
4.3 Application Circuitry
TH8065
GND
VBAT
VSUP
CIN
100μ
EN
100n
LIN-BUS
220p
CWD
10μ...100μ
MCU
GND
VCC
100n
RESET
GND
TxD
BUS
RxD
CWD
WDI
GND
GND
+5V
RST
Figure 21 - Application circuit (slave node)
4.4 EMI Supressing
To minimize the influence of EMI on the bus line a 220pF capacitor should be connected directly to the BUS
pin (see Figure 21). This EMI-Filter makes sure that the RF injections into the IC from the BUS line have no
affect resp. will be limited.
Alternatively to a pure C-filter it is also possible to use LC- or RC-filter. The dimension of C, L or R, L
depends on the corner frequency, the maximum LIN bus capacitance (10nF) and the compliance with the
DC- and AC LIN bus parameters.
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Voltage Regulator with LIN Transceiver and Watchdog
4.5 Connection to Flash-MCU
While programming a flash MCU the TH8065 should be disconnected from the MCU. This can be done via
disconnecting the supply voltage from the TH8065 or by switching off with the EN pin. The reverse current
supply of the IC via the RxD pin, if the connected MCU pin is used as normal signal input and programming
input, must be inhibited via a decoupling diode. In this case the MCU must be supplied via the programming
interface.
Prog.-Data
10u...47u
MCU
TH8065
VCC
47n...100n
RESET
TxD
RxD
Vhigh_RxD >= 4.7V at VCC = 5V
Vlow_RxD = 0.8V
0.7V
Vhigh = 4V at VCC = 5V
Figure 22 – Example circuitry for connection of RxD to MCU for flash programming
The programming of the Flash is also possible via the LIN pin, if the MCU supports this kind of flash mode.
TH8065 – Datasheet
3901008065
Page 30 of 40
May 2006
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TH8065
Voltage Regulator with LIN Transceiver and Watchdog
5. Operating during Disturbance
5.1 Operating without VSUP or GND
The absence of VSUP or GND connection will not influence or disturb the communication between other bus
nodes. No reverse supply of the IC can appear if without GND or VSUP connection the BUS pin is on VBAT
level.
5.2 Short Circuit BUS against VBAT
The reaction of the IC depends on the send state of the transceiver:
- Recessive
LIN bus is blocked, no influence to the TH8065
- Dominant
Current limitation, thermal shut down of TH8065 if power dissipation will make an
overrun of TJ
5.3 Short Circuit BUS against GND
LIN bus is blocked. No influence on the TH8065.
5.4 Short Circuit TxD against GND
The LIN transceiver is permanently in the dominant state, which means the whole LIN bus. This state can
only be detected from the LIN controller. In this case the controller must switch off the LIN node via the EN
input of the TH8065. A thermal shut down of TH8065 will appear if the power dissipation will make an
overrun of TJ.
5.5 TxD open
The internal pull-up resistor forces the LIN node to the recessive state. The communication between the
other bus-nodes will not be disturbed.
5.6 Short Circuit VCC against GND
The VCC pin is protected via a current limitation. This state is comparable with the behaviour in the sleep
mode.
5.7 Overload of VCC
Thermal switch off
The power dissipation is increasing if the load current is between IVCC_max and ILVCC. If the max junction
temperature of >155°C is reached, the IC will be switched off. The voltage regulator will also be switched off
and a reset signal is forced.
Over current
If the current limitation is active the voltage on VCC drops down. If this voltage under-runs the threshold
VRES, a reset will be forced.
5.8 Undervoltage VCC
The reset unit ensures the correct behaviour of the driver during under-voltage. The BUS pin generates the
recessive state if VCC < VMRes (3.15V). The inputs EN, WDI and TxD have pull-up or pull-down characteristics.
If VCC ≥ VMRes the TxD signal is transmitted to the bus. The receive mode is also active.
TH8065 – Datasheet
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Page 31 of 40
May 2006
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TH8065
Voltage Regulator with LIN Transceiver and Watchdog
5.9 Undervoltage VSUP
The combination of dynamic power on reset and low voltage reset guarantees a defined start up behaviour.
If the supply voltage VSUP drops below 3V the low voltage detection becomes active. If the VSUP voltage
rises again above 3.5V the low voltage reset will be terminated and the 5V voltage regulator will be started.
5.10 Short circuit RxD, RESET against GND or VCC
Both outputs are short circuit proof to VCC and ground.
5.11 Short circuit CWD against GND or VCC
The watchdog is deactivated if CWD is short circuit against GND. The reset signal is in this case only
determined by the thresholds.
If WDI is short circuit against VCC the reset pin outputs a permanent low level.
TH8065 – Datasheet
3901008065
Page 32 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
6. PIN Description
GND
1
14
GND
VSUP
2
13
VCC
EN
3
12
RESET
GND
4
11
TxD
BUS
5
10
RxD
CWD
6
9
WDI
GND
7
8
GND
TH8065
SOIC14
Pin
Name
IO-Typ
1
GND
P
Ground
2
VSUP
P
Supply voltage
3
EN
I
Enable input voltage regulator, HV-pull-down-input, High-active
4
GND
P
Ground
5
BUS
I/O
LIN bus line
6
CWD
I/O
Watchdog capacity
7
GND
P
Ground
8
GND
P
Ground
9
WDI
I
Watchdog trigger input, pull down
10
RxD
O
Receive output, 5V-push-pull
11
TxD
I
5V-Transmit input, pull-up-input
12
RESET
O
Reset 5V-output, active low
13
VCC
O
Regulator output 5V/70mA
14
GND
P
Ground
TH8065 – Datasheet
3901008065
Description
Page 33 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
7. Mechanical Specification
SOIC14NB
Small Outline Integrated Circiut (SOIC), SOIC 14, 150 mil
A1
B
D
E
e
H
h
L
A
α
ZD
A2
8.56
8.74
3.81
3.99
1.27
5.80
6.20
0.25
0.50
0.41
1.27
1.52
1.72
0°
8°
0.51
1.37
1.57
0.337
0.344
0.160
0.167
0.050
0.228
0.244
0.010
0.020
0.016
0.050
0.060
0.068
0°
8°
0.020
0.054
0.062
C
All Dimension in mm, coplanarity < 0.1 mm
min
max
0.10
0.25
0.36
0.45
0.19
0.25
All Dimension in inch, coplanarity < 0.004”
min
max
0.004
0.01
0.014 0.0075
0.018 0.0098
TH8065 – Datasheet
3901008065
Page 34 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
8. Tape and Reel Specification
8.1 Tape Specification
max. 10°
max. 10°
IC pocket
R
Top View
n.
mi
Sectional View
T2
P0
D0
T
P2
E
G1
< A0 >
F
K0
W
B0
B1
S1
G2
T1
P1
D1
Cover Tape
Abwickelrichtung
Standard Reel with diameter of 13“
Package
Parts per Reel
Width
Pitch
SOIC14NB
2500
16 mm
8 mm
D0
E
P0
P2
Tmax
T1 max
G1 min
G2 min
B1 max
D1 min
F
P1
Rmin
T2 max
W
1.5
+0.1
1.75
±0.1
4.0
±0.1
2.0
±0.1
0.6
0.1
0.75
0.75
12.1
1.5
7.5
±0.1
4 - 12
±0.1
30
8.0
16.0
±0.3
A0, B0, K0 can be calculated with package specification.
Cover Tape width 13.3 mm.
TH8065 – Datasheet
3901008065
Page 35 of 40
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Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
8.2 Reel Specification
W2
W1
B*
D*
C
A
N
Amax
B*
C
D*min
330
2.0 ±0.5
13.0 +0,5/-0,2
20.2
Width of half reel
Nmin
W1
W2 max
8 mm
100,0
8,4
11,1
TH8065 – Datasheet
3901008065
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TH8065
Voltage Regulator with LIN Transceiver and Watchdog
9. ESD/EMC Remarks
9.1 General Remarks
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
9.2 ESD-Test
The TH8065 is tested according CDF-AEC-Q100-002 / MIL883-3015.7 (human body model).
9.3 EMC
The test on EMC impacts is done according to ISO 7637-1 for power supply pins and ISO 7637-3 for dataand signal pins.
TH8065 – Datasheet
3901008065
Page 37 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
10. Revision History
Version
Changes
Remark
001
Preliminary Release
Date
Oct. 2004
002
Updated Static Characteristics
April 2005
003
Introduction of variable POR Reset times
May 2006
TH8065 – Datasheet
3901008065
Page 38 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
11. Assembly Information
Standard information regarding manufacturability of Melexis products with different soldering
processes
Our products are classified and qualified regarding soldering technology, solderability and moisture
sensitivity level according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
•
•
IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
•
EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Iron Soldering THD’s (Through Hole Devices)
•
EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
EIA/JEDEC JESD22-B102 and EN60749-21
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of
the Use of Certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality_leadfree.asp
TH8065 – Datasheet
3901008065
Page 39 of 40
May 2006
Rev 003
TH8065
Voltage Regulator with LIN Transceiver and Watchdog
12. Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the
information set forth herein or regarding the freedom of the described devices from patent infringement.
Melexis reserves the right to change specifications and prices at any time and without notice. Therefore,
prior to designing this product into a system, it is necessary to check with Melexis for current information.
This product is intended for use in normal commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional
processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical
data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering
of technical or other services.
© 2002 Melexis NV. All rights reserved.
For the latest version of this document. Go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe and Japan:
Phone: +32 1367 0495
E-mail: [email protected]
All other locations:
Phone: +1 603 223 2362
E-mail: [email protected]
ISO/TS16949 and ISO14001 Certified
TH8065 – Datasheet
3901008065
Page 40 of 40
May 2006
Rev 003
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