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Ultra-low capacitance single-line
ESD protection portfolio overview
‘Ultra Low’ (ULC) and ‘eXtra Low’ (XLC) capacitance ESD protection
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Overview
Basic
In depth
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ESD protection is needed for
Advanced technology with very thin lithography
and gate oxide highly vulnerable to ESD
Integrated electronics systems with PCBs
having a high component density facilitate
ESD coupling and propagation
Core ICs such as microcontrollers,
micro-processors, transceivers, etc.
IC manufacturers reluctant to make robust
embedded ESD protection diodes that would
require a significant active area of their
advanced and expensive technology.
When the application uses RF (Wi-Fi or Bluetooth), a common-mode filter
is required, in addition to ESD protection, to avoid RF performance decrease
due to the EMI generated by the high-speed link.
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Why ultra-low capacitance ?
• The parasitic capacitance of ESD protection devices must be low enough to allow highspeed signals to be transmitted without degradation.
• A high parasitic capacitance of ESD protection devices would increase too much the
signal rise/fall time and prevent the communications.
Example of the impact of parasitic capacitance on an HDMI signal simulated with discrete capacitance
Time domain
Fall time
too HIGH
Rise time
too HIGH
Frequency domain
Bandwidth is too narrow
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Single line for flexibility
Example of PCB density
• Single-line ESD protection provides flexibility on the PCB layout
• ST offers industry-standard micro-packages such as the 0402
and 0201 to release designers from space constraints
PCB area < 0.5 cm²
0402
0201
0.3 mm
More than 3 x
SMALLER AREA
0.5 mm
0.6 mm
1.0 mm
0.6 mm
0.6 mm²
0.18 mm²
Thickness: 0.5 mm
Thickness: 0.3 mm
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Clamping voltage
ESD response to IEC 61000-4-2 (+8 kV contact discharge)
Example of ESDARF02-1BU2CK
• The quality of protection lies in the
clamping voltage of the ESD diodes
• It is measured after 30 ns (the first peak
voltage is in the nanosecond range; too
fast to be significant)
• 0.2 pF single-line ESD protection devices
can clamp 8000 V ESD strikes down to
19 V !
IC to
protect
Clamping voltage
19 V after 30 ns
8000 V ESD
IEC 61000-4-2
ESD protection
diode
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Main selection criteria
• VBR Breakdown voltage higher than operating signal
Above this voltage, the ESD protection devices will enter Clamping mode
• CLINE Low parasitic capacitance (a consequence of high bandwidth) minimizing the impact
on transmission line impedance
• fc Cut-off frequency higher than high-speed signal bandwidth defined by the rise time value
• Rd Dynamic resistance & VCL Clamping voltage to keep the protected IC safe
Example of ESDARF02-1BU2CK
fc @ -3 dB >> 10 GHz
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Single-line portfolio
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CLINE
0402 package
0201 package
1.0 x 0.6 x 0.5 mm
0.6 x 0.3 x 0.3 mm
Line capacitance
< 2 pF
1.5 pF (typical)
13.5 V @ 30 ns
Ultra Low Capa
ULC
ESDAULC5-1BF4
Low clamping
ESDAULC6-1U2
0.8 pF (typical)
ESDARF01-1BF4
Low clamping
0.6 pF (typical)
6.8 V @ 30 ns, VBR = 0.6 V
eXtra Low Capa
XLC
< 0.5 pF
ESDAXLC6-1BT2
0.5 pF (maximum)
ESDAXLC6-1BU2
0.4 pF (typical)
20 kV ESD
ESDARF02-1BU2
ESDAXLC6-1MY2
0.24 pF (typical)
36 V @ 30 ns
0.35 pF (maximum)
ESDARF02-1BU2CK
0.2 pF (typical)
30 V @ 30 ns
Low clamping
Let’s go further
Basic presentation
Intermediate product presentation soon available:
‘Understanding ST’s ESD ultra-low capacitance
(XLC and ULC) series specification’
Application Notes:
In-depth information
Selection

TVS short-pulse dynamic resistance measurement ... (AN4022)

IEC 61000-4-2 standard testing (AN3353)
 Selection guide [pdf]
 www.st.com/esda-ultralowcapa
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Thank you
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