Data Sheet

LF
PA
K
56
PSMN4R0-30YLD
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56
using NextPowerS3 Technology
10 October 2013
Product data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package.
NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers
high efficiency, low spiking performance usually associated with MOSFETs with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
•
•
•
•
•
•
•
•
Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching
frequencies
Superfast switching with soft-recovery; s-factor > 1
Low spiking and ringing for low EMI designs
Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at
25 °C
Optimised for 4.5 V gate drive
Low parasitic inductance and resistance
High reliability clip bonded and solder die attach Power SO8 package; no glue, no
wire bonds, qualified to 175 °C
Wave solderable; exposed leads for optimal visual solder inspection
3. Applications
•
•
•
•
•
•
On-board DC-to-DC solutions for server and telecommunications
Secondary-side synchronous rectification in telecommunication applications
Voltage regulator modules (VRM)
Point-of-Load (POL) modules
Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
Brushed and brushless motor control
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
-
30
V
ID
drain current
Tmb = 25 °C; VGS = 10 V; Fig. 1
-
-
95
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
-
64
W
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PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Tj
junction temperature
Conditions
Min
Typ
Max
Unit
-55
-
175
°C
-
4.4
5.5
mΩ
-
3.4
4
mΩ
-
2.4
-
nC
-
9.1
-
nC
-
1.1
-
Static characteristics
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10
Dynamic characteristics
QGD
gate-drain charge
VGS = 4.5 V; ID = 25 A; VDS = 15 V;
Fig. 12; Fig. 13
QG(tot)
total gate charge
VGS = 4.5 V; ID = 25 A; VDS = 15 V;
Fig. 12; Fig. 13
Source-drain diode
S
softness factor
IS = 25 A; VGS = 0 V; dIS/dt = -100 A/µs;
VDS = 15 V; Fig. 16
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
mbb076
S
1 2 3 4
LFPAK56; PowerSO8 (SOT669)
6. Ordering information
Table 3.
Ordering information
Type number
PSMN4R0-30YLD
Package
Name
Description
Version
LFPAK56;
Power-SO8
Plastic single-ended surface-mounted package (LFPAK56;
Power-SO8); 4 leads
SOT669
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN4R0-30YLD
4D030L
PSMN4R0-30YLD
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PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
30
V
VDGR
drain-gate voltage
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage
-20
20
V
ID
drain current
VGS = 10 V; Tmb = 25 °C; Fig. 1
-
95
A
VGS = 10 V; Tmb = 100 °C; Fig. 1
-
67
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
-
378
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
64
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Tsld(M)
peak soldering temperature
-
260
°C
VESD
electrostatic discharge voltage
HBM
375
-
V
Source-drain diode
IS
source current
Tmb = 25 °C
-
54
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
378
A
-
63
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 25 A;
[1]
Vsup ≤ 30 V; RGS = 50 Ω; unclamped;
tp = 129 µs
[1]
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PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
003aal026
100
ID
(A)
03na19
120
Pder
(%)
80
80
60
40
40
20
0
Fig. 1.
0
25
50
75
100
125
150 175
Tj (°C)
Continuous drain current as a function of
mounting base temperature
ID
(A)
0
200
Fig. 2.
0
50
100
150
Tmb (°C)
200
Normalized total power dissipation as a
function of mounting base temperature
003aal028
103
Limit RDSon = VDS / ID
102
tp = 10 us
100 us
10
DC
1 ms
10 ms
100 ms
1
10-1
10-1
Fig. 3.
1
10
VDS (V)
102
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 6
-
2.14
2.33
K/W
PSMN4R0-30YLD
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PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-a)
thermal resistance
from junction to
ambient
Fig. 4
-
50
-
K/W
Fig. 5
-
125
-
K/W
aaa-005751
aaa-005750
Fig. 4.
PCB layout for thermal resistance junction to
ambient 1” square pad; FR4 Board; 2oz copper
Fig. 5.
PCB layout for thermal resistance junction to
ambient minimum footprint; FR4 Board; 2oz
copper
003aal029
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1
0.05
P
0.02
δ=
single shot
tp
10-2
10-6
Fig. 6.
10-5
10-4
10-3
10-2
10-1
tp
T
t
T
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C
1.2
1.74
2.2
V
Static characteristics
V(BR)DSS
VGS(th)
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N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ΔVGS(th)/ΔT
gate-source threshold
voltage variation with
temperature
25 °C < Tj < 150 °C
-
-4.1
-
mV/K
IDSS
drain leakage current
VDS = 24 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 24 V; VGS = 0 V; Tj = 150 °C
-
-
100
µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
-
4.4
5.5
mΩ
-
-
9.1
mΩ
-
3.4
4
mΩ
-
-
6.6
mΩ
f = 1 MHz
-
2.2
-
Ω
ID = 25 A; VDS = 15 V; VGS = 10 V;
-
19.4
-
nC
-
9.1
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
18.2
-
nC
IGSS
RDSon
gate leakage current
drain-source on-state
resistance
Fig. 10
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
RG
gate resistance
Dynamic characteristics
QG(tot)
total gate charge
Fig. 12; Fig. 13
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 12; Fig. 13
QGS
gate-source charge
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
-
2.6
-
nC
QGS(th)
pre-threshold gatesource charge
Fig. 12; Fig. 13
-
1.9
-
nC
QGS(th-pl)
post-threshold gatesource charge
-
0.7
-
nC
QGD
gate-drain charge
-
2.4
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13
-
2.3
-
V
Ciss
input capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
-
1272
-
pF
Coss
output capacitance
Tj = 25 °C; Fig. 14
-
812
-
pF
Crss
reverse transfer
capacitance
-
87
-
pF
td(on)
turn-on delay time
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
-
10.7
-
ns
tr
rise time
RG(ext) = 5 Ω
-
21.2
-
ns
td(off)
turn-off delay time
-
14.9
-
ns
tf
fall time
-
11.7
-
ns
PSMN4R0-30YLD
Product data sheet
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PSMN4R0-30YLD
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N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Qoss
output charge
VGS = 0 V; VDS = 15 V; f = 1 MHz;
-
16
-
nC
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage
IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 15
-
0.82
1.2
V
trr
reverse recovery time
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
25.1
-
ns
Qr
recovered charge
VDS = 15 V; Fig. 16
-
13.3
-
nC
ta
reverse recovery rise
time
-
11.9
-
ns
tb
reverse recovery fall
time
-
13.1
-
ns
S
softness factor
-
1.1
-
[1]
includes capacitive recovery
003aal030
100
ID
(A)
10 V
[1]
4.5 V
003aal031
30
RDSon
3.5 V
25
80
20
60
VGS = 3 V
40
20
15
2.8 V
10
2.6 V
5
2.4 V
0
Fig. 7.
0
0.5
1
1.5
VDS (V)
2
Output characteristics; drain current as a
Fig. 8.
function of drain-source voltage; typical values
PSMN4R0-30YLD
Product data sheet
0
0
2
6
8
10
12
14
VGS (V)
16
Drain-source on-state resistance as a function
of gate-source voltage; typical values
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N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
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ID
(A)
003aal033
50
003aal036
20
RDSon
40
16
30
12
20
8
2.8 V
3V
3.5 V
4.5 V
10
4
150°C
0
Fig. 9.
0
0.5
1
1.5
2
2.5
3
3.5
VGS (V)
0
4
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
0
20
40
60
80
ID (A)
100
Fig. 10. Drain-source on-state resistance as a function
of drain current; typical values
003aal037
2
a
10 V
Tj = 25°C
VDS
10 V
1.6
ID
VGS(pl)
1.2
VGS(th)
VGS = 4.5 V
0.8
VGS
QGS1
QGS2
QGS
0.4
QGD
QG(tot)
003aaa508
0
-60
-30
0
30
60
90
120 150
Tj (°C)
180
Fig. 12. Gate charge waveform definitions
Fig. 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN4R0-30YLD
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N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
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VGS
(V)
003aal038
10
003aal039
104
C
(pF)
8
Ciss
103
Coss
6
24 V
15 V
4
102
VDS = 6 V
Crss
2
0
0
5
10
15
20
QG (nC)
Fig. 13. Gate-source voltage as a function of gate
charge; typical values
IS
(A)
10
10-1
25
1
10
VDS (V)
Fig. 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aal160
003aal040
102
102
ID
(A)
trr
10
ta
tb
0
1
0.25 IRM
IRM
150°C
10-1
Tj = 25°C
0
0.2
0.4
0.6
0.8
1
VSD (V)
Fig. 15. Source current as a function of source-drain
voltage; typical values
PSMN4R0-30YLD
Product data sheet
t (s)
1.2
Fig. 16. Reverse recovery timing definition
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PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
11. Package outline
Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads
E
A2
A
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w
b
A
X
c
1/2 e
A
(A3)
A1
C
q
L
detail X
0
y C
θ
5 mm
8°
scale
0°
Dimensions (mm are the original dimensions)
Unit(1)
mm
A
A1
A2
A3
b
b2
max 1.20 0.15 1.10
0.50 4.41
nom
0.25
min 1.01 0.00 0.95
0.35 3.62
c
c2
D(1) D1(1) E(1) E1(1)
b3
b4
2.2
0.9
0.25 0.30 4.10 4.20
5.0
3.3
2.0
0.7
0.19 0.24 3.80
4.8
3.1
e
1.27
H
L
L1
L2
6.2
0.85
1.3
1.3
5.8
0.40
0.8
0.8
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
Outline
version
SOT669
References
IEC
JEDEC
JEITA
w
y
0.25
0.1
sot669_po
European
projection
Issue date
11-03-25
13-02-27
MO-235
Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669)
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PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
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punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
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changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
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PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN4R0-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
10 October 2013
© NXP N.V. 2013. All rights reserved
12 / 13
PSMN4R0-30YLD
NXP Semiconductors
N-channel 30 V, 4.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
13. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 2
8
Limiting values .......................................................3
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 5
11
Package outline ................................................... 10
12
12.1
12.2
12.3
12.4
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
© NXP N.V. 2013. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 October 2013
PSMN4R0-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
10 October 2013
© NXP N.V. 2013. All rights reserved
13 / 13