2ED020I06-FI

Datasheet, April 2010
2ED020I06-FI
Dual IGBT Driver IC
April 2010
Power Managment & Drives
N e v e r
s t o p
t h i n k i n g .
2ED020I06-FI
Revision History: 2010-04-20 Datasheet
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Edition 2010-04-20
Published by Infineon Technologies AG,
Am Campeon 1-12,
D-85579 Neubiberg
© Infineon 2007.
All Rights Reserved.
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2ED020I06-FI
Dual IGBT Driver IC
2ED020I06-FI
Product Highlights
•
•
•
•
•
•
Fully opera tional to ±650V
Power supply operating range from 14 to 18 V
Gate drive currents of +1 A / –2 A
Matched propagation delay for both channels
High dV/dt immunity
Low power consumption
PG-DS O-18-2
Features
•
•
•
•
•
•
•
•
Floating high side driver
Undervoltage lockout for both channels
3.3 V and 5 V TTL compatible inputs
CMOS Schmitt-triggered inputs with pull-down
Non-inverting inputs
Interlocking inputs
Dedicated shutdown input with pull-up
RoHS compliant
Type
Ordering Code
Package
2ED020I06-FI
Datasheet
PG-DSO-18-2
3
Packaging
Tape&Reel
April 2010
High and Low Side Driver
2ED020I06-FI
Overview
1
Overview
The 2ED020I06-FI is a high voltage, high speed power MOSFET and IGBT driver with
interlocking high and low side referenced outputs. The floating high side driver may be supplied
directly or by means of a bootstrap diode and capacitor. In addition to the logic input of each
driver the 2ED020I06-FI is equipped with a dedicated shutdown input. All logic inputs are
compatible with 3.3 V and 5 V TTL. The output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. Propagation delays are matched to simplify use
in high frequency applications. Both drivers are designed to drive an N-channel power MOSFET
or IGBT which operate up to 650V.
Datasheet
4
April 2010
High and Low Side Driver
2ED020I06-FI
Pin Configuration and Functionality
2
Pin Configuration and Functionality
2.1
Pin Configuration
GNDH
InL
OutH
SD
VSH
2ED020I06-FI
InH
GND
GND
GND
GND
NC
GNDH
NC
VSL
GND
OutL
GND
GNDL
P-DSO-18-2 (300mil)
Figure 1
2.2
Pin Configuration (top view)
Pin Definitions and Functions
Pin
Symbol
Function
1
InH
Logic input for high side driver
2
InL
Logic input for low side driver
3
SD
Logic input for shutdown of both drivers
4
GND
Common ground
5
GND
Connect to GND
6
GND
Connect to GND
7
GND
Connect to GND
8
Table 1
Datasheet
n.c.
Do not connect, Pin must stay open
Pin Description
5
April 2010
High and Low Side Driver
2ED020I06-FI
Pin Configuration and Functionality
Pin
Symbol
Function
9
GND
Connect to GND
10
GND
Connect to GND
11
GNDL
Low side power ground 1)
12
OutL
Low side gate driver output
13
VSL
Low side supply voltage
14
n.c.
(not connected)
15
n.e.
(not existing)
16
n.e.
(not existing)
17
GNDH
High side (power) ground
18
VSH
High side supply voltage
19
OutH
High side gate driver output
20
Table 1
1)
GNDH
High side (power) ground
Pin Description (cont’d)
Please note : GNDL has to be connected directly to GND
Datasheet
6
April 2010
High and Low Side Driver
2ED020I06-FI
Block Diagram
3
Block Diagram
High Side
InH
Voltage
Supply
UVLO
HS
RX
Logic
VSH
OutH
InL
GNDH
CLT
VSL
+5V
TX
SD
Input
Logic
OutL
UVLO
LS
GNDL
Voltage
Supply
GND
2ED020I06-FI
Low Side
Figure 2
Datasheet
Block Diagram
7
April 2010
High and Low Side Driver
2ED020I06-FI
Functional Description
4
Functional Description
4.1
Power Supply
The power supply of both sides, “VSL” and “VSH”, is monitored by an undervoltage lockout
block (UVLO) which enables operation of the corresponding side when the supply voltage
reaches the “on” threshold. Afterwards the internal voltage reference and the biasing circuit are
enabled. When the supply voltage (VSL, VSH) drops below the “off” threshold, the circuit is
disabled.
4.2
Logic Inputs
The logic inputs InH, InL and SD are fed into Schmitt-Triggers with thresholds compatible to
3.3V and 5V TTL. When SD is enabled (low), InH and InL are disabled. If InH is high (while InL
is low), OutH is enabled and vice versa. However, if both signals are high, they are internally
disabled until one of them gets low again. This is due to the interlocking logic of the device. See
Figure 3 (section 4.7).
4.3
Gate Driver
2ED020I06-FI features two hard-switching gate drivers with N-channel output stages capable to
source 1A and to sink 2A peak current. Both drivers are equipped with active-low-clamping
capability. Furthermore, they feature a large ground bounce ruggedness in order to compensate
ground bounces caused by a turn-off of the driven IGBT.
4.4
Coreless Transformer (CLT)
In order to enable signal transmission across the isolation barrier between low-side and high-side
driver, a transformer based on CLT-Technology is employed. Signals, that are to be transmitted,
are specially encoded by the transmitter and correspondingly restored by the receiver. In this way
EMI due to variations of GNDH (dVGNDH/dt) or the magnetic flux density (dΗ/dt) can be
suppresed.To compensate the additional propagation delay of transmitter, level shifter and
receiver, a dedicated propagation delay is introduced into the low-side driver.
Datasheet
8
April 2010
High and Low Side Driver
2ED020I06-FI
Functional Description
4.5
Diagrams
InH
InL
/SD
OutH
OutL
Figure 3
Datasheet
Input/Output Timing Diagram
9
April 2010
High and Low Side Driver
2ED020I06-FI
Electrical Parameters
5
Electrical Parameters
5.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead
to destruction of the integrated circuit. Unless otherwise noted all parameters refer to
GND.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
High side ground
GNDH
– 650
650
V
High side supply voltage
VSH
– 0.3
20
V
1)
High side gate driver output
OutH
– 0.3
VSH + 0.3
V
1)
Low side ground
GNDL
– 0.3
5.3
V
Low side supply voltage
VSL
– 0.3
20
V
2)
Low side gate driver output
OutL
– 0.3
VSL + 0.3
V
3)
Logic input voltages
(InH, InL, SD)
VIN
– 0.3
5.3
V
High side ground, voltage
transient
dVGNDH /dt – 50
50
V/ns
ESD Capability
VESD
—
2
kV
Human
Body Model
Package power disipation @TA PD
= 25°C
—
1.4
W
5)
Thermal resistance (both chips RTHJA
active), junction to ambient
—
90
K/W
6)
Thermal resistance (high side
chip), junction to ambient
RTHJA(HS)
—
110
K/W
6)
Thermal resistance (low side
chip), junction to ambient
RTHJA(LS)
—
110
K/W
6)
Junction temperature
TJ
—
150
°C
Storage temperature
TS
150
°C
– 55
1)
With reference to high side ground GNDH.
2)
With respect to both GND and GNDL.
3)
With respect to GNDL.
4)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor).
5)
Considering Rth(both chips active)=90K/W
Datasheet
10
4)
April 2010
High and Low Side Driver
2ED020I06-FI
Electrical Parameters
6)
Device soldered to reference PCB without cooling area
5.2
Operating Range
Note: Within the operating range the IC operates as described in the functional
description.Unless otherwise noted all parameters refer to GND.
Parameter
Symbol
min.
max.
High side ground
GNDH
– 650
650
V
High side supply voltage
VSH
14
18
V
1)
Low side supply voltage
VSL
14
18
V
2)
Logic input voltages
(InH, InL, SD)
VIN
0
5
V
Junction temperature
TJ
– 40
105
°C
Industrial
applications,
useful lifetime
87600h
Junction temperature
TJ
– 40
125
°C
Other
applications,
useful lifetime
15000h
1)
With reference to high side ground GNDH.
2)
With respect to both GND and GNDL.
5.3
Limit Values
Unit
Remarks
Electrical Characteristics
Note: The electrical characteristics involve the spread of values for the supply voltages, load and
junction temperature given below. Typical values represent the median values, which are
related to production processes. Unless otherwise noted all voltages are given with
respect to ground (GND). VSL = VSH – GNDH = 15 V, CL = 1 nF, TA = 25 °C. Positive
currents are assumed to be flowing into pins.
Voltage Supply
Parameter
Symbol
High side
leakage current
IGNDH
Limit Values
min.
Datasheet
—
typ
0
11
Unit
Test Condition
µA
GNDH = 1.2 kV
GNDL = 0 V
max.
—
April 2010
High and Low Side Driver
2ED020I06-FI
Electrical Parameters
Voltage Supply (cont’d)
Parameter
Symbol
Limit Values
Unit
Test Condition
3.2
mA
VSH = 15 V1)
2.3
3.2
mA
VSH = 15 V1)
TJ = 125 °C
min.
typ
max.
—
2.4
—
High side quiescent supply IVSH
current
High side undervoltage
lockout, upper threshold
VVSH1)
10.9
12.2
13.5
V
High side undervoltage
lockout, lower threshold
VVSH1)
—
11.2
—
V
High side undervoltage
lockout hysteresis
∆VVSH
0.7
Low side quiescent supply IVSL
current
—
1
1.3
V
3.9
5.0
mA
VSL = 15 V
3.9
5.5
mA
VSL = 15 V
TJ = 125 °C
Low side undervoltage
lockout, upper threshold
VVSL
10.7
12
13.3
V
Low side undervoltage
lockout, lower threshold
VVSL
—
11
—
V
Low side undervoltage
lockout hysteresis
∆VVSL
1)
0.7
1
1.3
V
With reference to high side ground GNDH.
Logic Inputs
Parameter
Symbol
Limit Values
min.
typ
Test Condition
Logic “1” input voltages
(InH, InL, SD)
VIN
Logic “0” input voltages
(InH, InL, SD)
VIN
—
—
0.8
V
Logic “1” input currents
(InH, InL)
IIN
—
40
55
µA
VIN = 5 V
Logic “0” input currents
(InH, InL)
IIN
—
µA
VIN = 0 V
Datasheet
2
Unit
max.
—
0
12
—
—
V
April 2010
High and Low Side Driver
2ED020I06-FI
Electrical Parameters
Logic Inputs (cont’d)
Parameter
Symbol
Limit Values
min.
Logic “1” input currents
(SD)
IIN
Logic “0” input currents
(SD)
IIN
—
typ
0
–60
Unit
Test Condition
—
µA
VIN = 5 V
—
µA
VIN = 0 V
Unit
Test Condition
max.
–40
Gate Drivers
Parameter
Symbol
Limit Values
min.
typ
max.
High side high level output VVSH –
voltage
VOutH
—
1.4
1.7
V
IOutH = –1mA
VInH = 5V
High side low level output VOutH1)
voltage
—
—
0.1
V
IOutH = 1mA
VInH = 0V
Low side high level output VVSL –
voltage
VOutL
—
1.4
1.7
V
IOutL = –1mA
VInL = 5V
Low side low level output VOutL
voltage
—
—
0.1
V
IOutL = 1mA
VInL = 0V
Output high peak current
(OutL, OutH)
IOut
—
—
–1
A
VIN = 5 V
VOut = 0 V
Output low peak current
(OutL, OutH)
IOut
High side active low
clamping
VOutH1)
Low side active low
clamping
1)
VOutL
2
—
—
A
VIN = 0 V
VOut = 15 V
—
2.6
3
V
InH =0V, VSH open
IOutH =200mA
—
2.7
3.2
V
InH =0V, VSH open
IOutH =200mA
TJ = 125 °C
—
2.6
3
V
InL =0V, VSL open
IOutL =200mA
—
2.7
3.2
V
InL =0V, VSL open
IOutL =200mA
TJ = 125 °C
With reference to high side ground GNDH.
Datasheet
13
April 2010
High and Low Side Driver
2ED020I06-FI
Electrical Parameters
Dynamic Characteristics
Parameter
Symbol
Limit Values
Unit
Test Condition
105
ns
GNDH = 0 V
20% Vout
95
120
ns
GNDH = 0 V
20% Vout
TJ = 125 °C
—
85
115
ns
80% Vout
—
100
130
ns
80% Vout
TJ = 125 °C
—
85
115
ns
80% Vout
—
100
130
ns
80% Vout
TJ = 125 °C
—
20
40
ns
20% to 80% Vout
—
30
50
ns
20% to 80% Vout
TJ = 125 °C
—
20
35
ns
80% to 20% Vout
—
25
40
ns
80% to 20% Vout
TJ = 125 °C
—
15
25
ns
TJ = 25°C
see Figure 6
—
15
30
ns
TJ = 125°C
see Figure 6
—
50
75
ns
1)
—
55
80
ns
1)
min.
Turn-on propagation delay tON
Turn-off propagation delay tOFF
Shutdown propagation
delay
tSD
Turn-on rise time
tr
Turn-off fall time
Delay mismatch (high &
low side turn-on/off)
Minimum turn-on input
(InH, InL) pulse width
Minimum turn-off input
(InH, InL) pulse width
1)
tf
∆t
tpON
tpOFF
typ
max.
—
85
—
—
50
75
ns
1)
—
55
80
ns
1)
TJ = 125°C
TJ = 125 °C
InH-Pulses shorter than the “minimum turn-on(off) input pulse width” are prolonged to 50ns (See Figure 7). InL-Input
doesn´t have this feature.
Datasheet
14
April 2010
High and Low Side Driver
2ED020I06-FI
Package Outline
6
Package Outline
Note: dimensions are given in mm.
6.1
Soldering Profile
The soldering profile qualified for 2ED020I06-FI (according to the standard IPC/JEDEC J-STD020C) is moisture sensitivity level 3. The peak reflow temperature for its package (volume < 350
mm3) is 260 +0/-5 °C.
Datasheet
15
April 2010
High and Low Side Driver
2ED020I06-FI
Diagrams
7
Diagrams
InH/L
2V
0.8V
tr
tOFF
80%
80%
OutH/L
20%
20%
tf
tON
Figure 4
Switching Time Waveform Definition
/SD
0.8V
tSD
80%
OutH/L
Figure 5
Datasheet
Shutdown Waveform Definition
16
April 2010
High and Low Side Driver
2ED020I06-FI
Diagrams
InL
2V
2V
0.8V
0.8V
InH
OutL
80%
80%
20%
20%
OutH
tOFFH
tOFFL
tONH
tONL
∆t = max (|tONH - tOFFL| , |tOFFH - tONL|)
Figure 6
Delay Matching Waveform Definitions
InH
OutH
50ns
50ns
Figure 7
Datasheet
Short InH-Pulses Prolongation
17
April 2010
High and Low Side Driver
2ED020I06-FI
Application Advices
8
Application Advices
8.1
Power Supply
a) The connection of a capacitor (>10nF) as close as possible to the supply pins VSH, VSL is
recommended for avoiding that possible oscillations in the supply voltage can cause erroneous
operation of the output driver stage. Total value of capacitance connected to the supply terminals
has to be determined by taking into account gatecharge, peak current, supply voltage and kind of
power supply.
b) If a bootstrap power supply for the high side driver is applied, a resistor of 10Ω minimum in
series with the bootstrap diode is required.
Datasheet
18
April 2010
High and Low Side Driver
2ED020I06-FI
Application Advices
Datasheet
19
April 2010
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