Data Sheet

UBA20260
600 V driver IC for step dimmable CFLs
Rev. 2 — 10 October 2011
Product data sheet
1. General description
The UBA20260 is a high-voltage integrated circuit designed to control high power
self-ballasted Compact Fluorescent Lamp (CFL) lighting applications. The UBA20260 is a
controller circuit with advanced features for step dimming and a lamp current controlled
boost feature for boosting cold (amalgam) CFLs.
The controller contains a half-bridge drive function for CFLs, a high-voltage level-shift
circuit with integrated bootstrap diode, an oscillator function, a current control function for
preheat and burn, a timer function and protection circuits. The UBA20260 is supplied
using the dV/dt current charge supply circuit from the half-bridge circuit.
Remark: The mains voltages given in this data sheet are AC voltages.
2. Features and benefits
2.1 Half-bridge features
 Integrated high-voltage level-shift function with integrated bootstrap diode
2.2 Preheat and ignition features




Coil saturation protection during ignition
Adjustable preheat time
Adjustable preheat current
Ignition lamp current detection
2.3 Lamp boost features
 Adjustable boost timing
 Fixed boost current ratio of 1.5
 Gradually boost to burn transition timing
UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
2.4 Dim features
 4-level step dimming adjustment using a standard on/off mains switch
 Adjustable memory retention time for step dimming
 Adjustable minimum dimming level
2.5 Protection





OverTemperature Protection (OTP)
Capacitive Mode Protection (CMP)
OverPower Protection (OPP)
OverCurrent Protection (OCP) in both boost and burn states
Power-down function
2.6 Other features
 Current controlled operation in both boost and burn state
 External power-down function
3. Applications
 Step-dimmable compact fluorescent lamps above 20 W and for universal mains
voltages
4. Ordering information
Table 1.
Ordering information
Type number
UBA20260T/N1
UBA20260
Product data sheet
Package
Name
Description
Version
SO16
Plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
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SUPPLY
REFERENCE
VOLTAGES
DIVIDE BY 2
LOGIC
14 FS
15 HBO
TEMPERATURE
SENSOR
160° 120° 80°
5 V DIGITAL MEMORY
5 V DIGITAL
16 GHS
HS driver
LEVEL
SHIFTER
DRIVER
LOGIC
LS driver
2 GLS
1 SLS
5 V ANALOG
CAPACITIVE MODE DETECTOR
STATE LOGIC
+
-
VDD(stop)
+
-
Vth(capm)SLS
RESET
+
-
STEP
DIMMER
LOGIC
6 μA
LOGIC
+
Vph(SLS)
INDUCTOR SATURATION/
OVERCURRENT DETECTOR
+
-
1 μA
PREHEAT CURRENT SENSOR
LOGIC
COUNTER
5V
CB 12
RESET STATE
START-UP STATE
PREHEAT STATE
IGNITION STATE
HOLD STATE
BOOST STATE
BURN STATE
POWER-DOWN STATE
+
25 μA
Vth(ocp)SLS
LOGIC
60 μA
IGNITION CURRENT DETECTOR
+
SGND 13
Vth(det)ign(CSI)
3 PGND
4
VOLTAGE
CONTROLLED OSCILLATOR
1.27 V
+
-
+ -
LOGIC
BOOST
AMPLIFIER
FREQUENCY
CONTROL
QA
QB
STEP DIM LEVEL SELECT
VMDL
VDIM_3
VDIM_2
OTA
VDIM_1
+
-
LAMP
CURRENT
SENSOR
V
3 of 30
© NXP B.V. 2011. All rights reserved.
25 μA
Vclamp(CSI)
10 n.c.
DSR
5
6
8
9
7
RREF
CF
CI
CSI
MDL
001aam761
Fig 1.
Block diagram
UBA20260
I
∆Vdim3(CSI)
REFERENCE
CURRENT
600 V driver IC for step dimmable CFLs
2
∆Vdim2(CSI)
Rev. 2 — 10 October 2011
All information provided in this document is subject to legal disclaimers.
CP 11
PREHEAT/
BOOST TIMER
NXP Semiconductors
BOOTSTRAP
5. Block diagram
UBA20260
Product data sheet
VDD
4
UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
6. Pinning information
6.1 Pinning
SLS
1
16 GHS
GLS
2
15 HBO
PGND
3
14 FS
VDD
4
13 SGND
UBA20260
RREF
5
12 CB
CF
6
11 CP
MDL
7
10 n.c.
CI
8
9
CSI
001aam762
Fig 2.
Pin configuration (SOT109-1)
6.2 Pin description
Table 2.
UBA20260
Product data sheet
Pin description
Symbol
Pin
Description
SLS
1
source low-side switch input
GLS
2
low-side gate driver output
PGND
3
power ground
VDD
4
low voltage supply
RREF
5
internal reference current input
CF
6
voltage controlled oscillator capacitor
MDL
7
minimum dimming level input
CI
8
voltage controlled oscillator input integrating capacitor
CSI
9
current feedback sense input
n.c.
10
not connected
CP
11
preheat timing capacitor
CB
12
boost timing capacitor
SGND
13
signal ground
FS
14
floating supply voltage
HBO
15
half-bridge output
GHS
16
high-side gate driver output
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UBA20260
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600 V driver IC for step dimmable CFLs
7. Functional description
7.1 Supply voltage
The UBA20260 is an IC for driving external half-bridge MOSFETs in self-ballasted
high-power CFLs. The UBA20260 has no dimming control input but instead, four preset
fixed dimming levels. Only minor adjustment of the presets is possible.
The UBA20260 is rated for a maximum continuous rectified mains voltage of 500 V (with
peak 600 V). The UBA20260 includes all functions necessary for preheat, ignition and
boost operation of the lamp. In addition, the IC includes the four-step dimming feature and
several protective features to safeguard CFL operation. The controller states are shown in
Figure 3.
VDD = 0
RESET STATE
VDD < VDD(rst)
HOLD = 0
VDD > VDD(rst)
VDD < VDD(rst)
START-UP STATE
POWER-DOWN STATE
VCP < Vth(rel)CP
(1)
PREHEAT STATE
(2)
HOLD STATE
(3)
HOLD = 1
preheat time
completed
IGNITION STATE
(4)
Ignition_Detected
VDD < VDD(stop)
BOOST AND BURN
STATES
(5)
001aam763
(1) VDD < VDD(start) and (HOLD = 0 OR VCP < Vth(rel)CP).
(2) VDD < VDD(stop).
(3) (End of ignition time AND HOLD = 0) OR VDD < VDD(stop).
(4) End of ignition time AND HOLD = 1
(5) VCP < Vth(pd)CP, OR overcurrent fault time > 1⁄10 tph OR fbridge(max) detected in capacitive mode.
Fig 3.
State diagram
UBA20260
Product data sheet
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UBA20260
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600 V driver IC for step dimmable CFLs
7.2 Lamp start-up cycle
7.2.1 Reset state
The UBA20260 is in the reset state when the supply voltage on the VDD pin is below the
VDD(rst) level. In the reset state, part of the internal supply is turned off and all registers,
counters and timers are undefined. The hold state latch is reset and both the external high
and low side power transistors (Q1/Q2) are non-conductive.
During power-up, the low voltage supply capacitor on the VDD pin is charged through the
external start-up resistor. The start-up state is entered when the voltage on the VDD pin is
above the VDD(rst) level. The UBA20260 enters the reset state when the supply voltage on
the VDD pin drops below VDD(rst).
7.2.2 Start-up state
The start-up state is entered by charging the low voltage supply capacitor on the VDD pin
through the external start-up resistor. At start-up, the High-Side (HS) transistor is
non-conductive and the Low-Side (LS) transistor is conductive to enable charging of the
bootstrap capacitor. This capacitor supplies the HS driver and Level shifter circuit
connected between the FS and HBO pin. A DC reset circuit is integrated into the HS
driver. This circuit ensures that below the FS pin lockout voltage, the output voltage
VGHS  VHBO is zero.
When the start-up state is entered, the circuit only starts oscillating at fbridge(max) when the
low voltage supply (VDD) reaches the VDD(start) value. The circuit always starts oscillating
at fbridge(max). The circuit enters the preheat state as soon as the capacitor connected to
the CP pin is charged above the Vth(CP)max voltage level. To keep oscillating, VDD must be
above VDD(stop) and below the VDD(clamp) upper limit.
During the start-up state, the voltage on the CF pin is zero and on the CB pin is close to
zero. The voltage on the CP pin rises just above Vth(CP)max during the start-up state as
shown in Figure 9.
7.2.3 Preheat state
After starting at fbridge(max), the frequency decreases by charging capacitor CCI using an
output current circuit. The preheat current sensor circuit controls the current output circuit,
until the momentary value of the voltage across sense resistor RSLS reaches the fixed
preheat voltage level (SLS pin). At this level, the current of the preheat current sensor
reaches the charge and discharge balanced state on capacitor CCI to set the half-bridge
frequency.
The preheat time consists of eight saw-tooth pulses at the CP pin. The preheat time
begins as soon as the capacitor on the CP pin is charged above Vth(CP)max value. During
the preheat time, the current feedback sensor circuit (input CSI pin) is disabled.
To increase noise immunity, an internal filter of 30 ns is included at the SLS pin.
If the level on the VDD pin drops below VDD(stop) during preheat, the preheat state is
immediately stopped and the circuit enters the hold state. The hold state delays a new
preheat cycle by a fixed delay time. A fixed voltage drop on the preheat capacitor CCP and
the fixed discharge current on the CP pin are used to set the delay time.
UBA20260
Product data sheet
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UBA20260
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600 V driver IC for step dimmable CFLs
New preheat cycles start after the CP pin level slowly discharges until VCP < Vth(rel)CP and
recharges above Vth(CP)max provided VDD > VDD(start) (see Figure 5).
f
(kHz)
100
start frequency
CFL ignition
A
B
C
preheat frequency
100 %
boost bottom ~22 kHz
time (s)
preheat
ignition
boost
transition
burn
001aam764
Fig 4.
CFL frequency from start to burn state
7.2.4 Ignition state
After the preheat state has been completed, the ignition state is entered. In the ignition
state, the frequency sweeps down on the CI pin due to capacitor CCI charging at a fixed
current as shown in Figure 4. During this continuous decrease in frequency, the circuit
approaches the resonant frequency of the resonant tank (L2, C5). This action causes a
high voltage across the lamp to ignite the lamp. The ignition current sensor circuit which
monitors the voltage over resistor RCSI (see Figure 12) detects lamp ignition.
If the voltage on pin CSI is above the typical ignition detection threshold voltage level of
0.6 V, lamp ignition is detected. The system changes from ignition state to either the boost
or burn state.
If ignition not is detected, the frequency drops further to the minimum half-bridge
frequency fbridge(min) frequency. To avoid repeated ignition attempts and overheating of the
application due to lamp damage, the IC only tries to ignite the lamp twice after power-up.
The ignition attempt counter increments at the end of the ignition enabling time when the
lamp ignition threshold voltage on the CSI pin is not exceeded. The ignition enabling time
is typically 1⁄4 of the preheat time tph. If a second ignition attempt also exceeds the ignition
time-out period, the IC enters the power-down state (see Figure 5).
UBA20260
Product data sheet
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UBA20260
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600 V driver IC for step dimmable CFLs
voltage
(V)
5V
2nd failed
ignition
attempt
1st failed
ignition
attempt
VCP
Vth(CP)max
Vth(CP)min
discharge
to 0 V
Vth(rel)CP
startup
time
1st preheat
time
tph
HOLD STATE
2nd preheat
time
ten(ign)
td(restart)
tph
1st ignition
enabling time
restart
delay time
2nd
startup
POWER DOWN STATE
ten(ign)
2nd ignition
enabling time
0V
time (s)
001aan537
Fig 5.
Retry cycle
7.2.5 Boost state and transition to burn state
When ignition is detected, by measuring lamp current on the CSI pin, the circuit enters the
boost state. Figure 7 shows the boost and burn state in more detail. In the boost state, the
nominal burn state lamp current can be increased with a fixed boost ratio of 1.5. This ratio
boosts the slow luminescence increase of a cold amalgam CFL lamp, provided the IC is in
the DIM_1 mode. If the IC is at a temperature (Tj(bp)bst) before entering the boost state, the
burn state is bypassed.
A boost timing circuit is included to determine the boost time and transition to burn time.
The circuit consists of a clock generator comprising CCB, Rext(RREF) and a 64-step counter.
When the timer is not operating, CCB is discharged below the Vth(CB)min level of 1.1 V. This
voltage, about 0.6 V, is still higher than the level at which the comparator on CCB detects if
the CB pin is shorted to ground.
The boost time consists of 63 saw-tooth pulses on the CB pin, automatically followed by
the transition time at the CP pin. The 32 saw-tooth pulses form the transition time from
boost to burn and enables a smooth transition between the current controlled boost and
burn state. The total transition time is approximately four times the preheat time (see
Figure 6).
UBA20260
Product data sheet
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UBA20260
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600 V driver IC for step dimmable CFLs
voltage
(V)
5V
VCP
Vth(CP)max 4.5 V
1
32
Vth(CP)min 3.8 V
Vth(CB)max 3.6 V
VCB
Vth(CB)min 1.1 V
1
2
61
62
63
0.6 V
ignition
boost
0V
transition
burn
time (s)
001aam765
Fig 6.
Boost timing
In the boost state, a lamp current feedback control is implemented to improve lamp
stability (see Section 7.2.6). The lamp current has a fixed ratio of 1.5 compared to the
burn state to boost the slow luminescence increase of a cold CFL lamp. In the boost to
burn transition time, there is a slow 15-step ratio decrease from 1.5 down to 1. The
preheat timer is reused for the transition to burn time and the boost ratio is gradually
decreased in 15 steps from 1.5 to 1, within 32 saw-tooth pulses on the CP pin. Using the
application values for CCB and Rext(RREF), a boost time of more than 300 s is possible. In
addition to boost bypass at a temperature of Tj(bp)bst ( 80 C), a temperature protection
function is implemented during boost state of Tj(end)bst ( 120 C). If the temperature
passes this level during boost, the transition timer is immediately started to enter the burn
state faster. Effectively this reduces the boost time (see Figure 4 [B]).
The boost state current boost does not start in dim modes DIM_2, DIM_3 or MDL;
see Figure 4[A].
Remark: If the CB pin is short circuited to ground, the boost function is disabled. In such a
situation, the bottom frequency fbridge(min) is 1.8 times higher than the boost bottom
frequency fbridge(bst)min.
7.2.6 Burn state
After the boost state or when it is bypassed, the burn state starts. The lamp current sensor
circuit remains enabled (see Figure 4[A]). The CSI (Current Sense Input) pin measures
the voltage across sense resistor RCSI. It is then passed through a Double-Sided Rectifier
(DSR) circuit and fed towards an Operational Transconductor Amplifier (OTA).
When the RMS voltage on the CSI pin reaches the actual internal reference level, the
lamp current sensor circuit takes over control of the lamp current. The internal current
output of the OTA is transferred using an integrator on the CI pin to the input for Voltage
Controlled Oscillator (VCO). The VCO regulates the frequency and as a result, the lamp
current.
UBA20260
Product data sheet
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UBA20260
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600 V driver IC for step dimmable CFLs
BOOST AND BURN
STATES
Temp < Tj(bp)bst AND
NOT Boost_Disable
00
burn select
Dim_1 state AND Boost
boost timer running
01
boost
Boost_ratio = 1
Boost_ratio = 1.5
NOT (Boost OR Boost transition)
Temp < Tj(otp) - Tj(otp)(hys)
Temp > Tj(bp)(bst) OR
Boost_Disable
Vi(CSI) = Votp(CSI)
(66 % level)
Vi(CSI) = Vdamp(CSI)
(100 % level)
Temp > Tj(end)bst
OR boost timer ended
Temp > Tj(otp)
10
burn
Fig 7.
11
boost transition
boost_transition timer ended
OR temp > Tj(otp)
001aam767
Boost and burn state machine
7.2.7 Hold state
The hold state is a special state that reduces lamp flicker at deep dim levels, on or near
dim and ignition threshold levels. The IC enters the hold state after an ignition failure or
when the low supply voltage VDD drops below VDD(stop) in the ignition or preheat states
(see Figure 3).
A repeated drop in supply voltage below VDD(stop) in preheat or ignition states, does not
increment the ignition attempt counter. The hold state is entered, delaying a new preheat
cycle with the same time delay/mechanism by the hold state retention time as shown in
Figure 5.
When CP is below Vth(rel)CP, the IC is released from the hold state and moves to the
start-up state as shown in Figure 3. Alternatively, the hold state ends when the supply
voltage drops below VDD(rst) and the IC is reset.
With a 470 nF capacitor on the CP pin, the typical hold state retention delay is between
1 s and 1.7 s. This delay is dependent on where the preheat cycle was cut-off on the rising
or falling edge of the preheat timing. The retention time for a failed ignition always starts
from the top of the rising edge on the CP pin (see Figure 5).
In the hold state, a hold state latch is set (hold state latch = 1) and the oscillator is
stopped. In addition, the HS transistor is non-conductive and the LS transistor is
conducting.
The voltage on the VDD pin alternates between VDD(start) and VDD(stop) until the voltage on
the CP pin reaches Vth(rel)CP (see Figure 5). The alternating supply voltage is caused by
the current drawn by the IC supply pin VDD. The supply current is less than 220 A, when
UBA20260
Product data sheet
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UBA20260
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600 V driver IC for step dimmable CFLs
the supply voltage VDD rises between VDD(stop) and VDD(start). Typically, the supply current
is 2 mA when VDD falls between VDD(start) and VDD(stop). More current is drawn during the
fall in VDD because the internal analog supply is turned on when VDD > VDD(start). This
function enables the comparators to monitor the voltage on the CP pin and if the supply
voltage VDD falls below VDD(stop).
7.3 Oscillation and timing
7.3.1 Oscillator control
The internal oscillator is a VCO which generates a saw-tooth waveform between the
Vth(CF)max level and 0 V. Capacitor CCF, resistor Rext(RREF) and the voltage on the CI pin
determine the saw-tooth frequency. Rext(RREF) and CCF determine the minimum and
maximum switching frequencies. Their ratio is internally fixed. Two ratios are available,
the ratio between fbridge(max) and fbridge(min) is 2.5 and the ratio between fbridge(max) and
fbridge(bst)min is 4.6. The saw-tooth frequency is twice the half-bridge frequency.
Transistors HS (Q1) and LS (Q2) are switched to conducting at a duty cycle of
approximately 50 %. An overview of the oscillator signal and driver signals is shown in
Figure 8. The oscillator starts oscillating at fbridge(max). The non-overlap time between the
gate driver signals VGLS and VGHS is tno.
voltage
(V)
VCF
0
tdch
V(GHS-HBO)
0
VGLS
tno
tno
0
VHBO
0
time (s)
001aam766
Fig 8.
UBA20260
Product data sheet
Saw-tooth, gate driver and half-bridge output signals
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600 V driver IC for step dimmable CFLs
7.3.2 Combined timing circuit
A combined timing circuit is used to determine the preheat time, ignition enabling time and
overcurrent time (see Figure 9). CCP, Rext(RREF) and the counter comprise the clock
generator circuit. When the timer is not running, CCP is charged to 5 V. The timing circuit
starts operating after the start-up state when the VDD supply voltage has reached VDD(start)
and the voltage on the CP pin passes Vth(CP)max. The preheat time consists of eight
saw-tooth pulses on the CP pin as shown in Figure 9.
The maximum ignition enabling time after the preheat phase is two complete saw-tooth
pulses. During the boost and burn state, part of the timer is used to generate the
maximum overcurrent time (more than one half of the saw-tooth pulse). If a continuous
overcurrent is detected, the timer starts.
voltage
(V)
ignition
enabling time
5V
VCP
Vth(CP)max
4.5 V
Vth(CP)min
3.8 V
CFL ignition overcurrent
ignition
time
startup
time
preheat time
0V
fault time
boost-burn
power down
time (s)
001aam768
Fig 9.
Timing diagram for preheat, ignition and overcurrent
7.4 Step dimming
The UBA20260 uses the step dimming method of dimming a lamp load. This method
enables the lamp to operate in four different light output level modes including full power.
The four different dim level modes can be selected by toggling the supply voltage which is
made possible by toggling the mains voltage switch.
To change the dim step, the low supply voltage must be above VDD(start). In addition, the
voltage must drop below VDD(rst), irrespective of whether the IC is in the preheat, ignition,
boost or burn states (see Figure 10).
The discharge time of capacitor CCP (while the VDD power supply is off) sets step memory
retention time. When the voltage on the CP pin drops below Vret(dim)CP (2 V typical), the
step memory is lost. The next time the supply is powered on, the lamp turns on at full
brightness. Using the default components, the retention time is  3 s. The retention time
calculation can be found in Section 11 on page 22.
UBA20260
Product data sheet
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UBA20260
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600 V driver IC for step dimmable CFLs
voltage
(V)
dim step
change
VDD(start)
VDD
VDD(stop)
lamp on
old dim level
lamp off
lamp on
new dim level
VDD(rst)
5
VCP
Vret(dim)CP
time (s)
0
retention
start-up
001aam769
Fig 10. Supply voltage cycle for dim step change
Four internal references determine the actual internal set point levels used for the different
step dim levels. Depending on the selected dim level, the current control feedback loop
regulates the voltage on the CSI pin. In this way, it ensures that Vi(CSI) is equal to one of
the selected internal set point voltages. The sequence of the four dim steps shown in
Figure 11 is as follows:
• The lamp is switched off longer than the memory retention time: the IC starts up in the
DIM_1 mode (lamp is 100 % on, no dimming)
• After lamp off/on toggling, the IC twice enters the DIM_2 mode: the lamp is dimmed to
approximately 66 % (1) of its initial light output
• The next lamp off/on toggling, the IC enters the DIM_3 mode: the lamp is dimmed
approximately 33 % (1) of its initial light output
• Toggling the lamp off/on again: the IC enters the MDL (Minimum Dimming Level)
mode. This level equals approximately 10 % (1) of the initial light output
• Renewed toggling enters the DIM_1 mode again.
Where (1) = RMDL = 2 k
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UBA20260
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600 V driver IC for step dimmable CFLs
Vi(CSI)
VRMS
1.2
1.0
Vclamp(CSI)
DIM_1
100 %
Internal clamp
0.8
VDD off-on toggle
0.6
VDD off-on toggle
DIM_2
0.4
∆Vdim2(CSI)
0.2
(1)
DIM_3
∆Vdim3(CSI)
Vi(CSI) = VMDL
(1)
MDL
0
(1) = VDD off-on toggle
001aam770
Fig 11. Voltage on pin CSI as function of dim step
As the internal step reference voltages are independent from the mains voltage, the lamp
current output is kept constant. Making the lamp current output not susceptible to line
voltage fluctuations. The MDL level sets the minimum lamp current level and is adjusted
using the MDL pin. An accurate minimum dimming voltage level is set using an internal
reference current and an external resistor RMDL. The internal reference current is derived
from the internal band gap reference circuit and resistor Rext(RREF). The other two step
dimming levels are set at a fixed voltage offset referenced to the adjusted MDL level. This
means that these levels shift by the same voltage as the MDL shifts. When the MDL level
is at the default level, the light output in DIM_2, DIM_3 and MDL modes is approximately
66 %, 33 % and 5 % from nominal.
7.5 Protection functions and Power-down mode
7.5.1 Coil saturation protection
CSP is integrated into the IC to allow the use of small CFL lamps and use of small coils.
Saturation of these coils is detected and excessive overcurrent due to saturation is
prevented. CSP is only enabled during the ignition state. A cycle-by-cycle control
mechanism is used to limit voltages and currents in the resonant circuit when there is no
or delayed ignition. It prevents coil saturation, limits high peak currents and the dissipation
in the half-bridge power transistors.
Coil saturation is detected by monitoring the voltage across the RSLS resistor. A trigger is
generated when this voltage exceeds the Vth(sat)SLS level. When saturation is detected, a
fixed current Io(sat)CF is injected into the CCF capacitor to shorten the half-bridge
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600 V driver IC for step dimmable CFLs
switching cycle. The injected current is maintained until the end of the switching cycle.
This action immediately increases the half-bridge switching frequency. Additionally, for
each successive cycle that coil saturation is detected, capacitor CCI discharges enabling
ignition time-out detection in the ignition state.
CSP is triggered when the voltage on the SLS pin exceeds Vth(sat)SLS (typically 2.5 V). The
voltage Vi(SLS) on the SLS pin is determined by the external resistor RSLS value and also
sets the preheat current.
7.5.2 Overcurrent protection
OCP is active in both the burn and boost states but not during boost transition.
Overcurrent is detected, when the peak voltage of the absolute value across the current
sense resistor connected to the SLS pin exceeds the OCP reference level Vth(ocp)SLS. A
current Io(CP) is then sunk from the capacitor connected to the CP pin for the next full
cycle.
If overcurrent is not present at the end of this cycle, the current is disabled. A current,
equal to Io(CP) is sourced to the CP pin instead. If overcurrent occurs in more than half the
number of cycles, a net discharging of the capacitor connected to the CP pin occurs.
When the voltage on the CP pin drops below Vth(CP)min, the IC enters Power-down mode.
During a continuous overcurrent condition, the overcurrent fault time of tfault(oc) takes
 1⁄9 tph after which the IC enters Power-down mode. The Vth(ocp)SLS level is the same as
the Vth(sat)SLS level during the ignition state.
7.5.3 Overpower protection
OPP is active in the boost and burn state. The lamp current is limited and regulated in all
dim step states to the internal dim step reference voltage levels. These reference voltage
levels are derived from an internal reference voltage. Consequently, supply voltage
fluctuations in the mains supply voltage during overvoltage situations do not affect these
reference voltage levels.
When the lamp is in the first dim mode (no dimming), the current is limited and regulated
to the nominal lamp current. In addition, in the boost state the first dim mode boosted by a
factor of 1.5.
7.5.4 Capacitive mode protection
CMP is active in the ignition, burn and boost states and during boost transition. The signal
across resistor RSLS also provides information about the half-bridge switching behavior.
When conditions are normal, the current flows from the LS transistor source to the
half-bridge when the LS transistor is switched on. This results in a negative voltage on the
SLS pin.
As the circuit yields to capacitive mode, the voltage becomes smaller and eventually
reverses polarity. CMP prevents this action by checking if the voltage on the SLS pin is
above the Vth(capm)SLS level.
If the voltage across resistor RSLS is above the Vth(capm)SLS threshold when the LS
transistor is switched on, the circuit recognizes it as capacitive mode. When capacitive
mode is detected, the currents from the OTA, which normally regulate the lamp current,
are disabled. Then the capacitive mode sink current Io(CI) is enabled.
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600 V driver IC for step dimmable CFLs
The capacitive mode sink current starts to discharge the capacitor/resistor circuitry on
the CI pin and as a result, gradually increases the half-bridge frequency. Discharging
continues for the remainder of the current switching cycle ensuring the total current on the
CI pin is equal to the sink current. If capacitive mode persists, the action is repeated until
capacitive mode is no longer detected. If capacitive mode is no longer detected, the OTA
takes over the regulation again.
If the conditions for capacitive mode persist, OTA regulates the system back to capacitive
mode and the protection takes over again. The system operates on the edge of capacitive
mode.
When in the boost and burn states, the half-bridge load is capacitive at higher
frequencies, CMP eventually drives the half-bridge to the maximum frequency fbridge(max).
This causes the IC to enter Power-down mode.
7.5.5 Overtemperature protection
The OTP circuit is designed to prevent the device from overheating in hazardous
environments. The circuit is triggered when the temperature exceeds the maximum
temperature value Tj(otp). OTP changes the lamp current to the level equal to the Votp(CSI)
level. This condition remains until the temperature decreases by  20 C = Tj(otp)hys. After
this decrease in temperature, the lamp current level returns to the nominal level.
7.5.6 Power-down mode
Power-down mode is entered when:
• The overcurrent time exceeds the maximum overcurrent fault time tfault(oc) or if the
overcurrent occurs in more than half the number of cycles when Vth(CP)min is reached
• If during boost or burn state, fbridge(max) is reached due to capacitive mode detection
• Two consecutive failed lamp ignition attempts
In Power-down mode, the oscillator is stopped, the HS transistor is non-conductive and
the LS transistor is conductive. The VDD supply is internally clamped. The circuit is
released from Power-down mode by lowering the low voltage supply below VDD(rst) (mains
switch reset).
An option is available which enables the IC to enter Power-down mode using external
logic. The external power-down option is only available when the IC is in the boost or burn
state. The CP pin is used to enable the external power-down option. When the CP pin is
connected using a 10 k resistor to the PGND pin or the SGND pin, VCP is pulled below
Vth(pd)CP. The IC then enters Power-down mode.
Remark: Do not connect the CP pin directly to pins PGND or SGND. Always connect in
series to pins PGND or SGND with a 10 k resistor. This action avoids the IC being not
starting up because of excessive currents flowing during the reset and start-up states.
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600 V driver IC for step dimmable CFLs
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
Rext(RREF)
external resistance on
pin RREF
Fixed nominal value 33 k
30
36
k
SR
slew rate
on pins HBO with respect to PGND
4
+4
V/ns
Tj
junction temperature
40
+150
C
Tamb
ambient temperature
40
+85
C
Tstg
storage temperature
55
+150
C
input current on pin CF
0
200
A
operating
-
500
V
during 1 s
-
600
V
with respect to HBO
0.3
+14
V
General
P = 0.8 W
Currents
Ii(CF)
Voltages
VHBO
voltage on pin HBO
VFS
voltage on pin FS
VDD
supply voltage
0.3
+14
V
Vi(CSI)
input voltage on pin CSI
5
+5
V
Vi(SLS)
input voltage on pin
SLS
6
+6
V
VCI
voltage on pin CI
0
3.5
V
VMDL
voltage on pin MDL
LPF used as input pin
0
5
V
electrostatic discharge
voltage
human body model:
2000
+2000
V
1000
+1000
V
500
+500
V
ESD
VESD
all pins, except pins 14, 15 and 16
pins 14, 15 and 16
charged device model:
all pins
[1]
Latch-up in accordance with SNW-FQ-303 on all pins.
9. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
in free air; SO16 package
100
K/W
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10. Characteristics
Table 5.
Characteristics
VDD = 13 V; VFS  VHBO = 13 V; Tamb = 25 C; settings according to default setting see Table 6 on page 25, all voltages
referenced to PGND and SGND, positive currents flow into the UBA20260, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD(rst)
reset supply voltage
HS = off; LS = on
5.7
6.2
6.7
V
VDD(stop)
stop supply voltage
9.6
10
10.4
V
VDD(start)
start supply voltage
11.9
12.4
12.9
V
VDD(hys)
hysteresis of supply voltage
start-stop
2.2
2.4
2.6
V
VDD(clamp)
clamp supply voltage
IDD(clamp) = 5 mA
13
13.4
13.8
V
IDD(clamp)
clamp supply current
VDD(clamp) = 14 V
20
30
-
mA
IDD(startup)
start-up supply current
VDD = 9 V
-
190
220
A
IDD(pd)
power-down supply current
VDD = 9 V
-
190
220
A
-
1.6
2
mA
-
-
30
A
2.7
3
3.3
V
-
80
-
mV
Start-up state
Pin VDD
IDD
supply current
default setting; VCI = VCI(clamp);
VCB = 0 V
[1]
High-voltage supply
Pins GHS, HBO and FS
Ileak
leakage current
500 V on high-voltage pins
Voltage controlled oscillator
Output pin CI
VCI(max)
maximum voltage on pin CI
Vhr(CI)
headroom voltage on pin CI
Vclamp(CI) = Vhr(CI) + VCI(max); burn
and boost state
fbridge(min)
minimum bridge frequency
CCF = 100 pF; VCI = Vclamp(CI);
VCB = 0 V
[2]
38
40
42
kHz
fbridge(max)
maximum bridge frequency
CCF = 100 pF; VCI = 0 V
[2]
88
100
112
kHz
[2]
Output pin CF
fbridge(bst)min
minimum boost bridge frequency
CCF = 100 pF; VCI = Vclamp(CI )
21
22
23
kHz
tno
non-overlap time
VHBO rising edge
1.3
1.5
1.7
s
VHBO falling edge
1.3
1.5
1.7
s
2.6
V
Vth(CF)max
maximum threshold voltage on pin
CF
CCF = 100 pF; VCI = Vclamp(CI);
VCB = 0 V
2.4
2.5
Io(bst)CF
boost output current on pin CF
VCF = 1.5 V; VCB = Vclamp(CI )
12.3
11.8 11.3 A
Io(CF)min
minimum output current on pin CF
VCF = 1.5 V; VCB = 0 V;
VCI = Vclamp(CI )
22.8
21.8 20.8 V
Io(CF)max
maximum output current on pin CF VCF = 1.5 V; VCB = 0 V
67
60
53
A
Gate driver output
Output pins GLS, GHS
Isource(drv)
driver source current
VG = 4 V (GLS or GHS);
VHBO = 0 V; VDD = VFS = 12 V
105
90
75
mA
Rsink(drv)
driver sink resistance
VG = 2 V (GLS or GHS);
VHBO = 0 V; VDD = VFS = 12 V
13
15.5
18

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Table 5.
Characteristics …continued
VDD = 13 V; VFS  VHBO = 13 V; Tamb = 25 C; settings according to default setting see Table 6 on page 25, all voltages
referenced to PGND and SGND, positive currents flow into the UBA20260, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
bootstrap diode; IFS = 5 mA;
(VF = VDD - VFS)
1.3
1.7
2.1
V
Boot strap diode
VF
forward voltage
Preheat current sensor
Input pin SLS
II(SLS)
input current on pin SLS
Vph(SLS)
preheat voltage on pin SLS
Vi(SLS) = 0.4 V
[3]
-
-
1
A
0.57
0.60
0.63
V
Output pin CI
Io(source)CI
source output current on pin CI
VCI = 2 V; Vi(SLS) < 0.6 V
10.6
9.6
8.6
A
Io(sink)CI
sink output current on pin CI
VCI = 2 V; Vi(SLS) < 0.6 V
26
29
32
A
Preheat timer, ignition timer, overcurrent timer function
tph
preheat time
CCP = 470 nF; Rext(RREF) = 33 k
-
0.93
-
s
ten(ign)
ignition enable time
CCP = 470 nF; Rext(RREF) = 33 k
-
0.22
-
s
tfault(oc)
overcurrent fault time
CCP = 470 nF; Rext(RREF) = 33 k;
initial voltage VCP = 5 V
-
0.1
-
s
tret(dim)
dimming retention time
CCP = 470 nF; Rext(RREF) = 33 k;
initial voltage VCP = 5 V
-
2.8
-
s
Io(CP)
output current on pin CP
VCP = 4 V; source (); sink (+)
5.5
5.9
6.3
A
Iret(dim)CP
dimming retention current on
pin CP
Current into pin CP; VDD = 0 V;
initial VCP = 5 V
-
0.5
-
A
Vth(CP)min
minimum threshold voltage on pin
CP
VCF = 0 V, VCI = 2 V
-
3.8
-
V
Vth(CP)max
maximum threshold voltage on
pin CP
VCF = 0 V, VCI = 2 V
-
4.5
-
V
Vhys(CP)
hysteresis voltage on pin CP
0.6
0.7
0.8
V
Ipu(CP)
pull-up current on pin CP
VCP = 3.8 V
-
60
-
A
Vret(dim)CP
dimming retention voltage on
pin CP
VDD = 0 V
-
2
-
V
Vth(pd)CP
power-down threshold voltage on
pin CP
burn state; 10 k connected in
series
-
1
-
V
Vth(rel)CP
release threshold voltage on pin CP hold state
-
2.7
-
V
Boost timer
Pin CB
tbst
boost time
CCB = 470 nF; Tj < 80 C
-
148
-
s
Io(CB)
output current on pin CB
VCB = 2.35 V; source (); sink (+)
0.8
1
1.2
A
Vth(CB)min
minimum threshold voltage on pin
CB
-
1.1
-
V
Vth(CB)max
maximum threshold voltage on pin
CB
-
3.6
-
V
Vhys(CB)
hysteresis voltage on pin CB
2.3
2.5
2.7
V
Tj(bp)bst
boost bypass junction temperature
Tj sensed at end of ignition time
65
80
95
C
Tj(end)bst
boost end junction temperature
Tj during boost time
105
120
135
C
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Table 5.
Characteristics …continued
VDD = 13 V; VFS  VHBO = 13 V; Tamb = 25 C; settings according to default setting see Table 6 on page 25, all voltages
referenced to PGND and SGND, positive currents flow into the UBA20260, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Idet(dis)bst
boost disable detection current
VCB = 0 V
30
25
20
A
tt(bst-burn)
transition time from boost to burn
CCP = 470 nF; Tj < 80 C
-
3.6
-
s
lamp current boost ratio
Vi(CSI) in boost state versus Vi(CSI) in
burn state; default start-up state
(no dimming)
1.4
1.5
1.6
V
Pin CSI
NLCBR
Coil saturation protection and overcurrent detection
Input: pin SLS
Vth(sat)SLS
saturation threshold voltage on
pin SLS
ignition state
2.3
2.5
2.7
V
Vth(ocp)SLS
overcurrent protection threshold
voltage on pin SLS
boost state and burn state
2.3
2.5
2.7
V
tleb
leading edge blanking time
detection disabled for first part of
GLS time
-
800
-
ns
sink output current on pin CI
VCI = 2 V; Vi(SLS) > Vth(sat)SLS; cycle
clocked
26
29
32
A
-
160
-
A
0.55
0.6
0.65
V
685
885
1085
ns
15
5
0
mV
Vi(SLS) > Vth(capm)SLS; VCI = 2 V;
ignition state or boost and burn
state
26
29
32
A
Vi(CSI) = 1 V
1
-
-
M
Vi(CSI) = 1 V
40
50
60
k
rectification linear for operation
2.5
-
+2.5
V
minimum dim level;
Rext(RREF) = 33 k; RMDL = 2 k
44
50
56
mV
RMS voltage; clamp active; default
start-up burn state; 100 % on
-
1
-
V
Output pin CI
Io(sink)CI
Output pin CF
Io(sat)CF
saturation output current difference VCF = 1.5 V; ignition state;
on pin CF
LS switch = on
Ignition current detection
Input pin CSI
Vth(det)ign(CSI)
ignition detection threshold voltage
on pin CSI
tw(det)ign(min)
minimum ignition detection pulse
width
Vth(det)ign(CSI) = 0.75 V square pulse
Capacitive mode detection
Input pin SLS
Vth(capm)SLS
[4]
capacitive mode threshold voltage
on pin SLS
Output pin CI
Io(sink)CI
sink output current on pin CI
Lamp current sensor and dimming control
Input pin CSI
Ri(CSI)
input resistance on pin CSI
Vi(CSI)
input voltage on pin CSI
Vclamp(CSI)
clamping voltage on pin CSI
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Table 5.
Characteristics …continued
VDD = 13 V; VFS  VHBO = 13 V; Tamb = 25 C; settings according to default setting see Table 6 on page 25, all voltages
referenced to PGND and SGND, positive currents flow into the UBA20260, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vdim2(CSI)
dimming 2 voltage difference on
pin CSI
RMS voltage; offset from Vi(CSI) at
DIM_2 compared to MDL
330
350
370
mV
Vdim3(CSI)
dimming 3 voltage difference on pin RMS voltage; offset from Vi(CSI) at
CSI
DIM_3 compared to MDL
90
100
110
mV
output current on pin CI
85
95
105
A
26.3
25
23.7 A
-
50
-
mV
Output pin CI
Io(CI)
burn state; VCI = 2 V; source ()
and sink (+)
Input pin MDL (minimum dimming level)
Isource(MDL)
source current on pin MDL
VMDL
voltage on pin MDL
Rext(RREF) = 33 k; RMDL = 2 k
Temperature protection
Tj(otp)
overtemperature protection junction
temperature
145
160
170
C
Tj(otp)hys
hysteresis overtemperature
protection junction temperature
10
20
30
C
overtemperature protection voltage RMS voltage; Rext(RREF)= 33 k;
on pin CSI
RMDL = 2 k; Tj > Tj(opt)  Tj(hys)(otp)
380
400
420
mV
Input pin CSI
Votp(CSI)
[1]
See Table 6 on page 25 for the default settings.
[2]
The half-bridge output switching frequency (HBO). The saw-tooth frequency on pin CF is twice as high.
[3]
Data sampling of Vph(SLS) is performed at the end of the LS power MOSFET conduction period in preheat state.
[4]
Data sampling of Vth(capm)SLS is performed at the start of conduction of the LS power MOSFET, in all states with oscillator active.
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600 V driver IC for step dimmable CFLs
11. Application information
11.1 Design equations
All described equations are only valid for Rext(RREF) = 33 k.
11.1.1 CCP related timing equations
• Preheat time
C CP
t ph = --------------   16  V hys  CP  + 5 – V th  CP max 
I o  CP 
(1)
• Ignition enabling time
C CP
t en  ign  = --------------  4  V hys  CP 
I o  CP 
(2)
• Overcurrent fault time
C CP
t fault  oc  = --------------   5 – V th  CP min 
I o  CP 
(3)
• Transition to burn time
C CP
t t  bst – burn  = --------------   64  V hys  CP  + 5 – V th  CP max 
I o  CP 
(4)
• Retain time step dimming
C CP
t ret  dim  = -------------------------   5 – V ret  dim CP 
I ret  dim CP
(5)
• Restart delay time
 V th  CP max – V th  rel CP 
t d  restart  = C CP  ------------------------------------------------------------I restart  CP 
(6)
Where Irestart(CP) = 0.5 A (typical).
11.1.2 CCB related timing equation
• Boost time
C CB
t bst = --------------   126  V hys  CB  + V th  CB min – 0.6 
I o  CB 
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600 V driver IC for step dimmable CFLs
11.1.3 CCF related frequency equations
• Maximum bridge frequency
0.5
f bridge  max  = ---------------------------------------------------------------------------C CF + C par
---------------------------  V th  CF max + t dch
I o  CF max
(8)
Where Cpar = 4.7 pF and tdch = 0.4 s.
• Minimum bridge frequency with disabled boost
0.5
f bridge  min  = ---------------------------------------------------------------------------C CF + C par
---------------------------  V th  CF max + t dch
I o  CF min
(9)
• Minimum bridge frequency with enabled boost
0.5
f bridge  bst min = ---------------------------------------------------------------------------C CF + C par
---------------------------  V th  CF max + t dch
I o  bst CF
(10)
11.1.4 RSLS related preheat current
V ph  SLS 
I ph  M  = -------------------R SLS
(11)
V ph  SLS 
I ph  RMS   ------------------------R SLS  3
(12)
11.1.5 RMDL related minimum dimming level
• MDL threshold voltage
V MDL = R MDL  I source  MDL 
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11.2 Application Diagram
D5
D6
C17
C3
12
R5
Q1
GHS
C11
L2
FS
R6
16
11
D1
L1
HBO
D2
C9
C1
CFL
C2
C10
D3
D8
D7
VDD
Q2
C6
GLS
SLS
C5
C4
C8
R9
CSI
n.c.
RCSI
C7
RSLS
CCP
R8
8
15
4
C13
D4
CP
CCB
14
C12
R1
CB
7
UBA20260
5
2
6
1
CI
MDL
C15
C16
RMDL
RREF RREF
CF
CCF
9
10
3
13
PGND
SGND
001aam771
Fig 12. UBA20260 default application diagram
Detailed in Table 6 is a list of typical application components. See Figure 12.
UBA20260
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
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UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
Table 6.
UBA20260
Product data sheet
Typical application components for a 230 V (AC) mains application
Reference
Component
Description
R1
4.7
2 W fusible resistor
R5; R6
220 k
R8
2.2 k
R9
1 k
RREF
33 k; 1 %
RSLS
1.2 
adjust for preheat current
RMDL
1 k
adjust for minimum lamp current
RCSI
8.2 
adjust for nominal lamp current
C1
47 nF; 630 V
C2
22 nF; 630 V
C3
47 nF; 400 V
C4
10 F; 400 V
C5
4.7 nF; 1 kV
C6
68 nF; 250 V
C7
100 pF
C8
47 nF; 400 V
C9
560 pF; 500 V
lamp capacitor
VDD charge pump capacitor
C10
not mounted
C11
68 nF; 250 V
C12
100 nF
C13
470 nF
C15
220 nF
C16
not mounted
C17
22 nF; 400 V
CCB
150 nF
CCP
330 nF
CCF
100 pF; 2 %
Q1; Q2
SPS02N60C3
D1 to D4
1N4007
D5; D6
1N4937
D7
BZX84JC12
D8
BAS20
L1
4.7 mH
mains filter inductor; ISAT = 300 mA
L2
Würth Elektronik: 7608000902
2000/21.31.3/22 H lamp inductor
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
25 of 30
UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 13. Package outline SOT109-1 (SO16)
UBA20260
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
26 of 30
UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
13. Abbreviations
Table 7.
Abbreviations
Acronym
Description
CFL
Compact Fluorescent Lamp
CMP
Capacitive Mode Protection
DSR
Double-Sided Rectifier
ESD
ElectroStatic Discharge
HS
High-Side
LS
Low-Side
MDL
Minimum Dimming Level
OCP
OverCurrent Protection
OPP
OverPower Protection
OTA
Operational Transconductance Amplifier
OTP
OverTemperature Protection
RMS
Root Mean Square
SR
Slew Rate
UVLO
UnderVoltage LockOut
VCO
Voltage Controlled Oscillator
14. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
UBA20260 v. 2
20111010
Product data sheet
-
UBA20260 v. 1
UBA20260 v. 1
20110909
Objective data sheet
-
-
UBA20260
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
27 of 30
UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
UBA20260
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
28 of 30
UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
UBA20260
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
29 of 30
UBA20260
NXP Semiconductors
600 V driver IC for step dimmable CFLs
17. Contents
1
2
2.1
2.2
2.3
2.4
2.5
2.6
3
4
5
6
6.1
6.2
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
8
9
10
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Half-bridge features . . . . . . . . . . . . . . . . . . . . . 1
Preheat and ignition features . . . . . . . . . . . . . . 1
Lamp boost features . . . . . . . . . . . . . . . . . . . . . 1
Dim features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Other features. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5
Lamp start-up cycle . . . . . . . . . . . . . . . . . . . . . 6
Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Start-up state . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Preheat state . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ignition state . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Boost state and transition to burn state . . . . . . 8
Burn state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Oscillation and timing . . . . . . . . . . . . . . . . . . . 11
Oscillator control . . . . . . . . . . . . . . . . . . . . . . . 11
Combined timing circuit . . . . . . . . . . . . . . . . . 12
Step dimming . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection functions and Power-down mode . 14
Coil saturation protection . . . . . . . . . . . . . . . . 14
Overcurrent protection . . . . . . . . . . . . . . . . . . 15
Overpower protection . . . . . . . . . . . . . . . . . . . 15
Capacitive mode protection . . . . . . . . . . . . . . 15
Overtemperature protection . . . . . . . . . . . . . . 16
Power-down mode . . . . . . . . . . . . . . . . . . . . . 16
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal characteristics . . . . . . . . . . . . . . . . . 17
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information. . . . . . . . . . . . . . . . . . 22
Design equations . . . . . . . . . . . . . . . . . . . . . . 22
CCP related timing equations . . . . . . . . . . . . . 22
CCB related timing equation . . . . . . . . . . . . . . 22
CCF related frequency equations . . . . . . . . . . 23
RSLS related preheat current. . . . . . . . . . . . . . 23
RMDL related minimum dimming level. . . . . . . 23
Application Diagram . . . . . . . . . . . . . . . . . . . . 24
12
13
14
15
15.1
15.2
15.3
15.4
16
17
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
27
27
28
28
28
28
29
29
30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 October 2011
Document identifier: UBA20260
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