D a t a S h e e t , R e v. 1 . 0 , M ar c h 2 00 8 B TS 41 30 Q G A S m a rt H i g h - S i d e P o w e r S w i t c h A u to m o t i v e P o w e r BTS 4130QGA 1 Overview 3 2 Block Diagram 5 3 3.1 3.2 3.3 Pin Configuration 6 Pin Assignment 6 Pin Definitions and Functions 6 Voltage and Current Definition 7 4 4.1 4.2 4.3 General Product Characteristics 8 Absolute Maximum Ratings 8 Functional Range 9 Thermal Resistance 9 5 5.1 5.2 5.3 5.3.1 5.4 Power Stage 10 Output ON-State Resistance 10 Turn ON / OFF Characteristics 10 Inductive Output Clamp 11 Maximum Load Inductance 12 Electrical Characteristics Power Stage 13 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 Protection Mechanisms 14 Loss of Ground Protection 14 Undervoltage Protection 14 Overvoltage Protection 14 Reverse Polarity Protection 15 Overload Protection 15 Current Limitation 16 Electrical Characteristics Protection Functions 17 7 7.1 7.2 7.2.1 7.2.2 7.3 Diagnostic Mechanism 18 ST 0/1/2/3 Pin 18 ST0/1/2/3 Signal in Case of Failures 18 Diagnostic in Open Load, Channel OFF 19 ST 0/1 Signal in case of Over Temperature 20 Electrical Characteristics Diagnostic Functions 21 8 8.1 8.2 Input Pins 22 Input Circuitry 22 Electrical Characteristics 22 9 9.1 Application Information 23 Further Application Information 23 10 Package Outlines 24 11 Revision History 25 Datasheet 2 1.0, 2008-27-02 Smart High-Side Power Switch BTS4130QGA Four Channel Device 1 Overview Basic Features • • • • • • • • • • • Withstand low Cranking Voltage Fit for 12V Application Four Channel device Very low Stand-by Current CMOS Compatible Inputs Electrostatic Discharge Protection (ESD) Optimized Electromagnetic Compatibility Logic ground independent from load ground Very low Leakage Current from OUT to the load in OFF State Green Product (RoHS compliant) AEC Qualified PG-DSO-20-32 Description The BTS4130QGA is a quad channel Smart High-Side Power Switch. It is embedded in a PG-DSO-20-32 package, providing protective functions and diagnostics. The power transistor is built by a N-channel power MOSFET with charge pump. The device is monolithically integrated in Smart technology. It is specially designed to drive relays as well as resistive loads in the harsh automotive environment. Table 1 Electrical Parameters (short form) Parameter Symbol Value Operating voltage range VSOP Vs (USO) PBULB VS (AZ) RDS(ON) IL (nom) IL_SCR IS(off) -Vs(REV) 5.5V .... 20V Undervoltage switch OFF at Tj = -40°C Maximum load per channel Over voltage protection Max ON State resistance at Tj = 150°C per channel Nominal load current (one channel active) Minimum current limitation Standby current for the whole device with load Maximum reverse battery voltage 3.2V 2 * R5W, relays or LED 43V 260mΩ 1.8A 5A 16µA 32V Type Package Marking BTS4130QGA PG-DSO-20-32 BTS4130QGA Data Sheet 3 Rev. 1.0, 2008-03-18 BTS4130QGA Overview Diagnostic Feature • • • Open load detection in OFF state Feedback of the thermal shutdown in ON state Diagnostic feedback with open drain output Protection Functions • • • • • • • • Short circuit protection Overload protection Current limitation Thermal shutdown Overvoltage protection (including load dump) with external resistor Reverse battery protection with external resistor Loss of ground and loss of VS protection Electrostatic discharge protection (ESD) Application • All types of resistiv, inductive and capacitive loads Data Sheet 4 Rev. 1.0, 2008-03-18 BTS4130QGA Block Diagram 2 Block Diagram Channel 0 VS voltage sensor internal power supply over temperature driver logic IN0 ESD protection T clamp for inductive load gate control & charge pump over current switch off OUT 0 open load detection ST 0/1 VS Channel 1 T IN1 Control and protection circuit equivalent to channel 0 OUT 1 Channel 2 VS voltage sensor internal power supply over temperature driver logic IN2 ESD protection T clamp for inductive load gate control & charge pump over current switch off OUT 2 open load detection ST 2/3 VS Channel 3 T IN3 Control and protection circuit equivalent to channel 0 OUT 3 Block diagram .emf GND Figure 1 Data Sheet Block diagram for the BTS4130QGA 5 Rev. 1.0, 2008-03-18 BTS4130QGA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment Vs 1 20 Vs GND0/1 2 19 Vs IN0 3 18 OUT0 ST 0/1 4 17 OUT1 IN1 5 16 Vs GND2/3 6 15 Vs IN2 7 14 OUT2 ST2/3 8 13 OUT3 IN3 9 12 Vs Vs 10 11 Vs Pinout SO20 shared diag.vsd Figure 2 Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1, 10, 11, 12, 15, 16, 19, 20 VS Battery voltage; Design the wiring for the simultaneous maximum short circuit currents from channel 0 and 1 and also for low thermal resistance 2 GND0/1 Ground; Ground connection for channel 0 and 1 3 IN0 Input channel 0; Input signal for channel 0. Activate the channel in case of logic high level 4 ST 0/1 Diagnostic feedback; of channel 0/1. Open drain. 5 IN1 Input channel 1; Input signal for channel 1. Activate the channel in case of logic high level 6 GND2/3 Ground; Ground connection for channel 2 and 3 7 IN2 Input channel 2; Input signal for channel 2. Activate the channel in case of logic high level 8 ST 2/3 Diagnostic feedback; of channel 2/3. Open drain. 9 IN3 Input channel 3; Input signal for channel 3. Activate the channel in case of logic high level Data Sheet 6 Rev. 1.0, 2008-03-18 BTS4130QGA Pin Configuration Pin Symbol Function 13 OUT3 Output 3; Protected High side power output channel 3 14 OUT2 Output 2; Protected High side power output channel 2 17 OUT1 Output 1; Protected High side power output channel 1 18 OUT0 Output 0; Protected High side power output channel 0 3.3 Voltage and Current Definition Figure 3 shows all terms used in this data sheet, with associated convention for positive values. IS VS VS IIN 0 V IN 0 IIN 1 IN0 OUT0 IN1 OUT1 VIN 1 IST0/1 VST0 /1 VD S0 VD S1 VD S2 VD S3 IOU T0 IOU T1 ST 0/1 IIN 2 IIN 3 IST2/3 IN2 OUT2 IN3 OUT3 IOU T2 IOU T3 ST 2/3 GND IGN D VOU T0 V OU T1 V OU T2 VOU T3 Voltage and current convention quad shared diag.vsd Figure 3 Data Sheet Voltage and current definition 7 Rev. 1.0, 2008-03-18 BTS4130QGA General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) TJ = 25°C; (unless otherwise specified) Pos. Parameter Symbol Limit values Unit Conditions Min. Max. -0.3 43 V – – 32 V – 0 20 V RECU = 20mΩ, RCable = 16mΩ/m, LCable = 1µH/m, Voltages 4.1.1 4.1.2 4.1.3 VS Reverse polarity Voltage - VS(REV) Supply voltage for short circuit protection Vbat(SC) Supply voltage l = 0 or 5m 2) see Chapter 6 Input pins 4.1.4 Voltage at INPUT pins 4.1.5 Current through INPUT pins 4.1.6 Current through INPUT pins pulsed VIN IIN IIN -10 16 V – -0.3 0.3 mA – -5 5 mA Only for testing IST0/1 IST2/3 -5 5 mA – -5 5 mA – Status pin 4.1.7 Current through ST 0/1 pin 4.1.8 Current through ST 2/3 pin Power stage 4.1.9 Load current | IL | – IL(LIM) A – 4.1.10 Power dissipation (DC), all channel active PTOT – 1.4 W 4.1.11 Maximum Switchable energy, single pulse EAS – 76 mJ TA = 85°C, Tj <150°C IL = 2.3A, VS = 12V Tj ∆T j -40 150 °C – – 60 K – Tstg -55 150 °C – VESD VESD VESD -1 1 kV HBM3) -4 4 kV HBM3) -5 5 kV HBM3) Temperatures 4.1.12 Junction Temperature 4.1.13 Dynamic temperature increase while switching 4.1.14 Storage Temperature ESD Susceptibility 4.1.15 ESD Resistivity IN pin 4.1.16 ESD Resistivity ST 0/1, 2/3 pins 4.1.17 ESD Resistivity OUT to all other pins shorted 1) Not subject to production test, specified by design 2) Set up in accordance to AEC Q100-012 and AEC Q101-006 3) ESD susceptibility HBM according to EIA/JESD 22-A 114B Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data Sheet 8 Rev. 1.0, 2008-03-18 BTS4130QGA General Product Characteristics Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Functional Range Tj = -40 °C to +150 °C; (unless otherwise specified) Pos. Parameter Symbol Limit values Min. Max. Unit Conditions 4.2.1 Operating Voltage VSOP 5.5 20 V VIN = 4.5V, RL = 12Ω, VDS < 0.5V 4.2.2 Undervoltage switch OFF VSUV – 3.2 V -1), Tj = -40°C, VDS < 0.5V 4.2.3 Operating current One channel active Four channels active IGND mA VIN = 5V – – 0.9 3.3 Standby current for whole device with load IS(OFF) – – – 16 16 24 µA Tj = 25°C Tj = 85°C2) Tj = 150°C, Vs = 12V, RL = 12Ω, VIN = 0V 4.2.4 1) Battery voltage is decreasing 2) Not subject to production test. Specified by design Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Pos. Thermal Resistance Parameter Symbol Limit values Min. Typ. Max. Unit Conditions 4.3.1 Junction to Soldering Point each channel RthJSP – – 15 K/W –1) 4.3.2 Junction to Ambient RthJA – 45 – K/W with 6cm² cooling area1) 1) Not subject to production test, specified by design Data Sheet 9 Rev. 1.0, 2008-03-18 BTS4130QGA Power Stage 5 Power Stage The power stages are built by an N-channel vertical power MOSFET (DMOS) with charge pump. 5.1 Output ON-State Resistance The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature Tj. Figure 4 shows the dependencies for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 6.4. 300 Rdson (mOhm) @ -40°C Rdson (mOhm) @ +25°C Rdson (mOhm) @ +150°C 250 Rdson (mOhm) 200 150 100 50 0 5 7 9 11 13 15 VS (V) Figure 4 17 19 ron.vsd Typical ON-state resistance A high signal (See Chapter 8) at the input pin causes the power DMOS to switch ON with a dedicated slope, which is optimized in terms of EMC emission. 5.2 Turn ON / OFF Characteristics Figure 5 shows the typical timing when switching a resistive load. IN VIN_H_min V IN_L_max t V OUT 90% V S dV/dt OFF tON 70% V S dV/dt ON 30% V S tOFF 10% V S t Switching times .vsd Figure 5 Data Sheet Turn ON/OFF (resistive) timing 10 Rev. 1.0, 2008-03-18 BTS4130QGA Power Stage 5.3 Inductive Output Clamp When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implemented that keeps the negative output voltage at a certain level (VS-VDS(AZ)). Please refers to Figure 6 and Figure 7 for details. Nevertheless, the maximum allowed load inductance is limited. VS V DS IN LOGIC IL V BAT OUT GND VIN VOUT L, RL Output clamp.vsd Figure 6 Output clamp (OUT0 and OUT1) IN t VOUT VS t VS-VDS(AZ) tpeak IL t Switching an inductance.vsd Figure 7 Data Sheet Switching an inductance 11 Rev. 1.0, 2008-03-18 BTS4130QGA Power Stage 5.3.1 Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the BTS4130QGA. This energy can be calculated with following equation: V S – V DS ( AZ ) RL × IL L E = V DS ( AZ ) × ------- × ---------------------------------- × ln 1 – --------------------------------- + IL RL RL V S – V DS ( AZ ) Following equation simplifies under the assumption of RL = 0Ω. VS 2 1 E = --- × L × I × 1 – --------------------------------- 2 V S – V DS ( AZ ) The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 8 for the maximum allowed inductivity. 1000 ZL (mH) 100 10 1 1 2 3 4 5 6 IL (A) max eas.vsd Figure 8 Data Sheet Maximum energy dissipation single pulse, Tj,Start = 150 °C 12 Rev. 1.0, 2008-03-18 BTS4130QGA Power Stage 5.4 Electrical Characteristics Power Stage Electrical Characteristics: Power stage VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. 5.4.1 Parameter ON-state resistance per channel Symbol RDS(ON) Limit values Min. Typ. Max. – 130 – Unit Conditions mΩ Tj = 25°C,1) IL = 2A, VIN = 5V, See Figure 4 A Tj = 150°C TA = 85°C1), Tj <150°C 52 V IDS = 40mA2) 1 5 µA VIN = 0V 0.2 – 1 V/µs RL=12Ω, VS=12V Slew rate OFF 70% to 40% VOUT -dV/dtOFF 0.2 – 1.1 V/µs See Figure 5 5.4.7 Turn-ON time to 90% VS Includes propagation delay tON – 100 250 µs 5.4.8 Turn-OFF time to 10% VS Includes propagation delay tOFF – 100 270 µs Nominal load current per channel One channel active Two channel active Four channel active IL(nom) 5.4.3 Drain to source clamping voltage VDS(AZ) = VS-VOUT VDS(AZ) 5.4.4 Output leakage current per channel IL(OFF) 5.4.5 Slew rate ON 10% to 30% VOUT dV/dtON 5.4.6 5.4.2 – 210 260 2.1 1.5 1.1 – – – – – – 41 47 – 1) Not subject to production test, specified by design 2) Voltage is measured by forcing IDS. Data Sheet 13 Rev. 1.0, 2008-03-18 BTS4130QGA Protection Mechanisms 6 Protection Mechanisms The device provides embedded protective functions. Integrated protection functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are designed for neither continuous nor repetitive operation. 6.1 Loss of Ground Protection In case of loss of the module ground, where the load remains connected to ground, the device protects itself by automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN pins. In that case, a maximum I(OUTGND) can flow out of the output. 6.2 Undervoltage Protection Below VSUV_max, the under voltage mechanism is met. If the supply voltage is below the under voltage mechanism, the device is OFF (turns OFF). As soon as the supply voltage is above the under voltage mechanism, then the device can be switched ON and the protection functions are operational. 6.3 Overvoltage Protection There is a clamp mechanism for over voltage protection. To guarantee this mechanism operates properly in the application, the current in the zener diode ZDAZ has to be limited by a ground resistor. Figure 9 shows a typical application to withstand overvoltage issues. In case of supply greater than VS(AZ), the power transistor switches ON and the voltage across logic section is clamped. As a result, the internal ground potential rises to VS - VS(AZ). Due to the ESD zener diodes, the potential at pins IN and ST 0/1/2/3 rises almost to that potential, depending on the impedance of the connected circuitry. Integrated resistors are provided at the IN pins to protect the input circuitry from excessive current flow during this condition but an external resistor must be provided at the ST0/1/2/3 pins. VccµC R VS PU_ST 0/1 IN0 IN1 R ZDAZ ST 0/1 ST 0/1 ZD ESD VccµC R LOGIC PU_ST 3 IN2 IN3 R VBAT R IN0 RIN1 ST 2/3 R IN2 RIN3 OUT RL ST 2/3 ZD ESD GND RGND Overvoltage protection quad diag shared.vsd Figure 9 Data Sheet Over voltage protection with external components 14 Rev. 1.0, 2008-03-18 BTS4130QGA Protection Mechanisms In the case the supply voltage is in between of VS(SC) max and VDS(AZ), the output transistor is still operational and follow the input. If at least one channel is in ON state, parameters are no longer warranted and lifetime is reduced compared to normal mode. This specially impacts the short circuit robustness, as well as the maximum energy EAS the device can handle. 6.4 Reverse Polarity Protection In case of reverse polarity, the intrinsic body diode causes power dissipation. The current in this intrinsic body diode is limited by the load itself. Additionally, the current into the ground path and the logical pins has to be limited to the maximum current described in Chapter 4.1, sometimes with an external resistor. Figure 10 shows a typical application. The RGND resistor is used to limit the current in the zener protection of the device. Resistors RIN and RST are used to limit the current in the logic of the device and in the ESD protection stage. The recommended value for RGND is 150Ω, for RST 0/1 = 15kΩ. In case the over voltage is not considered in the application, RGND can be replaced by a Shottky diode. VccµC Micro controller protection diodes R PU ST 0/1 IN0 IN 1 R ST /1 VS R IN0 V BAT R IN 1 -V DS(REV) ST 0 /1 ZD body OU T0 , 1, 2, 3 I L(nom) RL VccµC R PU ST 2/3 ZD ESD IN0 IN 1 R ST 2/3 ST 2 /3 R IN0 R IN 1 ZD ESD GND R GND Reverse Polarity quad shared diag .vsd Figure 10 Reverse polarity protection with external components 6.5 Overload Protection In case of overload, or short circuit to ground, the BTS4130QGA offers several protections mechanisms. Data Sheet 15 Rev. 1.0, 2008-03-18 BTS4130QGA Protection Mechanisms 6.5.1 Current Limitation At first step, the instantaneous power in the switch is maintained to a safe level by limiting the current to the maximum current allowed in the switch IL(LIM). During this time, the DMOS temperature is increasing, which affects the current flowing in the DMOS. At thermal shutdown, the device turns OFF and cools down. A restart mechanism is used, after cooling down, the device restarts and limits the current to IL(SCR). Figure 11 shows the behavior of the current limitation as a function of time. IN t IL IL(LIM) IL(SCr) t ST 0/1 t current limitation with diag shared.vsd Figure 11 Data Sheet Current limitation function of the time 16 Rev. 1.0, 2008-03-18 BTS4130QGA Protection Mechanisms 6.6 Electrical Characteristics Protection Functions Electrical Characteristics: Protection VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. Parameter Symbol Limit values Unit Conditions Min. Typ. Max. – – 2 mA VS = 32V VIN = 0V -VDS(REV) – 600 – mV IL= - 2A, Tj = 150°C VIN = 0V VS(AZ) 41 47 52 V Is = 40mA IL(LIM) – – 5 – 9 – 14 – – A Tj = -40°C, Tj = 25°C, Tj = 150°C – – 6.5 6.5 – – A One channel1) Two channel1) parallel 150 – – °C – – 10 – K – 1) Loss of ground 6.6.1 Output leakage current while GND IOUT(GND) disconnected Reverse polarity 6.6.2 Drain source diode voltage during reverse polarity Overvoltage 6.6.3 Over voltage protection Overload condition 6.6.4 Load current limitation 6.6.5 Repetitive short circuit current limit IL(SCR) 6.6.6 Thermal shutdown temperature 6.6.7 Thermal shutdown hysteresis TjSC ∆TJT 1) Not subject to production test, but specified by design Data Sheet 17 Rev. 1.0, 2008-03-18 BTS4130QGA Diagnostic Mechanism 7 Diagnostic Mechanism For diagnosis purpose, the BTS4130QGA provides status pin. 7.1 ST 0/1/2/3 Pin BTS4130QGA status pins are an open drain, active low circuit. Figure 12 shows the equivalent circuitry. As long as no “hard” failure mode occurs (Short circuit to GND / Over temperature or open load in OFF), the signal is permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the application. A suggested value for the RPU ST01 is 15 kΩ. . V ccµC R PU ST 0/1 R PU ST 2/3 Diagnostic Logic Channel 1 or 3 R ST 0/1 R ST 2/3 ST 0/1 or ST 2/3 Channel 0 or 2 OR ZD ESD Diagnostic Logic GND ST pin quad shared diag.vsd Figure 12 Status output circuitry 7.2 ST0/1/2/3 Signal in Case of Failures Table 2 gives a quick reference for the logical state of the ST 0/1/2/3 pins during device operation. Table 2 ST 0/1 2/3 truth table Device operation IN0/2 IN1/3 OUT0/2 OUT1/3 ST 0/1 ST2/3 Normal operation L L L L H L H L H H L H L H H H H L X > V(OL) X L1) H X H X H X L X > V(OL) L1) X H X H H L L L L H X H X L L H X L X L L X L X H H X L X L X L X L H X H X L L Open Load channel 0/2 Open Load channel 1/3 Over temperature both channel Over temp channel 0/2 Over temp channel 1/3 1) L if potential at the output exceeds the Openload detection voltage Data Sheet 18 Rev. 1.0, 2008-03-18 BTS4130QGA Diagnostic Mechanism 7.2.1 Diagnostic in Open Load, Channel OFF For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For calculation of the pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) has to be taken into account. Figure 13 gives a sketch of the situation and Figure 14 shows the typical timing diagram. Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.4) and external leakages e.g. due to humidity, corrosion, etc... in the application. To reduce the stand-by current of the system, an open load resistor switch SOL is recommended. If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by the device as open load. The voltage threshold is given by VOL(OFF). In that case, the ST 0/1 signal is switched to a logical low VST01(L). Vb a t SOL VS R OL OUT ILOFF OL comp. Ileakage VOL(OFF) GND R GND Rleakage O pen Load in O FF.vsd Figure 13 Open load detection in OFF electrical equivalent circuit IN V OUT t V(OL) t IL t ST 0/1 or ST 2/3 V ST(HIGH) VST(LOW) t Diagnostic In Open load quad shared diag.vsd Figure 14 Data Sheet ST 0/1 in open load condition 19 Rev. 1.0, 2008-03-18 BTS4130QGA Diagnostic Mechanism 7.2.2 ST 0/1 Signal in case of Over Temperature In case of over temperature, the junction temperature reaches the thermal shutdown temperature TjSC. In that case, the ST 0/1 signal is toggling between VST01(L) and VST01(H). Figure 15 gives a sketch of the situation. IN t V OUT t ST 0/1 t T JSC ∆T JSC TJ t Diagnostic In Overload shared toggling.vsd Figure 15 Sense signal in overtemperature condition . Data Sheet 20 Rev. 1.0, 2008-03-18 BTS4130QGA Diagnostic Mechanism 7.3 Electrical Characteristics Diagnostic Functions Electrical Characteristics: Diagnostics VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. Parameter Symbol Limit values Unit Conditions Min. Typ. Max. VOL(OFF) 1.7 2.8 4.0 V – Status output (open drain) High level; Zener limit voltage VST (HIGH) 5.4 – – V IST= +1.6mA1), Status output (open drain) Low level VST (LOW) – – 0.6 V IST= +1.6mA1) Load condition threshold for diagnostic 7.3.1 Open Load detection voltage ST 0/1 or ST 2/3 pin 7.3.2 7.3.3 Zener Limit voltage Diagnostic timing 7.3.4 Status change after positive input slope with open load tdST(ON_OL) – 10 20 µs –2) 7.3.5 Status change after positive input slope with overload tdST(ON_OvL) 30 – – µs –2) 7.3.6 Status change after negative input slope with open load tdST(OFF_OL) – – 500 µs – 7.3.7 Status change after negative tdST(OFF) input slope with overtemperature – – 20 µs –2) 1) If ground resistor RGND is used, the voltage drop across this resistor has to be added 2) Not subject to production test, specified by design Data Sheet 21 Rev. 1.0, 2008-03-18 BTS4130QGA Input Pins 8 Input Pins 8.1 Input Circuitry The input circuitry is CMOS compatible. The concept of the Input pin is to react to voltage transition and not to voltage threshold. With the Schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in an linear or undefined state. The input circuitry is compatible with PWM applications. Figure 16 shows the electrical equivalent input circuitry. The pull down current source ensures the channel is OFF with a floating input. IN RI II To driver’s logic ESD Input circuitry.vsd Figure 16 Input pin circuitry 8.2 Electrical Characteristics Electrical Characteristics: Diagnostics VS = 12 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Typical values are given at Tj = 25°C Pos. Parameter Symbol Limit values Unit Conditions Min. Typ. Max. – – 1 V –1) 2.5 – – V –1) – 0.2 – V –2) 5 – 20 µA 10 35 60 µA VIN = 0.4V VIN = 5V 2.5 4 6 kΩ See Figure 16 INput pins characteristics 8.2.1 Low level input voltage 8.2.2 High level input voltage 8.2.3 Input voltage hysteresis 8.2.4 Low level input current 8.2.5 High level input current 8.2.6 Input resistance VIN(L) VIN(H) VIN(HYS) IIN(L) IIN(H) RI 1) If ground resistor RGND is used, the voltage drop across this resistor has to be added 2) Not subject to production test, specified by design Data Sheet 22 Rev. 1.0, 2008-03-18 BTS4130QGA Application Information 9 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VDD VBAT VDD Vdd Vs OUT IN0 OUT0 OUT IN1 OUT1 IN Microcontroller (e.g. XC22xx) ST0/1 VDD OUT IN2 OUT2 OUT IN3 OUT3 ST2/3 IN GND GND Figure 17 Application diagram with BTS4130QGA Note: This is a very simplified example of an application circuit. The function must be verified in the real application. 9.1 • Further Application Information For further information you may visit http://www.infineon.com/ Data Sheet 23 Rev. 1.0, 2008-03-18 BTS4130QGA Package Outlines 1.27 8˚ ma x 7.6 -0.2 1) +0.09 0.35 x 45˚ 0.23 2.65 max 2.45 -0.2 Package Outlines 0.2 -0.1 10 0.4 +0.8 0.35 +0.15 2) 0.2 24x 20 10.3 ±0.3 0.1 11 GPS05094 1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Figure 18 PG-DSO-20-32 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Data Sheet 24 Rev. 1.0, 2008-03-18 BTS4130QGA Revision History 11 Revision History Version Date Changes 1.0 2008-03-18 Creation of the data sheet Data Sheet 25 Rev. 1.0, 2008-03-18 Edition 2008-03-18 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.