Highest Power Density, Multirail Power Solution for Space-Constrained Applications sequencing is critical to ensure that the FPGA is up and running before the memory is enabled. Regulators with a precision enable input and a dedicated power-good output allow power supply sequencing and fault monitoring. Power supply designers often want to use the same power IC in different applications, so the ability to change the current limits is important. This design reuse can significantly reduce time to market—a critical element in any new product development process. 4.5V TO 15V INPUT VOLTAGE 4A BUCK REGULATOR 4A BUCK REGULATOR As the overall size of communications, medical, and industrial equipment continues to decrease, power management becomes an increasingly important design consideration. This article looks at applications for new highly integrated power management solutions, the advantages these new devices bring for powering RF systems, FPGAs, and processors, and a design tool that helps empower designers to quickly implement a new design. The emergence of femtocells and picocells in communications infrastructure is driving the need for smaller base stations, which have complex requirements for powering digital baseband, memory, RF transceivers, and power amplifiers in the smallest area with the highest power efficiency, as shown in Figure 1. A typical small cell system needs a very dense power supply that can deliver large currents with fast transient response to power the digital baseband, along with low-noise, low-dropout regulators (LDOs) to power the AD9361 RF Agile Transceiver,™ temperature compensated crystal oscillator (TCXO), and other noise-critical rails. Setting the switching frequency of the switching regulators outside of the critical RF bands reduces noise, and synchronizing the switching regulators ensures that beat frequencies do not affect the RF performance. Reducing the core voltage (VCORE) of the digital baseband minimizes power consumption for low-power modes, and supply sequencing ensures that the digital baseband processor is up and running before the RF transceiver is enabled. An I2C interface between the digital baseband and the power management allows the output voltages of the buck regulators to be changed. To increase reliability, the power management system can monitor its own input voltage and die temperature, reporting any faults to the baseband processor. 12V INPUT 1.0V@4A 4A BUCK REGULATOR 4A BUCK REGULATOR ADP5050/ ADP5052 1.2A BUCK REGULATOR 200mA LDO DUAL FETS 1.5V@4A VCORE VDDIO ADP1741 2.5V/4A VCCAUX VCCO_0, 1, 2 1.5V/1.2A 1.2A BUCK REGULATOR VCC0_3 1.2A BUCK REGULATOR 2.5V CORE VOLTAGE FPGA AUXILIARY VOLTAGE BANK 0 I/Os BANK 1 BANK 2 I/Os BANK 3 DDR TERM. LDO 0.75V VPLL DDR3 MEMORY FLASH MEMORY 3.3V/1.2A 1.2V/100mA 200mA LDO PWRGD Figure 2. Powering an FPGA-based system. Consider a common multirail power management design specification for an FPGA with a 12-V input and five outputs: •Core: 1.2 V @ 4 A •Auxiliary: 1.8 V @ 4 A •I/O: 3.3 V @ 1.2 A •DDR memory: 1.5 V @ 1.2 A •Clock: 1.0 V @ 200 mA A typical discrete implementation, shown in Figure 3a, connects four switching regulators to the 12-V input rail. The output of one switching regulator preregulates the LDO to reduce power dissipation. An alternative approach, shown in Figure 3b, uses one regulator to step the 12-V input down to a 5-V intermediate rail, which is then regulated down to produce each of the required voltages. This implementation has a lower solution cost, but also a lower efficiency due to the two-stage power conversion. In both cases, each regulator has to be enabled independently, so supply sequencing may require a dedicated power supply sequencer. Noise may also be an issue, unless all of the switchers can be synchronized to reduce beat frequencies. VDD_1V3 VDD_INTERFACE [email protected] VDD_GPO ADM7160 1.2A BUCK REGULATOR VCCINT DDR3 PWRGD [email protected] DIGITAL BASEBAND 1.2V/4A FETS By Maurice O’Brien RF TRANSCEIVER AD9361 TCXO 12VIN PA [email protected] (a) BUCK 1 REG 1.2V @ 4A (CORE RAIL) BUCK 2 REG 1.8V @ 4A (AUX RAIL) BUCK 3 REG 3.3V @ 1.2A (I/O RAIL) BUCK 4 REG 1.5V @ 1.2A (DDR MEMORY RAIL) 1V @ 200mA (CLOCKING/MGT RAIL) LDO 1 Figure 1. Small base stations require a variety of power supplies. Similarly, the trend in medical and instrumentation devices—for example, portable ultrasound and handheld instrumentation—is toward significantly smaller form factors, so these products are driving the need for smaller, more efficient ways of powering FPGAs, processors, and memory, as shown in Figure 2. A typical FPGA and memory design needs a very dense power supply that can deliver large currents with fast transient response to power the core and I/O rails, along with a low-noise rail to power on-chip analog circuitry such as a phase-locked loop (PLL). Power supply Analog Dialogue 47-11, November (2013) 12VIN BUCK 1 REG 5V 1.2V @ 4A (CORE RAIL) BUCK 3 REG 1.8V @ 4A (AUX RAIL) BUCK 4 REG 3.3V @ 1.2A (I/O RAIL) BUCK 5 REG 1.5V @ 1.2A (DDR MEMORY RAIL) LDO 1 (b) BUCK 2 REG 1V @ 200mA (CLOCKING/MGT RAIL) Figure 3. (a) Discrete regulator design and (b) alternative discrete regulator design. www.analog.com/analogdialogue 1 Integrated Solution Yields High Efficiency, Small Size FREQUENCY (Hz) 1.2M VOUT5 7 FB5 ADP5050 7mm × 7mm DL1 31 PGND 30 8 PVIN5 DL2 29 9 PVIN4 SW2 28 10 SW4 SW2 27 11 PGND4 PVIN2 26 BST4 PVIN2 25 0.47µF 6.3V/XR5 0402 SS2 FB2 COMP2 EN2 1nF 6.3V/XR5 0402 1.0µF 6.3V/XR5 0402 100kΩ 0402 BST2 24 SCL 23 15 14 1nF 6.3V/XR5 0402 nINT VDDIO SDA 80 CIN1–10𝛍F 25V/X5R 0805 D2 G2 D2 S2 LAYOUT EXAMP VIN = 12V BUCK 1: 3A @ 6 BUCK 2: 2A @ 1 BUCK 3: 1.2A @ BUCK 4: 0.6A @ LDO: 0.1A 100𝛍F 6.3V/XR5 1206 47kΩ 0402 DUAL NFETS 3mm × 3mm POWERPAK D1 G1 D1 S1 47𝛍F 6.3V/XR5 1206 47kΩ 0402 CIN2–10𝛍F 25V/X5R 0805 0.47µF 6.3V/XR5 0402 100kΩ 0402 3.3𝛍H 5mm × 5mm 6 60 VOUT1 (1.2V/3A) 2.2𝛍H 4mm × 4mm 37 38 39 40 41 42 32 13 VOUT4 (5V/0.6A) 43 SW1 EN4 COMP4 FB4 COUT4–22𝛍F 6.3V/X5R 0805 44 33 EN 5 12 10𝛍H 5mm × 5mm 45 46 SW1 22 CIN4–10𝛍F 25V/X5R 0805 34 PVIN3 4 21 4.7µF 6.3V/XR5 0402 35 PVIN1 20 4.7µF 6.3V/XR5 0402 PVIN1 SW3 3 19 R1–10kΩ 0402 FB1 COMP1 EN1 PGND3 2 18 R1–10kΩ 0402 5VREG SS1 100kΩ 0402 36 17 VOUT5 (2.5V/100mA) 0.47µF 6.3V/XR5 0402 4.7µF 6.3V/XR5 0402 BST1 BST3 40 RT RESISTOR (k𝛀) In some designs it is desirable to have both: a lower switching frequency to provide the highest power efficiency for the higher current rails, and a higher switching frequency to reduce inductor size and minimize PCB area for the lower current rails. A divideby-two option on the master switching frequency allows the ADP5050 to operate at two frequencies, as shown in Figure 5. The switching frequency for Buck 1 and Buck 3 can be set via the I2C port to one-half of the master switching frequency. EN3 COMP3 FB3 SS34 PWRGD SYNC/ RT MODE 1 20 Figure 4. Switching frequency vs. RRT. 100kΩ 0402 16 CIN3–10𝛍F 25V/X5R 0805 47 48 6.8𝛍H 5mm × 5mm 0 1nF 6.3V/XR5 0402 100kΩ 0402 0.47µF 6.3V/XR5 0402 600k 0 1nF 6.3V/XR5 0402 COUT3–22𝛍F 6.3V/X5R 0805 800k 200k R RT = (14822/fSW)1.081, with R in kΩ and f in kHz. VOUT3 (1.8V/1.2A) 1.0M 400k The switching frequency, fSW, is set between 250 kHz and 1.4 MHz by resistor R RT. The flexible switching frequency range allows the power supply designer to optimize the design, reducing the frequency for highest efficiency or increasing the frequency for smallest overall size. Figure 4 shows the relationship between f SW and R RT. The value of R RT can be calculated as 13.39 VOUT2 (3.3V/2A) 23.17 TOTAL PCB AREA AROUND 23mm × 13.5mm = 310mm2 1nF 6.3V/XR5 0402 REG SS1 37 38 FB1 COMP1 EN1 BST1 36 PVIN1 35 PVIN1 34 SW1 33 2 SW1 32 DL1 31 CIN1–10𝛍F 25V/X5R 0805 VOUT1 (1.2V/3A) 2.2𝛍H 4mm × 4mm 0.47µF 6.3V/XR5 0402 100kΩ 0402 39 40 41 1.4M For highest efficiency, each of the buck regulators can be powered directly from 12 V (similar to Figure 3a), removing the need for a preregulator stage. Buck 1 and Buck 2 have programmable current limits (4 A, 2.5 A, or 1.2 A), allowing the power supply designer to quickly and easily change the currents for new designs and significantly reducing the development time. The LDO can be powered from a 1.7-V to 5.5-V supply. In this example, the 1.8-V output from one of the buck regulators powers the LDO to provide a low-noise 1-V rail for the noise-sensitive analog circuitry. 4.7µF 6.3V/XR5 0402 0 1.6M Integrating multiple buck regulators and LDOs into a single package can significantly reduce the overall size of a power management design. In addition, smart integrated solutions provide many advantages over traditional discrete implementations. Reducing the number of discrete components can significantly reduce the cost, complexity, and manufacturing cost of the design. The ADP5050 and ADP5052 integrated power management units (PMUs) can implement all these voltages and features in a single IC, using significantly less PCB area and fewer components. 100𝛍F 6.3V/XR5 1206 LAYOUT EXAMPLE: VIN = 12V BUCK 1: 3A @ 600kHz BUCK 2: 2A @ 1.2MHz BUCK 3: 1.2A @ 600kHz BUCK 4: 0.6A @ 1.2MHz LDO: 0.1A Figure 5. The ADP5050 operates at a low switching frequency for high efficiency on high-current rails and a high frequency for small inductor size on low-current rails. D2 G2 D2 S2 Analog Dialogue 47-11, November (2013) 47kΩ 0402 DUAL NFETS 47𝛍F Power Supply Sequencing CHANNELx As shown in Figure 6, the ADP5050 and ADP5052 have four features that simplify power supply sequencing that is required for applications using FPGAs and processors: precision enable inputs, programmable soft start, a power-good output, and an active output discharge switch. INTERNAL ENABLE R1 ENx R2 1. Precision Enabled Threshold Above 0.8V to enable the regulator, below 0.72V (hysteresis) to shutdown the regulator. VREG TOP RESISTOR LEVEL DETECTOR AND DECODER SS12 OR SS34 BOTTOM RESISTOR Programmable Soft Start: Soft start circuitry ramps the output voltage in a controlled manner, limiting the inrush current. The soft start time is set to 2 ms when the soft start pins are tied to VREG, or it can be increased up to 8 ms by connecting a resistor divider from the soft start pin to VREG and ground (Figure 6-2). This configuration may be required to accommodate a specific start-up sequence or an application with a large output capacitor. The configurability and flexibility of the soft start enable large, complex FPGAs and processors to power up in a safe, controlled manner. 2. Programmable Soft Start The different soft start on each channel can be programmable to be 2ms, 4ms, 8ms. VDDIO PWRGDMASK PWRGD1 PWRGD2 PWRGD3 PWRGD4 PWRGD MUX Power-Good Output: An open-drain power-good output (PWRGD) goes high when the selected buck regulators are operating normally (Figure 6-3). The power-good pins allow the power supply to signal the host system about its health. By default, PWRGD monitors the output voltage on Buck 1, but other channels can be custom ordered to control the PWRGD pin. The status of each channel (PWRGx bit) can be read back via the I2C interface on the ADP5050. A logic high on the PWRGx bit indicates that the regulated output voltage is above 90.5% of its nominal output. The PWRGx bit is set to logic low when the regulated output voltage falls below 87.2% of its nominal output for more than 50 µs. The PWRGD output is the logical AND of the internal unmasked PWRGx signals. An internal PWRGx signal must be high for at least 1 ms before PWRGD goes high; if any PWRGx signal fails, PWRGD goes low with no delay. The channels that control PWRGD (Channel 1 to Channel 4) are specified by factory fuse or by setting bits via the I2C interface. Analog Dialogue 47-11, November (2013) 0.8V DEGLITCH TIMER 1M𝛀 Precision Enable Inputs: Each regulator, including the LDO, has an enable input with a precise 0.8-V reference (Figure 6-1). When the voltage at an enable input is greater than 0.8 V, the regulator is enabled; when the voltage falls below 0.725 V, the regulator is disabled. An internal 1-MΩ pull-down resistor prevents errors if the pin is left floating. The precision enable threshold voltage allows easy sequencing within the device, as well as with external supplies. As an example, if Buck 1 is set to 5 V, a resistor divider can be used to set an accurate 4.0-V trip point to enable Buck 2, and so on, setting an accurate power-up sequence for all outputs. Active Output Discharge Switch: Each buck regulator integrates a discharge switch from the switching node to ground (Figure 6-4). Turned on when its associated regulator is disabled, the switch helps the output capacitor to discharge quickly. The typical resistance of the discharge switch is 250 Ω for Channel 1 to Channel 4. The active discharge switch pulls the output to ground when the regulator is disabled, even when a large capacitive load is present. This significantly increases the robustness of the system, particularly when it is power cycled. INPUT/OUTPUT VOLTAGE 1ms VALIDATION DELAY TIMER 3. PWRGD Output The desirable PWRGDx from CH1 to CH4 can be configured by the factory fuse or I2C. BSTx SW DISCHARGE SWITCH L VOUT COUT DISCHARGE 4. Active Output Discharge Switch The output discharge switch can be turned ON to shorten the discharge period of the output capacitors. Figure 6. ADP5050 and ADP5052 simplify power supply sequencing. 3 Figure 7 shows a typical power-up/power-down sequence. EN1 TIED TO INTERNAL 5VREG FOR AUTOMATIC 12V PLUG-IN EN1 TIED TO STARTUP INTERNALWHEN 5VREG FOR AUTOMATIC STARTUP WHEN 12V PLUG-IN 12V INPUT 12V INPUT PACKWOOD 12V (TIED TO VREG) ADP5050 12V (TIED TO VREGEN1 ) 115K 10K 10K CH1: BUCK PWRGD1 Vx Vx EN2 Vx STARTUP FIRSTLY, THEN ENABLE CH2 Vx STARTUP FIRSTLY, THEN ENABLE CH2 VCCAUX 1.8V @ 1.2A VCCAUX 1.8V @ 1.2A CH1: BUCK EN1 PWRGD1 DUAL DUAL FETs FETs 115K 115K/10K RESISTOR DIVIDER TO SET THE UVLORESISTOR OF CH3/CH4 TO BETO ~9VSET 115K/10K DIVIDER THE UVLO OF CH3/CH4 TO BE ~9V CH2: BUCK EN2 1.2V @ 1.2A CH2: BUCK CH3/CH4 WOULD BE HELD OFF BY PWRGD1 1.8V REACHES ITS CH3/CH4 BEFORE WOULD BE HELD OFF BY 90% REGULATION PWRGD1 BEFORE 1.8V REACHES ITS 90% REGULATION 1.2V @ 1.2A EN3 INTERNAL ACTIVE DISCHARGE SWITCH CAN BE TURNEDACTIVE ON TODISCHARGE FULLY DISCHARGE INTERNAL SWITCH CAN VCCO-3.3V IN SHUTDOWN BE TURNEDTO ONZERO TO FULLY DISCHARGE VCCO-2 2.5V @ 1.2A VCCO-3.3V TO ZERO IN SHUTDOWN VCCO-2 CH3: BUCK EN4 CH4: BUCK EN4 CH4: BUCK VDDIO SDA VDDIO SCL SDA SCL I2C INTERFACE CAN BE USED TO TURN OFF EACH CHANNEL I2C INTERFACE CAN BE USED TO TURN OFF EACH CHANNEL VCCO-1 3.3V @ 1.2A VCCO-1 3.3V @ 1.2A CH3: BUCK EN3 2.5V @ 1.2A OTHER PURPOSE OTHER PURPOSE CH5: LDO CH5: LDO VCCO = 3.3V VCCO = 3.3V VCCO = 3.3V VCCO = 3.3V ACTIVE DISCHARGE 3.3VCCO TO ZERO ACTIVE DISCHARGE 3.3VCCO TO ZERO VCCAUX = 1.8V PWRGD =1.8V TO START UP 3.3VCCO PWRGD =1.8V TO START UP 3.3VCCO 12VIN 12VIN PWRGD =1.8V PWRGD =1.8V a) 1.8V-VCCAUX STARTUP FIRSTLY, THEN 3.3V STARTUP UP BY PWRGD AFTER 1.8V REACHES ITS 90% REGULATION PLUS 2ms a) 1.8V-VCCAUX STARTUP FIRSTLY, THEN 3.3V STARTUP UP BY PWRGD DELAY PWRGD AFTER 1.8V REACHES ITS 90% REGULATION PLUS 2ms PWRGD DELAY I2C Interface VCCAUX = 1.8V VCCAUX = 1.8V VCCAUX = 1.8V VIN = ~9V TO SHUT DOWN 3.3VCCO VIN = ~9V TO SHUT DOWN 3.3VCCO b) 3.3V POWER-DOWN FIRSTLY AND FULLY DISCHARGED WHEN 12VIN DROPS BELOW ~9V, ALL OTHER VOLTAGES DISABLED WHEN POWER-DOWN FIRSTLY AND FULLY DISCHARGED WHEN b) 3.3V 12VIN DROPS BELOW <4V DROPS BELOW ~9V, ALL OTHER VOLTAGES DISABLED WHEN 12VIN 12VIN DROPS BELOW <4V Figure 7. Typical power-up/power-down sequence. Figure 8 shows the values that can be programmed to monitor the input voltage of the ADP5050. The I2C interface enables advanced monitoring capability and basic dynamic voltage scaling of the two buck regulator outputs (Channel 1 and Channel 4). Junction Temperature Monitor: The junction temperature can be monitored for faults such as overtemperature conditions. If the junction temperature increases above a preset level (105°C, 115°C, or 125°C), an alert is signaled on nINT. Unlike thermal shutdown, this function sends a warning signal, but does not shut down the device. The ability to monitor the junction temperature and alert the system processor to possible systems failures before they happen increases the system reliability, as shown in Figure 9. Input Voltage Monitor: The input voltage can be monitored for faults such as undervoltage conditions. As an example, with 12 V applied to the input, the I2C interface is configured to trigger an alert if the input voltage falls below 10.2 V. The signal on a dedicated pin (nINT) tells the system processor that a problem has occurred and shuts the system down for corrective action. The ability to monitor the input voltage increases system reliability. [3:0] 12V INPUT VOLTAGE LVIN_TH[3:0] R/W 10.2V (ADJUSTABLE) INTERRUPT TIME Low input voltage detection on PVIN1. These bits set the low input voltage detection threshold. 0000 = 4.2V (default) 0001 = 4.7V 0010 = 5.2V 0011 = 5.7V 0100 = 6.2V 0101 = 6.7V 0110 = 7.2V 0111 = 7.7V 1000 = 8.2V 1001 = 8.7V 1010 = 9.2V 1011 = 9.7V 1100 = 10.2V 1101 = 10.7V 1110 = 11.2V 1111 = low input voltage warning function disabled Undervoltage monitor values. Figure 8. Input undervoltage detection. 115˚ (ADJUSTABLE) [5:4] JUNCTION TEMPERATURE TEMP_TH[1:0] R/W These bits set the junction temperature overheat threshold. 00 = temperature warning function disabled (default) 01 = 105°C 10 = 115°C 11 = 125°C INTERRUPT TIME Low input voltage detection on PVIN1. Figure 9. Junction temperature monitoring. 4 Analog Dialogue 47-11, November (2013) Dynamic Voltage Scaling: Dynamic voltage scaling allows the system to reduce power consumption by dynamically lowering the power supply voltage on Channel 1 and Channel 4 for low-power modes, or it can dynamically change the output voltage depending on the system configuration and system loading. Also, the output voltages of all four buck regulators can be set via the I2C interface, as seen in Figure 10. The phase shift of Channel 2, Channel 3, and Channel 4 can be set to 0°, 90°, 180°, or 270° with respect to Channel 1 using the I2C interface, as shown in Figure 12. When parallel operation is configured to provide a single combined output of up to 8 A on Channel 1 and Channel 2, the switching frequency of Channel 2 is locked to a 180˚ phase shift with respect to Channel 1. SW1 Option 1: Resistor programmable output voltage from 0.8V to V IN 0.85 Option 2: Fixed output voltage with I2C programmability with these ranges for each channel 1 [CH1: 0.85V TO 1.60V, 25mV STEP] SW2 [CH2: 3.3V TO 5.0V, ~300mV STEP] 2 [CH3: 1.2V TO 1.80V, 100mV STEP] [CH4: 2.5V TO 5.5V, 100mV STEP] SW3 Figure 10. ADP5050 output voltage options. Low Noise Features Several features reduce system noise generated by the power supply: Wide Resistor Programmable Switching Frequency Range: A resistor on the RT pin programs the switching frequency between 250 kHz and 1.4 MHz. This flexibility allows the power supply designer to set the switching frequency to avoid system noise bands. Buck Regulator Phase Shifting: The phase shift of the buck regulators can be programmed via the I2C interface. By default, the phase shift between Channel 1 and Channel 2 and between Channel 3 and Channel 4 is 180°, as shown in Figure 11. The benefit of out-of-phase operation is reduced input ripple current and less ground noise on the power supply. 0° REFERENCE SW 180° PHASE SHIFT CH1 (½ fSW OPTIONAL) CH2 90° PHASE SHIFT 0°, 90°,180°, OR 270° ADJUSTABLE 270° PHASE SHIFT CH3 (½ fSW OPTIONAL) CH4 Figure 11. Phase shift of the buck regulators in the ADP5050/ADP5052. Analog Dialogue 47-11, November (2013) 3 SW4 4 CH1 10.0V BW CH3 10.0V BW CH2 10.0V BW CH4 10.0V BW M400ns A CH1 7.40V Figure 12. Phase shift of buck regulators can be configured via the I2C interface. Clock Synchronization: The switching frequency can be synchronized to an external clock in the 250-kHz to 1.4-MHz range via the SYNC/MODE pin. This ability is important in RF and noise-sensitive applications. When an external clock is detected, the switching frequency transitions smoothly to its frequency. When the external clock stops, the device switches back to the internal clock and continues to operate normally. Synchronizing to an external clock allows the system designer to stay away from critical noise frequency bands and reduces the noise generated by multiple devices in a system. For successful synchronization, the internal switching frequency must be programmed to a value close to that of the external clock value; a frequency difference of less than ±15% is suggested. The SYNC/MODE pin can be configured as a synchronization clock output via a factory fuse or the I2C interface. A positive clock pulse with a 50% duty cycle is generated at the SYNC/MODE pin with a frequency equal to the internal switching frequency. A short time delay (~15% of tSW ) occurs between the generated synchronization clock and the Channel 1 switching node. 5 Fig ure 13 shows t wo dev ices con f ig ured in f requenc y synchronization mode: one device is configured as the clock output to synchronize the other device. A 100 kΩ pull-up resistor should be used to prevent logic errors if the SYNC/MODE pin is left floating. ADIsimPower allows the user to quickly and easily input the design requirements on the software interface shown in Figure 15. STEP 1: STEP 2: OPTIMIZE FOR SIZE, COST, OR EFFICIENCY SPECIFY EACH CHANNEL’S OPERATING CONDITIONS, INCLUDING “DO NOT USE” ADP5050/ADP5052 (LDO VERSION) 12V 5V @ 3A CH1 BUCK (4A) 2.2V @ 1.7A CH2 BUCK (4A) ADP1754-1.8 ADP1754-1.8 1.8V @ 1A CH3 BUCK (1.2A) ADP171-ADJ 3.3V @ 1.2A 1.8V @ 0.5A 1.8V @ 1.2A 1.29V @ 0.3A 1.5V @ 1A CH4 BUCK (1.2A) 1.8V ADP3339-3.3 CH5 200MA LDO ADP5051/ADP5053 (WDI VERSION) 0.945V @ 0.2A CH1 BUCK (4A) CLOCK SYNC 0.92V @ 8A CH2 BUCK (4A) 1.2V @ 1.2A CH3 BUCK (1.2A) 12V WDI 3.3V @ 1.2A CH4 BUCK (1.2A) ADP171-ADJ 2.5V @ 0.3A Figure 15. ADIsimPower software interface. WATCHDOG AND RESET VTH nRESET A full bill of materials is generated with intelligent component selection. Evaluation boards can be requested from within the tool. The design tool allows for sophisticated controls for each channel, as shown in Figure 16. CLOCK SYNC Figure 13. RF application shows two devices synchronized to reduce power supply noise. Both devices are synchronized to the same clock, so the phase shift between Channel 1 of the first device and Channel 1 of the second device is 0°, as shown in Figure 14. SYNC-OUT AT FIRST ADP5050 1 SW1 AT FIRST ADP5050 (a) 2 SW1 AT SECOND ADP5050 3 CH1 2.00V BW CH3 5.00V BW CH2 5.00V BW M400ns A CH1 5V RAIL 560mV 4.5V Figure 14. Waveforms of two ADP5050 devices operating in synchronized mode. VOLTAGE ADIsimPower Design Tool RAIL 1 ™ A DIsi m Power now suppor ts t he A DP5050/A DP5052 multichannel high-voltage PMUs, which power 4/5 channels with load current up to 4 A per channel from inputs up to 15 V. The design tool allows users to optimize the design by cascading channels, placing high-current channels in parallel to create an 8-A rail, and considering the thermal contributions of each channel. With the advanced features, users can independently specify each channel’s performance for ripple and transient performance, switching frequency, and channels that support half the master frequency. 6 TIME (b) RAIL CAN BE FURTHER DELAYED USING AN RC DELAY Figure 16. (a) Ripple, transient, and response can be specified for each rail. (b) Advanced sequencing requirements using precision enable. Analog Dialogue 47-11, November (2013) ADIsimPower gives the power designer quick access to accurate, tested, reliable performance data, as shown in Figure 17. Figure 17. ADIsimPower simulation output. The design can then be assembled on an evaluation board, as shown in Figure 18. ADP505x IC 28.3mm × 21.2mm Figure 18. Power supply circuit using ADP5050/ADP5052. Analog Dialogue 47-11, November (2013) 7 ADP5050/ADP5052/ADP5051/ADP5053 Specifications Part Number Description VIN (V) VOUT (V) Number of Outputs Output Current (mA) I2C Key Features Package Price ($U.S.) ADP5050 Quad Buck Regulator, LDO, I2C Buck: 4.5 to 15 0.8 to 0.85 × VIN 2 × Buck 4000, 2500, or 1200 Yes 48-lead LFCSP 4.39 2 × Buck 1200 I2C interface with individual enable pins and power good LDO: 1.7 to 5.5 0.5 to 4.75 LDO 200 Quad Buck Regulator, POR/WDI, I2C Buck: 4.5 to 15 0.8 to 0.85 × VIN 2 × Buck 4000, 2500, or 1200 Yes 48-lead LFCSP 4.59 2 × Buck 1200 I2C interface with individual enable pins and power good Quad Buck Regulator, LDO Buck: 4.5 to 15 2 × Buck 4000, 2500, or 1200 No Individual enable pins and power good 48-lead LFCSP 3.59 2 × Buck 1200 No Individual enable pins and power good 48-lead LFCSP 3.79 ADP5051 ADP5052 ADP5053 Quad Buck Regulator, POR/WDI 0.8 to 0.85 × VIN LDO: 1.7 to 5.5 0.5 to 4.75 LDO 200 Buck: 4.5 to 15 0.8 to 0.85 × VIN 2 × Buck 4000, 2500, or 1200 2 × Buck 1200 ADP5050/ ADP5052 12V/5V INPUT OPTIONAL I 2C ADP5051/ ADP5053 12V/5V INPUT 4A BUCK REG1 1.0V 2.5V 4A BUCK REG1 2.5V 1.2A BUCK REG 1.8V 1.2A BUCK REG 1.8V 1.2A BUCK REG 3.3V 1.2A BUCK REG 3.3V 200mA LDO 1.5V 4A BUCK REG1 1.2V 4A BUCK REG1 OPTIONAL I 2C MR WDI PWRGD 1RESISTOR VTHR POWER-ON RESET AND WATCHDOG RESET PWRGD PROGRAMMABLE CURRENT LIMIT (4 A, 2.5 A, or 1.2 A). Figure 19. ADP5050/ADP5051/ADP5052/ADP5053: quad buck switching regulators with LDO or POR/WDI in LFCSP. Conclusion New highly integrated PMUs are enabling complex power management solutions with high power efficiency, high reliability, and ultrasmall size; and new design tools combined with flexible integrated circuits reduce the time to market for these complex power supplies. The ADP505x family, the latest addition to ADI’s portfolio of highly integrated multi-output regulators, allows a single IC to be used quickly and easily in many different applications, reducing power supply design time. To discuss technical aspects of these devices, please visit the EngineerZone® forum. 8 Author Maurice O’Brien [[email protected]] joined Analog Devices in 2002, following his graduation from t he Universit y of Limerick, Ireland, with a bachelor’s degree in electronic engineering. He currently works as a product marketing manager in the Power Management product line. In his spare time, Maurice enjoys horse riding, outdoor sports, and travel. Analog Dialogue 47-11, November (2013)