CXA1310AQ Single Chip Processing for CCD Monochrome Camera Description The CXA1310AQ is designed to perform the basic signal processing in CCD monochrome cameras with a single chip. This bipolar lC is most suitable for compact usage and low power consumption. 32 pin QFP (Plastic) Features • Processing from CCD output to 75Ω video output with a single chip • Wide variable AGC (4 to 32dB Typ.) • Built-in operational amplifier for AGC loop • 75Ω line capacitance minimized using sag compensation function • Variable white clip level realize wide dynamic range (140 IRE) Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) 7 V • Supply voltage VCC • Storage temperature Tstg –65 to +150 °C • Operating temperature Topr –20 to +75 °C • Allowable power dissipation PD 500 mW Application CCD monochrome camera Operating Conditions Supply voltage VCC 4.75 to 5.25 V γ IN γ CLP OP OUT SHP 11 10 17 24 23 22 21 20 19 18 17 S/H S/H S/H 18 OP IN– 19 OP IN+ AGC S/H CLP1 13 DET OUT BLK S/H 31 VCC2 AGC MAX DET OUT CLP1 12 AGC OUT CLP1 30 11 γ IN VCC2 31 10 γ CLP VIDEO 32 WC SETUP BLK SYNC 32 VIDEO DRIVE γ2 1 SAG 2 GND2 8 7 6 5 4 LINEAR γ OUT DRIVER IN WC CONT SET CONT SYNC 30 29 BLK 9 CLP1 28 IRIS CLP GND1 3 1 2 3 4 5 6 7 LINEAR 8 γ OUT γ1 WC CONT CLP1 VCC1 15 9 DRIVER IN BLK 14 13 SET CONT IRIS 27 IRIS 27 BLK 29 GND3 26 AGC CONT IRIS CLP 28 SYNC CLP2 16 15 VCC1 GND1 DATA 22 CLP2 25 GND3 26 SAG CLP2 GND2 PG 23 OP OUT AGC OUT 12 OP IN– AGC CONT 14 16 OP IN+ AGC MAX 20 SHD1 HSD2 21 SHD2 HSD1 24 DATA SHP 25 PG CLP2 Block Diagram and Pin Configuration Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89Z21A78-PS CXA1310AQ Pin Description No. Symbol I/O signal Description Equivalent circuit 10k 150Ω 1 SAG Inputs VIDEO OUT through capacitor Input pin of sag compensation signal 1 150Ω 6k 400µA 2 GND2 GND∗ GND for driver and IRIS 3 GND1 GND∗ GND for other than driver, sample hold and IRIS T 20µA 4 Sync pulse input pin (active at Low) 4 SYNC 150Ω High: 4.5V and above∗ Low: 0.5V and below T: 5µs Set-up level adjusting pin GND∗ 5 Turns to preset mode 1 SET CONT 2 to 3.5V∗ 5 Control mode 150Ω 40µA VCC∗ Turns to preset mode 2 White clip level adjusting pin 6 WC CONT GND∗ Preset mode 6 150Ω 40µA 2 to 3.5V∗ Control mode ∗ External applied voltage –2– CXA1310AQ No. Symbol 7 DRIVER IN I/O signal Description Equivalent circuit Input γ OUT through capacitor or LINEAR 7 Input pin to driver 40µA Gamma correction signal output pin. 8 Outputs γ 1 when Pin 9 is at OPEN 8 γ OUT 480µA DC 2V Outputs γ 2 when Pin 9 is turnedto 5V Linear signal (γ-OFF signal) output pin 150Ω 9 LINEAR DC 1.8V 9 480µA 15µA VCC∗ Pin 8 output signal turns to γ 2 output 150Ω 10 Capacitor connecting pin for gamma input clamp 10 γ CLP 150Ω 150Ω 11 γ IN 11 Input DC permissible range DC2 to 3V∗ Input pin of the gamma correction circuit 80µA 160µA ∗ External applied voltage –3– CXA1310AQ No. Symbol I/O signal Equivalent circuit Description 700µA 12 AGC OUT 12 Output pin of signal passed through AGC 13 Output pin of AGC detection signal Vp-p MAX 1300mV Vp-p TYP 500mV DC 2.55V 13 DET OUT MAX TYP DC 1500mV 500mV 2V 320µA 20µA 14 AGC MAX DC∗ 15 VCC1 5V∗ 16 AGC CONT DC∗ Maximum gain setting pin of AGC amplifier 14 150Ω Power supply for other than driver and IRIS 16 Gain control pin of AGC amplifier 150Ω 120µA 320µA 17 17 OP OUT Output pin of the operational amplifier ∗ External applied voltage –4– CXA1310AQ No. Symbol I/O signal Equivalent circuit 18 18 OP IN– Description Inverted input pin of the operational amplifier 150Ω 20µA 19 19 OP IN+ 150Ω 20µA Non inverted input pin of the operational amplifier (AGC detection signal input pin) T 100µA 20 SHD2 High: 4.5V and above∗ Low: 0.5V and below T: 15ns and above Input pin of the sample / hold pulse (active at High) 20 150Ω T 100µA 21 SHD1 High: 4.5V and above∗ Low: 0.5V and below T: 15ns and above 150Ω 150µA [∗1] [∗2] 22 DATA Input pin of the sample / hold pulse (active at High) 21 22 CCD signal input pin [∗1] MAX 800mV [∗2] MAX 800mV ∗ External applied voltage –5– CXA1310AQ No. Symbol I/O signal Equivalent circuit 150µA [∗1] [∗2] 23 23 PG Description CCD single input pin [∗1] MAX 800mV [∗2] MAX 800mV T 100µA 24 SHP Input pin of the sample / hold pulse (active at High) 24 150Ω High: 4.5V and above∗ Low: 0.5V and below T: 15ns T 50µA 25 150Ω High: 4.5V and above∗ Low: 0.5V and below T: 2µs 26 GND3 27 IRIS CLP2 pulse input pin (active at High) 25 CLP2 GND∗ Sample / hold GND 27 DC 1 3V DC 1.3V Output pin of the IRIS control signal 320µA 150Ω 28 IRIS CLP Capacitor connecting pin for IRIS output clamp 28 150Ω ∗ External applied voltage –6– CXA1310AQ No. Symbol I/O signal Equivalent circuit Description T 40µA 29 BLK High: 4.5V and above∗ Low: 0.5V and below T: 11µs BLK pulse input pin (active at Low) 29 150Ω T 50µA 30 CLP1 31 VCC2 32 VIDEO High: 4.5V and above∗ Low: 0.5V and below T: 2µs CLP1 pulse input pin (active at High) 30 150Ω 5V∗ Driver and IRIS power supply 32 VIDEO signal output pin BLK level 1.5V ∗ External applied voltage –7– CXA1310AQ Electrical Characteristics (Ta = 25°C, VCC = 5V, See Electrical Characteristics Test Circuit) Symbol Conditions No. Item 1 Current consumption lcc Current value of VCC1 and VCC2 AGC CONT = 1.5V 30 45 60 mA 2 Min. value of AGC MAX MAX GAIN between DATA input and AGC OUT DATA input = 100mV AGC MAX = 4V, AGC CONT = 1.5V — 18 20 dB 3 Min. value of AGC CONT AG1 GAIN between DATA input and AGC OUT DATA input = 500mV, AGC CONT = 5V — 4 6 dB 4 Max. value of AGC CONT AG2 GAIN between DATA input and AGC OUT DATA input = 30mV, AGC CONT = 1.5V 30 32 — dB 5 AGC CONT 10dB AG3 GAIN between DATA input and AGC OUT DATA input = 320mV, AGC CONT = 3.55V 8 10 12 dB 6 AGC OUT DC ADC DC output level of AGC OUT 2.25 2.55 2.85 V 7 γ 1 output level γ1 Test value of γ 1 output level γ IN input = 500mV 530 630 730 mV 8 γ 2 output level γ2 Test value of γ 2 output level γ IN input = 500mV, S9 ON 580 680 780 mV 9 LlNEAR AMP GAlN LG GAIN between γ IN input and LINEAR γ IN input = 500mV 1.6 2.6 3.6 dB 10 DET OUT DC DDC DC output level of DET OUT 1.8 2.0 2.2 V 11 IRlS AMP GAlN lG GAIN between DATA input and lRlS DATA input = 300mV 8 10 12 dB 12 IRIS OUT DC lDC DC output level of IRIS 1.1 1.3 1.5 V 13 DRlVER GAlN DG 5.7 6.0 6.3 dB 14 SYNC level SY 270 293 316 mV 15 SETUP 1 SE1 –15 0 15 mV 16 SETUP 2 SE2 0 20 40 mV 17 Min. value of SET CONT SE3 — –3 15 mV 18 Max. value of SET CONT SE4 80 130 — mV 19 W-CLIP level WC1 780 820 860 mV 20 Min. value of WC CONT WC2 — 300 600 mV 21 Max. value of WC CONT WC3 — mV 22 OP AMP output D range Low level OPL DC output level of OP OUT OP IN+ = 2.5V, OP lN– = 4V — 0.8 1.2 V 23 OP AMP output D range High level OPH DC output level of OP OUT OP IN+ = 4V, OP lN– = 2.5V 4.5 4.8 — V GAIN between DRlVER lN and VlDEO DRlVER IN = 700mV SYNC level/DG∗ of VIDEO output SETUP level of preset mode 1 SETUP level/DG∗ of VIDEO output SETUP level of preset mode 2 SETUP level/DG∗ of VIDEO output SETUP level/DG∗ of VIDEO output SET CONT = 2V SETUP level/DG∗ of VIDEO output SET CONT = 3.3V W-CLlP level /DG∗ of VlDEO output DRlVER IN = 1500mV, WC CONT = GND W-CLlP level /DG∗ of VlDEO output DRlVER IN = 1500mV, WC CONT = 2.2V W-CLlP level /DG∗ of VlDEO output DRlVER IN = 1500mV, WC CONT = 3.3V –8– Min. Typ. Max. Unit 1000 1300 ∗ Characteristics value at DRlVER GAlN item CXA1310AQ Electrical Characteristics Test Circuit 5V V 24 23 22 21 20 19 18 PG DATA SHD1 SHD2 OP IN+ OP IN– 0.1 SHP 0.1 17 OP OUT 5V 25 CLP2 AGC CONT 16 26 GND3 VCC1 15 (5V) 5V V A 27 IRIS AGC MAX 14 28 IRIS CLP DET OUT 13 V 29 BLK AGC OUT 12 V (0V) 0.01 30 CLP1 γ IN 11 31 VCC2 γ CLP 10 GND1 SYNC SET CONT WC CONT DRIVER IN γ OUT V GND2 A SAG 5V 1 2 3 4 5 6 7 8 32 VIDEO LINEAR 9 0.01 V 5V S9 0.01 V (0V) (0V) Notes) 1. µF is the capacitance unit of the capacitor. 2. For Pins 5, 6, 14 and 16, apply voltage in brackets unless otherwise specified in the conditions column of the Electrical Characteristics. 3. V indicates a test pin. (Test AC, DC voltage) 4. For Pins 7, 11 and 22, the input signal level is at 0mV, unless otherwise specified in the conditions column of the Electrical Characteristics. –9– CXA1310AQ Test Circuit I/O Waveform Diagram Input waveform Input pin 2.4V Input level 22. DATA 11. γ IN Input level 2.5V Input level 7. DRIVER IN 2.7V 5V 4. SYNC 5µs 0V 5V 29. BLK 15µs 50µs 0V 5V 30. CLP1 2µs 0V 5V 25. CLP2 2µs 0V Output pin Output waveform 12. AGC OUT Test 8. γ 1, 2 OUT Test 9. LINEAR Test 13. DET OUT Test 27. IRIS Test 32. VIDEO Test SYNC level – 10 – CXA1310AQ Application Circuit 100 ∗2 CCD ∗1 10k 1k 100k TG 2700 22 21 20 19 18 SHD2 OP IN+ OP IN– 25 CLP2 1µ 0.01 10k 2k 17 OP OUT 23 SHD1 47p 24 DATA 2200 1M PG 2200 1k 2.2µF SHP 2.2µF 47p 5V 22µF AGC CONT 16 0.01 5V 26 GND3 IRIS CONT IRIS DET VCC1 15 10µF AGC MAX 14 27 IRIS 5V 36k 14k 0.01 28 IRIS CLP DET OUT 13 29 BLK AGC OUT 12 0.01 LPF 0.01 30 CLP1 γ IN 11 31 VCC2 γ CLP 10 1µF 100µF SAG GND2 GND1 SYNC SET CONT WC CONT DRIVER IN γ OUT 5V 75 1 2 3 4 5 6 7 8 10µF 32 VIDEO 10µF 5V LINEAR 9 0.1 75Ω OUT 2200 47P 2200 47p SG ∗1 Use a high FT transistor. (2SC3355) ∗2 Use a FET similar to 2SK152 or 2SK300. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – CXA1310AQ Example of Representative Characteristics (Vcc = 5V, Ta = 25°C) AGC MAX control characteristics 40 40 30 30 GAIN [dB] GAIN [dB] AGC control characteristics 20 10 20 10 0 0 0 1 2 3 AGC CONT [V] 4 5 0 1 2 3 AGC MAX [V] 4 5 Setup control characteristics White clip control characteristics 100 Preset Setup level [mV] White clip level [mV] 1000 800 600 50 Preset 400 Preset 0 0 1 2 3 WC CONT [V] 4 0 5 2 3 SET CONT [V] 4 γ 2 I/O characteristics γ 1 I/O characteristics 1000 γ 2 output level [mV] 1000 γ 1 output level [mV] 1 500 0 500 γ IN input level [mV] 500 0 1000 – 12 – 500 γ IN input level [mV] 1000 5 CXA1310AQ Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE – 13 – 0.50 8 + 0.15 0.3 – 0.1