16-Channel I2C-bus LED Driver with Programmable Blink Rate

CAT9552
16-Channel I2C-bus LED
Driver with Programmable
Blink Rate
Description
The CAT9552 is a 16−channel, parallel input/output port expander
optimized for LED On/Off and blinking control. Each individual LED
may be turned ON, OFF, or set to blinking at one of two programmable
rates. The CAT9552 is compatible with I2C and SMBus applications
where it is desireable to limit the bus traffic or free−up the bus master’s
internal timer. Three address pins allow up to eight CAT9552 devices
to occupy the same bus.
The CAT9552 contains an internal oscillator and two PWM signals,
which drive the LED outputs. The user may program the period and
duty cycle for each individual PWM signal. After an initial set−up
command to program the Blink Rate 1 and Blink Rate 2 (frequency
and duty cycle), only one command from the bus master is required to
turn each individual open drain output ON, OFF, or cycle at Blink
Rate 1 or Blink Rate 2. Each open drain LED output can sink a
maximum current of 25 mA. The total continuous current sunk by all
I/Os must not exceed 200 mA per package.
Features
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SOIC−24
W SUFFIX
CASE 751BK
TSSOP−24
Y SUFFIX
CASE 948AR
• 16 LED Drivers with On/Off and Programmable Blink Rate Control
• 2 Selectable, Programmable Blink Rates:
•
•
•
•
•
•
•
•
– Frequency: 0.172 Hz to 44 Hz
– Duty Cycle: 0% to 99.6%
16 Open Drain Outputs Drive 25 mA Each
I/Os can be Used as GPIOs
400 kHz I2C Bus Compatible
2.3 V to 5.5 V Operation
5 V Tolerant I/Os
Active Low Reset Input
24−Lead SOIC, TSSOP and 24−pad TQFN (4 x 4 mm) Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
TQFN−24
HT6 SUFFIX
CASE 510AN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
Applications
•
•
•
•
TQFN−24
HV6 SUFFIX
CASE 510AG
Office Machines
Appliance Control Panels
Alarm Systems
Point of Sale Displays
© Semiconductor Components Industries, LLC, 2011
December, 2011 − Rev. 0
1
Publication Order Number:
CAT9552/D
SCL
SDA
VCC
A0
VCC
1
A1
A0
A2
CAT9552
A1
SDA
A2
LED0
RESET
LED0
SCL
RESET
LED1
LED15
LED1
LED15
LED2
LED14
LED2
LED14
LED3
LED13
LED3
LED13
LED4
LED12
LED4
LED12
LED5
LED11
LED5
LED11
LED6
LED10
LED7
LED9
VSS
LED8
SOIC (W), TSSOP (Y)
(Top View)
5V
5V
RS0
3 x 10 kW
SDA
SDA
SCL
SCL
RESET
RS1
RS11
VCC
RESET
I2C/SMBus
LED0
LED1
CAT9552
Master
LED0 to LED11 are shown being
used as LED drivers
LED12 to LED15 are used as
standard GPIOs
LED10
LED9
TQFN (HV6, HT6)
(Top View)
Figure 1. Pin Configurations
Notes:
LED8
VSS
LED7
LED6
1
LED11
LED12
A2
A1
A0
VSS
GPIOs
LED15
Figure 2. Typical Application Circuit
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CAT9552
Table 1. PIN DESCRIPTION
SOIC / TSSOP
TQFN
Pin Name
Function
1
22
A0
Address Input 0
2
23
A1
Address Input 1
3
24
A2
Address Input 2
4−11
1−8
LED0 − LED7
12
9
VSS
13−20
10−17
LED8 − LED15
21
18
RESET
Reset Input
22
19
SCL
Serial Clock
23
20
SDA
Serial Data
24
21
VCC
−
Pad
Backside pad
A2
VCC
A1
LED Driver Output 0 to 7, I/O Port 0 to 7
Ground
LED Driver Output 8 to 15, I/O Port 8 to 15
Power Supply
For enhanced heat dissipation. Electrically this
pad must be at ground potential.
A0
POWER ON
RESET
INPUT
REGISTER
RESET
INPUT
FILTERS
SCL
SDA
LED SELECT (LSx)
REGISTER
I2C BUS
CONTROL
LEDx
OSCILLATOR
VSS
PRESCALER 0
REGISTER
PWM 0
REGISTER
BLINK 0
PRESCALER 1
REGISTER
PWM 1
REGISTER
BLINK 1
CONTROL
LOGIC
CAT9552
Note: Only one I/O is shown for clarity
Figure 3. Block Diagram
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
VCC with Respect to Ground
−2.0 to +7.0
V
Voltage on Any Pin with Respect to Ground
−0.5 to +5.5
V
DC Current on I/Os
±25
mA
Supply Current
200
mA
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Junction Temperature
+150
°C
Storage Temperature
−65 to +150
°C
300
°C
−40 to +85
°C
Lead Soldering Temperature (10 seconds)
Operating Ambient Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
CAT9552
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.3 to 5.5 V, VSS = 0 V; TA = −40°C to +85°C, unless otherwise specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
−
5.5
V
SUPPLIES
VCC
Supply Voltage
ICC
Supply Current
Operating mode; VCC = 5.5 V; no load;
fSCL = 100 kHz
−
250
550
mA
Istb
Standby Current
Standby mode; VCC = 5.5 V; no load;
VI = VSS or VCC, fSCL = 0 kHz
−
2.1
5.0
mA
Additional Standby Current
Standby mode; VCC = 5.5 V; every
LED I/O = VIN = 4.3 V, fSCL = 0 kHz
−
−
2
mA
Power−on Reset Voltage
VCC = 3.3 V, No load;
VI = VCC or VSS
−
1.5
2.2
V
ΔIstb
VPOR (Note 1)
SCL, SDA, RESET
VIL (Note 2)
Low Level Input Voltage
−0.5
−
0.3 VCC
V
VIH (Note 2)
High Level Input Voltage
0.7 VCC
−
5.5
V
IOL
Low Level Output Current
VOL = 0.4 V
3
−
−
mA
IIL
Leakage Current
VI = VCC = VSS
−1
−
+1
mA
CI (Note 3)
Input Capacitance
VI = VSS
−
−
6
pF
CO (Note 3)
Output Capacitance
VO = VSS
−
−
8
pF
A0, A1, A2
VIL (Note 2)
Low Level Input Voltage
−0.5
−
0.8
V
VIH (Note 2)
High Level Input Voltage
2.0
−
5.5
V
Input Leakage Current
−1
−
1
mA
−0.5
−
0.8
V
IIL
I/Os
VIL (Note 2)
Low Level Input Voltage
VIH (Note 2)
High Level Input Voltage
IOL (Note 4)
Low Level Output Current
IIL
CI/O (Note 3)
1.
2.
3.
4.
Input Leakage Current
2.0
−
5.5
V
VOL = 0.4 V; VCC = 2.3 V
9
−
−
mA
VOL = 0.4 V; VCC = 3.0 V
12
−
−
VOL = 0.4 V; VCC = 5.0 V
15
−
−
VOL = 0.7 V; VCC = 2.3 V
15
−
−
VOL = 0.7 V; VCC = 3.0 V
20
−
−
VOL = 0.7 V; VCC = 5.0 V
25
−
−
VCC = 3.6 V; VI = VSS or VCC
−1
−
1
mA
−
−
8
pF
Input/Output Capacitance
VDD must be lowered to 0.2 V in order to reset the device.
VIL min and VIH max are reference values only and are not tested.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
The output current must be limited to a maximum 25 mA per each I/O; the total current sunk by all I/O must be limited to 200 mA (or 100 mA
for eight I/Os)
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CAT9552
Table 4. A.C. CHARACTERISTICS (VCC = 2.3 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified) (Note 5)
Standard I2C
Symbol
Min
Parameter
FSCL
Max
Clock Frequency
tHD:STA
Fast I2C
Min
100
START Condition Hold Time
Max
Units
400
kHz
4
0.6
ms
tLOW
Low Period of SCL Clock
4.7
1.3
ms
tHIGH
High Period of SCL Clock
4
0.6
ms
4.7
0.6
ms
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
ms
tSU:DAT
Data In Setup Time
250
100
ns
tR (Note 6)
SDA and SCL Rise Time
tF (Note 6)
SDA and SCL Fall Time
tSU:STO
1000
300
STOP Condition Setup Time
tBUF (Note 6)
Bus Free Time Between STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
Ti (Note 6)
300
ns
300
ns
4
0.6
ms
4.7
1.3
ms
3.5
100
Noise Pulse Filtered at SCL and SDA Inputs
0.9
50
100
ms
ns
100
ns
PORT TIMING
tPV
Output Data Valid
tPS
Input Data Setup Time
100
ns
tPH
Input Data Hold Time
1
ms
Reset Pulse Width
10
ns
0
ns
400
ns
200
ns
RESET
tW (Note 6)
tREC
Reset Recovery Time
tRESET (Note 7)
Time to Reset
5. Test conditions according to “AC Test Conditions” table.
6. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
7. The full delay to reset the part will be the sum of tRESET and the RC time constant of the SDA line.
Table 5. AC TEST CONDITIONS
Input Pulse Voltage
0.2 VCC to 0.8 VCC
Input Rise and Fall Times
≤5 ns
Input Reference Voltage
0.3 VCC, 0.7 VCC
Output Reference Voltage
0.5 VCC
Output Load
Current source: IOL = 3 mA; 400 pF for fSCL(max) = 400 kHz
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tDH
tAA
SDA OUT
Figure 4. 2−Wire Serial Interface Timing
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tBUF
CAT9552
Pin Description
device can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
SCL: Serial Clock
I2C Bus Protocol
The serial clock input clocks all data transferred into or out
of the device. The SCL line requires a pull−up resistor if it
is driven by an open drain output.
The features of the I2C bus protocol are defined as follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition
(Figure 5).
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs. A pull−up resistor must be connected
from SDA line to VCC.
START and STOP Conditions
LED0−LED15: LED Driver Outputs/General Purpose I/Os
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9552 monitors the SDA and
SCL lines and will not respond until this condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
These pins are open drain outputs used to directly drive
LEDs. Any of these pins can be programmed to drive the
LED ON, OFF, or to Blink Rate1 or Blink Rate2. A current
limiting resistor should be placed in series with each LED to
control the maximum LED current. When not used for
controlling the LEDs, these pins may be used as general
purpose parallel input/output.
Device Addressing
RESET: External Reset Input
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9552 for a read or
write operation. The four most significant bits of the slave
address are fixed as binary 1100 (Figure 6). The CAT9552
uses the next three bits as address bits.
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7−bit slave address is the R/W bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
Following the START condition and the slave address byte,
the CAT9552 monitors the bus and responds with an
acknowledge (on the SDA line) when its address matches the
transmitted slave address. The CAT9552 then performs a read
or a write operation depending on the state of the R/W bit.
Active low Reset input is used to initialize the CAT9552
internal registers and the I2C state machine. The internal
registers are held in their default state while Reset input is
active. An external pull−up resistor of maximum 25 kW is
required when this pin is not actively driven.
Functional Description
The CAT9552 is a 16−channel I/O bus expander that
provides a pair of programmable LED blinkers, controlled
through an I2C compatible serial interface.
The CAT9552 supports the I2C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and any
device receiving data to be a receiver. The transfer is controlled
by the Master device which generates the serial clock and all
START and STOP conditions for bus access. The CAT9552
operates as a Slave device. Both the Master device and Slave
SDA
SCL
START CONDITION
STOP CONDITION
Figure 5. Start/Stop Timing
SLAVE ADDRESS
1
1
0
FIXED
0
A2
A1
A0 R/W
PROGRAMMABLE
HARDWARE SELECTABLE
Figure 6. CAT9552 Slave Address
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CAT9552
Acknowledge
a stop condition to return the CAT9552 to the standby power
mode and place the device in a known state.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data. The SDA line
remains stable LOW during the HIGH period of the
acknowledge related clock pulse (Figure 7).
The CAT9552 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8− bit
byte.
When the CAT9552 begins a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT9552 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition. The master must then issue
Registers and Bus Transactions
After the successful acknowledgement of the slave
address, the bus master will send a command byte to the
CAT9552 which will be stored in the Control Register. The
format of the Control Register is shown in Figure 8.
The Control Register acts as a pointer to determine which
register will be written or read. The four least significant
bits, B0, B1, B2, B3, are used to select which internal
register is accessed, according to the Table 6.
If the auto increment flag is set (AI = 1), the four least
significant bits of the Control Register are automatically
incremented after a read or write operation. This allows the
user to access the CAT9552 internal registers sequentially.
The content of these bits will rollover to “0000” after the last
register is accessed.
Table 6. INTERNAL REGISTERS SELECTION
B3
B2
B1
B0
Register Name
Type
0
0
0
0
INPUT0
READ
Input Register 0
0
0
0
1
INPUT1
READ
Input Register 1
0
0
1
0
PSC0
READ/WRITE
Frequency Prescaler 0
0
0
1
1
PWM0
READ/WRITE
PWM Register 0
0
1
0
0
PSC1
READ/WRITE
Frequency Prescaler 1
0
1
0
1
PWM1
READ/WRITE
PWM Register 1
0
1
1
0
LS0
READ/WRITE
LED 0−3 Selector
0
1
1
1
LS1
READ/WRITE
LED 4−7 Selector
1
0
0
0
LS2
READ/WRITE
LED 8−11 Selector
1
0
0
1
LS3
READ/WRITE
LED 12−15 Selector
SCL FROM
MASTER
Register Function
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7. Acknowledge Timing
0
0
RESET STATE: 00h
0
AI
B3
B2
B1
B0
REGISTER ADDRESS
AUTO−INCREMENT FLAG
Figure 8. Control Register
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CAT9552
Input Register 0 and Input Register 1 reflect the incoming logic levels of the I/O pins, regardless of whether the pin is defined
as an input or an output. These registers are read only ports. Writes to the input registers will be acknowledged but will have
no effect.
Table 7. INPUT REGISTER 0 AND INPUT REGISTER 1
INPUT0
LED 7
LED 6
LED 5
LED 4
LED 3
LED 2
LED 1
LED 0
bit
7
6
5
4
3
2
1
0
default
X
X
X
X
X
X
X
X
LED 15
LED 14
LED 13
LED 12
LED 11
LED 10
LED 9
LED 8
bit
7
6
5
4
3
2
1
0
default
X
X
X
X
X
X
X
X
INPUT1
The Frequency Prescaler 0 and Frequency Prescaler 1
registers (PSC0, PSC1) are used to program the period of the
pulse width modulated signals BLINK0 and BLINK1
respectively:
T_BLINK0 = (PSC0 + 1) / 44;
T_BLINK1 = (PSC1 + 1) / 44
Every LED driver output can be programmed to one of
four states, LED OFF, LED ON, LED blinks at BLINK0 rate
and LED blinks at BLINK1 rate using the LED Selector
Registers (Table 10).
Table 10. LED SELECTOR REGISTERS
LS0
Table 8. FREQUENCY PRESCALER 0 AND
FREQUENCY PRESCALER 1 REGISTERS
LED 3
PSC0
bit
7
6
5
4
3
2
1
0
default
1
1
1
1
1
1
1
1
bit
7
6
5
4
3
2
1
0
default
1
1
1
1
1
1
1
1
4
3
2
1
0
default
1
0
0
0
0
0
0
0
bit
7
6
5
4
3
2
1
0
default
1
0
0
0
0
0
0
0
6
5
4
3
2
1
0
default
0
1
0
1
0
1
0
1
LED 6
LED 5
LED 4
bit
7
6
5
4
3
2
1
0
default
0
1
0
1
0
1
0
1
LED 11
LED 10
bit
7
6
5
4
3
LED 9
2
1
LED 8
0
default
0
1
0
1
0
1
0
1
LS3
LED 15
LED 14
LED 13
LED 12
bit
7
6
5
4
3
2
1
0
default
0
1
0
1
0
1
0
1
The LED output (LED0 to LED15) is set by the 2 bit value
from the corresponding LSx Register (x = 0 to 3):
00 = LED Output set LOW (LED On)
01 = LED Output set Hi−Z (LED Off – Default)
10 = LED Output blinks at BLINK0 Rate
11 = LED Output blinks at BLINK1 Rate
PWM0
5
7
LS2
Table 9. PWM REGISTER 0 AND PWM REGISTER 1
6
LED 0
bit
LED 7
The PWM Register 0 and PWM Register 1 (PWM0,
PWM1) are used to program the duty cycle of BLINK0 and
BLINK1 respectively:
Duty Cycle_BLINK0 = (256 − PWM0) / 256;
Duty Cycle_BLINK1 = (256 − PWM1) / 256
After writing to the PWM0/1 register an 8−bit internal
counter starts to count from 0 to 255. The outputs are low (LED
on) when the counter value is less than the value programmed
into PWM register. The LED is off when the counter value is
higher than the value written into PWM register.
7
LED 1
LS1
PSC1
bit
LED 2
PWM1
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CAT9552
Write Operations
LED Pins Used as General Purpose I/O
Data is transmitted to the CAT9552 registers using the
write sequence shown in Figure 9.
If the AI bit from the command byte is set to “1”, the
CAT9552 internal registers can be written sequentially.
After sending data to one register, the next data byte will be
sent to the next register sequentially addressed.
Any LED pins not used to drive LEDs can be used as
general purpose input/output, GPIO.
When used as input, the user should program the
corresponding LED pin to Hi−Z (“01” for the LSx register
bits). The pin state can be read via the Input Register
according to the sequence shown in Figure 11.
For use as a logic output, an external pull−up resistor
should be connected to the pin. The value of the pull−up
resistor is calculated according to the DC operating
characteristics. To set the output high, the user has to
program the output Hi−Z writing “01” into the
corresponding LED Selector (LSx) register bits. The output
pin is set low when the output is programmed low through
the LSx register bits (“00” in LSx register bits).
GPIO can also be used as PWM outputs by setting the
LED Selector (LSx) register to “10” or “11” to output either
the BLINK0 or BLINK1 waveform.
Read Operations
The CAT9552 registers are read according to the timing
diagrams shown in Figure 10 and Figure 11. Data from the
register, defined by the command byte, will be sent serially
on the SDA line.
After the first byte is read, additional data bytes may be
read when the auto−increment flag, AI, is set. The additional
data byte will reflect the data read from the next register
sequentially addressed by the (B3, B2, B1, B0) bits of the
command byte.
When reading Input Port Registers (Figure 11), data is
clocked into the register on the failing edge of the
acknowledge clock pulse. The transfer is stopped when the
master will not acknowledge the data byte received and issue
the STOP condition.
SCL
1 2 3 4 5 6 7 8
Slave Address
9
Command Byte
Data To Register 1
SDA S 1 1 0 0 A2 A1 A0 0 A 0 0 0 AI B3 B2 B1 B0 A
Start Condition
R/W
Acknowledge
From Slave
Data To Register 2
A
DATA 1
Acknowledge
From Slave
1.0 A
Acknowledge
From Slave
WRITE TO REGISTER
DATA OUT FROM PORT
tpv
Figure 9. Write to Register Timing Diagram
Slave Address
S 1
Acknowledge
From Slave
1 0 0 A2 A1 A0 0 A
R/W
Acknowledge
From Slave
COMMAND BYTE
A S
Slave Address
Acknowledge From Master
Acknowledge
From Slave Data From Register
1 1 0 0 A2 A1 A0 1 A MSB
At This Moment Master−Transmitter
Becomes Master−receiver and
Slave−Receiver Becomes
Slave−Transmitter
R/W
First Byte
Auto−increment
Register Address
If AI = 1
Data From Register
MSB
Note: Transfer can be stopped at any time by a STOP condition.
DATA
Last Byte
Figure 10. Read from Register Timing Diagram
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LSB A
DATA
No Acknowledge
From Master
LSB NA P
CAT9552
External Reset Operation
Power−On Reset Operation
The CAT9552 registers and the I2C state machine are
initialized to their default state when the RESET input is
held low for a minimum of tW. CAT9552’s registers will be
held in their default state until RESET returns to a logic
HIGH state. The external Reset timing is shown in
Figure 12.
Slave Address
SDA
S
1
1
0
Data From Port
0 A2 A1 A0
Start Condition
The CAT9552 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device is in a reset state for VCC
less than the internal POR threshold level (VPOR). When
VCC exceeds the VPOR level, the reset state is released and
the CAT9552 internal state machine and registers are
initialized to their default state. Thereafter VCC must be
taken below 0.2 V to reset the device.
R/W
Data From Port
A
DATA 1
A
Acknowledge
From Slave
DATA 4
Acknowledge
From Master
No Acknowledge
From Master
READ FROM
PORT
DATA INTO
PORT
DATA 1
DATA 2
DATA 3
tph
DATA 4
tps
Figure 11. Read Input Port Register Timing Diagram
START
ACK OR READ CYCLE
SCL
SDA
30%
tRESET
RESET
50%
50%
50%
tW
tRESET
tREC
LEDx
50% LED OFF
Figure 12. RESET Timing Diagram
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10
NA P
Stop
Condition
CAT9552
Application Information
Command Description
I2C Data
Programming Example
1
START
The following programming sequence is an example how
to set:
• LED0 to LED3: ON
• LED4 to LED7: Blink at 1 Hz with a 50% duty cycle
(Blink 0)
• LED8 to LED11: Blink at 4 Hz with a 20% duty cycle
(Blink 1)
• LED12 to LED15: OFF
2
Send Slave address, A0−A2 = low
C0h
3
Command Byte: AI=”1”; PSC0 Addr
12h
4
Set Blink 0 at 1 Hz, T_Blink1 =
(PSC0+1)/44 = 1
Write PSC0 = 43
2Bh
5
Set PWM0 duty cycle to 50%
(256−PWM0) / 256 = 0.5
Write PWM0=128
80h
6
Set Blink 1 at 4 Hz, T_Blink1 =
(PSC1+1)/44 = 0.25
Write PSC1 = 10
0Ah
7
Set PWM1 duty cycle to 25%
(256−PWM1) / 256 = 0.25
Write PWM1=192
C0h
8
Write LS0: LED0 to LED3 = ON
00h
9
Write LS1: LED4 to LED7 at Blink0
AAh
10
Write LS2: LED8 to LED11 at Blink1
FFh
11
Write LS3: LED12 to LED15 = OFF
55h
12
STOP
5V
5V
VCC
10 kW (x 3)
LED0
LED1
SDA
LED2
LED3
SCL
LED4
LED5
RESET
LED6
LED7
CAT9552
LED8
LED9
A2
LED10
A1
LED11
A0
LED12
VSS
LED13
LED14
LED15
VCC
SDA
SCL
RESET
GND
I2C/SMBus MASTER
GPIOs
Note: LED0 to LED11 are used as LED drivers and LED12 to LED15 are used as regular GPIOs.
Figure 13. Typical Application
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11
CAT9552
PACKAGE DIMENSIONS
SOIC−24, 300 mils
CASE 751BK−01
ISSUE O
E1
SYMBOL
MIN
A
2.35
E
e
PIN#1 IDENTIFICATION
MAX
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
e
b
NOM
7.60
1.27 BSC
h
0.25
0.75
L
0.40
1.27
θ
0º
8º
θ1
5º
15º
TOP VIEW
h
D
A2
A
A1
SIDE VIEW
h
q1
q
q1
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
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12
c
CAT9552
PACKAGE DIMENSIONS
TSSOP24, 4.4x7.8
CASE 948AR−01
ISSUE A
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
D
7.70
7.80
7.90
E
6.25
6.40
6.55
E1
4.30
4.40
4.50
e
L
0.65 BSC
0.50
L1
θ
0.20
0.60
0.70
1.00 REF
0º
8º
e
TOP VIEW
D
c
A2
A θ1
L
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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13
L1
CAT9552
PACKAGE DIMENSIONS
TQFN24, 4x4
CASE 510AG−01
ISSUE B
A
D
DETAIL A
E
E2
PIN#1 ID
PIN#1 INDEX AREA
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
A3
b
0.20
2.70
e
0.05
0.25
L
0.30
2.80
DETAIL A
2.90
4.00 BSC
2.70
e
L
b
4.00 BSC
E
E2
BOTTOM VIEW
0.20 REF
D
D2
D2
A1
2.80
2.90
0.50 BSC
0.30
0.50
A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-220.
(3) Minimum space between leads and flag cannot be smaller than 0.15 mm.
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14
FRONT VIEW
A3
CAT9552
PACKAGE DIMENSIONS
TQFN24, 4x4 TA
CASE 510AN−01
ISSUE O
A
D
DETAIL A
E
E2
PIN#1 ID
PIN#1 INDEX AREA
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
−
0.05
A3
b
0.20
0.25
−
e
L
0.30
DETAIL A
2.20
4.00 BSC
2.00
e
L
b
4.00 BSC
2.00
E
E2
BOTTOM VIEW
0.20 REF
D
D2
D2
A1
−
2.20
0.50 BSC
0.30
−
0.50
A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-220.
(3) Minimum space between leads and flag cannot be smaller than 0.15 mm.
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FRONT VIEW
A3
CAT9552
Table 11. ORDERING INFORMATION
Device Order
Number
Specific
Device
Marking
Package Type
Temperature
Range
Lead
Finish
Shipping
CAT9552HT6I−GT2
MAAE
TQFN−24
−40°C to +85°C
NiPdAu
Tape & Reel, 2,000 Units / Reel
CAT9552HV6I−GT2
LAAE
TQFN−24
−40°C to +85°C
NiPdAu
Tape & Reel, 2,000 Units / Reel
CAT9552WI−T1
9552W
SOIC−24, JEDEC
−40°C to +85°C
Matte−Tin
Tape & Reel, 1,000 Units / Reel
CAT9552YI−T2
CAT9552Y
TSSOP−24
−40°C to +85°C
Matte−Tin
Tape & Reel, 2,000 Units / Reel
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. For additional temperature options, please contact your nearest ON Semiconductor Sales office.
10. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor is licensed by Philips Corporation to carry the I2C Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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16
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAT9552/D
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