CAT5411 D

CAT5411
Dual Digital
Potentiometer (POT)
with 64 Taps
and SPI Interface
http://onsemi.com
Description
The CAT5411 is two digital potentiometers (POTs) integrated with
control logic and 16 bytes of NVRAM memory. Each digital POT
consists of a series of 63 resistive elements connected between two
externally accessible end points. The tap points between each resistive
element are connected to the wiper outputs with CMOS switches. A
separate 6-bit control register (WCR) independently controls the
wiper tap switches for each digital POT. Associated with each wiper
control register are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the wiper control
register or any of the non-volatile data registers is via a SPI serial bus.
On power-up, the contents of the first data register (DR0) for each of
the two potentiometers is automatically loaded into its respective
wiper control register.
The CAT5411 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.








Two Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via SPI Interface:
Mode (0, 0) and (1, 1)
Low Wiper Resistance, Typically 80 W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
24-lead SOIC and 24-lead TSSOP
Industrial Temperature Ranges
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
VCC
NC
1
RL0
NC
RH0
NC
RW0
NC
CS
A0
WP
Features




TSSOP24
Y SUFFIX
CASE 948AR
SI
CAT5411
SO
HOLD
SCK
A1
RL1
NC
RH1
NC
RW1
NC
GND
NC
SOIC−24 (W)
(Top View)
SI
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
SCK
HOLD
1
CAT5411
WP
CS
RW0
RH0
RL0
VCC
NC
NC
NC
NC
A0
SO
TSSOP24 (Y)
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
 Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 13
1
Publication Order Number:
CAT5411/D
CAT5411
MARKING DIAGRAMS
(SOIC−24)
(TSSOP−24)
L3B
CAT5411WT
−RRYMXXXX
RLB
CAT5411YT
3YMXXX
R = Resistance
1 = 2.5 KW
2 = 10 KW
4 = 50 KW
5 = 100 KW
L = Assembly Location
B = Product Revision (Fixed as “B”)
CAT5411Y = Device Code
T = Temperature Range (I = Industrial)
3 = Lead Finish − Matte-Tin
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
L = Assembly Location
3 = Lead Finish − Matte-Tin
B = Product Revision (Fixed as “B”)
CAT = Fixed as “CAT”
5411W = Device Code
T = Temperature Range (I = Industrial)
− = Dash
RR = Resistance
25 = 2.5 KW
10 = 10 KW
50 = 50 KW
00 = 100 KW
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
RH0
CS
SCK
SI
SO
SPI BUS
INTERFACE
RH1
WIPER
CONTROL
REGISTERS
RW0
RW1
WP
A0
A1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0
Figure 1. Functional Diagram
http://onsemi.com
2
RL1
CAT5411
PIN DESCRIPTIONS
SI: Serial Input
HOLD: Hold
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5411. Input data is latched on the rising edge of the
serial clock.
The HOLD pin is used to pause transmission to the
CAT5411 while in the middle of a serial sequence without
having to re-transmit entire sequence at a later time. To
pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to VCC or
tied to VCC through a resistor.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5411. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5411. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
Table 1. PIN CONNECTIONS
Pin
SOIC
Pin
TSSOP
Name
1
19
VCC
Supply Voltage
2
20
RL0
Low Reference Terminal
for Potentiometer 0
3
21
RH0
High Reference Terminal
for Potentiometer 0
4
22
RW0
Wiper Terminal for
Potentiometer 0
5
23
CS
Chip Select
6
24
WP
Write Protection
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
7
1
SI
Serial Input
8
2
A1
Device Address
RW: Wiper
9
3
RL1
The four RW pins are equivalent to the wiper terminal of
a mechanical potentiometer.
Low Reference Terminal
for Potentiometer 1
10
4
RH1
High Reference Terminal
for Potentiometer 1
CS: Chip Select
11
5
RW1
Wiper Terminal for
Potentiometer 1
12
6
GND
Ground
13
7
NC
No Connect
14
8
NC
No Connect
15
9
NC
No Connect
16
10
NC
No Connect
17
11
SCK
18
12
HOLD
19
13
SO
Serial Data Output
20
14
A0
Device Address, LSB
21
15
NC
No Connect
22
16
NC
No Connect
23
17
NC
No Connect
24
18
NC
No Connect
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5411.
RH, RL: Resistor End Points
CAT5251 and CS high disables the CAT5411. CS high
takes the SO output pin to high impedance and forces the
devices into a Standby mode (unless an internal write
operation is underway). The CAT5411 draws ZERO current
in the Standby mode. A high to low transition on CS is
required prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what initiates
an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high. When
WP is tied low, all non-volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
http://onsemi.com
3
Function
Bus Serial Clock
Hold
CAT5411
DEVICE OPERATION
The CAT5411 is two resistor arrays integrated with SPI
serial interface logic, two 6-bit wiper control registers and
eight 6-bit, non-volatile memory data registers. Each resistor
array contains 63 separate resistive elements connected in
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (RH and RL).
RH and RL are symmetrical and may be interchanged. The tap
positions between and at the ends of the series resistors are
connected to the output wiper terminals (RW) by a CMOS
transistor switch. Only one tap point for each potentiometer
is connected to its wiper terminal at a time and is determined
by the value of the wiper control register. Data can be read or
written to the wiper control registers or the non-volatile
memory data registers via the SPI bus. Additional instructions
allow data to be transferred between the wiper control
registers and each respective potentiometer’s non-volatile
data registers. Also, the device can be instructed to operate in
an “increment/decrement” mode.
SERIAL BUS PROTOCOL
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The first
byte contains one of the six op-codes that define the
operation to be performed.
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5411 to interface directly with many of
today’s popular microcontrollers. The CAT5041 contains an
8-bit instruction register. The instruction set and the
operation codes are detailed in the instruction set Table 12.
Table 2. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Parameter
Symbol
Reference Test Method
NEND (Note 1)
Endurance
MIL−STD−883, Test Method 1033
Min
Typ
Max
Units
1,000,000
Cycles/Byte
TDR (Note 1)
Data Retention
MIL−STD−883, Test Method 1008
100
Years
VZAP (Note 1)
ESD Susceptibility
MIL−STD−883, Test Method 3015
2000
Volts
ILTH (Note 1)
Latch-up
JEDEC Standard 17
100
mA
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 3. ABSOLUTE MAXIMUM RATINGS
Ratings
Units
Temperature Under Bias
Parameters
−55 to +125
C
Storage Temperature Range
−65 to +150
C
−2.0 to VCC +2.0
V
−2.0 to +7.0
V
Package Power Dissipation Capability (TA = 25C)
1.0
W
Lead Soldering Temperature (10 s)
300
C
Wiper Current
12
mA
Voltage to any Pins with Respect to VSS (Notes 2, 3)
VCC with Respect to GND
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
3. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V.
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameters
Ratings
Units
VCC
+2.5 to 6.0
V
Industrial Temperature
−40 to +85
C
http://onsemi.com
4
CAT5411
Table 5. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
RPOT
Potentiometer Resistance (−00)
100
kW
RPOT
Potentiometer Resistance (−50)
50
kW
RPOT
Potentiometer Resistance (−10)
10
kW
RPOT
Potentiometer Resistance (−25)
2.5
Potentiometer Resistance Tolerance
RPOT Matching
Power Rating
25C, each pot
IW
Wiper Current
RW
Wiper Resistance
IW = +3 mA @ VCC = 3 V
RW
Wiper Resistance
IW = +3 mA @ VCC = 5 V
VTERM
VN
Voltage on any RH or RL Pin
VSS = 0 V
Noise
80
GND
kW
+20
%
1
%
50
mW
+6
mA
300
W
150
W
VCC
V
(Note 4)
Resolution
nV/Hz
1.6
%
Absolute Linearity (Note 5)
RW(n)(actual)−R(n)(expected)
(Note 8)
+1
LSB
(Note 7)
Relative Linearity (Note 6)
RW(n+1)−[RW(n)+LSB]
(Note 8)
+0.2
LSB
(Note 7)
TCRPOT
Temperature Coefficient of RPOT
(Note 4)
TCRATIO
Ratiometric Temp. Coefficient
(Note 4)
CH/CL/CW
Potentiometer Capacitances
(Note 4)
10/10/25
pF
RPOT = 50 kW (Note 4)
0.4
MHz
fc
Frequency Response
+300
ppm/C
20
ppm/C
4. This parameter is tested initially and after a design or process change that affects the parameter.
5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
6. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
7. LSB = RTOT / 63 or (RH − RL) / 63, single pot
8. n = 0, 1, 2, ..., 63
Table 6. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Max
Units
1
mA
VIN = GND or VCC; SO Open
1
mA
VIN = GND to VCC
10
mA
VOUT = GND to VCC
10
mA
−1
VCC x 0.3
V
VCC x 0.7
VCC + 1.0
V
0.4
V
ICC
Power Supply Current
fSCK = 2 MHz, SO
Open Inputs = GND
ISB
Standby Current (VCC = 5 V)
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL1
Output Low Voltage (VCC = 3 V)
IOL = 3 mA
http://onsemi.com
5
Min
CAT5411
Table 7. PIN CAPACITANCE (Note 9)
(Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0 V (unless otherwise noted).)
Test Conditions
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0 V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0 V
Symbol
COUT
CIN
Min
Typ
Table 8. POWER UP TIMING (Note 9) (Over recommended operating conditions unless otherwise stated.)
Max
Units
tPUR (Note 10)
Symbol
Power-up to Read Operation
Parameter
Min
Typ
1
ms
tPUW (Note 10)
Power-up to Write Operation
1
ms
9. This parameter is tested initially and after a design or process change that affects the parameter.
10. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 9. ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tWH
SCK High Time
125
ns
tWL
SCK Low Time
125
ns
fSCK
Clock Frequency
DC
3
MHz
HOLD to Output Low Z
50
ns
tRI (Note 11)
Input Rise Time
2
ms
tFI (Note 11)
Input Fall Time
2
ms
tLZ
tHD
HOLD Setup Time
tCD
HOLD Hold Time
tWC
Write Cycle Time
tV
CL = 50 pF
100
ns
100
ns
Output Valid from Clock Low
5
ms
250
ns
tHO
Output Hold Time
tDIS
Output Disable Time
0
250
ns
ns
tHZ
HOLD to Output High Z
100
ns
tCS
CS High Time
250
ns
tCSS
CS Setup Time
250
ns
tCSH
CS Hold Time
250
ns
11. This parameter is tested initially and after a design or process change that affects the parameter.
Table 10. POTENTIOMETER AC CHARACTERISTICS
Symbol
Parameter
Max
Units
tWRL
Wiper response time after instruction issued (all load instructions)
10
ms
tWRID
Wiper response time from an active SCK edge (Increment/decrement instruction)
5
ms
http://onsemi.com
6
CAT5411
tCS
VIH
CS
VIL
tCSS
SCK
VIH
tWL
tWH
VIL
tH
tSU
VIH
SI
tCSH
VALID IN
VIL
tRI
tFI
tV
SO
VOH
tHO
tDIS
HI−Z
HI−Z
VOL
Figure 2. Synchronous Data Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Figure 3. HOLD Timing
http://onsemi.com
7
CAT5411
INSTRUCTION AND REGISTER DESCRIPTION
Device Type/Address Byte
Instruction Byte
The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5411 are fixed at
0101[B] (refer to Figure 4).
The two least significant bits in the slave address byte, A1
− A0, are the internal slave address and must match the
physical device address which is defined by the state of the A1
− A0 input pins for the CAT5411 to successfully continue the
command sequence. Only the device which slave address
matches the incoming device address sent by the master
executes the instruction. The A1 − A0 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS. The
remaining two bits in the device address byte must be set to 0.
The next byte sent to the CAT5411 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The R1 and
R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits point
to one of two Wiper Control Registers. The format is shown
in Figure 5.
Table 11. DATA REGISTER SELECTION
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Device Type Identifier
ID3
0
ID2
ID1
1
0
Slave Address
ID0
0
0
A1
A0
1
(MSB)
(LSB)
Figure 4. Identification Byte Format 0101 Device Type Identifier (MSB)
Instruction Opcode
I3
I2
(MSB)
I1
WCR/Pot Selection
Data Register Selection
I0
R1
R0
0
P0
(LSB)
Figure 5. Instruction Byte Format
CS
SCK
SI
...
...
MSB
tWRL
LSB
VW/RW
SO
High Impedance
Figure 6. Potentiometer Timing (for All Load Instructions)
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction, it can be
modified one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power-up.
The CAT5411 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 64 switches along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
http://onsemi.com
8
CAT5411
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non-volatile
operation and will take a maximum of 5 ms.
The Wiper Control Register is a volatile register that loses
its contents when the CAT5411 is powered-down. Although
the register is automatically loaded with the value in DR0
upon power-up, this may be different from the value present
at power-down.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS input goes HIGH after a
write sequence is received. The status of the internal write
cycle can be monitored by issuing a Read Status command
to read the Write in Process (WIP) bit.
Data Registers (DR)
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
INSTRUCTIONS
Four of the ten instructions are three bytes in length. These
instructions are:
 Read Wiper Control Register – read the current wiper
position of the selected potentiometer in the WCR
 Write Wiper Control Register – change current wiper
position in the WCR of the selected potentiometer
 Read Data Register – read the contents of the selected


Data Register
Write Data Register – write a new value to the
selected Data Register
Read Status – Read the status of the WIP bit which
when set to “1” signifies a write cycle is in progress.
Table 12. INSTRUCTION SET (Note: 1/0 = data is one or zero)
Instruction Set
Instruction
I3
I2
I1
I0
R1
R0
0
WCR0/ P0
Read Wiper Control Register
1
0
0
1
0
0
0
1/0
Read the contents of the Wiper Control
Register pointed to by P0
Write Wiper Control Register
1
0
1
0
0
0
0
1/0
Write new value to the Wiper Control Register
pointed to by P0
Read Data Register
1
0
1
1
1/0
1/0
0
1/0
Read the contents of the Data Register pointed
to by P0 and R1−R0
Write Data Register
1
1
0
0
1/0
1/0
0
1/0
Write new value to the Data Register pointed
to by P0 and R1−R0
XFR Data Register to Wiper
Control Register
1
1
0
1
1/0
1/0
0
1/0
Transfer the contents of the Data Register
pointed to by P0 and R1−R0 to its associated
Wiper Control Register
XFR Wiper Control Register
to Data Register
1
1
1
0
1/0
1/0
0
1/0
Transfer the contents of the Wiper Control
Register pointed to by P0 to the Data Register
pointed to by R1−R0
Global XFR Data Registers
to Wiper Control Registers
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data Registers
pointed to by R1−R0 of all four pots to their
respective Wiper Control Registers
Global XFR Wiper Control
Registers to Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1−R0 of all four pots
Increment/Decrement
Wiper Control Register
0
0
1
0
0
0
0
1/0
Enable Increment/decrement of the Control
Latch pointed to by P0
Read Status
0
1
0
1
0
0
0
1
Operations
Read WIP bit to check internal write cycle
status
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the CAT5411;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by tWRL.
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
http://onsemi.com
9
CAT5411
Increment/Decrement Command
 XFR Data Register to Wiper Control Register



The final command is Increment/Decrement (Figures 9
and 10). The Increment/Decrement command is different
from the other commands. Once the command is issued the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCK clock pulse (tHIGH) while SI is
HIGH, the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCK clock
pulse while SI is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instructions format for more detail.
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control Registers
to the specified associated Data Registers.
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3 A2 A1 A0
Internal
Address
Device ID
I3
I2
I1 I0 R1 R0 0 P0
Instruction
Opcode
Register Pot/WCR
Address Address
Figure 7. Two-byte Instruction Sequence
0
SI
1
0
1
0
0
ID3 ID2 ID1 ID0 A3 A2 A1 A0
I3
Internal
Address
Device ID
I2
I0 R1 R0 0 P0 D7 D6 D5 D4 D3 D2 D1 D0
I1
Instruction
Opcode
Data
Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 8. Three-byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3 A2 A1 A0
Device ID
Internal
Address
I3
I2
I1
I0
Instruction
Opcode
R1 R0 0
P0
I
N
C
Data Pot/WCR
Register Address 1
Address
I
N
C
2
I
N
C
n
Figure 9. Increment/Decrement Instruction Sequence
INC/DEC
Command
Issued
tWRL
SCK
SI
RW
Voltage Out
Figure 10. Increment/Decrement Timing Limits
http://onsemi.com
10
D
E
C
1
D
E
C
n
CAT5411
INSTRUCTION FORMAT
Table 13. READ WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
0
0
1
0
0
CS
DATA
0
P0
7
6
0
0
5
4
3
2
1
0
Table 14. WRITE WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
0
1
0
0
0
CS
DATA
0
P0
7
6
0
0
5
4
3
2
1
0
Table 15. READ DATA REGISTER (DR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
0
1
1
R1
R0
CS
DATA
0
P0
7
6
5
4
3
2
1
0
Table 16. WRITE DATA REGISTER (DR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
1
0
0
R1
R0
CS
DATA
0
P0
7
6
5
4
3
2
1
0
Table 17. READ STATUS (WIP)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
INSTRUCTION
A0
0
1
0
1
0
0
CS
DATA
0
1
7
6
0
0
5
4
3
2
1
W
I
P
Table 18. GLOBAL TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
CS
INSTRUCTION
A0
0
0
0
1
R1
R0
0
0
Table 19. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
CS
INSTRUCTION
A0
1
0
0
0
R1
R0
0
0
http://onsemi.com
11
High
Voltage
Write
Cycle
High
Voltage
Write
Cycle
CAT5411
Table 20. TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
CS
INSTRUCTION
A0
1
1
1
0
R1
R0
0
P0
High
Voltage
Write
Cycle
Table 21. TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
CS
INSTRUCTION
A0
1
1
0
1
R1
R0
0
P0
Table 22. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESS
0
1
0
1
0
0
A1
INSTRUCTION
A0
0
0
1
0
0
0
CS
DATA
0
P0
I/D
I/D
I/D
I/D
...
NOTE:
Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.
Table 23. ORDERING INFORMATION
Orderable Part Number
Resistance (kW)
CAT5411WI-25-T1
2.5
CAT5411WI-10-T1
10
CAT5411WI-50-T1
50
CAT5411WI-00-T1
100
CAT5411YI-25-T2
2.5
CAT5411YI-10-T2
10
CAT5411YI-50-T2
50
CAT5411YI-00-T2
100
CAT5411WI25
2.5
CAT5411WI10
10
CAT5411WI50
50
CAT5411WI00
100
CAT5411YI25
2.5
CAT5411YI10
10
CAT5411YI50
50
CAT5411YI00
100
Lead Finish
Package
Shipping†
SOIC−24
(Pb-Free)
1,000 / Tape & Reel
TSSOP24
(Pb-Free)
2,000 / Tape & Reel
SOIC−24
(Pb-Free)
31 Units / Tube
TSSOP24
(Pb-Free)
62 Units / Tube
Matte-Tin
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
12. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com.
13. All packages are RoHS-compliant (Pb-Free, Halogen Free).
14. The standard lead finish is Matte-Tin.
http://onsemi.com
12
CAT5411
PACKAGE DIMENSIONS
SOIC−24, 300 mils
CASE 751BK
ISSUE O
E1
SYMBOL
MIN
A
2.35
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
7.60
E
e
PIN#1 IDENTIFICATION
MAX
1.27 BSC
e
b
NOM
h
0.25
0.75
L
0.40
1.27
θ
0º
8º
θ1
5º
15º
TOP VIEW
h
D
A2
A
A1
SIDE VIEW
h
q1
q
q1
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
http://onsemi.com
13
c
CAT5411
PACKAGE DIMENSIONS
TSSOP24, 4.4x7.8
CASE 948AR
ISSUE A
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.80
7.90
E
6.25
6.40
6.55
E1
4.30
4.40
4.50
e
L
0.65 BSC
0.50
L1
θ
0.60
0.70
1.00 REF
0º
8º
e
TOP VIEW
D
c
A2
A θ1
L
A1
SIDE VIEW
END VIEW
L1
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
14
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAT5411/D
Similar pages