NUS3046MN Overvoltage Protection IC with Integrated MOSFET This device represents a new level of safety and integration by combining the NCP346 overvoltage protection circuit (OVP) with a 30 V P−channel power MOSFET. This IC is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such hazardous events, the IC quickly disconnects the input supply from the load, thus protecting the load before any damage can occur. The OVP IC is optimized for applications that use an external AC−DC adapter or a car accessory charger to power a portable product or recharge its internal batteries. It has a nominal overvoltage threshold of 5.5 V which makes it ideal for single cell Li−Ion as well as 3/4 cell NiCD/NiMH applications. Features • • • • • • • • Overvoltage Turn−Off Time of Less Than 1.0 ms Accurate Voltage Threshold of 5.5 V, Nominal Control Input Compatible with 1.8 V Logic Levels −30 V Integrated P−Channel Power MOSFET Low RDS(on) = 66 mW @ −4.5 V Low Profile 3.3 x 3.3 mm DFN Package Suitable for Portable Applications Maximum Solder Reflow temperature @ 260°C This is a Pb−Free Device Benefits • Provide Battery Protection • Integrated Solution Offers Cost and Space Savings • Integrated Solution Improves System Reliability Applications • Portable Computers and PDAs • Cell Phones and Handheld Products • Digital Cameras © Semiconductor Components Industries, LLC, 2009 May, 2009 − Rev. 2 http://onsemi.com MARKING DIAGRAM 8 1 1 DFN8 CASE 506AL 3046 AYWW G G 3046 = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT VCC 8 OUT 7 GATE 6 SRC 5 10 GND DRAIN 9 1 IN 2 GND 3 CNTRL 4 DRAIN (Bottom View) ORDERING INFORMATION Device Package Shipping† NUS3046MNT1G DFN8 (Pb−Free) 3000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NUS3046MN/D NUS3046MN Schottky Diode AC/DC Adapter of Accessory Charger SRC VCC DRAIN P−CH IN GATE + + Logic - FET Driver C1 LOAD OUT Vref NUS3046 CNTRL GND Microprocessor Port Figure 1. Simplified Schematic PIN FUNCTION DESCRIPTIONS Pin # Symbol Pin Description 1 IN 2, 10 GND 3 CNTRL This logic signal is used to control the state of OUT and turn−on/off the P−channel power MOSFET. A logic High results in the OUT signal being driven to within 1.0 V of VCC which disconnects the FET. If this pin is not used, the input should be connected to ground. 4, 9 DRAIN Drain pin of the P−channel power MOSFET 5 SRC Source pin of the P−channel power MOSFET 6 GATE Gate pin of the P−channel power MOSFET 7 OUT This signal drives the gate of a P−channel MOSFET. It is controlled by the voltage level on IN or the logic state of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of VCC in less than 1.0 msec provided that gate and stray capacitance is less than 12 nF. 8 VCC Positive Voltage supply. P−channel power MOSFET is guaranteed to be in ON state as long as VCC remains above 2.5 V and below the overvoltage threshold. This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (VTH), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the P−channel power MOSFET. The nominal threshold level is 5.5 V and this threshold level can be increased with the addition of an external resistor between IN and VCC. Circuit Ground OVERVOLTAGE PROTECTION CIRCUIT TRUTH TABLE IN CNTRL OUT <Vth L GND <Vth H VCC >Vth L VCC >Vth H VCC http://onsemi.com 2 NUS3046MN MAXIMUM RATINGS (TA = 25°C unless otherwise stated) Rating Pin Symbol Min Max Unit OUT Voltage to GND 7 VO −0.3 30 V Input and CNTRL Pin Voltage to GND 1 3 Vinput VCNTRL −0.3 −0.3 30 13 V VCC Maximum Range 8 VCC(max) −0.3 30 V Maximum Power Dissipation (Note 1) − PD − 1.0 W − RqJA − − 108.6 104.3 Junction Temperature − TJ − 150 °C Operating Ambient Temperature − TA −40 85 °C VCNTRL Operating Voltage 3 − 0 5.0 V Storage Temperature Range − Tstg −65 150 °C 1, 2, 3, 7, 8, 10 − 2.5 − kV −30 V 20 V −1.2 A Thermal Resistance Junction−to−Air (Note 1) OVP IC P−Channel FET ESD Performance (HBM) (Note 2) Drain−to−Source Voltage VDSS Gate−to−Source Voltage VGS Continuous Drain Current, Steady State, TA = 25°C (Note 1) ID −20 °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Human body model (HBM): MIL STD 883C Method 3015−7, (R = 1500 W, C = 100 pF, F = 3 pulses delay 1 s). http://onsemi.com 3 NUS3046MN OVERVOLTAGE PROTECTION IC ELECTRICAL CHARACTERISTICS (TA= 25°C, VCC = 6.0 V, unless otherwise specified) Characteristic Symbol Pin Min VCC(opt) 8 2.5(+3) − 25 V Isupply 1, 8 − 0.75 1.2 mA Input Threshold (VInput connected to VCC; VInput increasing) VTh 1 5.3 5.5 5.7 V Input Hysteresis (VInput connected to VCC; VInput decreasing) VHyst 1 20 50 200 mV Input Impedance (Input = VTh) Rin 1 30 60 100 kW CNTRL Voltage High (VCC = Vin = 4.0 V) Vih 3 1.5 − − V CNTRL Voltage Low (VCC = Vin = 4.0 V) Vil 3 − − 0.5 V CNTRL Current High (VihCNTRL = 5.0 V, VCC = Vin = 5.0 V) Iih 3 − 95 200 mA CNTRL Current Low (VilCNTRL = 0.5 V, VCC = Vin = 5.0 V) Iil 3 − 10 20 mA Output Sink Current (VCC = Vin = 5.0 V; VOUT = 1.0 V) ISink 7 4 10 16 mA Output Voltage High (VCC = Vin = 5.0 V; CNTRL = 0 V, ISource = 10 mA) Output Voltage High (VCC = Vin = 5.0 V; CNTRL = 0 V, ISource = 0.25 mA) Output Voltage High (VCC = Vin = 5.0 V; CNTRL = 0 V, ISource = 0 mA) Voh 7 VCC − 1.0 VCC − 0.25 VCC − 0.1 − − V Output Voltage Low (VCC = Vin = 5.0 V; ISink = 0 mA; CNTRL = 0 V) Vol 7 − − 0.1 V Turn ON Delay − Input (Note 3) (VInput connected to VCC; VInput step down signal from 6.0 to 5.0 V; measured to 50% point of OUT) TON IN 7 − 1.8 − ms Turn OFF Delay − Input (VInput connected to VCC; CNTRL = 0 V; VInput stepup signal from 5.0 to 6.0 V; CL = 12 nF; Output > VCC − 1.0 V) TOFF IN 7 − 0.5 1.0 ms Turn ON Delay − CNTRL (VCC = Vin = 5.0 V; CNTRL step down signal from 2.0 to 0.5 V; measured to 50% point of OUT) (Note 3) TON CT 7 − 10 − ms Turn OFF Delay − CNTRL (VCC = Vin = 5.0 V;CNTRL step up signal from 0.5 to 2.0 V; CL = 12 nF; Output > VCC −1.0 V) TOFF CT 7 − 0.6 1.0 ms VCC Operating Voltage Range Supply Current (ICC + IInput; VCC = 5.0 V Steady State) Typ Max Unit 3. Guaranteed by design. P−CHANNEL MOSFET ELECTRICAL CHARACTERISTICS (TA= 25°C unless otherwise specified) Symbol Parameter Drain to Source On Resistance VGS = −4.5 V, ID = −600 mA VGS = −4.5 V, ID = −1.0 A Min RDS(on) Zero Gate Voltage Drain Current VGS = 0 V, VDS = −24 V IDSS Turn On Delay (Note 4) VGS = −4.5 V, ID = −1.0 A, RG = 6.0 W, VDS = −15 V td(on) Turn Off Delay (Note 4) VGS = −4.5 V, ID = −1.0 A, RG = 6.0 W, VDS = −15 V td(off) Typ Max 66 66 110 110 Units mW mA −1.0 Input Capacitance (Note 3) VGS = 0 V, f = 1.0 MHz, VDS = −15 V V(BR)DSS Gate Threshold Voltage VGS = VDS, ID = −250 mA V(GS)th 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 4 pF 750 IGSS Drain to Source Breakdown Voltage VGS = 0 V, ID = −250 mA ns 28 Cin Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ns 11 nA ±10 V 30 −3.0 −1.0 V NUS3046MN Normal Operation which equates to: Figure 1 illustrates a typical configuration. The external adapter provides power to the protection system so the circuitry is only active when the adapter is connected. The OVP monitors the voltage from the charger and if the voltage exceeds the overvoltage threshold, Vth, the OUT signal drives the gate of the MOSFET to within 1.0 V of VCC, thus turning off the FET and disconnecting the source from the load. The nominal time it takes to drive the gate to this state is 400 nsec (1.0 msec maximum for gate capacitance of < 12 nF). The CNTRL input can be used to interrupt charging and allow the microcontroller to measure the cell voltage under a normal condition to get a more accurate measure of the battery voltage. Once the overvoltage is removed, the MOSFET will be turned on again. There are two events that will cause the OVP to turn off the MOSFET. • Voltage on IN Rises Above the Overvoltage Detection Threshold • CNTRL Input is Driven to a Logic HIGH VCC + Vx(1 ) R1ńR2 ) R1ńRin) So, as Rin approaches infinity: VCC + Vx(1 ) R1ńR2) Designing around the Maximum Voltage Rating Requirements, V(VCC, IN) The maximum breakdown voltage between pins VCC and IN is 15 V. Therefore, care must be taken that the design does not exceed this voltage. Normally, the designer shorts VCC to IN, V(VCC, IN) is shorted to 0 V, so there is no issue. However, one must take care when adjusting the overvoltage threshold. In Figure 2, the R1 resistor of the voltage divider divides the V(VCC, IN) voltage to a given voltage threshold equal to: (VCC, IN) + VCC * (R1ń(R1 ) (R2ńń Rin))) (eq. 4) V(VCC, IN) worst case equals 15 V, and VCC worst case equals 30 V, therefore, one must ensure that: The separate IN and VCC pins allow the user to adjust the overvoltage threshold, Vth, upwards by adding a resistor divider with the tap at the IN pin. However, the input impedance Rin does play a significant role in the calculation since it is several 10’s of kW (Rin = 54 kW typical). The following equation shows the effects of Rin. R1ń(R1 ) (R2ńń Rin)) t 0.5 (eq. 5) Where 0.5 = V(VCC, IN)max/VCCmax Therefore, the overvoltage threshold should be adjusted to voltage levels that are less than 15 V. If greater thresholds are desired, ON Semiconductor offers the NCP3045 which can withstand those voltages. (eq. 1) VCC R1 IN R2 (eq. 3) This shows that Rin shifts the Vth detection point in accordance to the ratio of R1 / Rin. However, if R1 << Rin, this shift can be minimized. The following steps show this procedure. Adjusting the Overvoltage Detection Point with External Resistors VCC + Vx(1 ) R1ń(R2ńńRin)) (eq. 2) Rin NUS3046 GND Figure 2. Voltage divider input to adjust overvoltage detection point http://onsemi.com 5 NUS3046MN Design Steps for Adjusting the Overvoltage Threshold The specification takes into account the hysteresis of the comparator, so the minimum input threshold voltage (Vth) is the falling voltage detection point and the maximum is the rising voltage detection point. One should design the input supply such that its maximum supply voltage in normal operation is less than the minimum desired overvoltage threshold. 8..Use worst case resistor tolerances to determine the maximum V(VCC,IN) 1..Use Typical Rin, and Vth Values from the Electrical Specifications 2..Minimize Rin Effect by Selecting R1 << Rin since: VOV + Vth(1 ) R1ńR2 ) R1ńRin). (eq. 6) 3..Let X = Rin / R1 = 100. 4..Identify Required Nominal Overvoltage Threshold. 5..Calculate nominal R1 and R2 from Nominal Values: R1 + RinńX V(VCC, IN) min + VCCmax * (R1minń(R1min ) R2max)) (eq. 12) (eq. 7) R1 R2 + (VOVńVth * R1ńRin * 1) (eq. 8) V(VCC, IN)typ + VCCmax * (R1typń(R1typ ) R2typ)) (eq. 13) 6..Pick Standard Resistor Values as Close as Possible to these Values V(VCC, IN) max + VCCmax * (R1maxń(R1max ) R2min)) (eq. 14) 7..Use min/max Data and Resistor Tolerances to Determine Overvoltage Detection Tolerance: VOVmin + Vthmin(1 ) R1min ń R2max ) R1min ń Rinmax) (eq. 9) VOVtyp + Vthtyp(1 ) R1typ ń R2typ ) R1typ ń Rintyp) (eq. 10) VOVmax + Vthmax(1 ) R1min R2max ) R1max ń Rinmin) (eq. 11) http://onsemi.com 6 NUS3046MN PACKAGE DIMENSIONS DFN8 CASE 506AL−01 ISSUE A PIN ONE REFERENCE 2X 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A D B ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 2X 0.15 C A (A3) 0.10 C STYLE 1: PIN 1. IN 2. GND 3. CNTRL 4. DRAIN 5. SOURCE 6. GATE 7. OUT 8. VCC 8X 0.08 C SEATING PLANE SIDE VIEW A1 D2 8X L C D2 1 SOLDERING FOOTPRINT* e 4 MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.35 0.40 0.45 3.30 BSC 0.95 1.05 1.15 3.30 BSC 1.80 1.90 2.00 0.80 BSC 0.21 −−− −−− 0.30 0.40 0.50 ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ 3.60 1 2X E2 2.95 8X K 8 5 8X 2X b 0.45 1.20 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ 8X 0.55 1.95 DIMENSIONS: MILLIMETERS 0.80 PITCH 2X 0.60 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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