5V ECL 3-Bit Scannable Registered Address Driver

MC10E212, MC100E212
5VECL 3-Bit Scannable
Registered Address Driver
The MC10E/100E212 is a scannable registered ECL driver typically
used as a fan-out memory address driver for ECL cache driving. In a
VLSI array based CPU design, use of the E212 allows the user to
conserve array output cell functionality and also output pins.
The input shift register is designed with control logic which greatly
facilitates its use in boundary scan applications.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAMS
1 28
Scannable Version E112 Driver
1025 ps Max. CLK to Output
MC10E212FN
Dual Differential Outputs
AWLYYWW
Master Reset
PECL Mode Operating Range: VCC= 4.2 V to 5.7 V
with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V
with VEE= −4.2 V to −5.7 V
Internal Input Pulldown Resistors
PLCC−28
FN SUFFIX
CASE 776
•
• ESD Protection: > 1 KV HBM, > 75 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
A
WL
YY
WW
1 28
= Assembly Location
= Wafer Lot
= Year
= Work Week
MC100E212FN
AWLYYWW
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL−94 code V−0 @ 1/8”,
•
ORDERING INFORMATION
Oxygen Index 28 to 34
Transistor Count = 259 devices
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 5
Device
1
Package
Shipping
MC10E212FN
PLCC−28
37 Units/Rail
MC10E212FNR2
PLCC−28
500 Units/Reel
MC100E212FN
PLCC−28
37 Units/Rail
MC100E212FNR2
PLCC−28
500 Units/Reel
Publication Order Number:
MC10E212/D
MC10E212, MC100E212
LOGIC DIAGRAM
5
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
SHIFT MR NC S-OUT VCCO Q2b Q2a
19
18
Q2b
27
17
Q2a
28
16
VCC
LOAD
26
CLK
D2
VEE
25
1
24
23
22
21
20
15
Pinout: 28-Lead PLCC
(Top View)
Q1b
14
Q1a
3
13
Q1b
4
12
Q1a
D1
2
D0
S-IN
5
6
7
8
9
10
D2
D1
11
D0
1
1
0
0
1
1
0
0
1
1
0
0
NC VCCO Q0a Q0b Q0a Q0b VCCO
S-IN
LOAD
SHIFT
CLK
MR
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
FUNCTION
D0 − D2
ECL Data Inputs
S-IN
ECL Scan Input
LOAD
ECL LOAD/HOLD Control
SHIFT
ECL Scan Control
CLK
ECL Clock
MR
ECL Reset
S-OUT
ECL Scan Output
Q[0:2]a, Q[0:2]b
ECL True Outputs
Q[0:2]a, Q[0:2]b
ECL Inverting Outputs
VCC, VCCO
Positive Supply
VEE
Negative Supply
NC
No Connect
FUNCTION TABLE
LOAD
SHIFT
MR
MODE
L
H
X
X
L
L
H
X
L
L
L
H
Load
Hold
Shift
Reset
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2
D
D
D
Q
Q
Q
S-OUT
Q2b
Q2a
Q2a
Q2b
Q1b
Q1a
Q1a
Q1b
Q0b
Q0a
Q0a
Q0b
MC10E212, MC100E212
MAXIMUM RATINGS (Note 1)
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI VCC
6
V
NECL Mode Input Voltage
VCC = 0 V
VI VEE
−6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
28 PLCC
22 to 26
°C/W
VEE
PECL Operating Range
4.2 to 5.7
V
NECL Operating Range
−5.7 to −4.2
V
265
°C
Symbol
Tsol
Wave Solder
Condition 1
Condition 2
<2 to 3 sec @ 248°C
1. Maximum Ratings are those values beyond which device damage may occur.
10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0°C
Symbol
Characteristic
Typ
Max
80
96
3980
4070
4160
Output LOW Voltage (Note 2)
3050
3210
VIH
Input HIGH Voltage
3830
VIL
Input LOW Voltage
3050
IIH
Input HIGH Current
IIL
Input LOW Current
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
VOL
Min
25°C
Min
Typ
Max
80
96
Typ
Max
Unit
80
96
mA
4020
4105
4190
4090
4185
4280
mV
3370
3050
3210
3370
3050
3227
3405
mV
3995
4160
3870
4030
4190
3940
4110
4280
mV
3285
3520
3050
3285
3520
3050
3302
3555
mV
150
μA
150
0.5
85°C
0.3
Min
150
0.5
0.25
0.3
0.2
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.06 V.
2. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 1)
0°C
Symbol
Characteristic
Typ
Max
80
96
−1020
−930
−840
Output LOW Voltage (Note 2)
−1950
−1790
VIH
Input HIGH Voltage
−1170
VIL
Input LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
VOL
Min
25°C
Min
85°C
Typ
Max
80
96
−980
−895
−810
−1630
−1950
−1790
−1005
−840
−1130
−1950
−1715
−1480
0.5
0.3
Typ
Max
Unit
80
96
mA
−910
−815
−720
mV
−1630
−1950
−1773
−1595
mV
−970
−810
−1060
−890
−720
mV
−1950
−1715
−1480
−1950
−1698
−1445
mV
150
μA
0.5
0.065
0.3
0.2
150
Min
150
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.06 V.
2. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
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MC10E212, MC100E212
100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
80
96
80
96
92
110
mA
VOH
Output HIGH Voltage (Note 2)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 2)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
4050
4120
3835
4120
4120
3835
4120
4120
mV
VIL
Input LOW Voltage
3190
3300
3525
3190
3525
3525
3190
3525
3525
mV
IIH
Input HIGH Current
150
μA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.4 6V / −0.8 V.
2. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
80
96
Min
85°C
Typ
Max
80
96
Min
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
−1025
−950
−880
−1025
−950
−880
−1025
VOL
Output LOW Voltage (Note 2)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
VIH
Input HIGH Voltage
−1165
−950
−880
−1165
−880
−880
−1165
VIL
Input LOW Voltage
−1810
−1700
−1475
−1810
−1475
−1475
−1810
IIH
Input HIGH Current
IIL
Input LOW Current
150
0.5
0.3
Typ
Max
Unit
92
110
mA
−950
−880
mV
−1740
−1620
mV
−880
−880
mV
−1475
−1475
mV
150
μA
150
0.5
0.25
0.5
0.2
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.8 V.
2. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 1)
0°C
Symbol
Characteristic
fMAX
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
ts
Setup Time
th
Min
Typ
25°C
Max
Min
TBD
Typ
85°C
Max
Min
TBD
Typ
Max
TBD
Unit
GHz
ps
CLK
MR
CLK to S-OUT
575
575
575
800
800
800
D
SHIFT
LOAD
S-IN
175
150
225
150
D
SHIFT
LOAD
S-IN
1025
1025
1025
575
575
575
800
800
800
25
− 50
50
− 50
175
150
225
150
250
300
225
300
25
100
0
100
600
350
1025
1025
1025
575
575
575
800
800
800
25
− 50
50
− 50
175
150
225
150
25
− 50
50
− 50
250
300
225
300
25
100
0
100
250
300
225
300
25
100
0
100
600
350
600
1025
1025
1025
ps
Hold Time
ps
tRR
Reset Recovery
350
ps
tSKEW
Within-Device Skew (Note 1.)
100
100
100
ps
tSKEW
Within-Gate Skew (Note 2.)
50
50
50
ps
tJITTER
Cycle−to−Cycle Jitter
TBD
TBD
TBD
tr
tf
Rise/Fall Times
(20 - 80%)
ps
ps
275
425
650
275
425
1. 10 Series: VEE can vary +0.46 V / −0.06 V.
100 Series: VEE can vary +0.46 V / −0.8 V.
1. Within-device skew is defined as identical transitions on similar paths through a device.
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4
650
275
425
650
MC10E212, MC100E212
2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input.
Q
D
Receiver
Device
Driver
Device
Q
D
50 W
50 W
V TT
VTT = VCC − 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
− ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
−
ECL Clock Distribution Techniques
AN1406
−
Designing with PECL (ECL at +5.0 V)
AN1503
−
ECLinPS I/O SPICE Modeling Kit
AN1504
−
Metastability and the ECLinPS Family
AN1568
−
Interfacing Between LVDS and ECL
AN1596
−
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
−
Using Wire−OR Ties in ECLinPS Designs
AN1672
−
The ECL Translator Guide
AND8001
−
Odd Number Counters Design
AND8002
−
Marking and Date Codes
AND8020
−
Termination of ECL Logic Devices
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5
MC10E212, MC100E212
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
-N-
0.007 (0.180)
B
Y BRK
U
T L −M
M
0.007 (0.180)
M
S
N
T L −M
S
S
N
S
D
-L-
Z
-M-
D
W
X
V
28
1
G1
0.010 (0.250)
S
T L −M
S
N
S
VIEW D-D
Z
C
A
0.007 (0.180)
R
0.007 (0.180)
M
T L −M
S
N
S
M
T L −M
S
N
S
H
0.007 (0.180)
M
T L −M
N
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
-T-
T L −M
S
N
0.007 (0.180)
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
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6
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2°
10°
0.410 0.430
0.040
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.79
2.29
0.33
0.48
1.27 BSC
0.81
0.66
0.51
0.64
11.58
11.43
11.58
11.43
1.07
1.21
1.07
1.21
1.42
1.07
0.50
2°
10°
10.42 10.92
1.02
M
T L −M
S
N
S
S
MC10E212, MC100E212
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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MC10E212/D
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