5V ECL Error Detection/Correction Circuit

MC100E193
5VECL Error Detection/
Correction Circuit
The MC100E193 is an error detection and correction (EDAC)
circuit. Modified Hamming parity codes are generated on an 8-bit
word according to the pattern shown in the logic symbol. The P5
output gives the parity of the whole word. The word parity is also
provided at the PGEN pin, after Odd/Even parity control and gating
with the BPAR input. This output also feeds to a 1-bit shiftable
register, for use as part of a scan ring.
Used in conjunction with 12-bit parity generators such as the E160,
a SECDED (single error correction, double error detection) error
system can be designed for a multiple of an 8-bit word.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
MARKING
DIAGRAM
MC100E193FN
AWLYYWW
Hamming Code Generation
PLCC−28
FN SUFFIX
CASE 776
8-Bit Word, Expandable
Provides Parity of Whole Word
Scannable Parity Register
A
WL
YY
WW
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input Pulldown Resistors
•
• ESD Protection: > 1 KV HBM, > 75 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
•
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For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 code V−0 @ 1/8″,
Oxygen Index 28 to 34
Transistor Count = 368 devices
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 1
1
28 1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC100E193FN
PLCC−28
37 Units/Rail
MC100E193FNR2
PLCC−28
500 Units/Reel
Publication Order Number:
MC100E193/D
MC100E193
EN
25
HOLD S-IN SHIFT CLK VCCO PGEN
24
23
22
21
20
PIN DESCRIPTION
19
EV/OD
26
18
PARERR
BPAR
27
17
PARERR
B0
28
16
VCC
15
P5
14
VCCO
VEE
1
Pinout: 28-Lead PLCC
(Top View)
B1
2
B2
3
13
P4
B3
4
12
P3
5
6
7
8
B4
B5
B6
B7
9
VCCO
10
11
P1
P2
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
PIN
FUNCTION
B0−B6
ECL Bit Inputs
P1−P5
ECL Parity Outputs
PARERR, PARERR
ECL Parity Error Outputs
PGEN
ECL Word Parity Generator Output
CLK
ECL Clock Input
SHIFT
ECL Shift Input (Active−High)
S−IN
ECL Serial Data Input
HOLD
ECL Hold (Active−Low)
EN
ECL Enable (Active−Low)
EV/DD
ECL Even/Odd Contact
BPAR
ECL Bit Parity Gate Input
VCC, VCCO
Positive Supply
VEE
Negative Supply
NC
No Connect
Figure 1. Pinout Assignment
B INPUTS
0 3 6 574 2 1
B2, B3, B6, B7
B1, B3, B5, B7
B4, B5, B6, B7
B1, B2, B4, B7
P2
P1
P3
P4
BYTE (B0 − B7)
P5
PGEN
BPAR
EV/OD
EN
0
0
1
1
D
HOLD
S-IN
SHIFT
CLK
Figure 2. Logic Diagram
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2
PARERR
PARERR
MC100E193
MAXIMUM RATINGS (Note 1)
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI ≤ VCC
6
V
NECL Mode Input Voltage
VCC = 0 V
VI ≥ VEE
−6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
θJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
θJC
Thermal Resistance (Junction−to−Case)
std bd
28 PLCC
22 to 26
°C/W
VEE
PECL Operating Range
4.2 to 5.7
V
NECL Operating Range
−5.7 to −4.2
V
265
°C
Symbol
Tsol
Wave Solder
Condition 1
Condition 2
< 2 to 3 sec @ 248°C
1. Maximum Ratings are those values beyond which device damage may occur.
100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 2)
0°C
Symbol
Characteristic
Typ
Max
112
134
3975
4050
4120
Output LOW Voltage (Note 3)
3190
3295
VIH
Input HIGH Voltage
3835
VIL
Input LOW Voltage
3190
IIH
Input HIGH Current
IIL
Input LOW Current
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
VOL
Min
25°C
Min
Typ
Max
112
134
Typ
Max
Unit
129
155
mA
3975
4050
4120
3975
4050
4120
mV
3380
3190
3255
3380
3190
3260
3380
mV
4050
4120
3835
4120
4120
3835
4120
4120
mV
3300
3525
3190
3525
3525
3190
3525
3525
mV
150
μA
150
0.5
85°C
0.3
Min
150
0.5
0.25
0.5
0.2
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.8 V.
3. Outputs are terminated through a 50 Ω resistor to VCC − 2.0 V.
100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)
0°C
Symbol
Characteristic
Typ
Max
112
134
−1025
−950
−880
Output LOW Voltage (Note 5)
−1810
−1705
VIH
Input HIGH Voltage
−1165
VIL
Input LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
VOL
Min
25°C
Min
85°C
Typ
Max
112
134
−1025
−950
−880
−1620
−1810
−1745
−950
−880
−1165
−1810
−1700
−1475
0.5
0.3
Typ
Max
Unit
129
155
mA
−1025
−950
−880
mV
−1620
−1810
−1740
−1620
mV
−880
−880
−1165
−880
−880
mV
−1810
−1475
−1475
−1810
−1475
−1475
mV
150
μA
0.5
0.25
0.5
0.2
150
Min
150
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.8 V.
5. Outputs are terminated through a 50 Ω resistor to VCC − 2.0 V.
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3
MC100E193
AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 6)
0°C
Symbol
Characteristic
fMAX
Maximum Toggle Frequency
tPLH
Propagation Delay to Output
tPHL
ts
th
Min
Typ
25°C
Max
Min
TBD
Typ
85°C
Max
Min
TBD
Typ
Max
TBD
Unit
GHz
ps
B to P1, P2, P3, P4
350
700
1000
350
700
1000
350
700
1000
B to P5
400
775
1150
400
775
1150
400
775
1150
EV/OD, BPAR to PGEN
350
650
850
350
650
850
350
650
850
B to PGEN
600
1000
1450
600
1000
1450
600
1000
1450
CLK to PARERR
300
550
850
300
550
850
300
550
850
SHIFT
400
150
400
150
400
150
S-IN
300
50
300
50
300
50
HOLD
750
350
750
350
750
350
Setup Time
ps
EN
500
250
500
250
500
250
EV/OD
1300
850
1300
850
1300
850
BPAR
1300
850
1300
850
1300
850
B
1700
1100
1700
1100
1700
1100
SHIFT
200
−150
200
−150
200
−150
S-IN
300
− 50
300
− 50
300
− 50
HOLD
100
− 350
100
− 350
100
− 350
Hold Time
ps
EN
tJITTER
Cycle−to−Cycle Jitter
tr
Rise/Fall Times
tf
(20 - 80%)
100
− 250
100
− 250
100
− 250
EV/OD
− 200
− 850
− 200
− 850
− 200
− 850
BPAR
− 200
− 850
− 200
− 850
− 200
− 850
B
− 300
−1100
− 300
−1100
− 300
−1100
TBD
TBD
TBD
ps
ps
300
700
1100
300
700
1100
300
6. 100 Series: VEE can vary +0.46 V / −0.8 V.
Q
D
Receiver
Device
Driver
Device
Q
D
50 Ω
50 Ω
VTT
VTT = VCC − 2.0 V
Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
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4
700
1100
MC100E193
Resource Reference of Application Notes
AN1404
− ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
−
ECL Clock Distribution Techniques
AN1406
−
Designing with PECL (ECL at +5.0 V)
AN1503
−
ECLinPS I/O SPICE Modeling Kit
AN1504
−
Metastability and the ECLinPS Family
AN1568
−
Interfacing Between LVDS and ECL
AN1596
−
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
−
Using Wire−OR Ties in ECLinPS Designs
AN1672
−
The ECL Translator Guide
AND8001
−
Odd Number Counters Design
AND8002
−
Marking and Date Codes
AND8020
−
Termination of ECL Logic Devices
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5
MC100E193
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
-N-
0.007 (0.180)
B
Y BRK
U
T L −M
M
0.007 (0.180)
M
S
N
T L −M
S
S
N
S
D
-L-
Z
-M-
D
W
X
V
28
1
G1
0.010 (0.250)
S
T L −M
S
N
S
VIEW D-D
Z
C
A
0.007 (0.180)
R
0.007 (0.180)
M
T L −M
S
N
S
M
T L −M
S
N
S
H
0.007 (0.180)
M
T L −M
N
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
-T-
T L −M
S
N
0.007 (0.180)
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
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6
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2°
10°
0.410 0.430
0.040
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.79
2.29
0.33
0.48
1.27 BSC
0.81
0.66
0.51
0.64
11.58
11.43
11.58
11.43
1.07
1.21
1.07
1.21
1.42
1.07
0.50
2°
10°
10.42 10.92
1.02
M
T L −M
S
N
S
S
MC100E193
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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