MC10153 Quad Latch The MC10153 is a high speed, low power, MECL quad latch consisting of four bistable latch circuits with D type inputs and gated Q outputs. Open emitters allow a large number of outputs to be wire-ORed together. Latch outputs are gated, allowing direct wiring to a bus. When the clock is low, outputs will follow D inputs. Information is latched on positive going transition of the clock. The MC10153 provides the same logic function as the MC10133, except for inversion of the clock. • PD = 310 mW typ/pkg (No Load) • tpd = 4.0 ns typ • tr, tf = 2.0 ns typ (20%–80%) http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 LOGIC DIAGRAM D0 3 G0 D1 5 7 CE 4 1 Q0 2 6 Q1 Q0 16 PDIP–16 P SUFFIX CASE 648 Q1 CC 13 1 PLCC–20 FN SUFFIX CASE 775 CE 12 Q2 D3 14 Q3 MC10153P AWLYYWW 1 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 D2 9 G1 10 MC10153L AWLYYWW 10153 AWLYYWW 11 Q2 A WL YY WW 15 Q3 DIP PIN ASSIGNMENT VCC1 1 16 VCC2 Q0 2 15 Q3 D0 3 14 D3 CE 4 13 CC G0 5 12 CE Q1 6 11 D1 7 VEE 8 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC10153L CDIP–16 25 Units / Rail Q2 MC10153P PDIP–16 25 Units / Rail 10 G1 MC10153FN PLCC–20 46 Units / Rail 9 D2 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). TRUTH TABLE G C D Qn+1 H L L L X H L L X X L H L Qn L H C = CC + CE Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Publication Order Number: MC10153/D MC10153 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Symbol Pin Under Test Max Unit Power Supply Drain Current IE 8 83 75 83 mAdc IinH 3 4 5 13 390 390 560 460 245 245 350 290 245 245 350 290 µAdc IinL 3 0.5 Input Current –30°C Min +25°C Max Min Typ +85°C Max 0.5 Min µAdc 0.3 Output Voltage Logic 1 VOH 2 2 –1.060 –1.060 –0.890 –0.890 –0.960 –0.960 –0.810 –0.810 –0.890 –0.890 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 2 2 2 –1.890 –1.890 –1.890 –1.675 –1.675 –1.675 –1.850 –1.850 –1.850 –1.650 –1.650 –1.650 –1.825 –1.825 –1.825 –1.615 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 2 2 2 2 2 2 2 –1.080 –1.080 –1.080 –1.080 –1.080 –1.080 –1.080 –1.080 Threshold Voltage Logic 0 VOLA 2 2 2 2 2 2 –0.980 –0.980 –0.980 –0.980 –0.980 –0.980 –0.980 –0.980 –0.910 –0.910 –0.910 –0.910 –0.910 –0.910 –0.910 –0.910 –1.655 –1.655 –1.655 –1.655 –1.655 –1.655 –1.630 –1.630 –1.630 –1.630 –1.630 –1.630 Vdc –1.595 –1.595 –1.595 –1.595 –1.595 –1.595 Switching Times (50Ω Load) Propagation Delay Vdc ns t3+2+ t4–2+ t5–2+ tsetup thold 2 2 2 3 3 1.0 1.0 1.0 2.5 1.5 5.6 5.6 3.2 1.0 1.0 1.0 2.5 1.5 4.0 4.0 2.0 0.7 0.7 5.4 5.6 3.1 1.1 1.2 1.0 2.5 1.5 5.9 6.2 3.4 Rise Time (20 to 80%) t2+ 2 1.0 3.6 1.1 2.0 3.5 1.1 3.8 Fall Time (20 to 80%) t2– 2 1.0 3.6 1.1 2.0 3.5 1.1 3.8 Output level to be measured after a clock pulse has been applied to the clock input (Pin 4) VIHmax VILmin Data input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured after device has latched. * Latch set to zero state before test. http://onsemi.com 2 MC10153 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 IinH 3 4 5 13 IinL 3 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VEE (VCC) Gnd 8 1, 16 8 8 8 8 1, 16 1, 16 1, 16 1, 16 3 8 1, 16 VILmin VIHAmin VILAmax 13 3 4 5 13 Output Voltage Logic 1 VOH 2 2 3 3 4 13 8 8 1, 16 1, 16 Output Voltage Logic 0 VOL 2 2 2 3,5 3,13 13 3,4 8 8 8 1, 16 1, 16 1, 16 8 8 8 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 13 8 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 Pulse In Pulse Out –3.2 V +2.0 V 3 4 5 3 3 2 2 2 2 2 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 Threshold Voltage Threshold Voltage Switching Times Logic 1 Logic 0 VOHA VOLA 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 3 (50Ω Load) Propagation Delay 3 3 4 4 4 3 3 4 13 4 4 4 2 2 2 3 3 5 3 3 3 +1.11 V t3+2+ t4–2+ t5–2+ tsetup thold 5 3 3* Rise Time (20 to 80%) t2+ 2 3 2 8 1, 16 Fall Time (20 to 80%) t2– 2 3 2 8 1, 16 Output level to be measured after a clock pulse has been applied to the clock input (Pin 4) VIHmax VILmin Data input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured after device has latched. * Latch set to zero state before test. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 3 MC10153 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) B Y BRK –N– M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D –L– –M– Z W 20 D 1 X V S T L-M S N S VIEW D–D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z 0.007 (0.180) H M T L-M S N S K1 K C E F 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L-M S N S 0.007 (0.180) M T L-M S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2 10 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2 10 7.88 8.38 1.02 --- N S MC10153 PACKAGE DIMENSIONS –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M S T A M http://onsemi.com 5 INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 MC10153 Notes http://onsemi.com 6 MC10153 Notes http://onsemi.com 7 MC10153 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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