AND8366 AMIS-4168x Fault Tolerant Transceiver Design Considerations Using CANLSFT http://onsemi.com APPLICATION NOTE Introduction The new AMIS−41682 and AMIS−41683 are interfaces between the protocol controller and the physical wires of the bus lines in a control area network (CAN). The AMIS−41683 is identical to the AMIS−41682 but has a true 3.3 V digital interface to the CAN controller. The device provides differential transmit capability but will switch in error conditions to a single−wire transmitter and/or receiver. Initially it will be used for low speed applications, up to 125 kB, in passenger cars. Both AMIS−41682 and AMIS−41683 are implemented in I2T100 technology enabling both high−voltage analog circuitry and digital functionality to co−exist on the same chip. This application note describes design considerations using AMIS−41682 and AMIS−41683 in low speed fault tolerant CAN networks conform to ISO 11898−3. More technical information can be found in: • AMIS−41682 Datasheet (http://www.onsemi.com) • ISO 11898−3 standard Key Characteristics AMIS−41682 / AMIS−41683 Device Parameters Table 1. KEY DEVICE PARAMETERS FOR THE AMIS−41682 AND AMIS−41683 Key Current consumption in normal mode (ICC) Current consumption in stand−by modes (IBAT + ICC) AMIS−41682 AMIS−41683 7 mA (recessive) 17 mA (dominant) 7 mA (recessive) 17 mA (dominant) 30 mA 30 mA Minimum operating voltage 5V 5V Prevention of VBAT reverse current Yes Yes Both edges Both edges No Yes During frame and inter frame space During frame and inter frame space WAKE−B sensitivity True 3.3 V microcontroller interface NERR reporting of open failures System Parameters Table 2. KEY SYSTEM PARAMETERS FOR THE AMIS−41682 AND AMIS−41683 Key AMIS−41682/3 System Size v 32 nodes Speed 40 – 125 kbps Emission ++ Immunity ++ TxD dominant monitoring yes Extended bus failure management (including Failure 3a CANH to VCC) yes Resolved problem of arbitration across open failures yes © Semiconductor Components Industries, LLC, 2009 January, 2009 − Rev. 0 1 Publication Order Number: AND8366/D AND8366 Pullup Resistors AMIS−41683 To interface with true 3.3 V microcontrollers AMIS−41683 has open drain outputs for RxD and ERR−B. To calculate the pullup resistor two considerations are important: • A too high resistance value will create extra delay when charging the equivalent input capacitance Ci (see Figure 1). A too low resistance will negatively influence the VOL level. • 3,3 V R PU AMIS−41683 ERR C 4 Failure handling i RxD 3 Figure 1. Pullup Resistor to Interface with True 3.3 V Microcontrollers Verifying RPU for Maximum VOL Calculating RPU for Minimum Propagation Delay The extra delay can be seen as the time needed to charge Ci up to 70% of the 3.3 V supply. This is given by: t delay + 1.2 * R PU * C i The maximum sink current when RxD or ERR−B are pulled low via the open drain outputs of the AMIS−41683 is given by: (eq. 1) The typical propagation delay can be found in the data sheet and is given in Table 3. I SINK + Symbol Parameter AMIS−41683 Typical propagation delay TxD to RxD (high) 750 ns R PU + t delay ǒ1.2 * C iǓ 37 ns ǒ1.2 * 6.5 pFǓ + 4.74 kW + 696 mA (Res.2) Table 4. OUTPUT LOW LEVEL OF THE OPEN−DRAIN OUTPUTS RXD AND ERR−B Assuming that this delay is symmetrical between TxD to BUS and BUS to RxD and that the extra delay should be less than 10% gives tdelay < 37 ns. Calculating further with Ci = Cinput + Cinterconnect = 3.5 pF + 3.0 pF = 6.5 pF in Equation 1 yields in: R PU + 4.74 kW This current is far below the maximum Isink = 1.6 mA to guarantee a VOL < 0.4 V as can be seen in the data sheet and in Table 4. Table 3. PROPAGATION DELAY tPD(H) 3.3 V Symbol VOL,max Parameter Low level output voltage @ Isink = 1.6 mA AMIS−41683 < 0.4 V Series Resistor at Pin BAT (eq. 2) The optional resistor RBAT gives the AMIS−41682/3 additional protection against automotive transients (ISO 7637 part 5). It is not really needed because the high voltage part of the circuit is designed to withstand these high energetic pulses. (Res.1) http://onsemi.com 2 AND8366 BATTERY IN OUT 5V−reg I CC RBAT IBAT VBAT 14 INH VCC 10 1 7 WAKE POR Mode & wake− up control 9 RTL 12 AMIS−4168x PC20051017.1 Figure 2. Connection via RBAT to VBAT Indication of Currents Conclusion The higher this series resistor the better the protection. However bigger series resistance results in a higher voltage drop thus increasing minimum operating battery voltage. To calculate this drop the maximum current consumption from VBAT in normal and low power mode needs to be determined. This shows that specifically in low power mode the voltage drop is relatively high due to the high output current on the RTL pin. For RBAT = 1 kW the minimum operating battery voltage is increased with 1.31 V. For RBAT = 2 kW this is almost an increase of 2.6 V leading to VBAT,min = 7.6 V. If a very low minimum operating voltage is required, RBAT can be eliminated. In all other cases RBAT should be < 2 kW. Normal Mode In normal mode the maximum voltage drop over RBAT is given by: V DROPN + R BAT * IBAT Table 5. MOST IMPORTANT PARAMETERS TO CALCULATE RBAT (eq. 3) Calculating with RBAT = 1 kW the parameters from copied from the AMIS−41682/3 data sheets yields in: V DROPN + 1 kW * 230 mA + 230 mV Symbol (Res.3) Low Power Mode In low power mode the maximum voltage drop over RBAT is given by: V DROPLP + R BAT * ǒI BAT ) I CC ) I RTLǓ (eq. 4) Calculating with RBAT = 1 kW the parameters from copied from the AMIS−41682/3 data sheets yields in: V DROPN + 1 kW * ǒ60 mA ) 1.25 mAǓ + 1.31 V (Res.4) Parameter AMIS−41682/3 VBAT Minimum operating voltage at VBAT supply pin 5V IBAT Max current in pin VBAT (5 V to 36 V) in all modes of operation 230 mA IBAT + ICC Max current in pin VBAT (5 V to 36 V) and VCC in low power mode 60 mA IRTL Maximum RTL current in low power modes 1.25 mA http://onsemi.com 3 AND8366 VCC Supply and Recommended Buffer Capacitance Introduction AMIS−41683 independently from the microcontroller. (See Figure 2). Depending on the used topology the dimensioning of the buffer capacitor and the power dissipation in the voltage regulator will differ. Two types of VCC supply topologies can be recognized. For 5 V microcontrollers, in most cases, a common VCC power supply is used for both the microcontroller and the AMIS−41682. (See Figure 1). In case of a 3.3 V microcontroller a separate VCC supply is needed for the OUT IN 5V−reg BATTERY * VCC VCC INH 10 EN ERR CAN controller STB RxD TxD WAKE VBAT 1 14 7 9 6 4 12 5 AMIS−41682 11 3 2 8 13 GND RTL CANL CANH RTH GND CAN BUS LINE PC20050610.1 * optional Figure 3. Single VCC Topology for 5 V Microcontroller 3.3V− OUT IN reg OUT IN 5V−reg BATTERY * 4.7 k Ω▯ 4.7 k Ω▯ VCC VCC 10 EN ERR 3.3V CAN controller STB RxD TxD INH VBAT 1 7 9 6 4 12 5 AMIS−41683 11 3 2 8 13 RTL CANL CANH RTH GND GND * optional WAKE 14 CAN BUS LINE PC20050610.2 Figure 4. Dual VCC Topology for 3.3 V Microcontroller Calculation The average supply current is needed to calculate the thermal load of the required VCC voltage regulator. The peak supply current may flow in case of certain bus failure conditions for a certain time and thus has an impact on the power supply buffering. For calculating the power dissipation in the voltage regulator the average current consumption is important. For dimensioning the buffer capacitor the peak current and the peak duration time is of importance. gives an overview of the calculated values discussed further in this document. http://onsemi.com 4 AND8366 The VCC supply of the transceiver is recommended to support the characteristics as follows: Table 6. OVERVIEW OF THE CALCULATED VCC SUPPLY CURRENTS Symbol Parameter Condition AMIS−41682/3 ICC,av_NF Average VCC supply current No bus failure 31.15 mA ICC,av_SF Average VCC supply current Single bus failure 66.15 mA ICC,pk_SF Peak VCC supply current Single bus failure 126 mA tSINGLE Over current duration Single bus failure < 6 Tbit ICC,pk_DF Peak VCC supply current Dual bus failure 127 mA tDOUBLE Over current duration Dual bus failure < 17 Tbit In the following, these two cases are discussed in more detail. Table 8. MAXIMUM ICC IN RECESSIVE STATE Calculating the Average Supply Current Without Bus Failure Condition ICC_rec Symbol The average supply current is determined by the current consumption in the recessive state Icc_rec as listed in the datasheet and the current consumption in dominant state. The latter is the sum of the corresponding supply current Icc0_dom , the bus current ICANH_dom and the current in the termination resistor ICANH_dom. The maximum dominant supply current (without bus wiring faults) is given by: I CC_dorm + I CC0_dom ) I CANH_dom ) IRTL_dom I RTL_dom + 6.3 mA (eq. 6) (Res.6) RT Parameter Supply Currents With Single Bus Failure Condition Average Supply Current in Single Fault Condition The average supply current is determined by the current consumption in the recessive state Icc_rec as listed in the datasheet and the worst case current consumption in dominant state. The latter is the sum of the corresponding supply current Icc0_dom , the bus current when CANH is shorted to ground ICANH_ sc1_dom and the current in the termination resistor ICANH_dom. The maximum dominant supply current (with SINGLE bus wiring faults CANH shorted to GND) is given by: AMIS−41682/3 ICC0_dom Max. VCC supply current dominant, no load 12 mA ICANH_dom Assumed CANH dominant current 40 mA RT Assumed termination resistor 1 kW VCANL_dom Assumed CANL dominant voltage 1V I CC_sc1_dom + ICC0_dom ) ICANH_sc1_dom ) I RTL_dom (eq. 8) Calculating with the given parameters in Table 9: Yields in: ǒ5 V * 1 VǓ 1 kW (eq. 7) Using the parameter in and result (Res 5) in Equation 7 yields in: I CC_nom_avg + 0.5 * ǒ6.3 mA ) 56 mAǓ + 31.15 mA max. Table 7. MOST IMPORTANT PARAMETERS TO CALCULATE THE MAXIMUM IOC IN DOMINANT STATE I CC_dom + 12 mA ) 40 mA ) Maximum VCC supply current recessive, no load I CC_nom_avg + 0.5 * ǒI CC_rec ) I CC_domǓ Calculating with the given parameters in Table 7. Symbol AMIS−41682/3 For thermal considerations the average supply current at pin VCC is relevant considering the transmit duty cycle. The worst case condition is a continuously transmitting node. With an assumed transmit duty cycle of 50% on pin TxD, the maximum average supply current is: (eq. 5) ǒVCC * VCANL_domǓ Parameter + 56 mA max. (Res.5) The maximum recessive supply current (without bus wiring faults) is given by the parameters in Table 8: http://onsemi.com 5 AND8366 the calculation of the buffer capacitor we need to distinguish between the two supply topologies: If there is a separate voltage regulator available supplying the transceiver exclusively (see Figure 5), no care has to be taken on this dual short circuit condition. If the voltage regulator enters the over−current protection level and its output will drop to limit the internal power dissipation, this under−voltage condition will only affect the function of the transceiver. The microcontroller is still powered properly by its own supply. In case of a shared voltage supply for transceiver and microcontroller, this dual fault condition is relevant to dimension the required buffer capacitor. Table 9. MAXIMUM DOMINANT CURRENT IN CASE OF A SHORT CIRCUIT IN THE CANH PIN Symbol Parameter AMIS−41682/3 ICANH_sc1_do CANH dominant current, short circuit 110 mA m Yields in: I CC_sc1_dom + 12 mA ) 110 mA ) ǒ5 V * 1 VǓ 1 kW + 126 mA max. (Res.7) For thermal considerations the average supply current at pin VCC is relevant considering the transmit duty cycle. The worst case condition is a continuously transmitting node. With an assumed transmit duty cycle of 50% on pin TxD, the maximum average supply current is: I CC_sc1_avg + 0.5 * ǒICC_rec ) ICC_sc1_domǓ Max VCC Supply Current in Worst−Case Dual Fault Condition I CC_sc2_dom + ICC0_dom ) ICANH_sc1_dom ) I RTL_sc_dom (eq. 9) ǒt t 17 bit timesǓ Using the parameter from and and result (Res 7) in Equation 9 yields in: I RTL_sc_dom + I CC_sc1_avg + 0.5 * ǒ6.3 mA ) 126 mAǓ + 66.15 mA max. (Res.8) Compared to the quiescent current in recessive state the maximum extra supply current when the CANH driver is turned on with CANH shorted to GND is needed to calculate the required worst case VCC buffer capacitance. This extra supply current has to be buffered for up to 6−bit times. This 6−bit time limitation is set by the CAN controller which is supposed to send an error flag within this timing window. (eq. 10) The minimum recessive supply current is given by the parameter in Table 10. Table 10. VCC MINIMUM CURRENT CONSUMPTION IN RECESSIVE STATE Symbol ICC_rec,min Parameter AMIS−41682/3 Min. VCC supply current recessive, no load 1 mA Using the parameter in and result (Res 7) in Equation 10 yields in: DI CC_sc1 + 126 mA * 1 mA + 125 mA max. V CC 2 (eq. 12) The 17−bit time−out limitation is determined by the CAN protocol. Due to the dual fault condition with CANH and CANL shorted to GND the RxD pin of the transceiver is continuously clamped recessive (CANL to GND forces CANH operation; CANH is clamped recessive). The moment the CAN controller starts a transmission, this dominant start of frame bit is not fed back via RxD and thus forces an error flag due to the bit failure condition (TX error counter increment by 8). This first bit of the error flag again is not reflected at RxD and forces the next error flag (TX error counter + 8). Latest after 17 bit times, depending on the TX error counter level before starting this transmission, the CAN controller reaches the error passive limit (128) and stops sending dominant bits. Now a sequence of 25 recessive bits follows (8 bit error delimiter + 3 bit intermission + 8 bit suspend transmission) and the VCC current becomes reduced to the recessive one. From now on only single dominant bits (start of frame) followed by 25 recessive bits (passive error flag + intermission + suspend transmission) are output until the CAN controller enters the bus off state. So, for dimensioning the VCC voltage source in this worst case dual failure scenario, up to 17 bit times might have to be buffered by a buffer capacitor depending on the regulation capabilities of the used voltage supply. Using the parameters from and in Equations 11 and 12 yields in: Extra Supply Current in Single Fault Condition DI CC_sc1 + ICC_sc1_dom * I CC_rec,min (eq. 11) (Res.9) Worst−Case Max VCC Supply at Presence of a Dual Short Circuit I CC_sc2_dom + 12 mA ) 110 mA ) 5 Vń1 kW + 127 mA The worst case maximum VCC supply current is flowing in case of a dual short−circuit of the bus. In this case the bus−lines CAN_H and CAN_L are shorted to ground and no communication is possible. Nevertheless the application supply should be able to deliver a proper VCC for the microcontroller in order to prevent erroneous operation. For (Res.10) VCC Extra Supply Current in Dual Fault Condition Compared to the quiescent current in recessive state the maximum extra supply current when the CANH driver is http://onsemi.com 6 AND8366 turned on in dual short−circuit condition is needed to calculate the required worst case VCC buffer capacitance. This extra supply current has to be buffered for that time the applications voltage regulator needs to react. DI CC_sc2 + ICC_sc2_dom * I CC_rec,min Important remarks: • The buffer capacitor CBUFF is calculated assuming the voltage regulator is not able to deliver any extra current within the maximum dominant output drive tdom_max during the dual fault condition due to bandwidth limitations of the regulator. • The voltage drop over the capacitor is assumed to be less than 5%. In the graphs also 7% and 9% are plotted. (eq. 13) Using the parameter in and result (Res 10) in Equation (13) yields in: DI CC_sc2 + 127 mA * 1 mA + 126 mA max. (Res.11) CBUFF Calculation for Separate Supplied Transceiver In case of a separate transceiver supply the buffer capacitance has to be calculated based on the single fault condition with CANH shorted to GND. Here the dual fault is not relevant. Assuming a communication speed of 100kBit/s gives: Calculation of Worst−Case Buffer Capacitor Depending on the power supply topology, the required worst−case buffer capacitor can be calculated. In case of a separate VCC supply for the transceiver only, the extra supply current DICC_sc1 in case of the single fault condition has to be taken with a maximum of six dominant bit times. C BUFF + DI CC_sc1 * t dom_max DV max t dom_max + 6 * 10 ms + 60 ms Maximum allowed VCC voltage drop of 5% yields in: DV max + 0.25 V (eq. 14) t dom_max DV max (Res.13) Using the results (Res 9), (Res 12) and (Res 13) in Equation (14) yields in: In case of a shared VCC supply for transceiver and microcontroller, the extra supply current DICC_sc2 in case of the dual fault condition has to be taken with a maximum of 17 dominant bit times. C BUFF + DI CC_sc2 * (Res.12) C BUFF + 125 mA * 60 msń0.25 V + 30 mF (eq. 16) For different communication speeds and allowed voltage drop, CBUFF can be looked up in the graph in Figure 5. (eq. 15) CBUFF at double fault CBUFF at single fault 1000 1000 D V = 0,25 V CBUFF (uF) CBUFF (uF) DV = 0,35 V DV = 0,45 V 100 DV = 0,25 V DV = 0,35 V 100 DV = 0,45 V 10 10 10 100 10 1000 100 1000 Speed (kBit/s) Speed (kBit/s) Figure 5. Needed VCC Buffer Capacitor for Single and Double Bus Failure CBUFF Calculation for Shared Supply DV max + 0.25 V In case of a shared supply concept the buffer capacitance has to be calculated based on the worst case dual fault condition in order to keep the micro−controller supply within the operating range: Assuming a communication speed of 100 kBit/s gives: t dom_max + 17 * 10 ms + 170 ms (Res.15) Using the results (Res 11), (Res 14) and (Res 15) in Equation 15 yields in: C BUFF + 126 mA * 170&msń0.25 V + 85.7 mF (Res.16) For different communication speeds and allowed voltage drop, CBUFF can be looked up in the graphs plotted in Figure 5. (Res.14) Maximum allowed VCC voltage drop of 5% yields in: http://onsemi.com 7 AND8366 Calculation of Bus Termination Resistors and EMC Issues How to Dimension the Bus Termination Resistor Values – Some Basic Rules It is recommended, that every node provides its own termination resistors. However this is not a strict requirement. A not well terminated node might be sensitive for false wake up signals, if a broken line error had occurred. Depending on the number of nodes in the network the local termination resistors can be calculated as: 11 CANH 8 RTH 12 CANL 11 CANH 8 RTH 600W 600W 12 CANL 9 RTL 600W 8 RTH 9 RTL 600W 11 CANH 600W 12 CANL 600W 600W 600W 600W 600W 8 RTH 9 RTL AMIS−41682 8 RTH 12 CANL 11 CANH Where n = number of nodes If the number of nodes is smaller than five the network termination is limited to 500 W. This will lead to a non optimal line termination, but in small networks this is not considered as a problem. AMIS−41682 PC20051013.1 11 CANH R TL + n * 100 W and R TH + n * 100 W (eq. 17) AMIS−41682 8 RTH 12 CANL 9 RTL AMIS−41682 11 CANH AMIS−41682 AMIS−41682 12 CANL 9 RTL 600W 9 RTL 600W The termination is provided by connecting the CANL line to the RTL pins of the transceiver devices and by connecting the CANH line to the RTH pins. By connecting the termination pins the following requirements have to be considered: • The overall network termination resistor of one line (all parallel resistors connected to RTL or RTH pins) shall be about 100 W, due to in circuit current limitations and CAN voltage definitions. • A single resistor connected to an individual transceiver device shall not be below 500 W, due to in circuit current limitations. CAN BUS LINE Figure 6. Example Network with Six Nodes, 600 W Termination at Each Node Tolerances of Bus Termination Resistors – EMC Considerations pair cable in order to achieve a symmetrical capacitive load for both bus wires resulting in a good EMC performance. The symmetry of the termination resistors within a single node has a major impact to the systems electromagnetic emission (EME) behavior. Thus it is important to have well matched termination resistors within each control unit. This means that the RTH resistor should have exactly the same value compared to the RTL resistor within one control unit in order to get the same time constant on each bus wire during signal transitions. The tolerance between two different control units is absolutely insignificant. The principle to achieve a good EME performance is that the differential signal on the bus wires eliminates any emission due to compensation effects if both CAN wires are carrying exactly the same signal, but with inverse polarities. Here the transceiver can only provide a perfect symmetry for the dominant transitions by design. The recessive transitions are mainly driven by the termination resistors and the network cables itself. So not only the transceiver’s output drivers have an impact to the EME performance but also the termination and the cable symmetry. It is obvious that also the layout of printed circuit boards has a significant impact to the EMC behavior if the CAN lines have different capacitive loads due to different wire lengths. It is recommended to provide a termination resistor accuracy (RTH compared to RTL) within the same node of 1% or lower. Also the bus cable has to be at least a twisted Power Dissipation of Bus Termination Resistors RT Average Power Dissipation – No Bus Failures To determine the average power dissipation of the termination resistors, the average time between dominant and recessive bits has to be taken into account. Additionally a worst case ground shift is contributing to additional dissipation. The power dissipation in recessive state is Prec = 0 because there is no voltage drop across the termination resistor. In dominant state the dissipation is given by: P dom + ǒVCC ) VGNDǓ 2 (eq. 18) RT CAN frames are assumed to have a worst case ratio of dominant bits in the range of 0.75. This results in an average power dissipation calculated as follows: P avg + 0.25 P rec ) 0.75 P dom + ǒ0.75 * ǒVCC ) VGNDǓǓ RT 2 (eq. 19) Assuming RT = 1 kW and a worst case ground shift of VGND = 1.5 V yields in: http://onsemi.com 8 AND8366 P avg + ǒ0.75 * ǒ5 V ) 1.2 VǓǓ 2 1 kW + 23.7 mW Table 11. MAXIMUM FAILURE DETECTION TIME Symbol (Res.17) tdet Maximum Peak Power Dissipation V BAT,max RT 2 ǒwith duration AMIS−41682/3 80 ms Calculating with data from , RT = 1 kW and VBAT = 27 V In case of a bus failure (CANH to VBAT) a peak current will flow in the termination resistor. However the duration is limited because after the maximum Failure Detection Time the termination resistor will be disabled from the circuit. The peak power can be calculated as: P peak + Parameter Failure Detection time P peak + ǒ27 VǓ 2 1 kW + 730 mW for less than 8 ms E peak + 5.84 mJ (Res.18) Because the energy Epeak is very limited, this peak power dissipation can be neglected. t t detǓ (eq. 20) The maximum failure detection time is given by the parameter in Table 11: Table 12. GLOSSARY Symbol Description Icc_dom Supply current at pin VCC while driving a dominant bit with a certain load to the pins Icc0_dom Supply current at pin VCC while driving a dominant bit without any load to the pins ICANH_dom Output current of pin CANH while driving a dominant bit with nominal bus load of 100 W in total IRTL_dom Output current of pin RTL while driving a dominant bit with a certain load Icc_rec Supply current at pin VCC while driving a recessive bit Icc_norm_avg Average supply current at pin VCC assuming no bus failure and continuous sending Icc_sc1_dom Supply current at pin VCC driving a dominant bit while CANH is shorted to GND ICANH_sc1_dom Output current of pin CANH driving a dominant bit while CANH is shorted to GND Icc_sc1_avg Average supply current at pin VCC assuming CANH shorted to GND and continuous sending DIcc_sc1 Supply current change at pin VCC in case a dominant bit is driven while CANH is shorted to GND Icc_sc2_dom Supply current at pin VCC driving a dominant bit while CANH and CANL are shorted to GND IRTL_sc_dom Output current of pin RTL while driving a dominant bit with CANL shorted to GND DIcc_sc2 Supply current change at pin VCC in case a dominant bit is driven while CANH and CANL are shorted to GND VCC Supply voltage at pin VCC VCANL_dom Voltage level on CANL while a dominant bit is driven RT Termination resistor connected to pins RTL and RTH tdom_max Maximum possible continuous dominant drive time DVmax Maximum allowed voltage change at pin VCC CBUFF Required buffer capacitance in case the voltage regulator does not deliver extra current within tdom_max tPD(H) Typical propagation delay TxD to RxD (High) Ci Input capacity seen from the open drain outputs RPU Pull up resistor 3.3 V open drain output VOL,max Maximum low level output voltage ISINK Sink current in open drain output RBAT Series resistor in VBAT connection VDROPN Voltage drop over VBAT series resistor in Normal mode VDROPLP Voltage drop over VBAT series resistor in Low Power mode VBAT Minimum operating voltage at VBAT supply pin IBAT Max current in pin VBAT (5 to 36 V) in all modes of operation http://onsemi.com 9 AND8366 Table 12. GLOSSARY Symbol Description IBAT + ICC Max current in pin VBAT (5 to 36 V) and VCC in low power mode IRTL Maximum RTL current in low power modes ICC,av_NF Average VCC supply current ICC,av_SF Average VCC supply current ICC,pk_SF Peak VCC supply current tSINGLE Overcurrent duration ICC,pk_DF Peak VCC supply current tDOUBLE Over current duration ICC,av_NF Average VCC supply current RTH ,RTL CAN bus termination resistors tdet Failure detection time Pavg Average power dissipation in CAN bus termination resistors Ppeak Peak power dissipation in CAN bus termination resistors Epeak Peak energy in CAN bus termination resistors ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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