3-In-1 PWM Dual Buck and Linear DDR Power Controller

NCP5210
3−in−1 PWM Dual Buck
and Linear DDR Power
Controller
The NCP5210, 3−in−1 PWM Dual Buck and Linear DDR Power
Controller, is a complete power solution for MCH and DDR memory.
This IC combines the efficiency of PWM controllers for the VDDQ
supply and the MCH core supply voltage with the simplicity of linear
regulator for the VTT termination voltage.
This IC contains two synchronous PWM buck controller for driving
four external N−Ch FETs to form the DDR memory supply voltage
(VDDQ) and the MCH regulator. The DDR memory termination
regulator (VTT) is designed to track at the half of the reference voltage
with sourcing and sinking current.
Protective features include, soft−start circuitry, undervoltage
monitoring of 5VDUAL and BOOT voltage, and thermal shutdown.
The device is housed in a thermal enhanced space−saving
QFN−20 package.
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MARKING
DIAGRAM
20
QFN−20
MN SUFFIX
CASE 505AB
1
Features
•
•
•
•
•
•
•
•
VMCH
Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A
All External Power MOSFETs are N−Channel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half the Reference Voltage
Fixed Switching Frequency of 250 kHz for VDDQ and VMCH
Doubled Switching Frequency of 500 kHz for VDDQ Controller in
Standby Mode to Optimize Inductor Current Ripple and Efficiency
Soft−Start Protection for all Controllers
Undervoltage Monitor of Supply Voltages
Overcurrent Protections for DDQ and VTT Regulators
Fully Complies with ACPI Power Sequencing Specifications
Short Circuit Protection Prevents Damage to Power Supply Due
to Reverse DIMM Insertion
Thermal Shutdown
5x6 QFN−20 Package
Pb−Free Package is Available*
PIN CONNECTIONS
COMP
FBDDQ
• DDR I and DDR II Memory and MCH Power Supply
SS
PGND
VTT
VDDQ
5VDUAL
COMP_1P5
BUF_Cut
TG_1P5
BG_1P5
GND_1P5
AGND
FBVTT
DDQ_REF
FB1P5
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
Device
Package
Shipping†
NCP5210MNR2
QFN−20
2500 Tape & Reel
QFN−20
(Pb−Free)
2500 Tape & Reel
NCP5210MNR2G
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
January, 2005 − Rev. 4
SW_DDQ
BG_DDQ
TG_DDQ
BOOT
ORDERING INFORMATION
Applications
 Semiconductor Components Industries, LLC, 2005
NCP5210
AWLYYWW
NCP5210 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
• Incorporates Synchronous PWM Buck Controllers for VDDQ and
•
•
•
•
•
•
1
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NCP5210/D
NCP5210
BUF_Cut
BUF_Cut
SS
12 V
CSS
BOOT
VTT
1.25 V,
13 V
Zener
VTT
5VDUAL
5VDUAL
2 Apk
COUT2
FBVTT
M1
AGND
DDQ_REF
R5
COUT1
SW_DDQ
CPM1
RZM2
RZM1
M2
COMP_1P5
BG_DDQ
FB_1P5
PGND
5VDUAL
R6
CZ2
COMP
M3
VMCH
2.5 V, 20 A
L
NCP5210
CZM1
CZM2
VDDQ
TG_DDQ
VDDQ
TG_1P5
CZ1
RZ1
L
CP1
RZ2
R1
FBDDQ
R2
1.5 V, 10 A
COUT3
M4
BG_1P5
VDDQ
GND_1P5
Figure 1. Application Diagram
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2
NCP5210
VREF
VOLTAGE
and CURRENT
REFERENCE
VCC
THERMAL
SHUTDOWN
_VREFGD
TSD
12 V
BOOT
13 V
Zener
BUF_CUT
VCC
_BOOTGD
R10
5VDUAL
S0
CONTROL
LOGIC
BOOT_
5VDUAL
S3
UVLO
VREF
R11
+
5VDUAL_
−
R12
UVLO
R13
5VDUAL
VOCP
+
ILIM
5VDUAL
VCC
VDDQ
M1
and
_5VDLGD
VREF
V1P5
PGND
PWM
LOGIC
L
TG_DDQ
SW_DDQ
VDDQ
COUT1
VCC
BG_DDQ
M2
PGND
PGND
CSS
OSC
S0
S3
COMP
VREF
AMP
CZ2
CP1
CZ1
RZ1
A1
5VDUAL
FBDDQ
VCC
R1
RZ2
R2
M3
180 Phase
Shift
VCC
PGND
VMCH
L2
TP_1P5
BG_1P5
COUT2
M4
GND_1P5
PGND
PGND
AMP_MCH
COMP_1P5
VREF
CZM1
RZM1
A1
CZM2
CPM1
RM1
RZM2
RM2
FBDDQ
DDQ_REF
5VDUAL
S0
VDDQ
R16
M2
VTT
VTT
Regulation
Control
R17
R18
VTT
AGND
5VDUAL
COUT2
M3
R19
AGND
AGND
PGND
Figure 2. Internal Block Diagram
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FBVTT
NCP5210
PIN DESCRIPTION
Pin
Symbol
Description
1
COMP
VDDQ error amplifier compensation node.
2
FBDDQ
DDQ regulator feedback pin.
3
SS
4
PGND
Soft−start pin of DDQ and MCH.
Power ground.
5
VTT
6
VDDQ
VTT regulator output.
Power input for VTT linear regulator.
7
AGND
Analog ground connection and remote ground sense.
8
FBVTT
VTT regulator pin for closed loop regulation.
9
DDQ_REF
10
FB1P5
11
GND_1P5
12
BG_1P5
Gate driver output for V1P5 regulator low side N−Channel Power FET.
13
TG_1P5
Gate driver output for V1P5 regulator high side N−Channel Power FET.
14
BUF_Cut
Active HIGH control signal to activate S3 sleep state.
15
COMP_1P5
16
5VDUAL
17
BOOT
18
TG_DDQ
Gate driver output for DDQ regulator high side N−Channel Power FET.
19
BG_DDQ
Gate driver output for DDQ regulator low side N−Channel Power FET.
20
SW_DDQ
DDQ regulator switch node and current limit sense input.
21
TH_PAD
Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under
the IC.
Reference voltage input of VTT regulator.
V1P5 switching regulator feedback pin.
Power ground for V1P5 regulator.
V1P5 error amplifier compensation node.
5.0 V Dual supply input, which is monitored by undervoltage lock out circuitry.
Gate driver input supply, which is monitored by undervoltage lock out circuitry, and a boost capacitor
connection between SWDDQ and this pin.
MAXIMUM RATINGS
Rating
Power Supply Voltage (Pin 16) to AGND (Pin 7)
BOOT (Pin 17) to AGND (Pin 7)
Gate Drive (Pins 12, 13, 18, 19) to AGND (Pin 7)
Input / Output Pins to AGND (Pin 7)
Pins 1−3, 5−6, 8−10, 14−15, 20
Symbol
Value
Unit
5VDUAL
−0.3, 6.0
V
BOOT
−0.3, 14
V
Vg
−0.3 DC,
−4.0 for 100 ns; 14
V
VIO
−0.3, 6.0
V
PGND (Pin 4), GND_1P5 (Pin 11) to AGND (Pin 7)
VGND
−0.3, 0.3
V
Thermal Characteristics, QFN−20 Plastic Package
Thermal Resistance Junction−to−Air
RJA
35
°C/W
Operating Junction Temperature Range
TJ
0 to + 150
°C
Operating Ambient Temperature Range
TA
0 to + 70
°C
Storage Temperature Range
Tstg
− 55 to +150
°C
Moisture Sensitivity Level
MSL
2.0
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard:
JESD22–A114. Machine Model (MM) 200 V per JEDEC standard: JESD22–A115.
2. Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
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NCP5210
ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0°C to 70°C, L = 1.7 H,
COUT1 = 3770 F, COUT2 = 470 F, COUT3 = NA, CSS = 33 nF, R1 = 2.166 k, R2 = 2 k, RZ1 = 20 k, RZ2 = 8 , CP1 = 10 nF,
CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 k, RM2 = 2 k, RZM1 = 20 k, RZM2 = 8 , CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nF
for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ.
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
5.0
5.5
V
12.0
13.2
V
SUPPLY VOLTAGE
5VDUAL Operating Voltage
BOOT Operating Voltage
V5VDUAL
VBOOT
SUPPLY CURRENT
S0 Mode Supply Current from 5VDUAL
I5VDL_S0
BUF_Cut = LOW, BOOT = 12 V,
TG_1P5 and BG_1P5 Open
10
mA
S3 Mode Supply Current from 5VDUAL
I5VDL_S3
BUF_Cut = HIGH, TG_1P5 and
BG_1P5 Open
5.0
mA
S5 Mode Supply Current from 5VDUAL
I5VDL_S5
BUF_Cut = LOW, TG_1P5 and
BG_1P5 Open
1.0
mA
S0 Mode Supply Current from BOOT
IBOOT_S0
BUF_Cut = LOW, BOOT = 12 V,
TG_1P5 and BG_1P5 Open
20
mA
S3 Mode Supply Current from BOOT
IBOOT_S3
BUF_Cut = HIGH, TG_1P5 and
BG_1P5 Open
20
mA
4.4
V
550
mV
10.4
V
UNDER−VOLTAGE−MONITOR
5VDUAL UVLO Upper Threshold
V5VDLUV+
5VDUAL UVLO Hysteresis
V5VDLhys
BOOT UVLO Upper Threshold
VBOOTUV+
BOOT UVLO Hysteresis
VBOOThys
250
400
1.0
V
THERMAL SHUTDOWN
Tsd
(Note 3)
145
°C
Tsdhys
(Note 3)
25
°C
VFBQ
TA = 25°C
TA = 0°C to 70°C
Feedback Input Current
IDDQFB
V(FBDDQ) = 1.3 V
Oscillator Frequency in S0 Mode
FDDQS0
217
Oscillator Frequency in S3 Mode
FDDQS3
434
Thermal Shutdown
Thermal Shutdown Hysteresis
DDQ SWITCHING REGULATOR
FBDDQ Feedback Voltage,
Control Loop in Regulation
1.178
1.166
1.190
1.202
1.214
V
1.0
A
250
283
KHz
500
566
KHz
Oscillator Ramp Amplitude
dVOSC
(Note 3)
1.3
Vp−p
Current Limit Blanking Time in S0 Mode
TDDQbk
(Note 3)
400
nS
Current Limit Threshold Offset from 5VDUAL
VOCP
(Note 3)
0.8
V
Minimum Duty Cycle
Dmin
0
%
Maximum Duty Cycle
Dmax
100
%
Iss1
V(SS) = 0 V
4.0
A
DC Gain
GAINDDQ
(Note 3)
70
dB
Gain−Bandwidth Product
GBWDDQ
COMP PIN to GND = 220 nF,
1.0 in Series (Note 3)
12
MHz
SRDDQ
COMP PIN TO GND = 10 pF
8.0
V/S
Soft−Start Pin Current for DDQ
DDQ ERROR AMPLIFIER
Slew Rate
3. Guaranteed by design, not tested in production.
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NCP5210
ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0°C to 70°C, L = 1.7 H,
COUT1 = 3770 F, COUT2 = 470 F, COUT3 = NA, CSS = 33 nF, R1 = 2.166 k, R2 = 2 k, RZ1 = 20 k, RZ2 = 8 , CP1 = 10 nF,
CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 k, RM2 = 2 k, RZM1 = 20 k, RZM2 = 8 , CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nF
for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ.
Characteristic
Symbol
Test Conditions
Min
dVTTS0
IOUT= 0 to 2.0 A (Sink Current)
IOUT= 0 to –2.0 A (Source Current)
−30
Typ
Max
Unit
30
mV
VTT ACTIVE TERMINATION REGULATOR
VTT tracking DDQ_REF/2 at S0 mode
VTT Source Current Limit
ILIMVTsrc
2.0
A
VTT Sink Current Limit
ILIMVTsnk
2.0
A
DDQ_REF Input Resistance
DDQREF
50
k
CONTROL SECTION
BUF_Cut Input Logic HIGH
Logic_H
BUF_Cut Input Logic LOW
Logic_L
0.8
V
Ilogic
1.0
A
BUF_Cut Input Current
2.0
V
GATE DRIVERS
TGDDQ Gate Pull−HIGH Resistance
RH_TG
VCC = 12 V, V(TGDDQ) = 11.9 V
3.0
TGDDQ Gate Pull−LOW Resistance
RL_TG
VCC = 12 V, V(TGDDQ) = 0.1 V
2.5
BGDDQ Gate Pull−HIGH Resistance
RH_BG
VCC = 12 V, V(BGDDQ) = 11.9 V
3.0
BGDDQ Gate Pull−LOW Resistance
RL_BG
VCC = 12 V, V(BGDDQ) = 0.1 V
1.3
TG1P5 Gate Pull−HIGH Resistance
RH_TPG
VCC = 12 V, V(TG1P5) = 11.9 V
3.0
TG1P5 Gate Pull−LOW Resistance
RL_TPG
VCC = 12 V, V(TG1P5) = 0.1 V
2.5
BG1P5 Gate Pull−HIGH Resistance
RH_BPG
VCC = 12 V, V(BG1P5) = 11.9 V
3.0
BG1P5 Gate Pull−LOW Resistance
RL_BPG
VCC = 12 V, V(BG1P5) = 0.1 V
1.3
VFB1P5 Feedback Voltage,
Control Loop in Regulation
VFB1P5
TA = 0°C to 70°C
Feedback Input Current
I1P5FB
MCH SWITCHING REGULATOR
Oscillator Frequency
F1P5
Oscillator Ramp Amplitude
dV1P5OSC
Minimum Duty Cycle
Dmin_1P5
Maximum Duty Cycle
Dmax_1P5
Soft−Start Pin Current for V1P5 regulator
0.784
0.8
0.816
1.0
A
217
250
283
KHz
(Note 4)
1.3
Vp−p
0
%
100
ISS2
(Note 4)
4. Guaranteed by design, not tested in production.
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6
V
8.0
%
A
NCP5210
TYPICAL OPERATING CHARACTERISTICS
550
S3 MODE
SWITCHING FREQUENCY (kHz)
VFBQ, FEEDBACK VOLTAGE (V)
1.196
1.194
1.192
1.19
1.188
1.186
1.184
500
450
400
350
300
S0 MODE
250
1.182
0
20
40
60
TA, AMBIENT TEMPERATURE (°C)
200 0
80
20
40
60
TA, AMBIENT TEMPERATURE (°C)
Figure 3. VFBQ Feedback Voltage
vs. Ambient Temperature
Figure 4. Oscillation Frequency in S0/S3
vs. Ambient Temperature
30
VTT, SINK CURRENT LOAD
REGULATION (mVp−p)
VFB1P5, FEEDBACK VOLTAGE (V)
0.81
0.805
0.8
0.795
0.79
0.785
29.5
29
28.5
28
2 A Sinking Current
with 10 ms Period
and 1 ms Pulse Width
27.5
27
0
20
40
60
TA, AMBIENT TEMPERATURE (°C)
80
0
Figure 5. VFB1P5 Feedback Voltage
vs. Ambient Temperature
VTT, OUTPUT VOLTAGE (VDDQ/2 V)
2 A Sourcing
Current with 10 ms
Period and 1 ms
Pulse Width
−5.5
−6
20
40
60
TA, AMBIENT TEMPERATURE (°C)
−6.5
0.02
Sourcing/Sinking
Current with 10 ms
Period and 1 ms
Pulse Width
0.015
0.01
0.005
0
TA = 25°C
−0.005
−7
−0.01
−0.015
−7.5
−8
−8.5
0
80
Figure 6. VTT Sink Current Load Regulation
vs. Ambient Temperature
−5
VTT, SOURCE CURRENT LOAD
REGULATION (mVp−p)
80
−0.02
−0.025
20
40
60
80
−0.03
−2.5
−1.5
−0.5
0.5
1.5
TA, AMBIENT TEMPERATURE (°C)
IVTT, OUTPUT LOAD CURRENT (A)
Figure 7. VTT Source Current Load Regulation
vs. Ambient Temperature
Figure 8. VTT Output Voltage
vs. Load Current
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2.5
NCP5210
TYPICAL OPERATING WAVEFORMS
Channel 2: VDDQ Output Voltage, 1.0 V/div
Channel 3: VTT Output Voltage, 1.0 V/div
Channel 4: V1P5 Output Voltage, 1.0 V/div
Time Base: 5.0 ms/div
Channel 1: BUF_CUT Pin Voltage, 5.0 V/div
Channel 2: VDDQ Output Voltage, AC−Coupled, 20 mV/div
Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div
Channel 4: V1P5 Output Voltage, AC−Coupled, 50 mV/div
Time Base: 10 ms/div
Figure 9. Power−Up Sequence
Figure 10. S0−S3−S0 Transition
Channel 1: Current Sourced out of VTT, 2.0 A/div
Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div
Channel 3: VTT Output Voltage, AC−Coupled, 50 mV/div
Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div
Time Base: 200 s/div
Channel 1: Current Sunk into of VTT, 2.0 A/div
Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div
Channel 3: VTT Output Voltage, AC−Coupled, 50 mV/div
Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div
Time Base: 200 s/div
Figure 11. VTT Source Current Transient, 0A−2A−0A
Figure 12. VTT Sink Current Transient, 0A−2A−0A
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NCP5210
TYPICAL OPERATING WAVEFORMS
Channel 1: Current Sourced into of VDDQ, 10 A/div
Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div
Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div
Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div
Time Base: 1.0 ms/div
Channel 1: Current Sourced into of V1P5, 10 A/div
Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div
Channel 3: VTT Output Voltage, AC−Coupled, 50 mV/div
Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div
Time Base: 1.0 ms/div
Figure 13. VDDQ Source Current Transient,
0A−20A−0A
Figure 14. V1P5 Source Current Transient,
0A−12A−0A
Channel 1: Current Sourced into of VDDQ, 2.0 A/div
Channel 2: VDDQ Output Voltage, AC−Coupled, 20 mV/div
Time Base: 1.0 ms/div
Figure 15. S3 Mode without 12VATX, 0A−2A−0A
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NCP5210
DETAILED OPERATION DESCRIPTIONS
General
S5−To−S0 Mode Power−Up Sequence
The NCP5210 3−In−1 PWM Dual Buck Linear DDR
Power Controller contains two high efficiency PWM
controllers and an integrated two−quadrant linear regulator.
The VDDQ supply is produced by a PWM switching
controller with two external N−Ch FETs. The VTT
termination voltage is an integrated linear regulator with
sourcing and sinking current capability which tracks at 1/2
VDDQ. The MCH core voltage is created by the secondary
switching controller.
The inclusion of soft−start, supply undervoltage monitors,
short circuit protection and thermal shutdown, makes this
device a total power solution for the MCH and DDR
memory system. This device is housed in a thermal
enhanced space−saving QFN−20 package.
The ACPI control logic is enabled by the assertion of
_VREFGD. Once the ACPI control is activated, the
powerup sequence starts by waking up the 5VDUAL
voltage monitor block. If the 5VDUAL supply is within the
preset levels, the BOOT under voltage monitor block is then
enabled. After 12VATX is ready and the BOOT UVLO is
asserted LOW, the ACPI control triggers this device from S5
shutdown mode into S0 normal operating mode by
activating the soft−start of DDQ switching regulator,
providing BUF_CUT remaining LOW.
Once the DDQ regulator is in regulation and the soft−start
interval is completed, the _INREGDDQ signal is asserted
HIGH to enable the VTT regulator as well as the V1P5
switching regulator.
ACPI Control Logic
DDQ Switching Regulator
The ACPI control logic is powered by the 5VDUAL
supply. External control is applied to the high impedance
CMOS input labeled BUF_CUT. This signal and two
internal under voltage detectors are used to determine the
operating mode according to the state diagram in Figure 17.
These UVLOs monitor the external supplies, 5VDUAL
and 12VATX, through 5VDUAL and BOOT pins
respectively. Two control signals, _5VDUALGD and
_BOOTGD, are asserted when the supply voltages are good.
The device is powered up initially in the S5 shutdown
mode to minimize the power consumption. When all three
supply voltages are good and BUF_CUT is LOW, the device
enters the S0 normal operating mode. Transition of
BUF_CUT from LOW to HIGH in S0 mode triggers the
device into S3 sleep mode. In S3 mode 12VATX supply
collapses. When BUF_CUT is deasserted the state will
change back to S0 mode. The IC can re−enter S5 mode by
removing one of the supplies during S0 mode. It should be
noted that transitions from S3 to S5 or vice versa are not
allowed. A timing diagram is shown in Figure 16.
Table 1 summarizes the operating states of all the
regulators, as well as the conditions of output pins.
In S0 mode the DDQ regulator is a switching synchronous
rectification buck controller driving two external power
N−Ch FETs to supply up to 20 A. It employs voltage mode
fixed frequency PWM control with external compensation
switching at 250kHz ± 13.2%. As shown in Figure 2, the
VDDQ output voltage is divided down and fed back to the
inverting input of an internal amplifier through the FBDDQ
pin to close the loop at VDDQ = VFBQ × (1 + R1/R2). This
amplifier compares the feedback voltage with an internal
reference voltage of 1.190 V to generate an error signal for
the PWM comparator. This error signal is compared with a
fixed frequency RAMP waveform derived from the internal
oscillator to generate a pulse−width−modulated signal. The
PWM signal drives the external N−Ch FETs via the
TG_DDQ and BG_DDQ pins. External inductor L and
capacitor COUT1 filter the output waveform. When the IC
leaves the S5 state, the VDDQ output voltage ramps up at a
soft−start rate controlled by the capacitor at the SS pin.
When the regulation of VDDQ is detected in S0 mode,
_INREGDDQ goes HIGH to notify the control block.
In S3 standby mode, the switching frequency is doubled
to reduce the conduction loss in the external N−Ch FETs.
Internal Bandgap Voltage Reference
An internal bandgap reference is generated whenever
5VDUAL exceeds 2.7 V. Once this bandgap reference is in
regulation, an internal signal _VREFGD is asserted.
Table 1. Mode, Operation and Output Pin Condition
OPERATING CONDITIONS
OUTPUT PIN CONDITIONS
MODE
DDQ
VTT
MCH
TGDDQ
BGDDQ
TP_1P5
BG_1P5
S0
Normal
Normal
Normal
Normal
Normal
Normal
Normal
S3
Standby
H−Z
OFF
Standby
Standby
Low
Low
S5
OFF
H−Z
OFF
Low
Low
Low
Low
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NCP5210
at the half of DDQ_REF. This regulator is stable with any
value of output capacitor greater than 470 F, and is
insensitive to ESR ranging from 1−m to 400 m.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive non−overlap timing control of the complementary
gate drive output signals is provided to reduce
shoot−through current that degrades efficiency.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bi−directional
current limit preset at 2.4 A magnitude is implemented. The
VTT current limit provides a soft−start function during
startup.
Tolerance of VDDQ
Both the tolerance of VFBQ and the ratio of the external
resistor divider R1/R2 impact the precision of VDDQ. With
the control loop in regulation, VDDQ = VFBQ × (1 +
R1/R2). With a worst case (for all valid operating
conditions) VFBQ tolerance of ±1.5%, a worst case range of
±2% for VDDQ will be assured if the ratio R1/R2 is
specified as 1.100 ±1%.
MCH Switching Regulator
The secondary switching regulator is identical to the DDQ
regulator except the output is 10 A, no fault protection is
implemented and the soft−start timing is twice as fast with
respect to CSS.
BOOT Pin Supply Voltage
Fault Protection of VDDQ Regulator
In typical application, a flying capacitor is connected
between SWDDQ and BOOT pins. In S0 mode, 12VATX is
tied to BOOT pin through a Schottky diode as well. A 13−V
Zener clamp circuit must clamp this boot strapping voltage
produced by the flying capacitor in S0 mode.
In S3 mode the 12VATX is collapsed and the BOOT
voltage is created by the Schottky diode between 5VDUAL
and BOOT pins as well as the flying capacitor. The
BOOT_UVLO works specially. The _BOOTGD goes low
and the IC remains in S3 mode.
In S0 mode, an internal voltage (VOCP) = 5VDUAL – 0.8
sets the current limit for the high−side switch. The voltage
VOCP pin is compared to the voltage at SWDDQ pin when
the high−side gate drive is turned on after a fixed period of
blanking time to avoid false current limit triggering. When
the voltage at SWDDQ is lower than VOCP, an overcurrent
condition occurs and all regulators are latched off to protect
against overcurrent. The IC can be powered up again if one
of the supply voltages, 5VDUAL or 12VATX, is recycled.
The main purpose is for fault protection but not to be for an
precise current limit.
In S3 mode, this overcurrent protection feature is
disabled.
Thermal Consideration
Assuming an ambient temperature of 50°C, the maximum
allowed dissipated power of QFN−20 is 2.8 W, which is
enough to handle the internal power dissipation in S0 mode.
To take full advantage of the thermal capability of this
package, the exposed pad underneath must be soldered
directly onto a PCB metal substrate to allow good
thermal contact.
Feedback Compensation of VDDQ Regulator
The compensation network is shown in Figure 2.
VTT Active Terminator
The VTT active terminator is a 2 quadrant linear regulator
with two internal N−Ch FETs to provide current sink and
source capability up to 2.0 A. It is activated only when the
DDQ regulator is in regulation in S0 mode. It draws power
from VDDQ with the internal gate drive power derived from
5VDUAL. While VTT output is connecting to the FBVTT
pin directly, VTT voltage is designed to automatically track
Thermal Shutdown
When the chip junction temperature exceeds 145°C, the
entire IC is shutdown, until the junction temperature drops
below 120°C. Below which, the chip resumes normal
operation.
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11
NCP5210
5VSTBY
or
5VDUAL
12 V
5V
BUF_CUT
Switching
Frequency
Doubles
SS pin
DDQ−S0
VTT
MCH
State
1
2
3
4
5
6
7
8
9
10
S0
11
12 13
S3
14
S0
15 16
17
S5
2. 5VSTBY or 5VSTB is the Ultimate Chip Enable. This supply has to be up first to ensure gates are in known state.
3. 12 V and 5 V supplies can ramp in either order.
4. DDQ will ramp with the tracking of SS pin, timing is 1.2 * CSS / 4 (sec).
5. DDQ SS is completed, then SS pin is released from DDQ. SS pin is shorted to ground.
5. MCH ramps with the tracking of SS pin ramp, timing is 0.8 * CSS / 8 (sec). VTT rises.
6. MCH SS is completed, then SS pin is released from MCH. SS pin is shorted to ground. S0 Mode.
7. S3 MODE − BUF_CUT = H.
8. VTT and MCH will be turned off.
9. 12 V and 5 V ramps to 0 V.
10. Standard S3 Mode.
11. 12 V and 5 V ramp back to regulation.
12. BUF_CUT goes LOW.
13. 12 V UVLO = L and BUF_CUT = L. MCH ramps with SS pin, timing is 0.8 * CSS / 8 (sec). VTT rises.
14. S0 Mode.
15. Prepare S5 Mode − BUF_CUT = L, and 12VUVLO = H or 5VUVLO = H.
16. DDQ, VTT, and MCH Turned OFF.
17. S5 Mode.
Figure 16. NCP5210 Timing Diagram
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12
NCP5210
S5
BUF_CUT = 0 AND
_BOOTGD = 1
BUF_CUT = 0 AND
(_BOOTGD = 0)
S0
BUF_CUT = 0 AND
_BOOTGD = 1
BUF_CUT = 1
NOTE: All possible state transitions are shown.
All unspecified inputs do not cause any state change.
S3
Figure 17. State Transitions Diagram of NCP5210
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13
12VATX
5VDUAL
L1
1 H
TP2
R6
8
VDDQ
C9
100 nF
R5
2.2 k
C10
R7
6.8 nF 20 k
2
4
C1
33 nF
5
VDDQ
6
7
SGND
COMP
SW_DDQ
FBDDQ
BG_DDQ
SS
TG_DDQ
PGND
BOOT
5VDUAL
VTT
VDDQ
AGND
R16
1k
20
18
17
1k
15 COMP_1P5
R4
1
TP5
VDDQ
2.5
VDDQ
C6
4.7 F
4
Q2
85N02R
DPAK
1
3
AGND to
PGND
Filtered
5VDUAL
+C21
100 F
+C7
2200 F
+C25
2200 F
R15
1k
4
R9
R18
51 k
Q4
40N03R
DPAK
1
4.7
+C24
470 F
C5
470 F
ZENER
MMSZ13T1
L2
1.8 H
C4
22 nF
3
R3
14 BUF_CUT
BUF_CUT
13
TG_1P5
12
BG_1P5
11
GND_1P5
C12
4.7 F
Q1
85N02R
DPAK
1
16 5VDUAL
C11
220 nF
+C13
470 F
4
R2
2.2
19
NCP5210
14
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SGND 8
FBVTT
VDDQ 9
DDQREF
C20
10
470 F
FB1P5
COMP_1P5
VTT
1.25
VTT
D2
BAT54HT1
NCP5210
3
TP7
D1
BAT54HT1
C23
10 F
U1
Vref = 1.20 V
SGND
TP2
+C2
3300 F
C8
10 nF
1
R8
2k
Filtered
5VDUAL
5VDUAL
4.7
DPAK
1
+C3
3300 F
L3
1.8 H
3
4
R10
C22
10 F
Q5
C16
40N03R 10 nF
VMCH
COMP_1P5
R12
20 K
1.5
VMCH
R11
2.2 k
3
C17
6.8 nF
TP6
TP8
C18
R13
100 nF
8
C14
4.7 F
+C26
2200 F
+C15
2200 F
R17
1k
TP16
R14
2k
Vref = 800 mV
SGND
AGND to PGND
SGND
Figure 18. NCP5210 Typical Application Circuit
GND
NCP5210
Application Circuit
Power MOSFET Selection
Figure 18 shows the typical application circuit for
NCP5210. The NCP5210 is specifically designed as a total
power solution for the MCH and DDR memory system. This
diagram contains NCP5210 for driving four external N−Ch
FETs to form the DDR memory supply voltage (VDDQ) and
the MCH regulator.
Power MOSFETs are chosen by balancing the cost with
the requirements for the current load of the memory system
and the efficiency of the converter provided. The selections
criteria can be based on the drain−to−source voltage,
drain−to−current, on−resistance RDS(on), and input gate
capacitance. Low RDS(on) and high drain−to−current power
MOSFETs are usually preferred to achieve the high current
requirement of the DDR memory system and MCH, as well
as the high efficiency of the converter. The tradeoff is a
corresponding increase in the input gate capacitor of the
power MOSFETs.
Output Inductor Selection
The value of the output inductor is chosen by balancing
ripple current with transient response capability. A value of
1.7 H will yield about 3.0 A peak−to−peak ripple current
when converting from 5.0 V to 2.5 V at 250 kHz. It is
important that the rated inductor current is not exceeded
during full load, and that the saturation current is not less
than the expected peak current. Low ESR inductors may be
required to minimize DC losses and temperature rises.
PCB Layout Consideration
With careful PCB layout the NCP5210 can supply 20 A or
more current. It is very important to use wide traces or large
copper shades to carry current from the input node through
the MOSFET switches, inductor, and to the output filters and
load. Reducing the length of high current nodes will reduce
losses and reduce parasitic inductance. It is usually best to
locate the input capacitors, the MOSFET switches, and the
output inductor in close proximity to reduce DC losses,
parasitic inductance and radiated EMI.
The sensitive voltage feedback and compensation
networks should be placed near NCP5210 and away from
the switch nodes and other noisy circuit elements. Placing
compensation components near each other will minimize
the loop area and further reduce noise susceptibility.
Input Capacitor Selection
Input capacitors for PWM power supplies are required to
provide a stable, low impedance source node for the buck
regulator to convert from. The usual practice is to use a
combination of electrolytic capacitors and multi−layer
ceramic capacitors to provide bulk capacitance and high
frequency noise suppression. It is important that the
capacitors are rated to handle the AC ripple current at the
input of the buck regulators, as well as the input voltage. In
the NCP5210 the DDQ and MCH regulators are interleaved
(out of phase by 180°) to reduce the peak AC input current.
Optional Boost Voltage Configuration
Output Capacitor Selection
The charge pump circuit in Figure 19 can be used instead
of boost voltage scheme of Figure 18. The advantage in
Figure 19 is the elimination of the requirement for the Zener
clamp. The tradeoff is slightly less boost voltage and a
corresponding increase in MOSFET conduction losses.
Output capacitors are chosen by balancing the cost with
the requirements for low output ripple voltage and transient
voltage. Low ESR electrolytic capacitors can be effective at
reducing ripple voltage at 250 kHz. Low ESR ceramic
capacitors are most effective at reducing output voltage
excursions caused by fast load steps of system memory and
the memory controller.
12VATX
TP2
5VDUAL
TP2
D2
BAT54HT1
D1
C27
100 nF
NCP5210
SW_DDQ 20
BG_DDQ 19
TG_DDQ 18
BOOT 17
5VDUAL 16
15
COMP_1P5
BUF_CUT 14
TG_1P5 13
12
BG_1P5
11
D1
BAT54HT1
BAT54HT1
5VDUAL
4
R2
4.7 1
Q2
3 NTD40N03
C4
5.6 nF
L
R3
1k
R4
4.7
TP5
VDDQ
1
4 DPAK
Q2
NTD40N03
3
C6
4.7
F
GND_1P5
Figure 19. Charge Pump Circuit at BOOT Pin
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15
+
C7
C25
+
2200
2200
F
F
R15 2.5 VDDQ
1k
NCP5210
Table 2. Bill of Material of NCP5210 Application Circuit
Ref Design
Description
Value
Qty
Part #
Manufacturer
Q1, Q2
Power MOSFET N−Channel
24 V, 4.8 m, 85 A
2
NTD85N02R
ON Semiconductor
Q3, Q4
Power MOSFET N−Channel
25 V, 12.6 m, 40 A
2
NTD40N03R
ON Semiconductor
D1, D2
Rectifier Schottky Diode
30 V
2
BAT54HT1
ON Semiconductor
U1
Controller
3−in−1 PWM Dual Buck
and Linear Power
Controller
1
NCP5210
ON Semiconductor
Zener
Zener Diode
13 V, 0.5 W
1
MMSZ13T1
ON Semiconductor
L1
Toroidal Choke
1.0 H, 25 A
1
T60−26(6T)
−
L2, L3
Toroidal Choke
1.8 H, 25 A
2
T50−26B(6T)
−
C2, C3
Aluminum Electrolytic Capacitor
3300 F, 6.3 V
2
EEUFJ0J332U
Panasonic
C5
Aluminum Electrolytic Capacitor
470 F, 35 V
1
EEUFC1V471
Panasonic
C21
Aluminum Electrolytic Capacitor
100 F, 50 V
1
EEUFC1H101
Panasonic
C20
Aluminum Electrolytic Capacitor
470 F, 16 V
1
EEUFC1C471
Panasonic
C13, C24
Aluminum Electrolytic Capacitor
470 F, 10 V
2
EEUFC1A471
Panasonic
C7, C25, C15, C26
Aluminum Electrolytic Capacitor
2200 F, 6.3 V
4
EEUFC0J222SL
Panasonic
C11
Ceramic Capacitor
220 nF, 10 V
1
ECJ1VB1A224K
Panasonic
C6, C12, C14
Ceramic Capacitor
4.7 F, 6.3 V
3
ECJHVB0J475M
Panasonic
C22, C23
Ceramic Capacitor
10 F, 25 V
2
ECJ4YB1E106M
Panasonic
C4
Ceramic Capacitor
22 nF, 25 V
1
ECJ1VB1E223K
Panasonic
C10, C17
Ceramic Capacitor
6.8 nF, 50 V
2
ECJ1VB1H682K
Panasonic
C9, C18
Ceramic Capacitor
100 nF, 16 V
2
ECJ1VB1C104K
Panasonic
C8, C16
Ceramic Capacitor
10 nF, 50 V
2
ECJ1VB1H103K
Panasonic
C1
Ceramic Capacitor
33 nF, 25 V
1
ECJ1VB1E333K
Panasonic
R2
Resistor
2.2 1
−
−
R4
Resistor
1.0 1
−
−
R9, R10
Resistor
4.7 2
−
−
R3, R15, R16, R17
Resistor
1.0 k
4
−
−
R7, R12
Resistor
20 k
2
−
−
R6, R13
Resistor
8.2 2
−
−
R8, R14
Resistor
2.0 k
2
−
−
R5, R11
Resistor
2.2 k
2
−
−
R18
Resistor
51 k
1
−
−
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16
NCP5210
PACKAGE DIMENSIONS
QFN−20, DUAL−SIDED, 6x5 mm
MN SUFFIX
CASE 505AB−01
ISSUE A
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINALS AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
B
PIN 1 LOCATION
E
2X
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
K
L
0.15 C
2X
TOP VIEW
0.15 C
0.10 C
A2
A
0.08 C
A1
SIDE VIEW (A3)
C
SEATING
PLANE
D2
20X
20X
L
e
1
10
E2
K
20
11
20X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
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17
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.65
0.75
0.20 REF
0.23
0.28
6.00 BSC
3.98
4.28
5.00 BSC
2.98
3.28
0.50 BSC
0.20
−−−
0.50
0.60
NCP5210
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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For additional information, please contact your
local Sales Representative.
NCP5210/D
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