VISHAY SI2324DS

SPICE Device Model Si2324DS
Vishay Siliconix
N-Channel 100 V (D-S) MOSFET
DESCRIPTION
CHARACTERISTICS
The attached SPICE model describes the typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to + 125 °C temperature ranges under the pulsed 0 V to
10 V gate drive. The saturated output impedance is best fit
at the gate bias near the threshold voltage. A novel
gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding
convergence difficulties of the switched Cgd model. All
model parameter values are optimized to provide a best fit
to the measured electrical data and are not intended as an
exact physical interpretation of the device.
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
R1
3
M2
Gy
G
RG
–
+
ETCV
Gx
CGS
DBD
M1
S
Note
• This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer
to the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 63245
S11-1189-Rev. A, 27-Jun-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPICE Device Model Si2324DS
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SIMULATED MEASURED
DATA
DATA
SYMBOL
TEST CONDITIONS
VGS(th)
VDS = VGS, ID = 250 μA
1.8
-
VGS = 10 V, ID = 1.5 A
0.199
0.195
VGS = 6 V, ID = 1 A
0.222
0.222
UNIT
Static
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
RDS(on)
V

Forward Transconductancea
gfs
VDS = 20 V, ID = 4.6 A
3
2
S
Body Diode Voltage
VSD
IS = 1.3 A
0.79
0.80
V
190
190
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 20 V, VGS = 0 V, f = 1 MHz
22
22
15
13
VDS = 50 V, VGS = 10 V, ID = 1.6 A
4.1
5.2
2.5
2.9
VDS = 50 V, VGS = 4.5 V, ID = 1.6 A
0.75
0.75
1.4
1.4
pF
nC
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
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Document Number: 63245
S11-1189-Rev. A, 27-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPICE Device Model Si2324DS
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ = 25 °C, unless otherwise noted)
5
3.0
4
2.4
ID - Drain Current (A)
ID - Drain Current (A)
TJ = 125 °C
3
VGS = 10 V, 7 V, 6 V, 5 V, 4 V
2
1.8
1.2
TJ = - 55 °C
0.6
1
TJ = 25 °C
VGS = 3 V
0
0.0
0.0
0.5
1.0
1.5
0
2.0
1
VDS - Drain-to-Source Voltage (V)
2
3
4
VGS - Gate-to-Source Voltage (V)
0.28
300
0.26
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
240
0.24
VGS = 6 V
0.22
VGS = 10 V
0.20
Ciss
180
120
60
0.18
Coss
0.16
Crss
0
0
1
2
3
4
5
0
ID - Drain Current (A)
20
40
60
80
100
VDS - Drain-to-Source Voltage (V)
10
10
ID = 1.6 A
IS - Source Current (A)
VGS - Gate-to-Source Voltage (V)
TJ = 150 °C
8
VDS = 50 V
6
VDS = 80 V
4
TJ = 25 °C
1
2
0.1
0
0.0
1.5
3.0
Qg - Total Gate Charge (nC)
4.5
6.0
0
0.3
0.6
0.9
1.2
VSD - Source-to-Drain Voltage (V)
Note
• Dots and squares represent measured data.
Document Number: 63245
S11-1189-Rev. A, 27-Jun-11
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Document Number: 91000
Revision: 11-Mar-11
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