ATA5577C - Complete

ATA5577C
Read/Write LF RFID IDIC 100 to 150kHz
DATASHEET
Features
● Contactless power supply
● Contactless Read/Write data transmission
● Radio frequency fRF from 100kHz to 150kHz
● Basic Mode or Extended Mode
● Compatible with Atmel® T5557, ATA5567
● Replacement for Atmel e5551/T5551 in most common operation modes
● Configurable for ISO/IEC 11784/785 compatibility
● Total 363 bits EEPROM memory: 11 blocks (32 bits + 1 lock bit)
● 7  32 bits EEPROM User Memory, including 32-bit Password Memory
● 2  32 bits for unique ID
● 1  32-bit option register in EEPROM to set up the Analog Front End:
● Clock and gap detection level
● Improved downlink timing
● Clamp and modulation voltage
● Soft modulation switching
● Write damping like the Atmel T5557/ATA5567 or with resistor
● Downlink protocol
● 1  32-bit configuration register in EEPROM to set up:
● Data rate:
● RF/2 to RF/128, binary selectable or
● Fixed Basic Mode rates
● Modulation/coding:
● Bi-phase, Manchester, FSK, PSK, NRZ
● Other options:
● Password Mode
● Max block feature
● Direct Access Mode
● Sequence terminator(s)
● Blockwise write protection (lock bit)
● Answer-On-Request (AOR) Mode
● Inverse data output
● Disable test mode access
● Fast downlink (~6Kbits/s versus ~3Kbits/s)
● OTP functionality
● Init delay (~67ms)
9187H-RFID-07/14
● High Q-antenna tolerance due to build in options
● Adaptable to different applications: access control, animal ID and waste management
● On-chip trimmed antenna capacitor:
● 250pF/330pF (±3%)
● 75pF/130pF (on request)
● Without on-chip capacitor (on request)
● Pad options
● Atmel ATA5577M1C
● 100µm  100µm for wire bonding or flip chip
● Atmel ATA5577M2C
● 200µm 400µm for direct coil bonding
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ATA5577C [DATASHEET]
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1.
Description
The Atmel® ATA5577C is a contactless read/write IDentification IC (IDIC®) for applications in the 125kHz or 134kHz
frequency band. A single coil connected to the chip serves as the IC's power supply and bi-directional communication
interface. The antenna and chip together form a transponder or tag.
The on-chip 363-bit EEPROM (11 blocks with 33 bits each) can be read and written block-wise from a base station (reader).
Data is transmitted from the IDIC (uplink) using load modulation. This is achieved by damping the RF field with a resistive
load between the two terminals, coil 1 and coil 2. The IC receives and decodes serial base station commands (downlink),
which are encoded as 100% amplitude modulated (OOK) pulse-interval-encoded bit streams.
2.
Compatibility
The Atmel ATA5577C is designed to be compatible with the Atmel T5557/ATA5567. The structure of the configuration
register is identical. The two modes, basic mode and extended mode, are also available. The Atmel ATA5577C is able to
replace the Atmel e5551/T5551 in most common operation modes. In all applications, the correct functionality of the
replacements must be evaluated and proved.
For further details, refer to the Atmel web site for product-relevant application notes.
System Block Diagram
Figure 3-1. RFID System Using Atmel ATA5577C Tag
Power
Reader
or
Base station
Data
1)
Controller
Transponder
Coil interface
3.
Memory
Atmel ATA5577
1) Mask option
ATA5577C [DATASHEET]
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3
4.
Atmel ATA5577C - Functional Blocks
Figure 4-1. Block Diagram
AFE option register
POR
1)
Mode register
Write
decoder
Coil 1
Analog front end
Modulator
Memory
(363-bit EEPROM)
Data-rate
generator
Controller
Coil 2
Input register
Test logic
HV generator
1) Mask option
4.1
Analog Front End (AFE)
The AFE includes all circuits that are directly connected to the coil terminals. It generates the IC's power supply and handles
the bi-directional data communication with the reader. It consists of the following blocks.
● Rectifier to generate a DC supply voltage from the AC coil voltage
●
●
●
●
4.2
Clock extractor
Switchable load between Coil1 and Coil2 for data transmission from the tag to the reader
Field-gap detector for data transmission from the base station to the tag
ESD-protection circuitry
AFE Option Register
The option register maintains a readable shadow copy of the data held in the EEPROM block 3, page 1. This contains the
analog front end's level and threshold settings, as well as enhanced downlink protocol selection with which the device can be
fine tuned for perfect operation and all application environments. It is continually refreshed during read-mode operation and
(re)-loaded after every power-on reset (POR) event or reset command. By default, the option register is pre-programmed
according to Table 10-1 on page 39.
4.3
Data-rate Generator
The data rate is binary programmable to operate at any even-numbered data rate between RF/2 and RF/128, or to any of the
fixed, basic-mode data rates (RF/8, RF/16, RF/32, RF/40, RF/50, RF/64, RF/100 and RF/128).
4.4
Write Decoder
The write decoder detects the write gaps and verifies the validity of the data stream according to the Atmel® e555x downlink
protocol (pulse interval encoding).
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4.5
HV Generator
This on-chip charge pump circuit generates the high voltage required to program the EEPROM.
4.6
DC Supply
Power is supplied to the IDIC externally via the two coil connections. The IC rectifies and regulates this RF source, and uses
it to generate its supply voltage.
4.7
Power-On Reset (POR)
The power-on reset (POR) circuit blocks the voltage supply to the IDIC until an acceptable voltage threshold has been
reached.
4.8
Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
4.9
Controller
The control logic module executes the following functions:
● Load mode register with configuration data from EEPROM block 0 after power on and during reading
4.10
●
Load option register with the settings for the analog front end stored in EEPROM page 1, block 3 after power on and
during reading
●
●
Control all EEPROM memory read/write access and data protection
Handles the downlink command decoding detecting protocol violations and error conditions
Mode Register
The mode register maintains a readable shadow copy of the configuration data held in block 0 of the EEPROM. It is
continually refreshed during read mode and (re-)loaded after every POR event or reset command. On delivery, the mode
register is pre-programmed according to Table 10-1 on page 39.
4.11
Modulator
The modulator encodes the serialized EEPROM data for transmission to a tag reader or base station. Several types of
modulation are available including Manchester, bi-phase, FSK, PSK, and NRZ.
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4.12
Memory
Page 0
Page 1
Figure 4-2. Memory Map
0
1.........................................................................................32
L
Analog front end option set-up
Block 3
1
Traceability data
Block 2
1
Traceability data
Block 1
L
Page 0 configuration data
Block 0
L
User data or password
Block 7
L
User data
Block 6
L
User data
Block 5
L
User data
Block 4
L
User data
Block 3
L
User data
Block 2
L
User data
Block 1
L
Configuration data
Block 0
32 bits
Not transmitted
The memory is a 363-bit EEPROM, which is arranged in 11 blocks of 33 bits each. Each block includes a single lock bit,
which is responsible for write-protecting the associated block. Programming takes place on a block basis, so a
complete block (including lock bit) can be programmed with a single command. The memory is subdivided into two
page areas. Page 0 contains eight blocks, and page 1 contains three blocks. All 33 bits of a block, including the lock bit, are
programmed simultaneously.
Block 0 of page 0 contains the mode/configuration data, which is not transmitted during regular-read mode operations.
Addressing block 0 will always affect block 0 of page 0 regardless of the page selector. Block 7 of page 0 may be used as
a protection password.
Block 3 of page 1 contains the analog front end option register, which is also not transmitted during regular-read mode
operation.
Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lock bit itself) is not reprogrammable via the RF field.
Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modulation parameters defined in the
configuration register after the opcode “11” is issued by the reader (see Figure 5-10 on page 19 and Figure 5-11 on page 19).
The traceability data blocks are programmed and locked by Atmel®.
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4.13
Traceability Data Structure/Unique ID
Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked by Atmel® during production testing
(1). The most significant byte of block 1 is fixed to E0h, the allocation class (ACL). as defined in ISO/IEC 15963-1. The
second byte is, therefore, defined in ISO/IEC 7816-6 as Atmel manufacturer ID (15h). The following 5 bits indicate chip ID
(CID - "00001b" for Atmel ATA5577M1, and "00010" for Atmel ATA5577M2), and the next bits (IC revision, ICR) are used by
Atmel for the IC and/or foundry version of the Atmel ATA5577C.
The lower 40 bits of data encode Atmel's traceability information, and conform to a unique numbering system (unique ID).
These 40 data bits contain the lot ID (year, quarter, number), wafer number (Wafer#), and die number of the wafer (DW).
Note:
1.
This is only valid for sawn wafer on foil delivery.
Figure 4-3. Atmel ATA5577C Traceability Data Structure
Example:
Bit No.
1
Block 1
“E0h“
“15h“
“0000 1b“
“010b“
“9h“
“00b“
“00b“
8 bit
8 bit
5 bit
3 bit
4 bit
2 bit
2 bit
…
8
9
ACL
Bit value
63
Bit value
31
Block 2
…
16
1
Example:
…
21
CID
22
…
24
25
ICR
…
28
Year
29
30
Quarter
31
32
LSB
…
Wafer#
12
13
…
32
Number
MSB
Number
Bit No.
17
MFC
0
DW
17
18
…
31
12 bit
5 bit
15 bit
“0000 1010 0100b“
“0110 0b“
“000 0100 1101 0010b“
32
(Example is for Atmel ATA5577M1330C, Year: 2009, Quarter: 1st, Number: 0164, Wafer#: 12, DW: 1234)
ACL
MFC
CID
ICR
Year
Quarter
Number
Wafer#
DW
Allocation class as defined in ISO/IEC 15963-1 = E0h
Atmel Corporation manufacturer code as defined in ISO/IEC 7816-6 = 15h
5 bit Chip ID for identification of the different products
“00001b” for Atmel ATA5577M1 and “00010b” for Atmel ATA5577M2
3-bit IC revision to identify foundry and/or revision of IC
1-digit BCD encoded year of manufacturing
2 bits for quarter of manufacturing
14 bits of consecutive number
5 bits for wafer number
15 bits designating sequential die number on wafer
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5.
Operating the Atmel ATA5577C
5.1
Configuring the Atmel ATA5577C
2
Block 3 Page 1– Analog Front End Option Set-up
L
1
Lock Bit
Table 5-1.
3
4
Option Key(1)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0
0
0
0
1
0
One pulse strong
1
0
0
Two pulses
1
1
0
Smooth
1
1
1
Write Damping
Downlink Protocol
Demod Delay
1
0 Leading Zero Reference
1
1 1 of 4 Coding Reference
0
0 None
0
1 One pulse
1
0 Two pulses
Clamp low typ . 5Vp
1
0
1
1 RFU
Clamp high typ(2). 8Vp
1
1
0
0
0
1 WD + high att.
RFU 0
1
0
1
0 Low att.
Mod low typ(2). 1Vp 1
0
0
1
1 High att.
Mod high typ(2). 3Vp 1
1
1
0
0 WD only
Clkdet med typ. 550mVp 0
0
1
0
1 Off
RFU 0
1
1
1
0 RFU
Clkdet low typ. 250mVp 1
0
1
1
1 RFU
Clkdet high typ. 800mVp 1
1
0
Gapdet low typ. 250mVp 1
0
Gapdet high typ. 850mVp 1
1
0
0
0
0
0 WD + low att.
Mod med typ(2). 2Vp 0
1. If the option key is 6 or 9, the front end options are activated. For all other values, they take on the default state (all 0). If
the option key is 6, then the complete page 1 (i.e., option register and traceability data) cannot be overwritten by any test
write command. This means that if the lock bits of the three blocks of page 1 are set and the option key is 6, then all of
page 1's blocks are locked against change.
2. Weak field condition
8
0 Fixed Bit Length
1
1
0
1 Long Leading Reference
0
RFU 0
0
0
0
Gapdet med typ. 550mVp 0
0
0
0
0
0
(RFU)
RFU
0
0
Reserved for Future Use
Clamp med typ(2). 6Vp
(2)
Notes:
Gap-detection Threshold
Off
One pulse weak
Clock-detection Threshold
1 Locked
Modulation Voltage
0 Unlocked
Clamp Voltage
Soft Modulation
0
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5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0
0
0
0
0
0
Master Key
0
0
0
Modulation
Data Bit
Rate
(1), (2)
RF/8 0
0
0
0
MAX
BLOCK
0 RF/2
RF/16 0
0
1
0
1 RF/4
0 Unlocked
RF/32 0
1
0
1
0 RF/8
1 Locked
RF/40 0
1
1
1
1 Res.
RF/50 1
0
0
0
0 Direct
RF/64 1
0
1
0
0
0
0
1 PSK1
1
0
0
0
0
1
0 PSK2
RF/128 1
1
1
0
0
0
1
1 PSK3
0
0
1
0
0 FSK1
0
0
1
0
1 FSK2
0
0
1
1
0 FSK1a
0
0
1
1
1 FSK2a
0
1
0
0
0 Manchester
1
0
0
0
0 Bi-phase
1
1
0
0
0 Reserved
7
8
0
0
0
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
n5 n4 n3 n2 n1 n0
Data Bit Rate
PSKCF
Modulation
0
0
RF/2
Direct 0
0
0
0
0
0
1
RF/4
0 Unlocked
PSK1 0
0
0
0
1
1
0
RF/8
1 Locked
PSK2 0
0
0
1
0
1
1
Res.
PSK3 0
0
0
1
1
FSK1 0
0
1
0
0
FSK2 0
0
1
0
1
Manchester 0
1
0
0
0
Bi-phase 1
0
0
0
0
Differential bi1
phase
1
0
0
0
Note:
RF/(2n+2)
MAXBLOCK
Init Delay
6
0
Inverse Data
Master Key(1), (2)
5
Fast Downlink
4
Seq. Start Marker
3
OTP
2
Block 0 Page 0 – Configuration Map in Extended Mode (X-mode)
AOR
Lock Bit
1
0
0
1. If the Master Key is 6 the test mode access is disabled
2. If the Master Key is neither 6 nor 9, the extended function mode and Init Delay are disabled
Table 5-3.
L
0
RF/100 1
X-mode
Notes:
0
0
Init Delay
4
ST Sequence Terminator
3
PWD
2
PWD
1
AOR
Lock Bit
L
Block 0 Page 0 – Configuration Mapping in Basic Mode
PSKCF
Table 5-2.
1. If the Master Key is 6 and bit 15 is set, the test mode access is disabled and the extended mode is active
2. If the Master Key is 9 and bit 15 is set, the extended mode is enabled
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5.2
Soft Modulation Switching
Abrupt rise of the modulation signal at the beginning of modulation - especially in applications with high-quality antennas could lead to clock losses and, therefore, timing violations. To prevent this, several soft modulation settings can be chosen
for a soft transition into the modulation state.
Soft modulation should only be used in combination with modulation schemes and data rates which do not involve high
frequency-modulation changes.
Table 5-4.
Bit 5-7 (bl3 p1)
000
010
100
110
111
Description
No soft
modulation
One pulse weak
One pulse strong
Two pulses
Smooth
clamp
5.3
Soft Modulation Switching Scheme
75%
50%
damp
Demodulation Delay
Soft modulation will cause imbalance in modulated and unmodulated phases. Depending on the soft modulation setting, the
unmodulated phase can be longer than the modulated phase. To balance out this mismatch, the switch point from the
modulated to the unmodulated phase can be delayed for one or two pulses.
These delays and soft modulation switching should only be used in combination with modulation schemes and data rates
which do not involve high frequency-modulation changes.
Table 5-5.
Demodulation Delay Scheme
Bits 19 and 20 (bl3 p1)
Description
mod
00
No demodulation delay
C1-C2
mod
Demodulation delay
one pulse
C1-C2
01
mod
10
10
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C1-C2
Demodulation delay
two pulses
5.4
Write Damping
Reader-to-tag communication is initialized by sending a start gap from the reader station. To ease gap detection with respect
to detecting subsequent field gaps reliably, receive damping and low attenuation are activated by default.
Especially in combination with high quality coils, a higher attenuation factor can be switched on to fasten the relaxation time.
Using antenna coils with low Q-factor might make it feasible to switch off the write damping. This results in better energy
balance and, therefore, improved write distance.
5.5
Initialization and Init-Delay
The power-on reset (POR) circuit remains active until an adequate voltage threshold has been reached. This, in turn,
triggers the default initialization delay sequence. During this configuration period of about 192 field clocks, the Atmel®
ATA5577C is initialized with the configuration data stored in EEPROM block 0 and with the options stored in block 3, page 1.
Tag modulation in regular-read mode will be observed about 3ms after entering the RF field. If the init-delay bit is set, the
Atmel ATA5577C variant with damping during initialization remains in a permanent damping state for t ~ 69ms at f = 125kHz.
The Atmel ATA5577C variant without damping will start modulation after t ~ 69ms without damping.
● Init delay = 0: TINIT = 192 TC + TPOR ~ 3ms; TC = 8µs at f = 125kHz
(TPOR denotes delay for POR and depends on environmental conditions)
Init delay = 1: TINIT = (192 + 8192)  TC + TPOR ~ 69ms
●
Any field gap occurring during this initialization phase will restart the complete sequence. After this initialization time, the
Atmel ATA5577C enters regular-read mode, and modulation starts automatically using the parameters defined in the
configuration register.
5.6
Modulator in Basic Mode
The modulator consists of data encoders for the following types of modulation in Basic mode:
Table 5-6.
Mode
Types of Modulation in Basic Mode
Direct Data Output
(1)
FSK1a
FSK/8 - FSK/5
0 = RF/8
1 = RF/5
FSK2a(1)
FSK/8 - FSK/10
0 = RF/8
1 = RF/10
(1)
FSK/5 - FSK/8
0 = RF/5
1 = RF/8
(1)
FSK/10 - FSK/ 8
0 = RF/10
1 = RF/8
(2)
PSK1
Phase change when input changes
PSK2(2)
Phase change on bit clock if input high
FSK1
FSK2
(2)
PSK3
Phase change on rising edge of input
Manchester
0 = falling edge, 1 = rising edge
Bi-phase
1 creates an additional mid-bit change
NRZ
Notes:
1 = damping on, 0 = damping off
1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub carrier frequency.
5.7
Maxblock
After entering regular-read mode, the Atmel ATA5577C transmits the data content starting with block 1. The MAXBLK
setting defines how many data blocks will be transmitted.
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5.8
Password
When password mode is active (PWD = 1), the first 32 bits after the opcode are regarded as the password. They are
compared bit by bit with the contents of block 7, starting at bit 1. If the comparison fails, the Atmel ATA5577C will not
program the memory. Instead it will restart in regular-read mode once the command transmission is finished.
Note:
In password mode, MAXBLK should be set to a value lower than 7 to prevent the password from being transmitted by the Atmel ATA5577C.
Each transmission of the direct access command (2 opcode bits, 32-bit password, “0” bit, plus 3 address bits = 38 bits)
needs about 18ms. Testing all possible combinations (about 4.3 billion) would take about two years.
5.9
Answer-On-Request (AOR) Mode
When the AOR bit in the configuration register is set, the Atmel® ATA5577C does not start modulation in the regular-read
mode after loading configuration block 0. The tag waits for a valid AOR data stream (wake-up command) from the reader
before modulation is enabled. The wake-up command consists of the opcode ("10" or "11") followed by a valid password.
The selected tag will remain active until the RF field is turned off or a new command with a different password is transmitted,
which may address another tag in the RF field.
Table 5-7.
PWD
1
Atmel ATA5577C - Modes of Operation
AOR
1
Behavior of Tag after Reset Command or POR
De-activate Function
Answer-On-Request (AOR) mode:
Command with non-matching
password deactivates the
selected tag
- Modulation starts after wake up with a matching password
- Programming needs valid password
Password mode:
1
0
- Modulation in regular-read mode starts after reset
- Programming and direct access needs valid password
Normal mode:
0
-
- Modulation in regular-read mode starts after reset
- Programming and direct access without password
Figure 5-1. Answer-on-request (AOR) Mode, Fixed Bit-length Protocol Example
Modulation
VCoil1 - Coil2
Loading
configuration
and option
POR
12
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No modulation
because AOR = 1
AOR wake-up command
(with valid PWD)
Figure 5-2. Anticollision Procedure Using AOR Mode
Reader
Tag
Initialize tags with
AOR = 1, PWD = 1
Field OFF
ON
POWER-ON RESET
Read configuration
Wait for tW > 2.5ms
Enter AOR mode
Wait for OPCODE +
PWD
"wake-up
command"
"Select a single tag"
send OPCODE + PWD
"wake-up command"
Receive damping ON
No
Password correct?
Yes
Decode data
No
Send block 1 to MAXBLK
All tags read?
Yes
Field ON
OFF
Exit
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5.10
ATA5577C in Extended Mode (X-mode)
In general, setting of the master key (bits 1 to 4) of block 0 to the value 6 or 9 together with the X-mode bit will enable the
extended mode functions such as the binary bit-rate generator, OTP functionality, fast downlink, inverse data output and
sequence start marker.
● Master key = 9: Test mode access and extended mode are both enabled.
●
Master key = 6: Any test mode access will be denied but the extended mode is still enabled.
Any other master key setting will prevent activation of the Atmel® ATA5577C extended mode options, even when the Xmode bit is set.
5.10.1 Modulator in Extended-Mode
Table 5-8.
Atmel ATA5577C Types of Modulation in Extended Mode
Mode
Direct Data Output Encoding
Inverse Data Output Encoding
FSK1(1)
FSK/5 - FSK/8
0 = RF/5; 1 = RF/8
FSK/8 - FSK/5
0 = RF/8; 1 = RF/5
(= FSK1a)
FSK2(1)
FSK/10 - FSK/8
0 = RF/10; 1 = RF/8
FSK/8 FSK/10
0 = RF/8; 1 = RF/10
(= FSK2a)
PSK1(2)
Phase change when input changes
Phase change when input changes
PSK2(2)
Phase change on bit clock if input high
Phase change on bit clock if input low
PSK3(2)
Phase change on rising edge of input
Phase change on falling edge of input
Manchester
0 = falling edge, 1 = rising edge mid bit
1 = falling edge, 0 = rising edge mid bit
Bi-phase
1 creates an additional mid-bit change
0 creates an additional mid-bit change
Differential bi-phase
0 creates an additional mid-bit change
1 creates an additional mid-bit change
NRZ
Notes:
1 = damping on, 0 = damping off
0 = damping on, 1 = damping off
1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.
5.10.2 Binary Bit-rate Generator
In extended mode the data rate is binary programmable to operate at any even-numbered data rate between RF/2 and
RF/128 as given in the formula below.
Data rate = RF / (2n + 2)
5.10.3 OTP Functionality
If the OTP bit is set to 1, all memory blocks are write protected and behave as if all lock bits are set to 1. If, in addition, the
master key is set to 6, the Atmel ATA5577C mode of operation is locked forever (one-time-programming functionality).
If the master key is set to 9, test-mode access allows re-configuration of the tag.
5.10.4 Fast Downlink
In the optional fast downlink mode, the time between two gaps is reduced. In the fixed bit-length protocol mode, there are
nominally 12 field clocks for a 0 and 28 field clocks for a 1. When there is no gap for more than 32 field clocks after a
previous gap, the Atmel ATA5577C in the fixed bit length protocol mode will exit the downlink mode (refer to Table 5-10 on
page 20).
The fast downlink mode timings for the long-leading-reference protocol are shown in Table 5-11 on page 21, for the leadingzero-reference protocol in Table 5-12 on page 21 and for the 1-of-4-coding protocol in Table 5-12 on page 21.
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5.10.5 Inverse Data Output
In extended mode (X-mode), the Atmel ATA5577C supports an inverse data output option. If inverse data is enabled, the
modulator shown in Figure 5-3 works on inverted data (see Figure 5-8 on page 14). This function is supported for all basic
types of encoding.
Figure 5-3. Data Encoder for Inverse Data Output
PSK1
PSK2
PSK3
Intern out
data
Direct/NRZ
Sync
D
Data output
MUX
XOR
FSK1
Data clock
CLK
R
FSK2
Manchester
Bi-phase
Inverse data output
5.11
Modulator
Tag-to-Reader Communication
During read operation (uplink mode), the data stored within the EEPROM are cycled, and the coil 1 and Coil 2 terminals are
load modulated. This resistive load modulation can be detected at the reader device.
5.11.1 Regular-read Mode
In regular-read mode, data from the memory are transmitted serially, starting with block 1, bit 1, up to the last block (for
example, 7), bit 32. The last block to be read is defined by the mode parameter field MAXBLK in EEPROM block 0. When
the data block addressed by MAXBLK has been read, data transmission restarts with block 1, bit 1.
The user may limit the cyclic data stream in regular-read mode by setting MAXBLK between 0 and 7 (representing each of
the eight data blocks). If set to 7, blocks 1 through 7 can be read. If set to 1, only block 1 is transmitted continuously. If set to
0, the contents of the configuration block (normally not transmitted) can be read. In the case of MAXBLK = 0 or 1, regularread mode cannot be distinguished from block-read mode.
Figure 5-4. Examples of Different MAXBLK Settings
MAXBLK = 5
0
Block 1
Block 4
Block 5
Block 1
Block 2
Block 2
Block 1
Block 2
Block 1
Block 0
Block 0
Block 0
Block 0
Loading block 0
MAXBLK = 2
0
Block 1
Loading block 0
MAXBLK = 0
0
Block 0
Loading block 0
Every time the Atmel® ATA5577C enters regular or block read mode, the first bit transmitted is a logical 0. The data stream
starts with block 1, bit 1, continues through MAXBLK bit 32, and, if in regular-read mode, cycles continuously.
Note:
This behavior is different from that of the original Atmel e555x, and helps to decode PSK-modulated data.
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5.11.2 Block-read Mode
With the direct-access command, only the addressed block is read repetitively. This mode is called block-read mode. Direct
access is entered by transmitting the page access opcode (“10” or “11”), a single 0 and the requested 3-bit block address
when the tag is in normal mode.
In password mode (PWD bit set), direct access to a single block needs the valid 32-bit password to be transmitted after the
page access opcode, followed by a 0 and the 3-bit block address. If the transmitted password does not match the contents of
block 7, the Atmel ATA5577C tag returns to regular-read mode.
Note:
A direct access to block 0 of page 1 will read the configuration data of block 0, page 0.
A direct access to block 4 to 7 of page 1 reads all data bits as zero.
5.11.3 Sequence Terminator (Basic Mode)
The sequence terminator (ST) is a special damping pattern which is inserted in front of the first block and may be used to
synchronize the reader. This sequence terminator is recommended only for FSK and Manchester coding. This basic mode
sequence terminator consists of four bit periods. During the first and third bit period, the data value is 1. During the second
and fourth bit periods, modulation is switched off (using Manchester encoding, switched on).
Bi-phase modulated data blocks need fixed leading and trailing bits in combination with the sequence terminator to be
reliably identified.
The sequence terminator may be individually enabled by setting mode bit 29 (ST = 1) in basic mode (X-mode = 0).
In the regular-read mode, the sequence terminator is inserted at the start of each MAXBLK-limited read data stream.
In block-read mode, after any block write or direct access command, or if MAXBLK was set to 1, the sequence terminator is
inserted before the transmission of the selected block.
This behavior is different from that of previous ICs (Atmel e5551/T5551, T5554). For further details, refer to the relevant
application notes.
Figure 5-5. Read Data Stream with Sequence Terminator
No terminator
Block 1
Block 2
MAXBLK
Block 1
Block 2
Regular-read mode
Sequence terminator
Sequence terminator
St = on
Block 1
Block 2
MAXBLK
Block 1
Block 2
Figure 5-6. Basic Mode Sequence Terminator Waveforms
Bit period
Sequence
Data 1
Modulation
off (on)
Last bit
Data 1
Modulation
off (on)
First bit
Waveforms per different modulation types
bit 1 or 0
Manchester
VCoilPP
FSK
Sequence terminator is not suitable for Bi-phase or PSK modulation
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5.11.4 Sequence Start Marker (X-mode)
The Atmel® ATA5577C sequence start marker is a special damping pattern in extended mode which may be used to
synchronize the reader. The sequence start marker consists of two bits ("01" or "10") which are inserted as a header before
the first block to be transmitted if, in extended mode, bit 29 is set. At the start of a new block sequence, the value of the two
bits is inverted.
Figure 5-7. Atmel ATA5577C Sequence Start Marker in Extended Mode
Sequence start marker
5.12
Block read mode
10
Block n
Regular read mode
10
Block 1
01
Block n
Block 2
10
Block n
01
MAXBLK
01
Block 1
Block n
Block 2
10
Block n
MAXBLK
01
10
Reader to Tag Communication
Data is transmitted to the tag by interrupting the RF field with short field gaps (on-off keying) in accordance with the Atmel
T5557/ATA5567 write method (downlink mode). The duration of these field gaps is, for example, 100µs. The time between
two gaps encodes the 0/1 information to be transmitted (pulse interval encoding). There are four different downlink protocols
available, which are selectable via bit 21 and bit 22 in the option register block 3, page 1 (see Table 5-1 on page 8).
Choosing the default downlink protocol (fixed-bit-length protocol), the time between two gaps is nominally 24 field clocks for
a 0 and 56 field clocks for a 1. When there is no gap for more than 64 field clocks after a previous gap, the Atmel ATA5577C
exits the downlink mode. The tag starts with the command execution if the correct number of bits were received. If a failure is
detected, the Atmel ATA5577C does not continue and enters regular-read mode.
Improved downlink performance could be achieved by choosing self-calibrating downlink protocols. The Atmel ATA5577C
offers three different possibilities to achieve better performance using self-calibrating downlink protocols.
● Long leading reference:
Fully forward and backward compatible with former tags and readers.
●
Leading zero:
A reader has to send a leading zero in front of the downlink bit stream. This leading zero serves as a reference for the
following zero and one bits.
●
1-of-4 coding:
Compact downlink protocol with optimized energy balance
5.12.1 Start Gap
The initial gap is referred to as the start gap. This triggers the reader-to-tag communication. In the option register (block 3,
page 1), several settings can be chosen to ease gap detection during this mode of operation; for example, the receive
damping can be activated (see Table 5-1 on page 8). The start gap may need to be longer than subsequent gaps — socalled write gaps — in order to be detected reliably.
A start gap will be accepted at any time after the mode register has been loaded (≥ 3ms). A single gap will not change the
previously selected page (by a previous opcode “10” or “11”).
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Figure 5-8. Start of Reader-to-tag Communication
Read mode
Write mode
Write damping settings
Sgap
Table 5-9.
Wgap
Gap Scheme
Parameters
Remark
Start gap
Write gap
Normal downlink mode
All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
Note:
Symbol
Min.
Max.
Unit
Sgap
8
50
TC
Wgap
8
20
TC
5.12.2 Downlink Data Protocols
The Atmel® ATA5577C expects to receive a dual-bit opcode as a part of a reader command sequence. There are three valid
opcodes:
● The opcode “10” precedes all downlink operations for page 0.
●
The opcode “11” precedes all downlink operations for page 1. Performing a direct access command on block 0 always
provides block 0 page 0 independently of the page selector
(see Figure 4-2 on page 6).
●
The RESET opcode “00” initiates an initialization cycle
The fourth opcode “01” precedes all test mode write operations. Any test mode access is ignored after master key (bits 1 to
4) in block 0 has been set to “6”. Any further modifications of the master key are prohibited by setting the lock bit of block 0
or the OTP bit.
Downlink has to follow these rules:
● Standard write needs the opcode, the lock bit, 32 data bits and the 3-bit address (38 bits total)
●
Protected write (PWD bit set) requires a valid 32-bit password between the opcode and the data and address bits
Protected write (PWD bit set) in conjunction with the leading-zero-reference protocol or with the 1-of-4-coding
protocol requires two padding zero bits between the opcode and the password (see also Figure 5-17 on page 24).
This ensures the uniqueness of the direct access with password and the standard write command (see also Table 6-1
on page 26).
●
For the AOR wake-up command an opcode and a valid password are necessary to select and activate a specific tag
Note:
The data bits are read in the same order as written.
If the transmitted command sequence is invalid, the Atmel ATA5577C enters regular-read mode with the previously selected
page (by previous opcode “10” or “11”).
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Figure 5-9. Complete Writing Sequence with Fixed-bit-length Protocol
Read mode
Write mode
Block data
Opcode
Configuration
loading
Start gap
Read mode
Block address
Programming
Lock bit
POR
Figure 5-10. Atmel ATA5577C Command Formats Fixed-bit-length Protocol and Long-leading-reference Protocol
Ref OP
Standard write
R**) 1p*) L
Protected write
R**) 1p*) 1
Password
32
AOR (wake-up command)
R**) 1p*) 1
Password
32
Direct access (PWD = 1)
R**) 1p*) 1
Password
32
Direct access (PWD = 0)
R**) 1p*) 0
Page 0/1 regular read
Reset command
1
Data
2 Addr
32
2 Addr
L
1
0
2 Addr
0
Data
32
2
Addr 0
0
0
R**) 1p*)
R**)
*) p = page selector
00
**) R = Reference pulse if necessary
Figure 5-11. Atmel ATA5577C Command Formats Leading-zero-reference Protocol and 1-of-4-coding Protocol
Ref OP
Standard write
R**) 1p*) L
1
Protected write
R**) 1p*) 00
1
AOR (wake-up command)
R**) 1p*) 00
Direct access (PWD = 1)
R**) 1p*) 00
Direct access (PWD = 0)
R**) 1p*) 0
Page 0/1 regular read
Reset command
32
2 Addr
Password
32
L
1
Data
1
Password
32
1
Password
32
0
2 Addr
0
2 Addr
Data
0
32
2
Addr 0
0
R**) 1p*)
R**)
00
*) p = page selector
**) R = Reference pulse
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19
5.12.3 Fixed-bit-length Protocol
In the fixed-bit-length protocol, the time between two gaps is nominally 24 field clocks for a 0 and 56 field clocks for a 1.
When there is no gap for more than 64 field clocks after a previous gap, the Atmel® ATA5577C exits the downlink mode. This
protocol is compatible with the Atmel T5557/ATA5567 transponder.
Table 5-10. Downlink Data Coding Scheme with Fixed-bit-length Protocol
Normal Downlink
Parameter
Remark
Fast Downlink
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Start gap
Sgap
8
15
50
8
15
50
Tc
Write gap
Wgap
8
10
20
8
10
20
Tc
32
8
12
16
Tc
64
24
28
32
Tc
Write data
0 data
d0
16
24
coding (gap
1 data
d1
48
56
separation)
Note:
All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
Figure 5-12. Fixed-bit-length Protocol
1
0
5.12.4 Long-leading-reference Protocol
To achieve better downlink performance, an enhanced Atmel ATA5577C reader places a reference pulse in front of the
opcode. This reference pulse is used as a timing reference for all following data, thus providing an auto-adjustment for
varying environmental conditions. The long-leading-reference protocol allows full compatibility and coexistence of both
Atmel T5557/ATA5567 and Atmel ATA5577C devices with both Atmel T5557/ATA5567 compatible readers and advanced
Atmel ATA5577C readers. However, only the Atmel ATA5577C devices can profit from the self calibration and the resultant
increase in write distance (see Table 5-1 on page 8 for option register settings).
In this mode, the reference pulse in front of the command is monitored. Depending on the pulse length, the remainder of the
command is either evaluated using the fixed-bit-length protocol, or is used as a measurement reference to evaluate the
following command bits. Otherwise, the following bits are considered as an invalid command.
a) For a reference-based command, the reference pulse (dRef) will have a length of 16 to 32 + 136 = 152 to 168 field clocks
(zero bit + timing bias = reference pulse). Hence, the expected length will lie between 152 and 168 field clocks. The
equivalent expected zero-bit length is then extracted and used as a reference for all following bits. The long-leadingreference pulse in this case is used as a timing reference only, and does not contribute to the command data itself (see
Figure 5-13, part a on 21).
b) Should the first bit lie within the fixed-bit-length frame (for example, in normal mode: 0: 16 to 32 clocks; 1: 48 to 64 clocks),
the device will then automatically switch to the fixed-bit-length protocol (see Section 5.12.3 “Fixed-bit-length Protocol” on
page 20) and this first pulse will be evaluated as the first command bit. This allows compatibility with long-leading-reference
programmed Atmel ATA5577C devices interacting with Atmel T5557/ATA5567 readers, which do not send any reference
pulses (see Figure 5-13, part b on 21).
c) If an Atmel T5557/ATA5567 device interacts with an enhanced Atmel ATA5577C reader, the reference pulse (152 to 168
field clocks) is ignored by the Atmel T5557/ATA5567 and the following data bits will evaluated correctly. Therefore, an Atmel
T5557/ATA5567 device is compatible with an enhanced Atmel ATA5577C reader (see Figure 5-13, part b on 21).
d) Should the first bit correspond to neither (a) nor (b) then it will be rejected as an invalid command.
20
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Table 5-11. Downlink Data Coding Scheme with Long Leading Reference
Normal Downlink
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Start gap
Sgap
8
15
50
8
15
50
Tc
Write gap
Wgap
Write data
coding (gap
separation)
Note:
Remark
Fast Downlink
Reference Pulse
dref
0 data
d0
8
10
20
8
10
20
Tc
152
160
168
140
144
148
Tc
136 clocks + 0 data bit
dref – 143
132 clocks + 0 data bit
Tc
dref – 136
dref – 128
dref – 135
dref – 132
dref – 124
Tc
1 data
d1
dref – 111 dref – 104
All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
dref – 96
dref – 119
dref – 116
dref – 112
Tc
Figure 5-13. Long-leading-reference Protocol
Reference pulse
1
0
a)
1
0
b)
Reference pulse
1
0
c)
5.12.5 Leading-zero-reference Protocol
If the device is programmed in this mode, it will always expect a reference pulse before the command data itself. This pulse
length should correspond exactly to the length of the zero bits in the following command. All further lengths of the zero and
one bits of the command are derived from the reference pulse. Therefore, downlink performance is optimal in different
environmental conditions.
Table 5-12. Downlink Data Coding Scheme with Leading-zero Reference
Normal Downlink
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Start gap
Sgap
8
15
50
8
15
50
Tc
Write gap
Wgap
8
10
20
8
10
20
Tc
Reference Pulse
dref
12
–
72
8
–
68
Tc
0 data
d0
dref – 7
dref
Write data
coding (gap
separation)
Note:
Remark
Fast Downlink
1 data
d1
dref + 9
dref + 16
All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
dref + 8
dref – 3
dref
dref + 4
Tc
dref + 24
dref + 5
dref + 8
dref + 12
Tc
Figure 5-14. Leading-zero-reference Protocol
Reference pulse
(0)
1
0
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21
5.12.6 1-of-4-coding Protocol
This protocol codes the data in bit pairs so that the length of each packet can have one of four discrete lengths. This protocol
is extremely compact and exhibits the least number of field gaps, which in turn improves the device's ability to extract power
from the field. Additionally, a leading reference pulse “00” is placed in front of the downlink command. This serves as a
reference pulse for all following data bits, thus providing an auto-adjustment for varying environmental conditions.
Table 5-13. Downlink Data Coding Scheme with 1-of-4 Coding
Normal Downlink
Parameter
Remark
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Sgap
8
15
50
8
15
50
Tc
Start gap
Write gap
Write data
coding (gap
separation)
Note:
Fast Downlink
Wgap
8
10
20
8
10
20
Tc
Reference pulse “00”
dref
12
–
72
8
–
68
Tc
“00” data
d00
dref – 7
dref
dref + 8
dref – 3
dref
dref + 4
Tc
“01” data
d01
dref + 9
dref + 16
dref + 24
dref + 5
dref + 8
dref + 12
Tc
“10” data
d10
dref + 25
dref + 32
dref + 40
dref + 13
dref + 16
dref + 20
Tc
“11” data
d11
dref + 41
dref + 48
All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
dref + 56
dref + 21
dref + 24
dref + 28
Tc
Figure 5-15. 1-of-4-coding Protocol
Reference pulse
(00)
10
Reference pulse
(00)
22
ATA5577C [DATASHEET]
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00
01
10
11
Figure 5-16. Standard Write Sequence Example
a) Fixed-bit-length Protocol
Read mode
Opcode
1
Blockdata: "100 ... 1"
0
0
1
Start gap
0
0
Blockaddr.: "011"
1
0
1
Programming
Read mode
1
Lock bit
b) Long-leading-reference Protocol
Read mode
Reference Pulse
Opcode
1
Blockdata: "100 ... 1"
0
0
1
Start gap
0
0
1
Blockaddr.: "011"
0
1
Programming
Read mode
1
Lock bit
c) Leading-zero-reference Protocol
Read mode
Opcode
0
1
0
Blockdata: "100 ... 1"
0
Start gap
1
0
0
1
Blockaddr.: "011"
0
1
Programming
Read mode
1
Lock bit
Reference Pulse
d) 1-of-4-coding Protocol
Read mode
00
Start gap
Blockdata:
"100 ... 1"
Opcode
10
01
00
Blockaddr.:
"011"
10
Programming
Read mode
11
Lock bit
Reference Pulse
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Figure 5-17. Protected Write Sequence Example
a) Fixed-bit-length Protocol
Read mode
Opcode
1
PWD: "1101 ... "
0
1
1
0
Blockdata: "100 ... 1"
1
0
Start gap
1
0
0
Blockaddr.: "011"
1
0
1
Programming
Read mode
1
Lock bit
b) Long-leading-reference Protocol
Read mode
Reference Pulse
Opcode
1
0
PWD: "1101 ... "
1
1
0
Blockdata: "100 ... 1"
1
0
1
Start gap
0
0
Blockaddr.: "011"
1
0
1
Programming Read mode
1
Lock bit
c) Leading-zero-reference Protocol
Read mode
Opcode
0
1
0
PWD: "1101 ... "
0
0
Start gap
1
1
0
Blockdata: "100 ... 1"
1
0
Padding zeros
1
0
0
1
Blockaddr.: "011"
0
1
Programming
Read mode
1
Lock bit
Reference Pulse
d) 1-of-4-coding Protocol
Read mode
00
10
Start gap
Blockdata:
"100 ... 1"
PWD: "1101 ... "
Opcode
00
11
01
Padding zeros
01
00
Blockaddr.:
"011"
10
Programming
Read mode
11
Lock bit
Reference Pulse
5.13
Programming
When all necessary information has been received by the Atmel® ATA5577C, programming may proceed. There is a clock
delay between the end of the writing sequence and the start of programming.
Typical programming time is 5.6ms. This cycle includes a data verification read to grant secure and correct programming.
After programming is successfully executed, the Atmel ATA5577C enters block-read mode, transmitting the block just
programmed (see Figure 5-18 on page 25).
Note:
This timing and behavior is different from that of the Atmel e555x-family predecessors. For further details, refer
to relevant Atmel application notes.
If the command sequence is validated and the addressed block is not write protected, the new data will be programmed into
the EEPROM memory. The new state of the block write protection bit (lock bit) will be programmed at the same time
accordingly.
Each programming cycle consists of four consecutive steps: erase block, erase verification (data = 0), programming, and
write verification (corresponding data bits = 1).
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Figure 5-18. Coil Voltage after Programming a Memory Block
VCoil 1 - Coil 2
Write data to tag
5.6 ms
Programming and
data verification
Notes:
1.
Read programmed
memory block
(Block-read mode)
POR/
Reset
or
Single
gap
Read block 1 to MAXBLK
(Regular-read mode)
Programming of page 1 with following single gap will lead to a page 1 read. To enter regular-read mode, a POR
or Reset command has to be performed.
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25
6.
Error Handling
Several error conditions can be detected to ensure that only valid bits are programmed into the EEPROM. There are two
error types, which lead to two different actions.
6.1
Errors During Command Sequence
The following detectable errors could occur while sending a command sequence to the Atmel® ATA5577C:
● Wrong number of field clocks between two gaps (that is, not a valid 1 or 0 pulse stream)
●
●
Password mode is activated and the password does not match the contents of block 7
The number of bits received in the command sequence is incorrect
Valid bit counts accepted by the Atmel ATA5577C are listed in the following table.
Table 6-1.
Bit Counts of Command Sequences
Command
Protect
Fixed-bitlength
Protocol
Long-leadingreference
Protocol
Leading-zeroreference
Protocol
1-of-4coding
Protocol
Standard write
(PWD = 0)
38 bits
38 bits
38 bits
38 bits
Direct access
(PWD = 0)
6 bits
6 bits
6 bits
6 bits
Password write
(PWD = 1)
70 bits
70 bits
72 bits
72 bits
Direct access with PWD
(PWD = 1)
38 bits
38 bits
40 bits
40 bits
AOR wake up
(PWD = 1)
34 bits
34 bits
36 bits
36 bits
Reset command
2 bits
2 bits
2 bits
2 bits
Page 0/1 regular read
2 bits
2 bits
2 bits
2 bits
If any of these erroneous conditions (except AOR mode) are detected, the Atmel ATA5577C enters regular-read mode,
starting with block 1 of the page defined in the command sequence. An erroneous AOR wake-up command will stop
modulation (modulation defeat).
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6.2
Errors Before/During Programming the EEPROM
If the command sequence was received successfully, the following error could still prevent programming:
● The lock bit of the addressed block is already set
●
In case of a locked block, programming mode will not be entered. The Atmel® ATA5577C reverts to block-read mode
continuously transmitting the currently addressed block
●
If a data verification error is detected after an executed data block programming, the tag will stop modulation
(modulation defeat) until a new command is transmitted.
Figure 6-1. Atmel ATA5577C Functional Diagram
Power-on reset
AOR = 1
Set-up modes
AOR mode
AOR = 0
Regular-read mode
Page 0
Page 0 or 1
addr = 1 to MAXBLK
Block-read mode
Gap
Start
gap
addr = current
Command mode
Gap
Modulation
defeat
Single gap
Page 1
OP(00)
Reset
to page 0
Direct access
OP(1p) 1)
Command decode
OP(11..)
OP(1p) 1)
Page 0
OP(10..)
OP(01)
Write
OP(1p) 1)
Test mode
if master key < > 6
Write
Number of bits
Password check
Lock bit check
Data verification failed
1)
Program and verify
fail
data = old
fail
data = old
fail
data = old
ok
data = new
p = page selector
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RF field
Inverted modulator
signal
Manchester coded
Data stream
1
12
8 FC
8
9
8 FC
16 1
Data rate =
16 field clocks (FC)
8
9
0
16
1
8
0
16 1
8
9
1
16
12
8
9
1
16 1
8
9
0
16
Figure 6-2. Example with Manchester Coding with Data Rate RF/16
RF field
Inverted modulator
signal
Bi-phase coded
Data stream
1
12
8 FC
8
9
8 FC
16
Data rate =
16 field clocks (FC)
1
8 9
0
16
1
8
0
16
1
8
9
1
16
12
8
9
1
16
1
8 9
0
16
Figure 6-3. Example of Bi-phase Coding with Data Rate RF/16
ATA5577C [DATASHEET]
9187H–RFID–07/14
29
30
ATA5577C [DATASHEET]
9187H–RFID–07/14
RF field
1 5
f1 = RF/5
f0 = RF/8
Inverted modulator
signal
Data stream
1
Data rate =
40 field clocks (FC)
1
8
0
1
8
0
1 5
1
1 5
1
1
8
0
Figure 6-4. Example: FSK1a Coding with Data Rate RF/40, Sub-carrier f0 = RF/8, f1 = RF/5
RF field
Subcarrier RF/2
Inverted modulator
signal
Data stream
1
12
8 FC
8 9
8 FC
16 1
Data rate =
16 field clocks (FC)
8
0
16 1
8
0
16 1
8
1
16 1
8
1
16 1
8
0
Figure 6-5. Example of PSK1 Coding with Data Rate RF/16
ATA5577C [DATASHEET]
9187H–RFID–07/14
31
32
ATA5577C [DATASHEET]
9187H–RFID–07/14
RF field
Subcarrier RF/2
Inverted
modulator signal
Data stream
1
12
8 FC
8 9
8 FC
16 1
Data rate =
16 field clocks (FC)
8
0
16 1
8
0
16 1
8
1
16 1
8
1
16 1
8
0
Figure 6-6. Example of PSK2 Coding with Data Rate RF/16
RF field
Inverted
modulator signal
Subcarrier RF/2
Data stream
1
12
8 FC
8 9
8 FC
16 1
Data rate =
16 field clocks (FC)
8
0
16 1
8
0
16 1
8
1
16 1
8
1
16 1
8
0
Figure 6-7. Example of PSK3 Coding with Data Rate RF/16
ATA5577C [DATASHEET]
9187H–RFID–07/14
33
7.
Animal ID
In ISO11784/11785, the code structure of a 128-bit FDX-B telegram is defined. Following is an example of how to program
the Atmel ATA5577C for ISO 11785 FDX-B.
Figure 7-1. Structure of the ISO 11785 FDX-B Telegram
Bits
11
8 x (8+1)
2 x (8+1)
LSB
Bit No.
1
...
11 12
MSB
Control bit '1'
...
...
20
Header
83
LSB
Identification Code
11-bit fixed
00000000001
CRC
Trailer
16-bit CRC
+ 2 bits
24-bit trailer all zeros
+ 3 bits
LSB
Country Code 10 bits
Unique
Number 8 bits
Control bit '1'
Unique
Number 8 bits
Control bit '1'
Unique
Number 8 bits
Control bit '1'
Unique
Number
6 bits
20
Control bit '1'
Country Code
8 bits
Control bit '1'
Country Code
2 bits
Control bit '1'
RFU 7 bits
Data Block Flag
Control bit '1'
Control bit '1'
Animal Flag
RFU 7 bits
...
12
Unique
Number 8 bits
Unique Number 38 bits
Except for the header, every eight bits are followed by one control bit (1), to prevent the header from recurring.
2.
All data is transmitted LSB first.
3.
Country codes are defined in ISO 3166
4.
The bits reserved for future use (RFU) are all set to 0.
5.
If the data block flag is not set, the trailer bits are all set to 0.
6.
CRC is performed on the 64-bit identification code without the control bits. The generator polynomial is
P(x) = x16 + x12 + x5 + 1. Reverse CRC-CCITT (0x 8 408) is used. Data stream is LSB first.
Example Data for Animal ID
Code
Dec. Value
Hex. Value
Animal flag
1
1
Use for animal ID
RFU
0
0
Reserved for future use
Data block flag
0
0
No data in trailer
Country code
Unique number
CRC
999
3E7
78187493530
123456789A
36255
8D9F
Comment
Country code for demo tags
Any demo number
CRC for the identification code
Programming of the Atmel® ATA5577C for animal ID:
● Encoding of the data is differential bi-phase RF/32
●
128
1.
Table 7-1.
34
...
102
...
83
RFU 14 bits
Notes:
101
64-bit Identification Code
+ 8 bits
MSB
Bit No.
MSB
...
84
3 x (8+1)
128 bits have to be transmitted in regular-read mode (Maxblock = 4)
ATA5577C [DATASHEET]
9187H–RFID–07/14
Table 7-2.
Programming the Atmel ATA5577C with Example Data
Block
Address
Value
Comment
(1)
Option register
Block 3, page 1
0x 6DD0 0000
Soft modulation, two pulses recommended
Configuration register
Block 0, page 0
0x 603F 8080
RF/32, differential bi-phase, Maxblock = 4
User data block 1
Block 1, page 0
0x 002B 31EB
Header, unique number
User data block 2
Block 2, page 0
0x 54B2 979F
Unique number (cont.), country code
User data block 3
Block 3, page 0
0x 8040 7F3B
Data block flag, RFU, animal flag, CRC
User data block 4
Block 4, page 0
0x 1804 0201
Note:
1. Depending on application, settings may vary
CRC (cont.), trailer bits
ATA5577C [DATASHEET]
9187H–RFID–07/14
35
8.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
Maximum DC current into Coil1/Coil2
Icoil
20
mA
Maximum AC current into Coil1/Coil2, f = 125kHz
Icoil p
20
mA
Power dissipation (die) (free-air condition, time of
application: 1s)
Ptot
100
mW
Electrostatic discharge maximum to ANSI/ESDSTM5.1-2001 standard (HBM)
Vmax
3000
V
Operating ambient temperature range
Tamb
–40 to +85
°C
Storage temperature range (data retention
reduced)
Tstg
–40 to +150
°C
9.
Electrical Characteristics
Tamb = +25°C; fcoil = 125kHz; unless otherwise specified
No.
1
2.1
2.2
2.3
Parameters
Supply current (without
current consumed by
the external LC tank
circuit)
3.1
3.2
Coil voltage (AC
supply)
5.3
Min.
Typ.
Max.
Unit
fRF
100
125
150
kHz
1.5
3
µA
T
2
5
µA
Q
Tamb = 25°C(1)
Read - full temperature
range
IDD
Start-up time
Clamp voltage
(depends on settings in
option register)
25
µA
Q
POR threshold
(50-mV hysteresis)
3.6
V
Q
Read mode and write
command(2)
Vcoil pp = 6V
3-mA current into
Coil1/Coil2
20-mA current into
Coil1/Coil2
5.4
Type*
Programming - full
temperature range
5.1
5.2
Symbol
Vcoil pp
Program EEPROM(2)
3.3
4
Test Conditions
RF frequency range
6
Vclamp
V
Q
8
Vclamp
V
Q
tstartup
2.5
ms
Q
Vpp clamp lo
11
V
Q
Vpp clamp
13
V
Q
med
Vpp clamp hi
14
17
21
V
T
Vpp clamp
13
15
18
V
T
med
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes:
1.
IDD measurement set-up: EEPROM programmed to 00 ... 000 (erase all); chip in modulation defeat.
2. Current into Coil1/Coil2 is limited to 10mA.
3. Since EEPROM performance is influenced by assembly processes, Atmel cannot confirm the parameters for -DDW
(tested die on unsawn wafer) delivery.
4. See Section 10. “Ordering Information” on page 38.
36
ATA5577C [DATASHEET]
9187H–RFID–07/14
9.
Electrical Characteristics (Continued)
Tamb = +25°C; fcoil = 125kHz; unless otherwise specified
No.
Parameters
6.1
6.2
6.3
Modulation parameters
(depends on settings in
option register)
6.4
6.5
Thermal stability
7.1
Clock detection level
(depends on settings in
option register)
7.2
7.3
7.4
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
3-mA current into
Coil1/Coil2 and
modulation ON
Vpp mod lo
2
3
4
V
T
Vpp mod med
5
V
Q
Vpp mod hi
7
V
Q
20-mA current into
Coil1/Coil2 and
modulation ON
Vpp mod med
V
T
Vcoil pp = 8V
6
–1
mV/°C
Q
Vclkdet lo
250
mV
Q
Vclkdet med
mV
T
Vclkdet hi
400
800
mV
Q
Vgapdet lo
250
mV
Q
mV
T
mV
Q
ms
T
Cycles
Q
Years
Q
hrs
T
hrs
Q
Vcoil pp = 8 V
8
Programming time
From last command
gap to re-enter read
mode (64 + 648
internal clocks)
Tprog
5
9
Endurance
Erase all/Write all(3)
ncycle
100000
7.6
10.1
10.2
Vgapdet med
Top = 55°C
Data retention
10.3
tretention
10
tretention
96
(3)
tretention
Top = 150°C
Top = 250°C
11.2
Resonance capacitor
Mask option
(4)
550
550
5.7
20
340
242
250
258
Cr
130
10
Cr
50
330
75
Capacitance tolerance
Tamb
6
24
11.5
Micromodule capacitor
parameters(4)
730
320
11.4
12.1
730
850
(3)
11.1
11.3
400
Vgapdet hi
(3)
9
Vmod lo /
Tamb
Gap detection level
(depends on settings in
option register)
7.5
7.5
320
330
T
pF
Q
340
pF
T
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes:
1.
IDD measurement set-up: EEPROM programmed to 00 ... 000 (erase all); chip in modulation defeat.
2. Current into Coil1/Coil2 is limited to 10mA.
3. Since EEPROM performance is influenced by assembly processes, Atmel cannot confirm the parameters for -DDW
(tested die on unsawn wafer) delivery.
4. See Section 10. “Ordering Information” on page 38.
ATA5577C [DATASHEET]
9187H–RFID–07/14
37
10.
Ordering Information
ATA5577M
1
ccc
C -xxx
Package
Drawing
DDB
6” sawn wafer on foil with ring, thickness 150µm
(approx. 6mil)
DDW
6” wafer, thickness 680µm (approx. 27mil)
Figure 11-1 on page 40
On-chip Capacity Value in pF
000
pF
On request
075
pF
On request
250
pF
On request
330
pF
Standard pads
ATA5577M
-PAE
330
C
1
330
C -UFQW XDFN package 1.5mm by 2mm, thickness 0.37mm
Figure 11-6 on page 45
1
330
C -PPMY Transponder Brick package
See datasheet
ATA5577M1330C-PPMY
1
33S
C
As ATA5577M1330C-DDB, pre-programmed in unique format
Figure 11-1 on page 40
2
ccc
C -xxx
Package
Drawing
-DDB
NOA3 micromodule (lead-free)
Figure 11-4 on page 43/
Figure 11-5 on page 44
1
DBB
6” sawn wafer on foil with ring, thickness 150µm
(approx. 6mil) with gold bumps 25µm
DBQ
Die in blister tape, thickness 280µm (approx. 11mil),
Figure 11-3 on page 42
plus gold bumps 25µm
Figure 11-2 on page 41
On-chip Capacity Value in pF
250
pF
330
pF
On request
Mega pads 200µm by 400µm
38
2
2
33S
33S
C
C
-DBB As ATA5577M2330C-DBB, pre-programmed in unique format
-DBQ As ATA5577M2330C-DBQ, pre-programmed in unique format
2
33A
C
-DBB
ATA5577C [DATASHEET]
9187H–RFID–07/14
6” sawn wafer on foil with ring, thickness 280µm (approx. 11mil)
with gold bumps 25µm
Figure 11-2 on page 41
Figure 11-3 on page 42
10.1
Available Order Codes
ATA5577M1330C-DDB
ATA5577M1330C-DDW
ATA5577M1330C-PAE
ATA5577M1330C-UFQW
ATA5577M1330C-PPMY
ATA5577M133SC-DDB
ATA5577M2330C-DBB
ATA5577M2330C-DBQ
ATA5577M233AC-DBB
ATA5577M233SC-DBB
New order codes will be created by customer request if order quantities are over 250k pieces.
10.2
Configuration on Delivery
Table 10-1. Configuration on Delivery
Block
Address
Value
Comment
AFE option set up
Block 3, page 1
0x 0000 0000
All option take on the default state
Configregister
Block 0, page 0
0x 0008 8040
RF/32, Manchester, Maxblock = 2
User data block 1
Block 1, page 0
0x 0000 0000
All “0”
User data block 2
Block 2, page 0
0x 0000 0000
All “0”
ATA5577C [DATASHEET]
9187H–RFID–07/14
39
11.
Package Information
Figure 11-1. Sawn Wafer on Foil with Ring (Type 1, Standard Pads)
1
Die Dimensions
0.181
20:1
0.15±0.012
(0.08)
1.15
C1
C2
(0.08)
Dimensions in mm
0.095
0.07
59.5
Orientation on frame
0.125
technical drawings
according to DIN
specifications
0.117
0.1
0.347
0.1
63.6
B
212
87.5
86.5
4B
Label:
Prod: ATA5577M1xxxC-DDB
Lot no:
Wafer no:
Qty:
Option
xxx
330
Wafer ATA5577M1xxxC-DDB
33D
UV Tape Adwill D176
6" Wafer frame, plastic
thickness 2.5mm
Ø227.7
Ø150
Ø3 A
A
Ø194.5
212
07/19/10
TITLE
Package Drawing Contact:
[email protected]
40
ATA5577C [DATASHEET]
9187H–RFID–07/14
Dimensions
ATA5577M1xxxC-DDB
GPC
DRAWING NO.
REV.
9.920-6676.03-4
1
Figure 11-2. Sawn Wafer on Foil with Ring (Type 2, Mega Pads and Au Bumps)
Die Dimensions
1±0.015
0.155±0.014
(0.08)
0.005±0.002
(BCB coating)
technical drawings
according to DIN
specifications
(0.08)
1.355±0.015
0.177±0.015
0.4±0.015
20:1
(Au bump)
0.025±0.005
0.04×45°
0.2
0.15±0.012
0.324
Dimensions in mm
0.175±0.017
59.5
63.6
B
Orientation on frame
Option
xxx
330
212
87.5
86.5
4B
Label:
Prod: ATA5577M2xxxC-DBB
Lot no:
Wafer no:
Qty:
Wafer ATA5577M2xxxC-DBB
UV Tape Adwill D176
6" Wafer frame, plastic
thickness 2.5mm
Ø227.7
Ø150
Ø3 A
A
Ø194.5
212
07/19/10
TITLE
Package Drawing Contact:
[email protected]
Dimensions
ATA5577M2xxxC-DBB
GPC
DRAWING NO.
REV.
9.920-6679.02-4
1
ATA5577C [DATASHEET]
9187H–RFID–07/14
41
Figure 11-3. Die in Blister Tape
1
0.285±0.0135
(0.08)
0.005±0.0015
(BCB coating)
technical drawings
according to DIN
specifications
0.4±0.015
0.177±0.015
20:1
C2
C1
1.355±0.015
Die Dimensions
(Au bump)
0.025±0.005
0.28±0.012
0.04 x 45°
0.2
0.324
0.305±0.0017
Label acc. ’’Packaging and Packing Spec.’’
’’X’’
cover tape
carrier tape
8.4
4
’’X’’
8
reel Ø330
1.3
Specification Tape and reel
Dimensions in mm
Option
xxx
330
1.52
Packing acc. IEC 60286-3
0.5
0.254
02/28/12
TITLE
Package Drawing Contact:
[email protected]
42
ATA5577C [DATASHEET]
9187H–RFID–07/14
Dimensions
ATA5577M2xxxC-DBQ
GPC
DRAWING NO.
REV.
9.800-5110.01-4
2
Figure 11-4. NOA3 Micromodule
9.5±0.03
4.75+0.02
4.625
1.42±0.05
0.03 A B
1.42±0.05
31.83
25.565
21.815
Ф2±0.05
Note 1
15.915
12.165
6.265
B
technical drawings
according to DIN
specifications
2.515
0
1.585
A
Dimensions in mm
X
2.375
2.375
0.05 A
Note 3
5.15±0.03
Note 2
8-0.02
Note 4
8.1±0.03
Note 2
0.03 B
R1.5±0.03
0.09-0.01
R0.2 max.
5.1±0.05
0.38-0.035
Note:
1. Reject hole by testing device
2. Punching cutline
recommendation for singulation
3. Total package thickness
exclusive punching burr
4. Module dimension
after electrical disconnection
0.05 B
X5:1
4.8±0.05
R1.1±0.03 (4x)
Drawing-No.: 6.549-5035.01-4
Issue: 1; 28.04.06
Subcontractor: NedCard
5.06±0.03
Drawing refers to following types: Micromodule NOA-3
Note 4
04/28/06
TITLE
Package Drawing Contact:
[email protected]
Package: Micro Module
Subcontractor: Ned Card
GPC
DRAWING NO.
REV.
6.549-5035.01-4
1
ATA5577C [DATASHEET]
9187H–RFID–07/14
43
Figure 11-5. Shipping Reel for NOA3 Micromodule
41.4 to
max 43.0
0
° (3
x)
Ø 329.6
Ø 298.5
12
R1.14
Ø13
2.3
Ø171
Ø175
16.7
2
2.2
44
ATA5577C [DATASHEET]
9187H–RFID–07/14
Figure 11-6. XDFN Package
E
E1
D
D1
D2
technical drawings
according to DIN
specifications
e
A
A1
Dimensions in mm
PIN 1 ID
COMMON DIMENSIONS
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
0.32
0.37
0.4
A1
0.1 nom.
D
1.95
2
2.05
D1
0.6
0.7
0.8
D2
0.6
0.7
0.8
E
1.45
1.5
1.55
E1
1
1.1
1.2
e
1 BSC
04/06/11
TITLE
Package Drawing Contact:
[email protected]
Package: XDFN_1.5x2_2L
GPC
DRAWING NO.
REV.
6.543-5159.01-4
1
ATA5577C [DATASHEET]
9187H–RFID–07/14
45
12.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
9187H-RFID-07/14
9187G-RFID-04/13
History
Section 10 “Ordering Information” on pages 38 to 39 updated
Section 11 “Package Information” on pages 40 to 45 updated
Section 10 “Ordering Information” on pages 37 to 38 updated
Section 5.5 “Initialization and Init-Delay” on page 11 updated
9187F-RFID-01/13
Figure 5-1 “Answer-on-request (AOR) Mode ...” on page 12 updated
Figure 5-9 “Complete Writing Sequence ...” on page 19 updated
Ordering Information for ATA5577M1cccC-DDW on pages 37 and 38 added
9187E-RFID-07/12
9187D-RFID-04/12
9187C-RFID-04/11
Section 10 “Ordering Information” on pages 37 to 38: Ordering codes added
Figure 11-4 “Die in Blister Tape” on page 42 added
Figure 11-5 “Die on Sticky Tape” on page 43 updated
Figure 11-1 “Pad Layout (Type 1, Standard Pads)” on page 41 removed
Figure 11-2 “Pad Layout (Type 2, Mega Pads)” on page 42 removed
Section 10 “Ordering Information” on page 39 changed
9187BX-RFID-03/11
Section 10.1 “Available Order Codes” on page 40 changed
Figure 11-4 “Die in Waffle Pack” on page 44 added
46
ATA5577C [DATASHEET]
9187H–RFID–07/14
XXXXXX
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
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© 2014 Atmel Corporation. / Rev.: 9187H–RFID–07/14
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