ATV2500B(BQ)(BQL) - Mature

Features
• High-performance, High-density Programmable Logic Device
– Typical 7 ns Pin-to-pin Delay
– Fully Connected Logic Array with 416 Product Terms
• Flexible Output Macrocell
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
– Achieves Over 80% Gate Utilization
• Enhanced Macrocell Configuration Selections
– D- or T-type Flip-flops
– Product Term or Direct Input Pin Clocking
– Registered or Combinatorial Internal Feedback
• Several Power Saving Options
•
•
•
•
Device
ICC, Standby
ATV2500B
110 mA
ATV2500BQ
30 mA
ATV2500BL
2 mA
ATV2500BQL
2 mA
High-speed
High-density
UV-erasable
Programmable
Logic Device
Backward Compatible with ATV2500H/L Software
Proven and Reliable High-speed UV EPROM Process
Reprogrammable – Tested 100% for Programmability
40-lead Dual-in-line and 44-lead Surface Mount Packages
ATV2500B
ATV2500BQ
ATV2500BQL
Block Diagram
Pin Configurations
CLK/IN
Pin Clock and
Input
I/O
Bi-directional
Buffers
I/O 0,2,4..
“Even” I/O Buffers
I/O 1,3,5..
“Odd” I/O Buffers
GND
Ground
VCC
+5V Supply
Note:
For ATV2500BQ and
ATV2500BQL (PLCC/LCC
package only) pin 4 and
pin 26 connections are not
required.
I/O1
I/O0
GND
IN
IN
CLK/IN
IN
IN
IN
IN
I/O06
Logic Inputs
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
6
5
4
3
2
1
44
43
42
41
40
IN
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
Function
DIP
I/O12
IN
IN
IN
IN
IN
IN
IN
GND
I/O18
I/O19
Pin Name
LCC/PLCC
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
CLK/IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
Rev. 0249J–05/00
1
Functional Logic Diagram ATV2500B
Note:
2
1. Not required for PLCC versions of ATV2500BQ or ATV2500BQL, making them compatible with ATV2500H and ATV2500L
pinout.
ATV2500B(Q)(L)
ATV2500B(Q)(L)
Description
The ATV2500Bs are the highest density PLDs available in
a 40- or 44-lead package. With their fully connected logic
array and flexible macrocell structure, high-gate utilization
is easily obtainable.
The ATV2500Bs are organized around a single universal
and-or array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array
inputs, as are the outputs of each flip-flop.
In the ATV2500Bs, four product terms are input to each
sum term. Furthermore, each macrocell’s three sum terms
can be combined to provide up to 12 product terms per
sum term with no performance penalty. Each flip-flop is
individually selectable to be either D- or T-type, providing
further logic compaction. Also, 24 of the flip-flops may be
bypassed to provide internal combinatorial feedback to the
logic array.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each
output has its own enable product term. Eight synchronous
preset product terms serve local groups of either four or
eight flip-flops. Register preload functions are provided to
simplify testing. All registers automatically reset upon
power-up.
Several low-power device options allow selection of the
optimum solution for many power-sensitive applications.
Each of the options significantly reduces total system
power and enhances system reliability.
Functional Logic Diagram Description
The ATV2500B functional logic diagram describes the
interconnections between the input, feedback pins and
logic cells. All interconnections are routed through the
single global bus.
The ATV2500Bs are straightforward and uniform PLDs.
The 24 macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172
inputs. The five lower product terms provide AR1, CK1,
CK2, AR2, and OE. These are: one asynchronous reset
and clock per flip-flop, and an output enable. The top 12
product terms are grouped into three sum terms, which are
used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset 0, the next two
share Preset 1, and so on, ending with the last two macrocells sharing Preset 7.
The 14 dedicated inputs and their complements use the
numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right)
feedback F2(1) true and false, flip-flop Q1 true and false,
and the pin true and false. The positions occupied by these
signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Note:
1. Either the flip-flop input (D/T2) or output (Q2) may be
3
Absolute Maximum Ratings*
*NOTICE:
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Integrated UV Erase Dose..............................7258 W•sec/cm2
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC
which may overshoot to +7.0V for pulses of less
than 20 ns.
DC and AC Operating Conditions
Operating Temperature
VCC Power Supply
Commercial
Industrial
Military
0°C - 70°C
(Ambient)
-40°C - 85°C
(Ambient)
-55°C - 125°C
(Case)
5V ± 5%
5V ± 10%
5V ± 10%
Pin Capacitance
f = 1 MHz, T = 25°C (1)
Typ
Max
Units
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
4
Conditions
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
ATV2500B(Q)(L)
ATV2500B(Q)(L)
Output Logic, Registered(1)
S2 = 0
Terms in
S1
S0
D/T1
D/T2
Output Configuration
0
0
8
4
Registered (Q1); Q2 FB
(1)
Registered (Q1); Q2 FB
4
Registered (Q1); D/T2 FB
1
0
12
1
1
8
S3
4
Output
Configuration
S6
Q1 CLOCK
0
Active Low
0
CK1
1
Active High
1
CK1 • PIN1
S7
Q2 CLOCK
S4
Register 1 Type
0
D
0
CK2
1
T
1
CK2 • PIN1
S5
Register 2 Type
0
D
1
T
Output Logic, Combinatiorial(1)
S2 = 1
Terms in
S5
S1
S0
D/T1
D/T2
X
0
0
4(1)
4
Combinatorial (8 Terms);
Q2 FB
X
0
1
4
4
Combinatorial (4 Terms);
Q2 FB
X
1
0
4(1)
4(1)
Combinatorial (12 Terms);
Q2 FB
1
1
1
4(1)
4
Combinatorial (8 Terms);
D/T2 FB
0
1
1
4
4
Combinatorial (4 Terms);
D/T2 FB
Note:
Output Configuration
1. These four terms are shared with D/T1.
Clock Option
Note:
1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
5
DC Characteristics
Symbol
Parameter
Condition
IIL
Input Load Current
ILO
Output Leakage
Current
Min
Typ
Max
Units
VIN = -0.1V to VCC + 1V
10
µA
VOUT = -0.1V to VCC + 0.1V
10
µA
Com.
110
190
mA
Ind., Mil.
110
210
mA
Com.
30
70
mA
Ind., Mil.
30
85
mA
Com.
2
5
mA
Ind., Mil.
2
10
mA
Com.
2
4
mA
Ind., Mil.
2
5
mA
-120
mA
-0.6
0.8
V
2.0
VCC +
0.75
V
ATV2500B
ICC
Power Supply
Current,
Standby
VCC = MAX,
VIN = GND or
VCC f = 0 MHz,
Outputs Open
ATV2500BQ
ATV2500BL
ATV2500BQL
IOS
Output Short
Circuit Current
VOUT = 0.5V
VIL
Input Low Voltage
MIN ≤ VCC ≤ MAX
VIH
Input High Voltage
VOL
Output Low
Voltage
VIN = VIH or VIL,
VCC = 4.5V
VOH
Output High
Voltage
VCC = MIN
Note:
6
IOL = 8 mA
Com., Ind.
0.5
V
IOL = 6 mA
Mil.
0.5
V
IOH = -100 µA
IOH = -4.0 mA
1. See ICC versus frequency characterization curves.
ATV2500B(Q)(L)
VCC - 0.3
2.4
V
ATV2500B(Q)(L)
AC Waveforms(1) Input Pin Clock
AC Waveforms(1) Product Term Clock
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
7
Register AC Characteristics, Input Pin Clock
-12
-15
-20
-25
-30
Symbol
Parameter
tCOS
Clock to Output
tCFS
Clock to Feedback
0
tSIS
Input Setup Time
7
9
14
20
23
ns
tSFS
Feedback Setup Time
7
9
14
20
23
ns
tHS
Hold Time
0
0
0
0
0
ns
tWS
Clock Width
5
6
7
8
9
ns
tPS
Clock Period
10
12
14
16
18
ns
FMAXS
tARS
8
Min
Max
Min
7.5
4
Max
Min
10
0
5
Max
Min
11
0
6
Max
Min
12
0
7
0
Max
Units
15
ns
8
ns
External Feedback 1/(tSIS + tCOS)
69
52
40
31
26
MHz
Internal Feedback 1/(tSFS + tCFS)
90
71
50
37
32
MHz
No Feedback 1/(tPS)
100
83
71
62
55
MHz
Asynchronous Reset/Preset
Recovery Time
ATV2500B(Q)(L)
7
12
15
20
25
ns
ATV2500B(Q)(L)
Register AC Characteristics, Product Term Clock
-12
-15
-20
-25
-30
Symbol
Parameter
tCOA
Clock to Output
tCFA
Clock to Feedback
3
tSIA
Input Setup Time
4
5
10
15
19
ns
tSFA
Feedback Setup Time
4
5
8
10
10
ns
tHA
Hold Time
3
5
10
12
13
ns
tWA
Clock Width
5.5
7.5
11
14
15
ns
tPA
Clock Period
11
15
22
28
30
ns
FMAXA
tARA
Min
Max
Min
12
7
Max
Min
15
5
12
Max
Min
20
10
16
Max
Min
22
12
18
13
Max
Units
25
ns
20
ns
External Feedback 1/(tSIA + tCOA)
62.5
50
33
27
23
MHz
Internal Feedback 1/(tSFA + tCFA)
90
58
38
36
24
MHz
No Feedback 1/(tPS)
90
66
45
36
33
MHz
Asynchronous Reset/Preset
Recovery Time
3
8
12
15
18
ns
AC Waveforms(1) Combinatorial Outputs and Feedback
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
9
AC Characteristics
-12
-15
-20
-25
Symbol
Parameter
tPD1
Input to Non-registered Output
12
15
20
tPD2
Feedback to Non-registered
Output
12
15
tPD3
Input to Non-registered Feedback
8
tPD4
Feedback to Non-registered
Feedback
tEA1
-30
Max
Units
25
30
ns
20
25
30
ns
11
15
18
20
ns
8
11
15
18
20
ns
Input to Output Enable
12
15
20
25
30
ns
tER1
Input to Output Disable
12
15
20
25
30
ns
tEA2
Feedback to Output Enable
12
15
20
25
30
ns
tER2
Feedback to Output Disable
12
15
20
25
30
ns
tAW
Asynchronous Reset Width
tAP
Asynchronous Reset to
Registered Output
15
18
22
28
30
ns
tAPF
Asynchronous Reset to
Registered Feedback
12
15
19
25
30
ns
Min
Max
6
Min
Max
8
Input Test Waveforms and
Measurement Levels
Min
Max
12
Min
Max
15
Min
18
ns
Output Test Load
Preload and Observability of Registered Outputs
The ATV2500Bs registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the odd I/O pins will force the
appropriate register high; a VIL will force it low, independent
of the polarity or other configuration bit settings.
The PRELOAD state is entered by placing an 10.25V to
10.75V signal on SMP lead 42. When the preload clock
10
ATV2500B(Q)(L)
SMP lead 23 is pulsed high, the data on the I/O pins is
placed into the 12 registers chosen by the Q select and
even/odd select pins.
Register 2 observability mode is entered by placing an
10.25V to 10.75V signal on pin/lead 2. In this mode, the
contents of the buried register bank will appear on the
associated outputs when the OE control signals are active.
ATV2500B(Q)(L)
Level Forced on
Odd I/O Pin
during
PRELOAD Cycle
Q Select Pin
State
Even/Odd Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
VIH/VIL
Low
Low
High/Low
X
X
X
VIH/VIL
High
Low
X
High/Low
X
X
VIH/VIL
Low
High
X
X
High/Low
X
VIH/VIL
High
High
X
X
X
High/Low
Power-up Reset
The registers in the ATV2500Bs are designed to reset during power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
.
This feature is critical for state as nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin or
terms high, and
3. The clock pin, and any signals from which clock
terms are derived, must remain stable during tPR.
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
11
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of ATV2500B fuse patterns. Once programmed, the outputs will read programmed during verify. The security fuse
should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2
observability.
Atmel CMOS PLDs
The ATV2500Bs utilize an advanced 0.65-micron CMOS
EPROM technology. This technology’s state of the art features are the optimum combination for PLDs:
• CMOS technology provides high speed, low power, and
high noise immunity.
• EPROM technology is the most cost effective method for
producing PLDs – surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
running on separate clocks. Individual flip-flop clock
source selection further allows mixing higher
performance pin clocking and flexible product term
clocking within one design.
• A Total of 48 Registers – The ATV2500B provides two
flip-flops per macrocell – a total of 48. Each register has
its own clock and reset terms, as well as its own sum
term.
• Independent I/O Pin and Feedback Paths – Each I/O
pin on the ATV2500B has a dedicated input path. Each
of the 48 registers has its own feedback term into the
array as well. These features, combined with individual
product terms for each I/O’s output enable, facilitate true
bi-directional I/O design.
• Combinable Sum Terms – Each output macrocell’s
three sum terms may be combined into a single term.
This provides a fan in of up to 12 product terms per sum
term with no speed penalty.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
Programming Software Support
Using the ATV2500Bs Many Advanced
Features
S ev e r al th i r d pa r ty p r og r am m er s wi l l s u pp o r t th e
ATV2500B as well. Additionally, the ATV2500B may be
programmed to perform the ATV2500H/Ls functional subset (no T-type flip-flops, pin clocking or D/T2 feedback)
using the ATV2500H/L JEDEC file. In this case, the
ATV2500B becomes a direct replacement or speed
upgrade for the ATV2500H/L (additional GND connections
are required). Please refer to the Programmable Logic
Development Tools section for a complete PLD software
and programmer listing.
The ATV2500Bs advanced flexibility packs more usable
gates into 44 leads than other PLDs. Some of the
ATV2500Bs key features are:
• Fully Connected Logic Array – Each array input is
always available to every product term. This makes logic
placement a breeze.
• Selectable D- and T-Type Registers – Each ATV2500B
flip-flop can be individually configured as either D- or Ttype. Using the T-type configuration, JK and SR flip-flops
are also easily created. These options allow more
efficient product term usage.
• Buried Combinatorial Feedback – Each macrocell’s
Q2 register may be bypassed to feed its input (D/T2)
directly back to the logic array. This provides further logic
expansion capability without using precious pin
resources.
• Selectable Synchronous/Asynchronous Clocking –
Each of the ATV2500Bs flip-flops has a dedicated clock
product term. This removes the constraint that all
registers use the same clock. Buried state machines,
counters and registers can all coexist in one device while
12
ATV2500B(Q)(L)
As with all other Atmel PLDs, several third party PLD development software products and programmers will support
the ATV2500Bs.
Erasure Characteristics
The entire memory array of an ATV2500B is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µW/cm 2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of 15 W•sec/cm2. To
prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
ATV2500B(Q)(L)
Note:
1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.
13
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (VCC=5V, TA=25°C)
0
-1
I
O
H
-2
-3
m
A
-4
-5
3.5
3.8
4.1
4.4
4.7
5.0
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
0
I
O
H
m
A
vs. OUTPUT VOLTAGE (VCC=5V,TA=25°C)
-20
-40
-60
-80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
NORMALIZED TPD
vs. AMBIENT TEMPERATURE (VCC = 5V)
1.3
N
O
R
M
ATV2500B(L)
1.2
1.1
1.0
T
P
D
ATV2500BQ(L)
0.9
0.8
-55
-25
5
35
65
95
125
AMBIENT TEMPERATURE (C)
NORMALIZED TCO
NORMALIZED TCO
vs. SUPPLY VOLTAGE (TA=25°C)
vs. AMBIENT TEMPERATURE (VCC = 5V)
1.3
N
O
R
M
1.3
1.2
1.1
ATV2500BQ(L)
N
O
R
M
1.0
T
C
O
0.9
0.8
4.75
5.00
5.25
SUPPLY VOLTAGE (V)
Note:
14
1.1
1.0
ATV2500B(L)
4.50
ATV2500B(L)
1.2
5.50
T
C
O
ATV2500BQ(L)
0.9
0.8
-55
-25
5
35
1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.
ATV2500B(Q)(L)
65
AMBIENT TEMPERATURE (C)
95
125
ATV2500B(Q)(L)
Note:
1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.
15
Ordering Information
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz)
12
7.5
15
10
20
20
11
11
Ordering Code
Package
69
ATV2500B-12JC
ATV2500B-12KC
44J
44KW
Commercial
(0°C to 70°C)
52
ATV2500B-15JC
ATV2500B-15KC
44J
44KW
Commercial
(0°C to 70°C)
ATV2500B-15JI
ATV2500B-15KI
44J
44KW
Industrial
(-40°C to 85°C)
ATV2500B-15KM
ATV2500B-15LM
44KW
44LW
Military
(-55°C to 125°C)
ATV2500B-15KM/883
ATV2500B-15LM/883
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
ATV2500BL-20JC
ATV2500BL-20KC
44J
44KW
Commercial
(0°C to 70°C)
ATV2500BL-20JI
ATV2500BL-20KI
44J
44KW
Industrial
(-40°C to 85°C)
ATV2500BL-20KM
ATV2500BL-20LM
44KW
44LW
Military
(-55°C to 125°C)
ATV2500BL-20KM/883
ATV2500BL-20LM/883
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
ATV2500BQ-20DC
ATV2500BQ-20JC
ATV2500BQ-20KC
ATV2500BQ-20PC
40DW6
44J
44KW
40P6
Commercial
(0°C to 70°C)
40
40
Operation Range
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
40DW6
40-pin, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip)
44J
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
44KW
44-lead, Windowed, Ceramic J-leaded Chip Carrier (JLCC)
40P6
40-pin, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP)
44LW
44-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
16
ATV2500B(Q)(L)
ATV2500B(Q)(L)
Ordering Information (Continued)
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz)
25
12
31
Ordering Code
Package
ATV2500BQ-25DC
ATV2500BQ-25JC
ATV2500BQ-25KC
ATV2500BQ-25PC
40DW6
44J
44KW
40P6
Operation Range
Commercial
(0°C to 70°C)
ATV2500BQ-25DI
ATV2500BQ-25JI
ATV2500BQ-25KI
ATV2500BQ-25PI
40DW6
44J
44KW
40P6
Industrial
(-40°C to 85°C)
ATV2500BQ-25DM
ATV2500BQ-25KM
ATV2500BQ-25LM
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
ATV2500BQ-25DM/883
ATV2500BQ-25KM/883
ATV2500BQ-25LM/883
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
25
12
31
ATV2500BQL-25DC
ATV2500BQL-25JC
ATV2500BQL-25KC
ATV2500BQL-25PC
40DW6
44J
44KW
40P6
Commercial
(0°C to 70°C)
25
12
31
ATV2500BQL-25DI
ATV2500BQL-25JI
ATV2500BQL-25KI
ATV2500BQL-25PI
40DW6
44J
44KW
40P6
Industrial
(-40°C to 85°C)
30
15
26
ATV2500BQL-30DM
ATV2500BQL-30KM
ATV2500BQL-30LM
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
15
26
ATV2500BQL-30DM/883
ATV2500BQL-30KM/883
ATV2500BQL-30LM/883
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
40DW6
40-pin, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip)
44J
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
44KW
44-lead, Windowed, Ceramic J-leaded Chip Carrier (JLCC)
40P6
40-pin, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP)
44LW
44-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
17
Ordering Information (Continued)
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz)
Ordering Code
Package
15
10
52
5962 - 9154504MXX
5962 - 9154504MYX
44LW
44KW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
20
11
40
5962 - 9154505MXX
5962 - 9154505MYX
44LW
44KW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
25
12
31
5962 - 9154506MXX
5962 - 9154506MYX
5962 - 9154506MQA
44LW
44KW
40DW6
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
30
15
26
5962 - 9154507MXX
5962 - 9154507MYX
5962 - 9154507MQA
44LW
44KW
40DW6
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
Operation Range
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
40DW6
40-pin, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip)
44J
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
44KW
44-lead, Windowed, Ceramic J-leaded Chip Carrier (JLCC)
40P6
40-pin, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP)
44LW
44-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
18
ATV2500B(Q)(L)
Packaging Information
40DW6, 40-pin, 0.600” Wide, Windowed, Ceramic
Dual Inline Package (Cerdip)
Dimensions in Inches and (Millimeters)
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
MIL-STD-1835 D-5 CONFIG A
.045(1.14) X 45°
.045(1.14) X 30° - 45°
PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.050(1.27) TYP
.500(12.7) REF SQ
.022(.559) X 45° MAX (3X)
44KW, 44-lead, Windowed, Ceramic J-leaded Chip
Carrier (JLCC)
Dimensions in Inches and (Millimeters)
40P6, 40-pin, 0.600” Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 CJ1
JEDED STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.035(.889) X 45°
.010(.254)
.006(.152)
.045(1.14) X 45°
.630(16.0)
.590(15.0)
.665(16.9)
SQ
.645(16.4)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
.566(14.4)
.530(13.5)
.021(.533)
.017(.432)
.045(1.14)
.035(.889)
.120(3.05)
.090(2.29)
.180(4.57)
.156(3.96)
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.025(.635) RADIUS MAX (3X)
.012(.305)
.008(.203)
ATV2500B(Q)(L)
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
19
.090(2.29)
MAX
1.900(48.26) REF
.690(17.5)
.610(15.5)
ATV2500B(Q)(L)
Packaging Information
44LW, 44-pad, Windowed, Ceramic Leadless Chip
Carrier (LCC)
Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-5
*Controlling dimension: millimeters
20
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© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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