Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2T08VD020N
Rev. 0, 1/2016
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
A2T08VD020NT1
This 2 W RF power LDMOS transistor is designed for cellular base station
applications covering the frequency range of 728 to 960 MHz.
900 MHz
 Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQA = IDQB = 40 mA, Pout = 2 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
ACPR
(dBc)
920 MHz
19.3
21.3
–43.4
940 MHz
19.3
21.5
–43.8
960 MHz
19.1
21.1
–43.9
700 MHz
728–960 MHz, 2 W AVG., 48 V
AIRFAST RF POWER LDMOS
TRANSISTOR
PQFN 8  8
PLASTIC
 Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQA = IDQB = 40 mA, Pout = 2 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
ACPR
(dBc)
728 MHz
19.2
18.9
–42.3
748 MHz
19.2
19.2
–42.6
768 MHz
18.9
18.7
–42.6
Features
 Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
 On--Chip Matching (50 Ohm Input, DC Blocked)
 Integrated Quiescent Current Temperature Compensation with
Enable/Disable Function (1)
 Integrated ESD Protection
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
 Freescale Semiconductor, Inc., 2016. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2T08VD020NT1
1
RFinA
RFoutA
RFinB
RFoutB
1
2
3
4
5
6
GND
GND
N.C.
RFinB
N.C.
N.C.
N.C.
7 8 9 10 11 12
N.C.
N.C.
Quiescent Current
Temperature Compensation (1)
24 23 22 21 20 19
18
17
16
15
14
13
RFoutA/VDSA
N.C.
GND
GND
N.C.
RFoutB/VDSB
N.C.
N.C.
N.C.
RFinA
N.C.
VGSB
Quiescent Current
Temperature Compensation (1)
VGSA
N.C.
N.C.
VGSA
VGSB
Note: Exposed backside of the package is
the source terminal for the transistors.
Figure 1. Functional Block Diagram
Figure 2. Pin Connections
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain--Source Voltage
VDSS
–0.5, +105
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
55, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
TJ
–40 to +225
C
Symbol
Value (3,4)
Unit
RJC
3.7
C/W
Operating Junction Temperature Range
(2,3)
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 80C, 2 W CW, 48 Vdc, IDQA = IDQB = 40 mA, 940 MHz
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
1C
Machine Model (per EIA/JESD22--A115)
A
Charge Device Model (per JESD22--C101)
III
Table 4. Moisture Sensitivity Level
Test Methodology
Per JESD22--A113, IPC/JEDEC J--STD--020
Rating
Package Peak Temperature
Unit
3
260
C
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
2. Continuous use at maximum temperature will affect MTTF.
3. MTTF calculator available at http://www.nxp.com/RF/calculators.
4. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.nxp.com/RF and search for AN1955.
A2T08VD020NT1
2
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 105 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 55 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 26 Adc)
VGS(th)
1.3
1.8
2.3
Vdc
Gate Quiescent Voltage
(VDS = 48 Vdc, IDQ = 80 mAdc)
VGS(Q)
—
2.5
—
Vdc
Fixture Gate Quiescent Voltage (2)
(VDD = 48 Vdc, IDQ = 80 mAdc, Measured in Functional Test)
VGG(Q)
4.0
5.0
6.0
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 64 mAdc)
VDS(on)
0.1
0.21
0.8
Vdc
Characteristic
Off Characteristics (1)
On Characteristics (1)
Functional Tests (3) (In Freescale Test Fixture, 50 ohm system) VDD = 48 Vdc, IDQA = IDQB = 40 mA, Pout = 2 W Avg., f = 960 MHz,
Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz
Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
18.0
19.1
21.0
dB
Drain Efficiency
D
20.0
21.1
—
%
ACPR
—
–43.9
–41
dBc
Adjacent Channel Power Ratio
Load Mismatch (In Freescale Test Fixture, 50 ohm system) IDQA = IDQB = 40 mA, f = 940 MHz, 10 sec(on), 10% Duty Cycle
VSWR 10:1 at 55 Vdc, 35 W Pulsed CW Output Power
(3 dB Input Overdrive from 26.9 W Pulsed CW Rated Power)
No Device Degradation
Typical Performance (In Freescale Test Fixture, 50 ohm system) VDD = 48 Vdc, IDQA = IDQB = 40 mA, 920–960 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
18.6
—
W
Pout @ 3 dB Compression Point (4)
P3dB
—
21.9
—
W

—
–10.5
—

VBWres
—
120
—
MHz
Gain Flatness in 40 MHz Bandwidth @ Pout = 2 W Avg.
GF
—
0.2
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.017
—
dB/C
P1dB
—
0.007
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C)
Table 6. Ordering Information
Device
A2T08VD020NT1
1.
2.
3.
4.
Tape and Reel Information
T1 Suffix = 1,000 Units, 16 mm Tape Width, 13--inch Reel
Package
PQFN 8  8
Each side of device measured separately.
Side A and Side B are tied together for this measurement.
Part internally input matched.
P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
3
VGGA
R1
C7
C5
C3
VDDA
C13
C9
C1
C11
Z1
R4
R5
Z2
C12
C2
C4
C10
C6
D75703
R3
A2T08VD020N
Rev. 5
VGGB
C8
R2
C14
VDDB
Figure 3. A2T08VD020NT1 Test Circuit Component Layout
Table 7. A2T08VD020NT1 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C2, C5, C6, C7, C8, C9, C10 47 pF Chip Capacitors
ATC100B470JT500XT
ATC
C3, C4
1.1 pF Capacitors
ATC100B1R1BT500XT
ATC
C11, C12
2 pF Chip Capacitors
ATC100B2R0BT500XT
ATC
C13, C14
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
R1, R2
2 k, 1/8 W Chip Resistors
SG73P2ATTD2001F
KOA Speer
R3
0 , 1.5 A Chip Resistor
CWCR08050000Z0EA
Vishay
R4, R5
50 , 10 W Chip Resistors
C8A50Z4A
Anaren
Z1, Z2
600–900 MHz Band, 90, 3 dB Hybrid Couplers
X3C09F1-03S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D75703
MTL
A2T08VD020NT1
4
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS
22
20
19.5
18
Gps
19
16
18.5
–40
18
–41
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
17.5
17
16.5
16
820
860
880
900
920
f, FREQUENCY (MHz)
940
–42
–43
–44
ACPR
840
ACPR (dBc)
Gps, POWER GAIN (dB)
VDD = 48 Vdc, Pout = 2 W (Avg.), IDQA = IDQB = 40 mA
20.5 Single--Carrier W--CDMA, 3.84 MHz
D
20 Channel Bandwidth
D, DRAIN
EFFICIENCY (%)
24
21
–45
980
960
IMD, INTERMODULATION DISTORTION (dBc)
Figure 4. Broadband Performance @ Pout = 2 Watts Avg.
0
VDD = 48 Vdc, Pout = 9 W (PEP), IDQA = IDQB = 40 mA
Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 940 MHz
–15
IM3--U
–30
IM5--U
IM3--L
IM5--L
–45
IM7--U
–60
–75
IM7--L
1
10
200
100
TWO--TONE SPACING (MHz)
19.3
0
19.2
19.1
19
18.9
18.8
VDD = 48 Vdc, IDQA = IDQB = 40 mA, f = 940 MHz
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
50
–30
45
–33
ACPR
–1
–1 dB = 2.94 W
–2
40
D
35
Gps
–3
30
–2 dB = 3.92 W
–3 dB = 5.1 W
–4
PARC
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–5
2
3
4
5
Pout, OUTPUT POWER (WATTS)
6
–36
–39
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
19.4
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 5. Intermodulation Distortion Products
versus Two--Tone Spacing
–42
25
–45
20
–48
7
Figure 6. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
19
960 MHz
940 MHz 920 MHz
17
D
16
920 MHz
15
1
–20
50
–25
40
Gps
920 MHz
940 MHz
960 MHz
18
60
30
20
960 MHz
940 MHz
10
0
30
10
Pout, OUTPUT POWER (WATTS) AVG.
–30
–35
–40
ACPR (dBc)
VDD = 48 Vdc, IDQA = IDQB = 40 mA, Single--Carrier
W--CDMA, 3.84 MHz Channel Bandwidth
20 Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
ACPR
D, DRAIN EFFICIENCY (%)
Gps, POWER GAIN (dB)
21
–45
–50
Figure 7. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
22
20
Gain
GAIN (dB)
18
16
14
VDD = 48 Vdc
Pin = 0 dBm
IDQA = IDQB = 40 mA
12
10
500
600
700
800
900
1000
f, FREQUENCY (MHz)
1100
1200
1300
Figure 8. Broadband Frequency Response
A2T08VD020NT1
6
RF Device Data
Freescale Semiconductor, Inc.
Table 8. Load Pull Performance — Maximum Power Tuning
VDD = 48 Vdc, IDQ = 40 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
Zload
()
f
(MHz)
Zsource
()
Zin
()
920
41.8 + j35.9
34.1 – j36.2
940
33.0 + j36.5
31.9 – j33.8
960
32.2 + j41.2
27.6 – j31.3
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
19.4 + j28.6
18.7
40.8
12
56.7
–7
24.2 + j26.5
18.7
41.2
13
61.8
–8
27.8 + j24.6
18.5
41.3
14
61.7
–9
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
41.8 + j35.9
34.8 – j35.7
25.0 + j28.7
16.7
41.8
15
63.3
–9
940
33.0 + j36.5
32.2 – j34.6
27.5 + j24.4
16.5
42.0
16
62.3
–10
960
32.2 + j41.2
27.4 – j32.2
30.3 + j23.1
16.3
42.0
16
62.4
–11
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Table 9. Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 48 Vdc, IDQ = 40 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
920
41.8 + j35.9
29.0 – j28.6
17.2 + j47.6
20.0
38.9
8
69.1
–9
940
33.0 + j36.5
27.8 – j29.3
18.5 + j42.2
19.9
39.6
9
70.9
–11
960
32.2 + j41.2
24.3 – j27.6
19.3 + j41.0
19.7
39.8
9
71.0
–12
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
41.8 + j35.9
31.3 – j31.3
21.2 + j45.2
17.8
40.5
11
72.3
–13
940
33.0 + j36.5
28.3 – j31.2
18.9 + j41.2
17.8
40.4
11
71.0
–15
960
32.2 + j41.2
24.5 – j29.3
19.8 + j39.3
17.6
40.6
11
70.7
–16
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
7
P1dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
80
37
70
38.5
38
39
39.5
IMAGINARY ()
IMAGINARY ()
70
60
80
37.5
50
40
E
40
40.5
30
P
20
20
41
30
40
60
40
50
REAL ()
70
70
60
60
IMAGINARY ()
70
19.5
19
E
40
18.5
30
18
P
10
10
16
20
30
40
50
REAL ()
60
70
80
Figure 11. P1dB Load Pull Gain Contours (dB)
NOTE:
40
50
REAL ()
50
40
–14
60
70
80
–6
E
–12
–10
P
–8
20
17
17.5
17
30
–4
30
20
58
56
54
P
20
60
Figure 10. P1dB Load Pull Efficiency Contours (%)
80
20
62
66
64
10
10
80
80
50
68
E 70
20
Figure 9. P1dB Load Pull Output Power Contours (dBm)
IMAGINARY ()
50
30
40
10
10
60
10
10
20
30
40
50
REAL ()
60
70
80
Figure 12. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T08VD020NT1
8
RF Device Data
Freescale Semiconductor, Inc.
P3dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
80
80
39.5
38
70
40
60
50
IMAGINARY ()
70
IMAGINARY ()
39
38.5
40.5
E
40
41
50
P
20
10
10
41.5
40
20
30
40
50
REAL ()
60
70
80
70
60
60
E
17
16.5
30
20
IMAGINARY ()
70
17.5
P
14
14.5 15
10
20
10
40
50
REAL ()
60
70
80
Figure 15. P3dB Load Pull Gain Contours (dB)
NOTE:
20
30
40
50
REAL ()
60
70
80
–4
–14
50
40
–20
E
–6
–16
P
–12
20
15
15.5
30
54
30
16
58
56
Figure 14. P3dB Load Pull Efficiency Contours (%)
80
18
66 64 62 60
68
P
10
10
80
40
70
20
Figure 13. P3dB Load Pull Output Power Contours (dBm)
50
E
40
30
30
IMAGINARY ()
60
10
10
–8
–10
20
30
40
50
REAL ()
60
70
80
Figure 16. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
9
VGGA
R1
VDDA
C6
C4
C2
C1
C5
R3
C3
Z1
C7
Z2
C10
C14
R4
C12
C8
R2
A2T08VD020N
D71504 Rev. 3
C9
C11
VGGB
C13
R5
VDDB
Figure 17. A2T08VD020NT1 Test Circuit Component Layout — 728–768 MHz
Table 10. A2T08VD020NT1 Test Circuit Component Designations and Values — 728–768 MHz
Part
Description
Part Number
Manufacturer
C1, C8
2.2 F Chip Capacitors
C3225X7R0H225M
TDK
C2, C4, C5, C9, C11, C12
68 pF Chip Capacitors
ATC100B680JT500XT
ATC
C3, C7, C10, C14
3.9 pF Chip Capacitors
ATC100B3R9BT500XT
ATC
C6, C13
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
R1, R5
2 k, 1/8 W Chip Resistors
SG73P2ATTD2001F
KOA Speer
R2
0 , 1.5 A Chip Resistor
CWCR08050000Z0EA
Vishay
R3, R4
50 , 10 W Chip Resistors
C8A50Z4A
Anaren
Z1, Z2
600–900 MHz Band, 90, 3 dB Hybrid Couplers
X3C07F1-03S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D71504
MTL
A2T08VD020NT1
10
RF Device Data
Freescale Semiconductor, Inc.
20
20
19.8
19
18
D
19.2
16
VDD = 48 Vdc, Pout = 2 W (Avg.)
IDQA = IDQB = 40 mA, Single--Carrier
W--CDMA, 3.84 MHz Channel Bandwidth
19
18.8
17
–42
Gps
–42.2
18.6
–42.4
18.4
18.2
18
710
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
720
730
740
750
760
f, FREQUENCY (MHz)
ACPR
770
780
–42.6
–42.8
ACPR (dBc)
Gps, POWER GAIN (dB)
19.6
19.4
D, DRAIN
EFFICIENCY (%)
TYPICAL CHARACTERISTICS — 728–768 MHz
–43
790
Figure 18. Broadband Performance @ Pout = 2 Watts Avg.
Gps, POWER GAIN (dB)
20
19
–20
60
–25
50
748 MHz
18
17
728 MHz
768 MHz
16
15
70
1
D
768 MHz
728 MHz
748 MHz
768 MHz
728 MHz
748 MHz
40
30
Gps
20
10
30
10
Pout, OUTPUT POWER (WATTS) AVG.
–30
–35
–40
ACPR (dBc)
VDD = 48 Vdc, IDQA = IDQB = 40 mA, Single--Carrier
W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01%
ACPR
Probability on CCDF
D, DRAIN EFFICIENCY (%)
21
–45
–50
Figure 19. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
24
21
Gain
GAIN (dB)
18
15
12
VDD = 48 Vdc
Pin = 0 dBm
IDQA = IDQB = 40 mA
9
6
400
500
600
700
800
900
f, FREQUENCY (MHz)
1000
1100
1200
Figure 20. Broadband Frequency Response
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
11
Table 11. Load Pull Performance — Maximum Power Tuning
VDD = 48 Vdc, IDQ = 40 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
Zload
()
Zsource
()
Zin
()
728
46.6 – j11.0
61.7 + j5.77
748
51.5 – j10.2
66.0 + j0.74
768
51.6 – j5.44
67.2 – j4.42
f
(MHz)
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
40.4 + j26.1
19.0
41.2
13
60.7
–8
39.9 + j26.8
19.0
41.3
14
61.8
–8
39.7 + j24.8
18.8
41.4
14
61.5
–8
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
728
46.6 – j11.0
63.6 + j7.43
39.6 + j24.6
16.8
41.9
16
61.2
–9
748
51.5 – j10.2
68.6 + j2.36
39.5 + j24.5
16.8
42.0
16
62.0
–9
768
51.6 – j5.44
69.9 – j3.72
40.7 + j22.8
16.7
42.1
16
62.2
–9
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Table 12. Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 48 Vdc, IDQ = 40 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
728
46.6 – j11.0
61.8 – j9.22
31.6 + j57.1
20.5
39.4
9
71.4
–11
748
51.5 – j10.2
61.7 – j11.9
33.0 + j54.0
20.3
39.6
9
69.8
–10
768
51.6 – j5.44
59.9 – j14.8
33.7 + j51.8
20.2
39.8
9
69.4
–10
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
728
46.6 – j11.0
64.0 – j5.03
32.4 + j55.2
18.4
40.3
11
71.3
–13
748
51.5 – j10.2
65.2 – j9.06
33.6 + j52.7
18.3
40.4
11
69.8
–12
768
51.6 – j5.44
65.1 – j11.0
37.5 + j46.3
17.9
41.0
12
69.5
–11
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T08VD020NT1
12
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL LOAD PULL CONTOURS — 748 MHz
80
80
38
38.5
70
39
37.5
39.5
60
E
50
IMAGINARY ()
IMAGINARY ()
70
40
40.5
40
41
30
P
50
20
30
60
40
50
REAL ()
70
64
40
60
62
58
P
10
10
80
Figure 21. P1dB Load Pull Output Power Contours (dBm)
70
70
60
60
20
E
50
IMAGINARY ()
80
20.5
19.5
40
19
30
54
20
30
40
50
REAL ()
40
50
REAL ()
60
70
80
50
–8
–10
–14
–20 –16
–18
–12
–6
E
40
P
20
18.5
18
30
30
P
16.5 17 17.5
20
56
Figure 22. P1dB Load Pull Efficiency Contours (%)
80
10
10
66
20
38
10
10
20
68
E
30
20
IMAGINARY ()
60
60
70
80
Figure 23. P1dB Load Pull Gain Contours (dB)
NOTE:
10
10
20
30
40
50
REAL ()
60
70
80
Figure 24. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
13
P3dB – TYPICAL LOAD PULL CONTOURS — 748 MHz
80
38
39
39.5
70
40
60
40.5
E
50
IMAGINARY ()
IMAGINARY ()
70
80
38.5
41
40
41.5
P
20
10
10
42
68
40
39
20
30
40
50
REAL ()
60
70
80
70
70
18.5
40
IMAGINARY ()
18
E
50
17.5
30
P
14.5 15 15.5
20
16
30
58
56
P
54
20
30
40
50
REAL ()
60
70
80
–16
–12
–10
–14
–18
60
–8
–4
E
50
–6
40
30
17
P
20
16.5
40
50
REAL ()
62 60
Figure 26. P3dB Load Pull Efficiency Contours (%)
80
60
64
66
10
10
80
10
10
E
50
20
Figure 25. P3dB Load Pull Output Power Contours (dBm)
IMAGINARY ()
60
30
30
20
54
60
70
80
Figure 27. P3dB Load Pull Gain Contours (dB)
NOTE:
10
10
20
30
40
50
REAL ()
60
70
80
Figure 28. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T08VD020NT1
14
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
15
A2T08VD020NT1
16
RF Device Data
Freescale Semiconductor, Inc.
A2T08VD020NT1
RF Device Data
Freescale Semiconductor, Inc.
17
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.nxp.com/RF
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Jan. 2016
Description
 Initial Release of Data Sheet
A2T08VD020NT1
18
RF Device Data
Freescale Semiconductor, Inc.
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E 2016 Freescale Semiconductor, Inc.
A2T08VD020NT1
Document
Number:
RF
Device
Data A2T08VD020N
Rev. 0, 1/2016Semiconductor, Inc.
Freescale
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