PIC16F527 Memory Programming

PIC16F527
PIC16F527 Memory Programming Specification
This document includes the
programming specifications for the
following devices:
1.1
Hardware Requirements
The PIC16F527 requires one power supply for VDD
(5.0V) and one for VPP (12.5V).
• PIC16F527
1.2
1.0
PROGRAMMING THE
PIC16F527
The Program/Verify mode for the PIC16F527 allows
programming of user program memory, user ID
locations, backup OSCCAL location and the
Configuration Word.
The PIC16F527 is programmed using a serial method.
The Serial mode will allow the PIC16F527 to be
programmed while in the user’s system. This allows for
increased design flexibility. This programming
specification applies to the PIC16F527 devices in all
packages.
FIGURE 1-1:
Program/Verify Mode
20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16F527
20-pin PDIP, SSOP, SOIC
1
2
3
RA4
RA3/MCLR/VPP
RC5
 2012 Microchip Technology Inc.
4
5
17
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
16
RC0
15
14
RC1
RC2
20
19
18
PIC16F527
VDD
RA5
RC4
RC3
6
RC6
8
13
RB4
RC7
9
12
RB5
RB7
10
11
RB6
7
Preliminary
DS41640A-page 1
PIC16F527
FIGURE 1-2:
20-PIN QFN DIAGRAM FOR PIC16F527
16
VDD
VSS
RA0/ICSPDAT
RA5
18
17
15
RA1/ICSPCLK
14
RA2
3 PIC16F527 13
12
4
11
5
RC0
7
8
9
10
RB6
RB5
RB4
RC4
RC3
6
2
RB7
1
RC5
RC7
RA3/MCLR/VPP
RC6
TABLE 1-1:
20
19
RA4
20-pin QFN
RC1
RC2
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Pin Name
Function
Pin Type
Pin Description
RA1
ICSPCLK
I
RA0
ICSPDAT
I/O
Data input/output – Schmitt Trigger input
Program/Verify mode
P(1)
Programming Power
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
MCLR/VPP/RA3
Clock input – Schmitt Trigger input
Legend: I = Input, O = Output, P = Power
Note 1: In the PIC16F527, the programming high voltage is internally generated. To activate the Program/Verify
mode, high voltage of IIHH current capability (see Table 6-1) needs to be applied to the MCLR input.
DS41640A-page 2
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
2.0
MEMORY MAPPING
2.3
The program memory map of the PIC16F527 device is
shown in Figure 2-1. In Program/Verify mode, the
program memory extends from 0x000 to 0x7FF.
Data Memory
Space
User Memory
Space
FIGURE 2-1:
MEMORY MAP
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
Reset Vector
Configuration Memory
Space
Backup OSCCAL
Locations
3FEh
3FFh
400h
43Fh
440h
443h
444h
447h
448h
2.3.2
CONFIGURATION WORD
The Configuration Word is physically located at 0x7FF.
It is only available upon Program mode entry. Once an
Increment Address command is issued, the
Configuration Word is no longer accessible, regardless
of the address of the program counter.
Note:
49Fh
4A0h
Unimplemented
7FEh
7FFh
User Memory
The user memory space is the on-chip user program
memory. As shown in Figure 2-1, it extends from 0x000
to 0x3FF and partitions into pages, including the Reset
vector, at address 0x3FF, and the Interrupt vector, at
address 0x004. Note that the PC will increment from
(0x000-0x3FF) then to 0x400, (not to 0x000).
Data Memory
The data memory space is the self-writable Flash data
memory block and is located at addresses PC = 400h43Fh. All program mode commands that work on the
normal Flash memory work on the self-writable Flash
data memory block. This includes Bulk Erase, Load
and Read Data commands.
 2012 Microchip Technology Inc.
USER ID LOCATIONS
A user may store identification information (ID) in four
user ID locations. The user ID locations are mapped in
[0x440:0x443]. It is recommended that users use only
the four Least Significant bits (LSb) of each user ID
location and program the upper eight bits as ‘1’s. The
user ID locations read out normally, even after code
protection is enabled. It is recommended that user ID
location is written as ‘1111 1111 bbbb’ where ‘bbbb’
is user ID information.
1FFh
200h
Reserved
Configuration Word
2.2
The configuration memory space extends from 0x440
to 0x7FF. Locations from 0x448 through 0x49F are
reserved. The user ID locations extend from 0x440
through 0x443. The Configuration Word is physically
located at 0x7FF, and the backup OSCCAL locations
extend from 0x444 through 0x447.
2.3.1
Self-writable
Flash Data Memory
User ID Locations
2.1
000h
Configuration Memory
2.3.3
By convention, the Configuration Word is
stored at the logical address location of
0xFFF within the hex file generated for the
PIC16F527. This logical address location
may not reflect the actual physical
address for the part itself. It is the responsibility of the programming software to
retrieve the Configuration Word from the
logical address within the hex file and
granulate the address to the proper physical location when programming.
BACKUP OSCCAL VALUE
The backup OSCCAL locations, 0x444-0x447, are the
locations where the OSCCAL values are stored during
testing of the INTOSC. This location is not erased during a standard Bulk Erase, but is erased if the PC is
moved into configuration memory prior to invoking a
Bulk Erase. If this value is erased, it is the user’s
responsibility to rewrite it back to this location for future
use.
2.4
Oscillator Calibration Bits
The oscillator Calibration bits are stored at the Reset
vector as the operand of a MOVLW instruction.
Programming interfaces must allow users to program
the Calibration bits themselves for custom trimming of
the INTOSC. Capability for programming the
Calibration bits when programming the entire memory
array must also be maintained for backwards
compatibility.
Preliminary
DS41640A-page 3
PIC16F527
3.0
COMMANDS AND
ALGORITHMS
3.1
Program/Verify Mode
3.1.2
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising VDD pin from
VIL to VDD. Then raise VPP from VIL to VIHH. Once in
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.
The sequence that enters the device into the Programming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at VIL). This means
that all I/Os are in the Reset state (high-impedance
inputs).
3.1.1
PROGRAMMING
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x7FF. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1:
ENTERING HIGHVOLTAGE PROGRAM/
VERIFY MODE
TPPDP
SERIAL PROGRAM/VERIFY
OPERATION
The RA1 pin is used as a clock input pin, and the RA0
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RA1) is cycled six times. Each command bit
is latched on the falling edge of the clock with the Least
Significant bit (LSb) of the command being input first.
The data on pin RA0 is required to have a minimum
setup and hold time of 100 ns with respect to the falling
edge of the clock. Commands that have data associated with them (Read and Load) are specified to have
a minimum delay of 1 µs between the command and
the data. After this delay the clock pin is cycled 16 times
with the first cycle being a Start bit and the last cycle
being a Stop bit. Data is also input and output LSb first,
with data input being latched on the falling edge of the
clock and data output being driven on the rising edge of
the clock. Therefore, during a read operation the LSb
will be transmitted onto pin RA0 on the rising edge of
the second cycle, and during a load operation the LSb
will be latched on the falling edge of the second cycle.
A minimum 1 µs delay is also specified between consecutive commands; except the “End Programming”
command which requires a 100 µs delay. Because this
is a 12-bit core, the two MSbs of the data word are
ignored. The commands that are available are
described in Table 3-1.
THLD0
VPP
VDD
RA0
(ICSPDAT)
RA1
(ICSPCLK)
TABLE 3-1:
COMMAND MAPPING LOAD DATA
Mapping
(MSb ... LSb)
Hex
Value
Load Data
X X 0 0 1 0
2
start_bit, data (14), stop_bit
Read Data
X X 0 1 0 0
4
start_bit, data (14), stop_bit
Increment Address
X X 0 1 1 0
6
Begin Programming
X X 1 0 0 0
8
End Programming
X X 1 1 1 0
E
Bulk Erase Program Memory
X X 1 0 0 1
9
Command
DS41640A-page 4
Preliminary
Data
 2012 Microchip Technology Inc.
PIC16F527
3.1.2.1
Load Data
After receiving this command, the device will clock in
14 bits as a “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-2.
FIGURE 3-2:
LOAD DATA COMMAND (PROGRAM/VERIFY)
1
RA1
(ICSPCLK)
RA0
(ICSPDAT)
3.1.2.2
2
3
1
0
4
5
0
0
TSET1
THLD1
x
6
TDLY2
1
2
4
5
16
15
MSb stp_bit
LSb
strt_bit
x
3
TSET1
-+THLD1
TDLY1
Read Data
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The RA0
pin will go into Output mode on the second rising clock
edge and it will revert back to Input mode (high-impedance) after the 16th rising edge. Because this is a 12bit core, the two MSbs will read as ‘1’. A timing diagram
of this command is shown in Figure 3-3.
FIGURE 3-3:
READ DATA FROM PROGRAM MEMORY COMMAND
TDLY2
1
2
3
4
1
0
5
1
6
2
3
4
RA1
(ICSPCLK)
5
15
16
TDLY3
RA0
(ICSPDAT)
1
0
0
x
x
strt_bit
TDLY1
TSET1
MSb stp_bit
LSb
THLD1
Input
 2012 Microchip Technology Inc.
Output
Preliminary
Input
DS41640A-page 5
PIC16F527
3.1.2.3
Increment Address
The PC is incremented when this command is
received.
FIGURE 3-4:
INCREMENT ADDRESS COMMAND (SERIAL PROGRAM/VERIFY)
VIHH
MCLR/VPP
TDLY2
1
2
0
1
3
4
5
6
0
X
X
1 µs min.
Next Command
1
2
RA1
(ICSPCLK)
RA0
(ICSPDAT)
1
TSET1
THLD1
}
}
100 ns
min.
Reset
3.1.2.4
Begin Programming
A Load command (Load Data) must be given before
every Begin Programming command. Programming of
the appropriate memory (User program memory, selfwritable Flash data memory or Test program memory)
will begin after this command is received and decoded.
FIGURE 3-5:
BEGIN PROGRAMMING COMMAND
VIHH
MCLR/VPP
TPROG
1
2
0
0
3
4
5
6
1
X
X
Next Command
1
2
RA1
(ICSPCLK)
RA0
(ICSPDAT)
0
TSET1
THLD1
}
}
100 ns
min.
Reset
DS41640A-page 6
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
3.1.2.5
End Programming
After receiving this command, the chip stops
programming the memory (User program memory, selfwritable Flash data memory or Test program memory)
it was programming at the time.
FIGURE 3-6:
END PROGRAMMING COMMAND
VIHH
MCLR/VPP
TDIS
1
2
0
1
3
4
5
6
1
X
X
1 µs min.
Next Command
1
2
RA1
(ICSPCLK)
RA0
(ICSPDAT)
1
TSET1
THLD1
}
}
100 ns
min.
Reset
3.1.2.6
Bulk Erase Program Memory
After this command is performed, the specific section of
program memory and Configuration Word is erased.
See Table 3-2 for details.
Note 1: A fully erased part will read ‘1’s in every
program memory location.
2: The oscillator Calibration bits are erased
if a Bulk Erase is invoked. They must be
read and saved prior to erasing the
device and restored during the programming operation. Oscillator Calibration bits
are stored at the Reset vector as the
operand of a MOVLW instruction.
FIGURE 3-7:
BULK ERASE PROGRAM MEMORY COMMAND
VIHH
MCLR/VPP
TERA
1
2
1
0
3
4
5
6
1
X
X
Next Command
1
2
RA1
(ICSPCLK)
RA0
(ICSPDAT)
0
TSET1
THLD1
}
}
100 ns
min.
Reset
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 7
PIC16F527
TABLE 3-2:
BULK ERASE MEMORY PORTIONS
Config.
Word
(Fuses)
User Program
Memory Erased
Configuration Word
(Fuses)
Yes
Yes
CPSW = 0 – Yes
CPSW = 1 – No
No
000h-3FFh
(User Memory)
Yes
Yes
CPSW = 0 – Yes
CPSW = 1 – No
No
400h-43Fh
(Data Memory)
No
No
CPSW = 0 – No
CPSW = 1 – Yes
No
440h-447h
(Configuration Memory)
No
No
No
Yes
PC
Note:
Self-writable Flash Data
Memory
Erased
User ID Memory
Erased
Yes = Erase
No = Unchanged
DS41640A-page 8
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
FIGURE 3-8:
READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC =
0x3FF?
Yes
Read Calibration
Bits and Save in
Computer/Programmer
Temp. Memory
Increment
Address
No
PC =
0x444?
Yes
Read Backup OSCCAL
Calibration Bits
and Save in
Computer/Programmer
Temp. Memory
Exit Programming Mode
Done
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 9
PIC16F527
FIGURE 3-9:
RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC =
0x3FF?
Yes
Read Calibration
Bits from
Computer/Programmer
Temp. Memory
Write Calibration Bits
back as the operand
of a MOVLW instruction
to 0x3FF
Increment
Address
No
PC =
0x444?
Yes
Read Backup OSCCAL
Calibration Bits from
Computer/Programmer
Temp. Memory
Write Backup OSCCAL
Bits back to 0x444
Exit Programming Mode
Done
DS41640A-page 10
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
FIGURE 3-10:
PROGRAM FLOWCHART – USER MEMORY
Start
Enter Programming
Mode
PC = 0x7FF
(Config Word)
Increment
Address
PROGRAM CYCLE
Load Data
for
Program Memory
One Word
Program Cycle
Begin
Programming
Command
(Externally timed)
Read Data
from
Program Memory
Wait TPROG
Data Correct?
No
Report
Programming
Failure
End
Programming
Yes
Increment
Address
Command
No
All Programming
Locations
Done?
Wait TDIS
Yes
Exit Programming
Mode
Done
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 11
PIC16F527
FIGURE 3-11:
PROGRAM FLOWCHART – SELF-WRITABLE FLASH DATA MEMORY
Start
Enter Programming
Mode
PC = 0x7FF
(Config Word)
Increment
Address
No
PC = 0x400?
PROGRAM CYCLE
Load Data
for
Program Memory
Yes
One Word
Program Cycle
Begin
Programming
Command
(Externally timed)
Read Data
from
Program Memory
Wait TPROG
Data Correct?
No
Report
Programming
Failure
End
Programming
Yes
Increment
Address
Command
No
All Programming
Locations
Done?
Wait TDIS
Yes
Exit Programming
Mode
Done
DS41640A-page 12
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
FIGURE 3-12:
PROGRAM FLOWCHART – CONFIGURATION MEMORY
Start
Enter Programming
Mode
PC = 0x7FF
(Config Word)
Load Data Command
Programs Configuration Word
One-Word
Programming
Cycle
(see Figure 3-10)
Read Data Command
Data
Correct?
No
Report
Programming
Failure
Yes
Increment Address
Command
No
Address =
0x440?
Yes
Load Data
Command
Programs User IDs
One-Word
Programming
Cycle
(see Figure 3-10)
Read Data Command
Data
Correct?
No
Report
Programming
Failure
Yes
Increment Address
Command
No
Address =
0x444?
Yes
Exit Programming Mode
Done
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 13
PIC16F527
FIGURE 3-13:
PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD
Start
Bulk Erase Device
Read and Save
OSCCAL bits
(Figure 3-8)
Wait TERA
Exit Programming
Mode
Enter
Program/Verify mode
PC = 0x7FF
(Config Word)
Restore OSCCAL bits
(Figure 3-9)
Done
Note:
Self-writable Flash Data Memory block will also be erased if CPSW = 0 (see Table 3-2 for more information).
FIGURE 3-14:
PROGRAM FLOWCHART – ERASE SELF-WRITABLE FLASH DATA MEMORY
Start
Bulk Erase Device
Read and Save
OSCCAL bits
(Figure 3-8)
Wait TERA
Exit Programming
Mode
Enter
Program/Verify mode
PC = 0x7FF
(Config. Word)
Restore OSCCAL bits
(Figure 3-9)
Increment Address
Done
No
PC =
0x400?
Yes
Note 1:
This operation requires that CPSW = 1.
DS41640A-page 14
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
FIGURE 3-15:
PROGRAM FLOWCHART – ERASE USER ID
Read and Save
OSCCAL bits
(Figure 3-8)
Start
Enter
Program/Verify mode
PC = 0x7FF
(Config. Word)
Increment
PC
No
PC = 0x440?
(First User ID)
Yes
Bulk Erase Device
Wait TERA
Exit Programming Mode
Restore OSCCAL bits
(Figure 3-9)
Done
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 15
PIC16F527
FIGURE 3-16:
PROGRAM FLOWCHART – HIGH-LEVEL FULL DEVICE PROGRAM
Start
Read OSCCAL bits
Bulk Erase
User Memory
Bulk Erase
Data Memory
Bulk Erase
ID/OSCCAL
Program
User Memory
Program
Data Memory
Program
Configuration Memory
Restore
OSCCAL bits
Done
DS41640A-page 16
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
FIGURE 3-17:
PROGRAM FLOWCHART – HIGH-LEVEL FULL DEVICE ERASE
Start
Read OSCCAL bits
Bulk Erase
User Memory
Bulk Erase
Data Memory
Bulk Erase
ID/OSCCAL
Restore
OSCCAL bits
Done
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 17
PIC16F527
4.0
CONFIGURATION WORD
The implemented Configuration bits can be
programmed at their default values, or they are not
programmed.
See Register 4-1 below for details.
REGISTER 4-1:
U-1
U-1
—
—
CONFIGURATION WORD
R/P-1
R/P-1
R/P-1
DRTEN BOREN
CPSW
R/P-1
R/P-1
IOSCFS MCLRE
R/P-1
R/P-1
CP
WDTE
R/P-1
R/P-1
R/P-1
FOSC2 FOSC1 FOSC0
bit 11
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
‘1’ = Bit is set
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘1’
-n/n = Value at POR and BOR/Value at all
other Resets
P = Programmable bit
bit 11-10
Unimplemented: Read as ‘1’
bit 9
DRTEN: Device Reset Timer Enable bit
1 = DRT enabled (18 ms)
0 = DRT disabled
bit 8
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 7
CPSW: Code Protection bit – Self-Writable Flash Data Memory
1 = Code protection off
0 = Code protection on
bit 6
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 5
MCLRE: Master Clear Enable bit
1 = RA3/MCLR pin functions as MCLR
0 = RA3/MCLR pin functions as RA3, MCLR tied internally to VDD
bit 4
CP: Code Protection bit – User Program Memory
1 = Code protection off
0 = Code protection on
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
001 = XT oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
010 = HS oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
011 = EC oscillator with RA4 function on RA4/OSC2/CLKOUT and 10 us start-up time(1), (2)
100 = INTRC with RA4 function on RA4/OSC2/CLKOUT and 10 us start-up time(1), (2)
101 = INTRC with CLKOUT function on RA4/OSC2/CLKOUT and 10 us start-up time(1), (2)
110 = EXTRC with RA4 function on RA4/OSC2/CLKOUT and 10 us start-up time(1), (2)
111 = EXTRC with CLKOUT function on RA4/OSC2/CLKOUT and 10 us start-up time(1), (2)
Note 1:
It is the responsibility of the application designer to ensure that the use of the 10 us start-up time will result
in acceptable operation. Refer to Section 6.0 “Program/Verify Mode Electrical Characteristics” for
VDD rise time and stability requirements for this mode of operation.
The optional DRTEN fuse can be used to extend this start-up time to 18 ms.
2:
DS41640A-page 18
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
5.0
CODE PROTECTION
5.2
Checksum Computation
For the PIC16F527, once code protection is enabled,
all program memory locations 0x40-0x3FE, read all
‘0’s. Program memory locations 0x000-0x03F and
0x3FF are always unprotected. The user ID locations,
backup OSCCAL location and the Configuration Word
read out in an unprotected fashion. It is possible to program the user ID locations, backup OSCCAL location
and the Configuration Word after code-protect is
enabled.
5.2.1
The code protection of the self-writable Flash data
memory is dependant on the CPSW bit. If the CPSW
bit is set, only the self-writable Flash data memory
block is code-protected. See Table 3-2 for erase
conditions involving the CPSW bit.
The checksum is calculated by summing the following:
5.1
Disabling Code Protection
It is recommended that the following procedure be
performed before any other programming is attempted.
It is also possible to turn code protection off using this
procedure. However, all data within the program
memory will be erased when this procedure is executed, and thus, the security of the code is not
compromised. See Table 3-2 for more information on
self-writable Flash data memory.
CHECKSUM
Checksum is calculated by reading the contents of the
PIC16F527 memory locations and adding up the
opcodes up to the maximum user addressable location.
Any Carry bits exceeding 16 bits are neglected. Finally,
the Configuration Word (appropriately masked) is
added to the checksum. The checksum computation
for the PIC16F527 is shown in Table 5-1.
• The contents of all program memory locations
• The Configuration Word, appropriately masked
• Masked user ID locations (when applicable)
The Least Significant 16 bits of this sum is the
checksum.
The following table describes how to calculate the
checksum for each PIC16F527.
Note:
The
checksum
calculation
differs
depending on the code-protect setting.
The Configuration Word and user ID
locations can always be read regardless
of the code-protect settings.
To disable code-protect:
a)
b)
c)
Enter Program mode
Execute Bulk Erase program memory command
(001001).
Wait TERA
Note:
To allow portability of code, the
programmer is required to read the
Configuration Word and user ID locations
from the hex file when loading the hex file.
If Configuration Word information was not
present in the hex file, then a simple
warning message may be issued.
Similarly, while saving a hex file,
Configuration Word and user ID
information must be included. An option to
not include this information may be
provided.
Microchip Technology Incorporated feels
strongly that this feature is important for
the benefit of the end customer.
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 19
PIC16F527
TABLE 5-1:
Device
PIC16F527
CHECKSUM COMPUTATIONS(1)
Code-Protect
Checksum*
Blank
Value
0x723 at 0
and Max.
Address
OFF
SUM[0x000:0x3FE] + CFGW & 0x3FF
0xF000
0xDE48
ON
SUM[0x00:0x3F] + CFGW & 0x3FF + SUM_ID
0xF3AF
0xD91B
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.
DS41640A-page 20
Preliminary
 2012 Microchip Technology Inc.
PIC16F527
6.0
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1:
AC/DC TIMING REQUIREMENTS
AC TARGETS
Sym.
Characteristics
Min.
Typ.
Max.
Units
VIHH
VPP High voltage on MCLR for Program/
Verify mode entry
VDD +
3.5
—
13.5
V
VIHL
Voltage on MCLR to be in Normal mode
VSS
—
VDD + 1.0
V
TVHHR
MCLR rise time (VSS to VIHH) for Test
mode entry
—
—
1.0
s
VIH1
Clock (RA1) and Data (RA0) input highlevel
0.85*VDD
—
—
V
VIL1
Clock (RA1) and Data (RA0) input lowlevel
—
—
0.15*VDD
V
VDDOK
Minimum VDD to perform Bulk Erase
VPROG
High voltage on MCLR for programming
IDDPROG
Conditions
General
2.6
2.7
2.8
V
VDD +
3.5
13.0
13.5
V
IDD level for programming operations,
program memory
—
—
1.8
mA
IDDERA
IDD level for Bulk Erase operations, program memory
—
—
1.8
mA
IPP
MCLR pin current during Program/Verify
mode
—
—
0.4
mA
TPROG
Programming time
1000
—
2000
s
TPPDP
Hold time after VPP
5
—
—
s
THLD0
ICSPCLK, ICSPDAT hold time after
MCLR (Program/Verify mode selection
pattern setup time)
5
—
—
s
Serial Program/Verify
TSET1
Data in setup time before clock
100
—
—
ns
THLD1
Data in hold time after clock
100
—
—
ns
TDLY1
Data input not driven to next clock input
(delay required between command/data
or command/command)
1.0
—
—
s
TDLY2
Delay between clock to clock of next
command or data
1.0
—
—
s
TDLY3
Clock to data out valid (during Read
Data)
80
—
—
ns
TERA
Bulk Erase Time
4
—
10
ms
Total time to perform
both stages of Bulk
Erase and accept the
next command.
TDIS
High Voltage Discharge Time
100
—
—
s
Time to discharge high
voltage.
VSW
Self-write/erase voltage
2.0
—
—
V
Minimum voltage to perform a Row Erase or
self-write to the Flash
memory.
TSW
Self-write/erase timing
2.0
—
5
ms
Time allotted to perform
a Row Erase or a write
to one word of the selfwrite Flash.
 2012 Microchip Technology Inc.
Preliminary
DS41640A-page 21
PIC16F527
NOTES:
DS41640A-page 22
Preliminary
 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620763124
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Preliminary
DS41640A-page 23
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DS41640A-page 24
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11/29/11
Preliminary
 2012 Microchip Technology Inc.