10 Amp TO-220AB, N-Channel, VDSS 400

MTP10N40E
Designer’s™ Data Sheet
TMOS E−FET™
High Energy Power FET
N−Channel Enhancement−Mode Silicon
Gate
This advanced high voltage TMOS E−FET is designed to withstand
high energy in the avalanche mode and switch efficiently. This new
high energy device also offers a drain−to−source diode with fast
recovery time. Designed for high voltage, high speed switching
applications such as power supplies, PWM motor controls and other
inductive loads, the avalanche energy capability is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source−to−Drain Diode Designed to Replace External Zener
Transient Suppressor — Absorbs High Energy in the Avalanche
Mode
• Source−to−Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
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TMOS POWER FET
10 AMPERES, 400 VOLTS
RDS(on) = 0.55 W
TO-220AB
CASE 221A−06
Style 5
D
®
G
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
MTP10N40E/D
MTP10N40E
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−Source Voltage
VDSS
400
Vdc
Drain−Gate Voltage (RGS = 1.0 MΩ)
VDGR
400
Vdc
Gate−Source Voltage — Continuous
Gate−Source Voltage — Non−repetitive
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Pulsed
ID
IDM
10
40
Adc
Total Power Dissipation
Derate above 25°C
PD
125
1.0
Watts
W/°C
TJ, Tstg
−65 to 150
°C
WDSR(1)
mJ
WDSR(2)
520
83
13
RθJC
RθJA
1.0
62.5
°C/W
TL
275
°C
Operating and Storage Temperature Range
UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)
Single Pulse Drain−to−Source Avalanche Energy — TJ = 25°C
Single Pulse Drain−to−Source Avalanche Energy — TJ = 100°C
Repetitive Pulse Drain−to−Source Avalanche Energy
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds
(1) VDD = 50 V, ID = 10 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
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MTP10N40E
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
V(BR)DSS
400
—
—
Vdc
Zero Gate Voltage Drain Current
(VDS = 400 V, VGS = 0)
(VDS = 320 V, VGS = 0, TJ = 125°C)
IDSS
—
—
—
—
0.25
1.0
OFF CHARACTERISTICS
mAdc
Gate−Body Leakage Current — Forward (VGSF = 20 Vdc, VDS = 0)
IGSSF
—
—
100
nAdc
Gate−Body Leakage Current — Reverse (VGSR = 20 Vdc, VDS = 0)
IGSSR
—
—
100
nAdc
2.0
1.5
—
—
4.0
3.5
—
0.4
0.55
—
—
—
—
6.0
4.75
gFS
4.0
—
—
mhos
Ciss
—
1570
—
pF
Coss
—
230
—
Crss
—
55
—
td(on)
—
25
—
tr
—
37
—
td(off)
—
75
—
tf
—
31
—
Qg
—
46
63
Qgs
—
10
—
Qgd
—
23
—
VSD
—
—
2.0
Vdc
ton
—
**
—
ns
trr
—
250
—
—
—
3.5
4.5
—
—
—
7.5
—
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
(TJ = 125°C)
VGS(th)
Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 5.0 A)
RDS(on)
Drain−to−Source On−Voltage (VGS = 10 Vdc)
(ID = 5.0 A)
(ID = 2.5 A, TJ = 100°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 5.0 A)
Vdc
Ohms
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS*
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 200 V, ID ≈ 10 A,
RL = 20 Ω, RG = 9.1 Ω,
VGS(on) = 10 V)
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
(VDS = 320 V, ID = 10 A,
VGS = 10 V)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
Forward Turn−On Time
(IS = 10 A, di/dt = 100 A/μs)
Reverse Recovery Time
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Ld
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
Ls
* Pulse Test: Pulse Width = 300 μs, Duty Cycle ≤ 2.0%.
** Limited by circuit inductance.
TYPICAL ELECTRICAL CHARACTERISTICS
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3
nH
nH
20
VGS = 10 V
I D, DRAIN CURRENT (AMPS)
TJ = 25°C
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
MTP10N40E
7V
16
12
6V
8
4
0
5V
0
4
8
12
16
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
20
1.2
1
0.9
0.8
0.7
−50
25
I D, DRAIN CURRENT (AMPS)
VDS = 50 V
20
15
10
TJ = 25°C
100°C
0
0
1
−55°C
2
4
6
3
5
7
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
8
9
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
TJ = 100°C
1
25°C
0.5
−55°C
0
15
20
1
1.1
VGS = 0
ID = 250 μA
1
0.9
0.8
−50
−25
0
25
50
75
100
125
1
Figure 4. Breakdown Voltage Variation
With Temperature
VGS = 10 V
10
125
TJ, JUNCTION TEMPERATURE (°C)
1.5
5
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
1.2
Figure 3. Transfer Characteristics
0
−25
Figure 2. Gate−Threshold Voltage Variation
With Temperature
VBR(DSS), DRAIN−TO−SOURCE BREAKDOWN VOLTAGE
(NORMALIZED)
Figure 1. On−Region Characteristics
5
VDS = VGS
ID = 0.25 mA
1.1
25
3
VGS = 10 V
ID = 5 A
2
1
0
−50
30
−25
0
25
50
75
100
125
ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance versus Drain Current
Figure 6. On−Resistance Variation
With Temperature
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1
MTP10N40E
SAFE OPERATING AREA INFORMATION
45
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 μs
10
I D, DRAIN CURRENT (AMPS)
I D, DRAIN CURRENT (AMPS)
100
100 μs
1 ms
1
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
30
TJ ≤ 150°C
15
dc
0
1
1000
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
50
100
200
300
400
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Switching
Safe Operating Area
The power averaged over a complete switching cycle
must be less than:
FORWARD BIASED SAFE OPERATING AREA
TJ(max) − TC
RθJC
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of
linear systems. The curves are based on a case
temperature of 25°C and a maximum junction temperature
of 150°C. Limitations for repetitive pulses at various case
temperatures can be determined by using the thermal
response curves. Motorola Application Note, AN569,
“Transient Thermal Resistance−General Data and Its Use”
provides detailed instructions.
10000
VDD = 200 V
ID ≈ 10 A
VGS = 10 V
TJ = 25°C
tf
tr
t, TIME (ns)
1000
td(off)
td(on)
100
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is
the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental limits
are the peak current, IDM and the breakdown voltage,
V (BR)DSS . The switching SOA shown in Figure 8 is
applicable for both turn−on and turn−off of the devices for
switching times less than one microsecond.
10
1
10
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
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100
RGS
DUT
MTP10N40E
I D, DRAIN CURRENT (AMPS)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
12
9
6
3
0
−
1
0.7
0.5
0.3
0.2
0.02
VDS
20 V
−
VGS P
(pk)
0.1
0.03
Li
IS
+
0.1
0.07
0.05
IFM
+
0.2
RθJC(t) = r(t) RθJC
RθJC = 1°C/W MAX
VR = 80%APPLY
OF RATED
DS
D CURVES
FOR VPOWER
V
=
V
+
L
⋅
dl
/dt
dsL
f
i
s
PULSE
TRAIN
SHOWN
t1
READ TIME AT t1
t2
TJ(pk)
− TOperating
C = P(pk) RθJC(t)
Figure
13.
Commutating
Safe
Area
DUTY CYCLE, D = t1/t2
0.05
0.02 di/dt ≤ 120 A/μs
0.01
0.01
0.01
0
VR
D = 0.5
Test Circuit
SINGLE PULSE
0.02
0.05
0.1
0.2
100
200
300
400
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.5
1
500
2
5
t, TIME (ms)
10
20
50
V(BR)DSS
Figure 10. Thermal
Response
Figure 12. Commutating Safe Operating Area (CSOA)
100
200
500
Vds(t)
COMMUTATING SAFE OPERATING AREA (CSOA)
IO
15 V
The Commutating Safe Operating Area (CSOA) of Figure
L
12 defines the limits of safe operation
for commutated
source-drain current Vversus re-applied drain voltage
when
C
DS
the source-drain diode has undergone forward
4700bias.
μF The
ID
VR250
forV a given
curve shows the limitations of IFM and peak
commutation speed. It is applicable when waveforms
VDD
similar to those of Figure 11 are present. Full or half-bridge
PWM DC motor controllers are common applications
t
requiring CSOA
data.
The time interval tfrr is Rthe
GS speed of the commutation
50 Ω
cycle. Device stresses increase
with commutation speed,
so t frr is specified with a minimum value. Faster
commutation
speeds
require an appropriate
of IFM,
Figure
14. Unclamped
Inductive derating
Switching
peak VR or both. Ultimately,
t
is
limited
primarily
by
device,
frr Circuit
Test
package, and circuit impedances. Maximum device stress
occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain−to−source voltage that the
device must sustain during commutation; I FM is the
maximum forward source-drain diode current just prior to
the onset of commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has
only a second order effect on CSOA.
Stray inductances, L i in Motorola’s test circuit are
assumed to be practical minimums.
VGS
0
IFM
90%
ID(t)
dlS/dt
IS
trr
10%
VDD
ton
IRM
tP
(TIME)
0.25 It,RM
tfrr
V(BR)DSS
WDSR + 1 LIO2 VDS(pk)
2
V(BR)DSS–VDD
ǒ
Ǔǒ
Ǔ
V
R Inductive Switching
Figure 15. Unclamped
Waveforms
VDS
Vf
VdsL
MAX. CSOA
STRESS AREA
Figure 11. Commutating Waveforms
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MTP10N40E
TJ = 25°C
C, CAPACITANCE (pF)
3000
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
3500
VGS = 0 V
2500
2000
Crss
Ciss
1500
1000
500
0
10
VDS = 0 V
5
Coss
5
0
VGS
10
15
20
16
12
250 V
320 V
8
4
0
25
VDS = 100 V
TJ = 25°C
ID = 10 A
0
20
40
60
QG, TOTAL GATE CHARGE (nC)
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 16. Capacitance Variation
Figure 17. Gate Charge versus
Gate−To−Source Voltage
+18 V
VDD
1 mA
47 k
Vin
10 V
15 V
SAME
DEVICE TYPE
AS DUT
100 k
2N3904
0.1 μF
2N3904
100 k
47 k
100
FERRITE
BEAD
Vin = 15 Vpk; PULSE WIDTH ≤ 100 μs, DUTY CYCLE ≤ 10%
Figure 18. Gate Charge Test Circuit
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DUT
8
MTP10N40E
PACKAGE DIMENSIONS
CASE 221A−06
ISSUE Y
−T−
B
F
T
SEATING
PLANE
C
S
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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