Si9912 Datasheet

End of Life. Last Available Purchase Date is 31-Dec-2014
Si9912
Vishay Siliconix
Half-Bridge MOSFET Driver for Switching Power Supplies
FEATURES
D
D
D
D
D
D
D
D
D
D
APPLICATIONS
4.5- to 5.5-V Operation
Undervoltage Lockout
250-kHz to 1-MHz Switching Frequency
Shutdown Quiescent Current <5 mA
One Input PWM Signal Generates Both Drive
Bootstrapped High-Side Drive
Operates from 4.5- to 30-V Supply
TTL/CMOS Compatible Input Levels
1-A Peak Drive Current
Break-Before-Make Circuit
D
D
D
D
D
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Mobile Computing CPU Core Power Converters
Standard-Synchronous Converters
High Frequency Switching Converters
DESCRIPTION
The Si9912 is a dual MOSFET high-speed driver with
break-before-make. It is designed to operate in high frequency
dc-dc switchmode power supplies. The high-side driver is
bootstrapped to handle the high voltage slew rate associated
with “floating” high-side gate drivers. Each driver is capable of
switching a 3000-pF load with 60-ns propogation delay and
25-ns transition time. The Si9912 comes with an internal
break-before-make feature to prevent shoot-through current in
the external MOSFETs. A shutdown pin is used to enable the
driver. When disabled, the quiescent current of the driver is
less than 5 mA.
The Si9912 is available in both standard and lead (Pb)-free, 8-pin
SOIC packages for operation over the industrial operation range
(−40_C to 85_C).
FUNCTIONAL BLOCK DIAGRAM AND TRUTH TABLE
BOOT
VDD
D1
VDC
Q1
Level Shift
TRUTH TABLE
CBOOT
OUTH
VS SD
Undervoltage
OUTPUT
VS
VDD
SD
OUTL
IN
Q2
IN
VOUTL
VOUTH
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
H
H
L
H
H
L
L
L
L
H
L
H
L
L
H
H
L
L
L
H
H
H
L
H
+
−
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
VBBM
GND
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Si9912
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Limit
VDD
7.0
Input Voltage on IN
VIN
−0.3 to VDD +0.3
Shutdown Pin Voltage
VSD
−0.3 to VDD +0.3
VBOOT
35.0
Low Side Driver Supply Voltage
Bootstrap Voltage
High Side Driver (Bootstrap) Supply Voltage
Unit
V
VBOOT − VS
7.0
Operating Junction Temperature Range
TJ
−40 to 125
Storage Temperature Range
Tstg
−40 to 150
Power Dissipation (Note a and b)
PD
830
mW
Thermal Impedance
qJA
125
°C/W
300
°C
Lead Temperature (soldering 10 Sec)
_C
Notes
a. Device mounted with all leads soldered to P.C. Board
b. Derate 8.3 W/_C above 25_C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Bootstrap Voltage (High-Side Drain Voltage)
Logic Supply
Bootstrap Capacitor
Ambient Temperature
Symbol
Limit
Unit
VBOOT
4.5 to 30
VDD
4.5 to 5.5
CBOOT
100 n to 1 m
F
TA
−40 to 85
_C
V
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Symbol
VDD = 4.5 to 5.5 V
VBOOT = 4.5 to 30 V, TA = −40 to 85_C
Limits
Mina
Typb
Maxa
Unit
Power Supplies
VDD Supply
VDD
IDD Supply
IDD1(en)
SD = H, IN = H, VS = 0 V
1000
IDD Supply
IDD2(en)
SD = H, IN = L, VS = 0 V
500
IDD Supply
IDD3(dis)
SD = L, IN = X, VS = 0 V
5
IDD Supply
IDD4(en)
SD = H, IN = X, VS = 25 V, VBOOT = 30 V
200
IDD Supply
IDD5(dis)
SD = L, IN = X, VS = 25 V, VBOOT = 30 V
IDD(en)
FIN = 300 kHz, SD = High, Driving Si4412DY
9
mA
IDD(dis)
FIN = 300 kHz, SD = Low, Driving Si4412DY
3
mA
IBOOT
VBOOT = 30 V, VS = 25 V, VOUTH = High
IDD Supply
Boot Strap Current
4.5
mA
5
0.9
3
mA
VBBM
1.1
3
V
Input High
VIH
0.7 VDD
VDD + 0.3
Input Low
VIL
−0.3
0.3 VDD
Reference Voltage
Break-Before-Make Reference Voltage
Logic Inputs (SD, IN)
V
Undervoltage Lockout
VDD Undervoltage
VDD Undervoltage Hysteresis
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2
VUVL
VHYST
VDD Rising
3.7
4.3
0.4
V
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
Si9912
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Symbol
VDD = 4.5 to 5.5 V
VBOOT = 4.5 to 30 V, TA = −40 to 85_C
VFD1
Forward Current = 100 mA
Limits
Mina
Typb
Maxa
Unit
0.8
1
V
Bootstrap Diode
Diode Forward Voltage
Output Drive Current
OUTH Source Current
IOUT(H+)
VBOOT − VS = 3.7 V, VOUTH − VS = 2 V
OUTH Sink Current
IOUT(H−)
VBOOT − VS = 3.7 V, VOUTH − VS = 1 V
OUTL Source Current
IOUT(L+)
VDD = 4.5 V, VOUTL = 2 V
OUTL Sink Current
IOUT(L−)
VDD = 4.5 V, VOUTL = 1 V
−0.4
0.4
−0.4
A
0.6
Timing (CLOAD = 3 nF)
OUTL Off Propagation Delay
tpdl(OUTL)
OUTL On Propagation Delay
tpdh(OUTL)
OUTH Off Propagation Delay
tpdl(OUTH)
OUTH On Propagation Delay
tpdh(OUTH)
OUTL Turn On Time
30
VDD = 4.5
45V
20
30
VBOOT − VS = 4.5
45V
tr(OUTL)
20
OUTL = 10 to 90%
25
OUTL Turn Off Time
tf(OUTL)
OUTL = 90 to 10%
25
OUTH Turn On Time
tr(OUTH)
OUTH − VS = 10 to 90%
30
OUTH Turn Off Time
tf(OUTH)
OUTH − VS = 90 to 10%
20
ns
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
TIMING WAVEFORMS
IN
50%
50%
tpdh(OUTL)
tf(OUTL)
90%
OUTL
90%
10%
10%
tr(OUTL)
tpdl(OUTH)
tpdl(OUTL)
OUTH
tf(OUTH)
tr(OUTH)
tpdh(OUTH)
90%
10%
90%
10%
VS
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
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Si9912
Vishay Siliconix
PIN CONFIGURATION
SO-8
OUTH
1
8
VS
GND
2
7
BOOT
IN
3
6
VDD
SD
4
5
OUTL
Top View
PIN DESCRIPTION
Pin Number
Name
Function
1
OUTH
Output drive for upper MOSFET.
2
GND
Ground supply
3
IN
CMOS level input signal. Controls both output drives.
4
SD
Shutdown pin
5
OUTL
6
VDD
7
BOOT
8
VS
Output drive for lower MOSFET.
Input power supply
Floating bootstrap supply for the upper MOSFET
Floating GND for the upper MOSFET. VS is connected to the buck switching node and the source side of the upper MOSFET.
ORDERING INFORMATION
Part Number
Temperature Range
Si9912DY
Si9912DY-T1
Package
Bulk
−40 to 85_C
Si9912DY-T1—E3 (Lead (Pb)-Free)
Tape and Reel
Eval Kit
Temperature Range
Board Type
Si9912DB
−40 to 85_C
Surface Mount
TYPICAL WAVEFORMS
Driver On Switch Delay
VS
CL = Si4412DY
Driver Off Switch Delay
OUTH
OUTH
See Figure 1
OUTL
IN
IN
Si9912 tr, tf, tpd
4
See Figure 1
OUTL
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CL = Si4412DY
VS
Si9912 tr, tf, tpd
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
Si9912
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
IDD Supply Current vs. Frequency
Rise and Fall Time vs. CLOAD
30
50
See Figure 2
40
Rise and Fall times (ns)
See Figure 1
Current (mA)
10
tr(OUTH)
tf(OUTL)
30
tf(OUTH)
20
tr(OUTL)
10
1
0
1
10
100
1000
0.3
1
Frequency (kHz)
VOUT(H+) vs. Supply
5
See Figure 3
0.5 A
4
Output Voltage Drop (V)
Output Voltage Drop (V)
−1
−2
1A
−3
1.5 A
−5
3.0
3
1.5 A
2
1A
1
See Figure 3
3.5
2A
4.0
4.5
5.0
5.5
0
3.0
6.0
0.5 A
3.5
4.0
Supply Voltage (V)
0.5 A
6.0
See Figure 3
2.0
1A
1.5 A
−3
−4
2A
−6
4.0
5.5
VOUT(L−) vs. Supply
−2
−5
5.0
2.5
Output Voltage Drop (V)
Output Voltage Drop (V)
−1
4.5
Supply Voltage (V)
VOUT(L+) vs. Supply
0
10
VOUT(H−) vs. Supply
0
−4
3
Load Capacitance (nF)
5.0
Supply Voltage (V)
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
1.5 A
1.0
1A
0.5
See Figure 3
4.5
2A
1.5
5.5
6.0
0.0
4.0
0.5 A
4.5
5.0
5.5
6.0
Supply Voltage (V)
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Si9912
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
VOUT(H+) vs. Temperature
VOUT(H−) vs. Temperature
0
5
See Figure 3
0.5 A
−2
4
Output Voltage Drop (V)
Output Voltage Drop (V)
−1
1A
−3
See Figure 3
−4
−5
−50
3
2A
1.5 A
2
1A
1
−25
0
25
50
75
0
−50
100
0.5 A
−25
0
Temperature (_C)
VOUT(L+) vs. Temperature
0
−1
75
100
75
100
VOUT(L−) vs. Temperature
See Figure 3
1A
Output Voltage Drop (V)
Output Voltage Drop (V)
50
2.0
0.5 A
−2
1.5 A
−3
−4
1.5
1.0
2A
1.5 A
1A
0.5
0.5 A
2A
−5
−50
25
Temperature (_C)
−25
0
See Figure 3
25
50
75
100
Temperature (_C)
0.0
−50
−25
0
25
50
Temperature (_C)
THEORY OF OPERATION
Break-Before-Make Function
Under Voltage Lockout Function
The Si9912 has an internal break-before-make function to
ensure that both high-side and low-side MOSFETs are not
turned on at the same time. The high-side drive (OUTH) will not
turn on until the low-side gate drive voltage (measured at the
OUTL pin) is less than VBBM, thus ensuring that the low-side
MOSFET is turned off. The low-side drive (OUTL) will not turn
on until the voltage at the MOSFET half-bridge output
(measured at the VS pin) is less than VBBM, thus ensuring that
the high-side MOSFET is turned off.
The Si9912 has an internal under-voltage lockout feature to
prevent driving the MOSFET gates when the supply voltage (at
VDD) is less than the under-voltage lockout specification
(VUVL). This prevents the output MOSFETs from being turned
on without sufficient gate voltage to ensure they are fully on.
There is hysteresis included in this feature to prevent lockout
from cycling on and off.
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Document Number: 71311
S-40134—Rev. B, 16-Feb-04
Si9912
Vishay Siliconix
Bootstrap Supply Operation
(see Functional Block Diagram)
Layout Considerations
There are a few critical layout considerations for these parts.
Firstly, the IC must be decoupled as closely as possible to the
power pins. Secondly the IC should be placed physically close
to the high- and low-side MOSFETs it is driving. The major
consideration is that the MOSFET gates must be charged or
discharged in a few nanoseconds, and the peak current to do
this is of the order of 1 A. This current must flow from the
decoupling and bootstrap capacitors to the IC, and from the
output driver pin to the MOSFET gate, returning from the
MOSFET source to the IC. The aim of the layout is to reduce
the parasitic inductance of these current paths as much as
possible. This is accomplished by making these traces as
short as possible, and also running trace and its current return
path adjacent to each other.
The power to drive the high-side MOSFET (Q2) gate comes
from the bootstrap capacitor (CBOOT). This capacitor charges
through D1 during the time when the low-side MOSFET is on
(VS is at GND potential), and then provides the necessary
charge to turn on the high-side MOSFET. CBOOT should be
sized to be greater than ten times the high-side MOSFET gate
capacitance, and large enough to supply the bootstrap current
(IBOOT) during the high-side on time, without significant voltage
droop.
Shutdown (SD)
(shutdown input, active low)
When this pin is high, the IC operates normally. When this pin
is low, both high- and low-side MOSFETs are turned off .
APPLICATIONS
5
6
7
8
+VDC
Q1
4
Enable
3
4
OUTH
GND
VS
BOOT
IN
SD
VDD
OUTL
7
6
L1
1
2
3
8
C1
0.1 mF
15 mH
5
6
7
8
PWM IN
Si4412
5
C2
0.1 mF
GND
1 mF
C5
RLOAD
Q2
4
Si9912
Si4412
1
2
3
2
15 mF
C4 +
+5 V
U1
1
0.1 mF
C3
GND
GND
FIGURE 1.
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
Typical Applications Schematic Circuit Used to Obtain Typical Rising and Falling Switching Waveforms
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Si9912
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+5 V
+5 V
U1
U1
1
2
PWM IN
3
4
OUTH
GND
VS
BOOT
IN
SD
VDD
OUTL
Si9912
8
7
1
CLOAD
C9
6
2
3
Input
4
5
CLOAD
C8
FIGURE 2. Capacitive Load Test Circuit Used to Measure
Rise and Fall Times vs. Capacitance
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8
GND
BOOT
VDD
IN
SD
OUTL
Si9912
8
ISRC
7
6
5
ISRC
C2
0.1 mF
C2
0.1 mF
GND
VS
OUTH
GND
FIGURE 3. Load Test Schematic Circuit Used to
Measure Driver Output Impedance
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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Revision: 02-Oct-12
1
Document Number: 91000