AN-913: Isolating I2C Interfaces (Rev. 0) PDF

AN-913
APPLICATION NOTE
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Isolating I2C Interfaces
by Ronn Kliger
the other. In addition, at any instance, a device can be a master
or a slave. A master is a device that initiates a data transfer by
addressing another device while a slave is a device that is
addressed by a master.
INTRODUCTION
2
The Inter-Integrated Circuit (I C®) bus is a two-wire bidirectional
bus used for low speed, short-distance communication between
integrated circuits. Developed by Philips1 in the early 1980s for
use amongst ICs on a single board, I2C today is increasingly
being used in multiboard applications as new bus extensions
and control devices help overcome the original 400 pF maximum allowable load capacitance.
The I2C bus allows for more than two devices to be connected
to it and for multiple master/slave relationships to exist. The
operation of the bus under such circumstances is defined by
an arbitration procedure defined in the I2C standard.
Note that the master/slave designations are independent of
whether a device is a transmitter or a receiver. For example, in
a sequence in which a master initiates a data transfer from a
slave, it is first a transmitter (as it addresses the slave), then
a receiver (as it receives the data from the slave), and then a
transmitter again (as it terminates the transfer). In a similar
fashion, the slave is first a receiver, then a transmitter, and
then a receiver.
Often, in multicard applications such as blade servers or
digitally-controlled power converters, it is desired that
each interface be isolated to allow for trouble-free card
insertion/removal or for safety considerations. However,
isolating I2C interfaces is complicated by the bidirectional
nature of the I2C bus. This characteristic is not compatible
with the unidirectional behavior of optocouplers.
This application note provides a brief overview of the I2C bus
(focusing on its physical layer), discusses the challenges in
isolating I2C interfaces, and describes iCoupler® solutions for
isolating I2C interfaces.
The I2C bus operates on the principle of open-drain/opencollector wire-AND functionality (see Figure 1). All devices
connected to the bus must be at a logic high state in order for
the bus to be at a logic high state. When this situation exists
for both the SDA and SCL lines, the bus is considered to be free
for a device to initiate a data transfer. Both SDA and SCL are
bidirectional lines to support the ability of devices to take on
both transmitter and receiver roles.
I2C OVERVIEW
The I2C interface is defined by The I2C-Bus Specification,
Version 2.1, January 2000 (NXP Semiconductors). This
interface consists of two wires: serial data (SDA) and serial
clock (SCL). These wires convey information to and from
devices connected to the bus, each of which is identified by
a unique address. At any instance, a device can be a transmitter
or a receiver although some devices may operate only as one or
1
In 2006, Philips spun out their semiconductor operations (including their I2C
portfolio) to create a new independent company called NXP Semiconductors.
+VDD
SDA (SERIAL DATA LINE)
PULL-UP
RESISTORS
RP
RP
SCL (SERIAL CLOCK LINE)
SCLK
SCLKN1
OUT
DATAN1
OUT
SCLKN2
OUT
DATAN2
OUT
SCLK
IN
DATA
IN
SCLK
IN
DATA
IN
DEVICE 1
DEVICE 2
Figure 1. I2C Bus
Rev. 0 | Page 1 of 8
06751-001
SCLK
AN-913
TABLE OF CONTENTS
Introduction ...................................................................................... 1
iCoupler I2C Isolation Solutions......................................................4
I2C Overview ..................................................................................... 1
ADuM1250/ADuM1251 Usage Notes............................................5
2
The Challenge of Isolated I C Interfaces ....................................... 3
Rev. 0 | Page 2 of 8
AN-913
Table 1. I2C Logic Levels
Parameter
Logic Low Input Voltage
Symbol
VIL
Min
−0.5
Max
0.3 × VDD
Unit
V
Logic High Input Voltage
Logic Low Output Voltage (for 3 mA sink current)
VDD > 2 V
VDD < 2 V
VIH
0.7 × VDD
VDD + 0.5
V
VOL1
VOL3
0
0
0.4
0.2 × VDD
V
V
SDA PULLED LOW
VIA OPTOCOUPLER IC1
BUS GLITCH
SDA
OPTOCOUPLER IC1
5V
D1
R4
3.3kΩ
OCTOCOUPLER
IC1
SDA
Figure 2. An Optocoupler-Based I2C interface
06751-002
ON
An additional problem with a circuit such as this is that it
results in undesirable bus glitches (see Figure 3).
•
A high-to-low transition occurs at SDA. In this situation,
IC1 is turned on by the current flowing through R2. This,
in turn, pulls Node 1 low and consequently pulls SDA'
low via D2.
•
SDA' is taken low. Nothing changes except D2 no longer
conducts.
•
SDA is released and goes high as there is nothing holding it
low. The LED in IC1 turns off. After a delay, the transistors
of IC1 turn off. Node 1 goes high and turns on the LED in
IC2. After another delay, the transistors of IC2 turn on and
SDA is pulled low to the desired state.
SLAVE
D2
OFF
Figure 3. Optocoupler-based I2C Interface Waveforms
SDA
OCTOCOUPLER
IC2
OFF
06751-003
OPTOCOUPLER IC2
NODE1
MASTER
ON
SDA
The bidirectional nature of the I2C interface presents special
challenges in implementing isolation in a manner that avoids
bus glitches or lock-up. Figure 2 shows a circuit based on
optocoupler technology. Since optocouplers are inherently
unidirectional devices, each bidirectional I2C line must be
broken out into two unidirectional lines to support communication through the optocouplers. In Figure 2, only the SDA
lines are shown for simplicity. Isolating a complete I2C interface
requires four optocouplers. The resulting increase in cost, board
space, and complexity diminishes the inherent value (that of
providing a simple, low cost, 2-wire interface) of I2C.
R3
2.2kΩ
OFF
NODE1
THE CHALLENGE OF ISOLATED I2C INTERFACES
R2
2.2kΩ
SDA RELEASED
BY MASTER
SDA RECOVERS
TO LOW STATE
AFER OPTOCOUPLER
PROPAGATION DELAYS
SDA TAKEN
LOW BY MASTER
An important aspect of the I2C interface is that SDA logic
transitions can only occur while the SCL clock signal is low.
Also, the start and stop signals that bound the transmittal of
data are SDA logic transitions that occur while the SCL clock
signal is high. Therefore, it is important that the SCL signal be
stable in both its low and high states to avoid communication
problems on the bus.
R1
3.3kΩ
Standard mode does not allow for VDD < 2 V
SDA TAKEN
LOW BY SLAVE
Data transfer can occur at up to either 100 kbps (standard mode),
400 kbps (fast mode), 1 Mbps (fast mode plus), or 3.4 Mbps
(high speed mode). There is no limit to the number of devices
that can be connected to the bus—as long as a 400 pF bus limit
is not exceeded. The logic levels for I2C are shown in Table 1.
5V
Comments
Standard mode allows for a fixed-input
specification (−0.5 V min, +1.5 V max)
Notice that SDA is high for the duration it takes for IC1 to turn
off and IC2 to turn on. This is an unwanted glitch on the bus in
which SDA is high while SDA' is trying to bring the bus low.
Rev. 0 | Page 3 of 8
AN-913
iCOUPLER I2C ISOLATION SOLUTIONS
In contrast, Analog Devices, Inc.’s ADuM1250/ADuM1251
iCoupler products are single-component I2C isolators free of
any glitch or lock-up issues and without the size, cost, and
complexity of optocoupler-based solutions.
The ADuM1250 supports interfaces with bidirectional data
and clock lines while the ADuM1251 supports interfaces with
a bidirectional data line and a unidirectional clock line. Both
products carry UL approved 2.5 kV rms isolation ratings and
are offered in an 8-lead SOIC package.
VDD1
1
DECODE
ENCODE
8
VDD2
SDA1
2
ENCODE
DECODE
7
SDA2
SCL1
3
DECODE
ENCODE
6
SCL2
GND1
4
ENCODE
DECODE
5
GND2
06751-004
A solution offered by NXP Semiconductors in the P82B96 data
sheet consists of their dual bidirectional bus buffer and four
optocouplers. This solution is free of glitches or lock-up but it
still requires multiple components bringing board space and
cost penalties that undermine the benefits of the I2C interface.
VDD1
1
DECODE
ENCODE
8
VDD2
SDA1
2
ENCODE
DECODE
7
SDA2
SCL1
3
ENCODE
DECODE
6
SCL2
GND1
4
5
GND2
Figure 5. ADuM1251 Functional Block Diagram
Rev. 0 | Page 4 of 8
06751-005
Figure 4. ADuM1250 Functional Block Diagram
AN-913
SIDE 1
An isolated I2C interface using the ADuM1250/ADuM1251 is
extremely simple (see Figure 6). It consists of just one component
and a bypass capacitor for each supply. The pull-up resistors are
those associated with any I2C interface. Guidelines for the selection of resistor values are provided within the I2C specification.
SCL1
GND1
ADuM1250
8
2
7
3
6
4
5
SDA
0.4V
SDA
0.9V
0.7V
VDD2
SDA2
0.3VDD
I2C BUS
SCL2
GND2
06751-007
SDA1
1
Figure 7. ADuM1250/ADuM1251 Side 1 Logic Voltage Levels
06751-006
VDD1
SIDE 2
Figure 6. An Isolated I2C Interface Using the ADuM1250
The ADuM1250/ADuM1251 isolators support two bidirectional communication lines by internally configuring four
unidirectional isolation channels in the wire-AND opendrain configuration of the I2C interface. Special logic voltage
levels at Side 1 of the devices are used to avoid bus glitches or
latch-up. This prevents a logic low asserted by the Side 1
receiver from being interpreted as being input low by the Side 1
transmitter, thereby breaking the loop between Side 1 and Side 2
(see Figure 7).
The logic low output from the Side 1 receiver is 0.9 V (maximum). This is low enough to be read as an input low by other
standard CMOS devices’ Side 1, but high enough to avoid being
interpreted as a logic low by the Side 1 transmitter, which has its
logic low threshold at 0.7 V (maximum). Therefore, an output
low from the Side 1 receiver is properly detected by devices
connected to the bus, but is not fed back to Side 2 by the
Side 1 transmitter. This prevents the bus problems commonly
associated with optocoupler solutions while still supporting
clock frequencies up to 1 MHz. Because the feedback loop is
broken at Side 1, there is no need to do the same at Side 2. On
that side, standard logic voltage levels are used.
ADuM1250/ADuM1251 USAGE NOTES
The recommended method of using the ADuM1250/ADuM1251
is to connect Side 2 to the I2C bus. This side of these isolators is
fully compliant with the I2C specification for standard and fast
mode operation. Side 1 (while fully compatible with I2C devices) is
not strictly compliant to the I2C specification due to the special
logic low voltage levels used to prevent bus latch-up.
Rev. 0 | Page 5 of 8
AN-913
GND2
VDD1A
1
SDA1A
ADuM1250
VDD2
8
2
7
3
6
4
5
SDA2A
DEVICE A
SCL1A
GND1A
VDD1B
1
SDA1B
ADuM1250
SCL2A
8
2
7
3
6
4
5
SDA2B
I2C BUS
DEVICE B
SCL1B
GND1B
VDD1N
1
SDA1N
ADuM1250
SCL2
8
2
7
3
6
4
5
SDA2N
DEVICE N
GND1N
SCL2N
06751-008
SCL1N
Figure 8. Isolating Multiple Devices on an I2C Bus
Figure 8 shows an I2C bus with multiple devices connected
via ADuM1250 isolators. Each device has its own power
supply and is connect to Side 1 of an ADuM1250. Side 2
of each ADuM1250 is connected to the bus and powered
from a common VDD2 supply.
In any I2C interface, care should be taken to make sure that
design is compliant with the timing requirements in the I2C
specification. Specifically, the propagation delays of the
isolation channels as well as the propagation delay mismatches
between isolation channels need to be considered to make sure
the resultant interface meets I2C requirements.
There are two timing parameters, which isolators in an I2C
interface can affect:
•
SDA setup time (250 ns for fast mode)
•
SDA hold time (300 ns for fast mode)
Rev. 0 | Page 6 of 8
AN-913
MASTER
SLAVE
tSETUP
tSETUP – Δt tHOLD – Δt
(250ns MIN) (300ns MIN)
tHOLD
SDA
ISOLATOR
SDA
CHANNEL-TO-CHANNEL
PROPAGATION DELAY MISMATCH, Δt
SCL
06751-009
SCL
Figure 9. Impact of Isolator Channel Mismatch in Master/Write Mode
SLAVE
tSETUP
tRESPONSE
ISOLATOR
SDA
(RECEIVED BY
MASTER)
SDA
(TRANSMITTED BY
MASTER)
PROPAGATION DELAY, tSDA
SCL
(TRANSMITTED BY
MASTER)
SCL
(RECEIVED BY
MASTER)
PROPAGATION DELAY, tSCL
tLOW
t0
t0 + tSCL
06751-010
MASTER
t0 + tSCL+ tRESPONSE + tSDA
Figure 10. Impact of Isolator Round-Trip Propagation Delay in Slave/Write Mode
Two situations need to be considered when analyzing the
impact of I2C isolators. The first is when the master device is
writing to the slave (see Figure 9). In this situation, the channelto-channel mismatch of the isolator can decrease the setup or
hold time of the SDA signal as received by the slave. To protect
against this possibility, the master setup and hold times should
be increased by at least the amount of channel mismatch to
ensure that required setup and hold times are met at the receiving
slave device.
The second scenario is that when the slave device is writing to
the master (see Figure 10). In this situation, the master provides
the SCL clock to the slave, which in turn writes the SDA signal
to the master. The master pulls the SCL low and must receive
the SDA edge from the slave before the SCL returns to a logic
high state (less the required setup time). This means that the
round-trip propagation delay through the isolator plus the
slave's response time must be less than that of the SCL logic
low duration less its setup time:
t0 + tSCL + tRESPONSE < TLOW − TSETUP
This, in turn, places a constraint on the response time of
the slave.
tRESPONSE < TLOW − tSETUP −t0 − tSCL
In both scenarios, an ideal I2C isolator has short propagation
delays and tight, channel-to-channel matching. In this regard
(in addition to their size, cost, and simplicity benefits), the
ADuM1250/ADuM1251 also offer superior performance
characteristics because they impact the timing of I2C interfaces to a lesser degree.
Rev. 0 | Page 7 of 8
AN-913
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN06751-0-6/07(0)
Rev. 0 | Page 8 of 8
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