Altera AN-712 (AD9625-Stratix 5)

Altera JESD204B IP Core and ADI AD9625 Hardware
Checkout Report
2016.06.13
AN-712
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The Altera® JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).
The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC
(analog-to-digital converter) devices.
This report highlights the interoperability of the JESD204B IP core with the AD9625 converter evaluation
module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout
methodology and test results.
Related Information
• JESD204B IP Core User Guide
• ADI AD9625 Datasheet
Hardware Requirements
The hardware checkout test requires the following hardware and software tools:
•
•
•
•
•
Stratix V Advanced Systems Development Kit with 15 V power adaptor
Arria 10 GX FPGA Development Kit
ADI AD9625 EVM
Mini-USB cable
Clock source card capable of generating device clock frequencies
Hardware Setup for Stratix V Advanced Systems Development Kit
A Stratix V Advanced Systems Development Kit is used with the ADI AD9625 daughter card module
attached to the FMC connector of the development board.
• The AD9625 EVM derives power through the development kit FMC connector.
• The ADC device clock is supplied by external clock source card through the SMA connector on the
AD9625 EVM.
• The AD9625 divides the sampling clock by four and supplies this divided clock through its DIVCLK
pins to the FPGA.
• For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
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Hardware Setup for Stratix V Advanced Systems Development Kit
Figure 1: Hardware Setup
Transceiver Lanes
2.5 GHz
External Clock
Device Clock
rx_dev_sync_n FPGA 1
sysref
SPI
Power
FPGA 2
Stratix V Advanced Systems Development Kit
ADI AD9625 EVM
Figure 2: System-Level Block Diagram
mgmt_clk jesd204b_ed_top.sv
Stratix V FPGA #1
rx_serial_data[7:0]
(6.25 Gbps) L0 - L7
Qsys System
JTAG to
Avalon Master
Bridge
Avalon-MM
Slave
Translator
sclk, ss_n[0], miso, mosi
ADC
4 Wire
Conversion
Circuit
link_clk (156.25 MHz)
Avalon-MM
Interface
Signals
global_rst_n
PIO
AD9625 EVM
AD9625
jesd204b_ed.sv
Design Example
SignalTap II
FMC
3 Wire
Sysref
Generator
device_clk (625 MHz)
JESD204B
MegaCore IP
L = 8, M = 1, F =1
sysref_out
(19.5313 MHz)
SPI Slave
Clock and
Sync
rx_dev_sync_n
SMA
2.5 GHz
The system-level block diagram shows how the different modules connect in this design. In the setup
depicted above, LMF=811 and the data rate of transceiver lanes is 6.25 Gbps. An external clock source
card provides 2.5 GHz sampling clock to the AD9625 device and the ADC supplies 625 MHz FPGA
device clock through its DIVCLK pin.
Related Information
JESD204B IP Core and AD9625 Configurations on page 11
For more information about other configurations.
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Hardware Setup for Arria 10 GX FPGA Development Kit
3
Hardware Setup for Arria 10 GX FPGA Development Kit
Figure 3: Hardware Setup
An Arria 10 FPGA Development Kit is used with the ADI AD9625 daughter card module attached to the
FMC connector on the development board.
• The AD9625 EVM derives power from the Arria 10 FMC connector.
• Both the FPGA and ADC device clock must be sourced from the same clock source card with two
different frequencies, one for the FPGA and one for ADC.
• An internal on-board oscillator present on the AD9625 EVM provides 2.5 GHz device clock to the
ADC.
• The AD9625 divides the sampling clock by four (625 MHz) and supplies this divided clock through its
DIVCLK pins to the FPGA.
• For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.
Arria 10 GX FPGA Development Kit
FPGA SYNC_N SYSREF
Device Clock
ADI AD9625 EVM
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Hardware Checkout Methodology
Figure 4: System Diagram
The system-level diagram shows how the different modules connect in this design.
In this setup, where LMF=811, the data rate of the transceiver lanes is 6.25 Gbps. An on-board internal
clock oscillator on the EVM board provides 2.5 GHz sampling clock to the ADC and divides the 2.5 GHz
device clock by four to provide the clock (625 MHz) to the FPGA.
mgmt_clk
100 MHz
FMC
Arria 10 GX FPGA Development Kit
jesd204b_ed_top.sv
jesd204b_ed.sv
rx_serial_data[7:0]
(6.25 Gbps)
SignalTap II
Avalon-MM
Slave
Translator
Design Example
Avalon-MM
Interface
signals
global_rst_n
PIO
AD9625
L0 – L7
Qsys System
JTAG to Avalon
Master Bridge
AD9625 Evaluation Module
JESD204B
IP Core
(Duplex)
L=8, M=1, F=1
sclk, ss_n[0], 4 Wire Conversion
miso, mosi
Circuit
link_clk
(156.25 MHz)
PLL
frame_clk
(156.25 MHz)
device_clk
(62.5 MHz)
Sysref
(19.5313 MHz)
Sysref
Generator
3 Wire
SPI
Slave
Oscillator
device_clk
2.5 GHz
ADC
Sysref (19.5313 MHz)
rx_dev_sync_n
Hardware Checkout Methodology
The following section describes the test objectives, procedure, and the passing criteria. The test covers the
following areas:
•
•
•
•
Receiver data link layer
Receiver transport layer
Descrambling
Deterministic latency (Subclass 1)
Receiver Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initial frame and lane
synchronization.
On link start-up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5)
characters. The SignalTap II Logic Analyzer tool monitors the receiver data link layer operation.
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Code Group Synchronization (CGS)
5
Code Group Synchronization (CGS)
Table 1: CGS Test Cases
Test Case
Objective
Description
Passing Criteria
CGS.1
Check whether
sync request is
deasserted after
correct reception
of four
successive /K/
characters.
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• /K/ character or K28.5 (0xBC)
is observed at each octet of the
jesd204_rx_pcs_data bus.
• jesd204_rx_pcs_data[(L*32)• The jesd204_rx_pcs_data_
1:0]
valid signal is asserted to
• jesd204_rx_pcs_data_valid[Lindicate data from the PCS is
1:0]
valid.
• jesd204_rx_pcs_kchar_
•
The jesd204_rx_pcs_kchar_
data[(L*4)-1:0] (1)
data signal is asserted
whenever
control characters
The following signals in <ip_variant_
like
/K/,
/R/,
/Q/ or /A/
name>.v are tapped:
characters are observed.
• rx_dev_sync_n
• The rx_dev_sync_n signal is
• jesd204_rx_int
de-asserted after correct
reception of at least four
The rxlink_clk is used as the
successive /K/ characters.
SignalTap II sampling clock.
• The jesd204_rx_int signal is
Each lane is represented by 32-bit data
deasserted if there is no error.
bus in jesd204_rx_pcs_data signal.
The 32-bit data bus is divided into 4
octets.
CGS.2
Check full CGS at
the receiver after
correct reception
of another four
8B/10B
characters.
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• jesd204_rx_pcs_
•
errdetect[(L*4)-1:0]
jesd204_rx_pcs_disperr[(L*4)
-1:0] (1)
The jesd204_rx_pcs_errdetect,
jesd204_rx_pcs_disperr, and
jesd204_rx_int signals should
not be asserted during CGS phase.
The following signal in <ip_variant_
name>.v are tapped:
• jesd204_rx_int
The rxlink_clk is used as the
SignalTap II sampling clock.
(1)
L indicates the number of lanes.
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Initial Frame and Lane Synchronization
Initial Frame and Lane Synchronization
Table 2: Initial Frame and Lane Synchronization Test Cases
Test Case
Objective
Description
ILA.1
Check whether
the initial frame
synchronization
state machine
enters FS_DATA
state upon
receiving non /K/
characters.
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
(2)
Passing Criteria
• /R/ character or K28.0 (0x1C) is
observed after /K/ character at
the jesd204_rx_pcs_data bus.
• jesd204_rx_pcs_data[(L*32)• The jesd204_rx_pcs_data_
1:0]
valid signal must be asserted
• jesd204_rx_pcs_data_valid[Lto indicate that data from the
1:0]
PCS is valid.
• jesd204_rx_pcs_kchar_
• The rx_dev_sync_n and
data[(L*4)-1:0] (2)
jesd204_rx_int signals are
deasserted.
The following signals in <ip_variant_
name>.v are tapped:
• Each multiframe in ILAS phase
ends with /A/ character or
• rx_dev_sync_n
K28.3 (0x7C).
• jesd204_rx_int
• The jesd204_rx_pcs_kchar_
data signal is asserted
The rxlink_clk is used as the
whenever control characters
SignalTap II sampling clock.
like /K/, /R/, /Q/ or /A/
Each lane is represented by 32-bit data
characters are observed.
bus in jesd204_rx_pcs_data. The
32-bit data bus is divided into 4 octets.
L indicates the number of lanes.
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Receiver Transport Layer
Test Case
ILA.2
Objective
Check the
JESD204B
configuration
parameters from
ADC in second
multiframe.
Description
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• jesd204_rx_pcs_data[(L*32)1:0]
• jesd204_rx_pcs_data_valid[L1:0] (2)
The following signal in <ip_variant_
name>.v is tapped:
• jesd204_rx_int
7
Passing Criteria
• /R/ character is followed by /Q/
character or K28.4 (0x9C) at
the beginning of second
multiframe.
• The jesd204_rx_int signal is
deasserted if there is no error.
• Octets 0–13 read from these
registers match with the
JESD204B parameters in each
test setup.
The rxlink_clk is used as the
SignalTap II sampling clock.
The system console accesses the
following registers:
•
•
•
•
ilas_octet0
ilas_octet1
ilas_octet2
ilas_octet3
The content of 14 configuration octets
in the second multiframe is stored in
these 32-bit registers—ilas_octet0,
ilas_octet1, ilas_octet2, and ilas_
octet3.
ILA.3
Check the lane
alignment
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• jesd204_rx_pcs_data[(L*32)•
1:0]
jesd204_rx_pcs_data_valid[L1:0] (2)
The following signals in <ip_variant_
name>.v are tapped:
• rx_somf[3:0]
• dev_lane_aligned
• jesd204_rx_int
• The dev_lane_aligned signal
is asserted upon the last /A/
character of the ILAS is
received, which is followed by
the first data octet.
• The rx_somf signal marks the
start of multiframe in user data
phase.
• The jesd204_rx_int signal is
deasserted if there is no error.
The rxlink_clk is used as the
SignalTap II sampling clock.
Receiver Transport Layer
The ADC is configured to output ramp or PRBS-23 test data pattern to check the data integrity of the
payload data stream through the RX JESD204B IP core and transport layer. The ADC is also set to operate
with the same configuration as in the JESD204B IP core. The ramp or PRBS checker in the FPGA fabric
checks the data integrity for one minute.
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Descrambling
Figure 5: Data Integrity Check Using Ramp or PRBS Checker
This figure shows the conceptual test setup for data integrity checking.
ADC
Ramp/PRBS
Generator
TX Transport
Layer
TX PHY
and Link Layer
RX Transport
Layer
RX JESD204B
IP Core
PHY and Link Layer
FPGA
Ramp/PRBS
Checker
The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.
Table 3: Transport Layer Test Case
Test Case
Objective
TL.1
Check the
transport layer
mapping using
ramp test pattern
or PRBS-23 test
pattern.
Description
The following signal in altera_
jesd204_transport_rx_top.sv are
tapped:
• jesd204_rx_data_valid
Passing Criteria
• The jesd204_rx_data_valid
signal is asserted.
• The data_error and jesd204_
rx_int signals are deasserted.
The following signals in jesd204b_
ed.sv are tapped:
• data_error
• jesd204_rx_int
The rxframe_clk is used as the
SignalTap II sampling clock.
The data_error signal indicates a
pass or fail for the ramp checker.
Related Information
JESD204B IP Core and AD9625 Configurations on page 11
For more information about the test data pattern settings.
Descrambling
The ramp or PRBS checker at the RX transport layer checks the data integrity of the descrambler. The
SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.
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Deterministic Latency (Subclass 1)
Table 4: Descrambler Test Case
Test Case
Objective
Description
SCR.1
Check the
functionality of
the descrambler
using ramp test or
PRBS-23 test
pattern.
Passing Criteria
Enable scrambler at the ADC and
descrambler at the RX JESD204B IP
core.
• The jesd204_rx_data_valid
signal is asserted.
• The data_error and jesd204_
rx_int signals are deasserted.
The signals that are tapped in this test
case are similar to test case TL.1
Deterministic Latency (Subclass 1)
Figure below shows the block diagram of deterministic latency test setup. A SYSREF generator provides a
periodic SYSREF pulse for both the AD9625 and JESD204B IP core. The SYSREF generator is running in
link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The
SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.
Figure 6: Deterministic Latency Test Setup Block Diagram for Stratix V FPGA
mgmt_clk jesd204b_ed_top.sv
Stratix V FPGA #1
SignalTap II
Qsys System
JTAG to
Avalon Master
Bridge
Avalon-MM
Slave
Translator
Deterministic
Latency
Measurement
AD9625 EVM
AD9625
rx_serial_data[7:0]
(6.25 Gbps) L0 - L7
sclk, ss_n[0], miso, mosi
ADC
4 Wire
Conversion
Circuit
link_clk (156.25 MHz)
Avalon-MM
Interface
Signals
3 Wire
Sysref
Generator
device_clk (625 MHz)
global_rst_n
PIO
jesd204b_ed.sv
Design Example
FMC
JESD204B
MegaCore IP
L = 8, M = 1, F =1
sysref_out
(19.5313 MHz)
SPI Slave
Clock and
Sync
rx_dev_sync_n
SMA
2.5 GHz
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Deterministic Latency (Subclass 1)
Figure 7: Deterministic Latency Test Setup Block Diagram for Arria 10 GX FPGA
mgmt_clk
100 MHz
Arria 10 GX FPGA Development Kit
jesd204b_ed_top.sv
FMC
jesd204b_ed.sv
rx_serial_data[7:0]
(6.25 Gbps)
SignalTap II
Qsys System
JTAG to Avalon
Master Bridge
Avalon-MM
Slave
Translator
PIO
AD9625
L0 – L7
Deterministic
Latency
Measurement
sclk, ss_n[0], 4 Wire Conversion
miso, mosi
Circuit
link_clk
(156.25 MHz)
PLL
frame_clk
(156.25 MHz)
device_clk
(62.5 MHz)
Design Example
Avalon-MM
Interface
signals
global_rst_n
AD9625 Evaluation Module
JESD204B
IP Core
(Duplex)
L=8, M=1, F=1
Sysref
(19.5313 MHz)
3 Wire
SPI
Slave
Oscillator
device_clk
2.5 GHz
Sysref
Generator
ADC
Sysref (19.5313 MHz)
rx_dev_sync_n
Figure 8: Deterministic Latency Measurement Timing Diagram
Link Clock
State
ILAS
USER_DATA
SYNC~
RX Valid
Link Clock Count
1
2
3
n-1
n
With the setup above, three test cases were defined to prove deterministic latency. By default, the
JESD204B IP core does a single SYSREF detection. The SYSREF single-shot mode is enabled on the
AD9625 for this deterministic latency measurement.
Table 5: Deterministic Latency Test Cases
Test Case
DL.1
Altera Corporation
Objective
Check the FPGA
SYSREF single
detection.
Description
Check that the FPGA detects the first
rising edge of SYSREF pulse.
Passing Criteria
The value of sysref_singledet
identifier should be zero.
Read the status of sysref_singledet
(bit[2]) identifier in syncn_sysref_ctrl
register at address 0x54.
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JESD204B IP Core and AD9625 Configurations
Test Case
DL.2
Objective
Check the
SYSREF capture.
Description
Passing Criteria
Check that the FPGA and ADC
capture SYSREF correctly and restart
the LMF counter for every reset and
power cycle.
Read the value of rbd_count
(bit[10:3]) identifier in rx_status0
register at address 0x80.
DL.3
Check the latency
from start of
SYNC~ deasser‐
tion to first user
data output.
11
Check that the latency is fixed for
every FPGA and ADC reset and
power cycle.
Record the number of link clocks
count from the start of SYNC~
deassertion to the first user data
output, which is the assertion of
jesd204_rx_link_valid signal. The
deterministic latency measurement
block in Figure 6 has a counter to
measure the link clock count.
If the SYSREF is captured correctly
and the LMF counter restarts, for
every reset and power cycle, the
rbd_count value should only vary
by two integers due to the word
alignment.
Consistent latency from the start
of SYNC~ deassertion to the
assertion of jesd204_rx_link_
valid signal.
JESD204B IP Core and AD9625 Configurations
The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the
AD9625 device. The transceiver data rate, sampling clock frequency, and other JESD204B parameters
comply with the AD9625 operating conditions.
The hardware checkout test implements the JESD204B IP core with the following parameter configura‐
tion.
Stratix V FPGA
Table 6: Parameter Settings for Stratix V FPGA
Configuration
(3)
Setting
LMF
118
214
412
611
811
HD
0
0
0
1
1
S
4
4
4
4
4
N
16 (3)
12
12
12
12
This 16-bit test pattern is an output from the JESD204X test pattern block in the AD9625 device.
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JESD204B IP Core and AD9625 Configurations
Configuration
Setting
N’
16
16
16
12
16
CS
0
0
0
0
0
CF
0
0
0
0
0
ADC Device Clock (MHz)
2500
625
1250
2500
2500
ADC Sampling Clock (MHz) 156.25
625
1250
2500
2500
FPGA Device Clock (MHz) (4) 625
156.25
312.5
625
625
FPGA Management Clock
(MHz)
100
100
100
100
FPGA Frame Clock (MHz) (5) 78.125
156.25
312.5
156.25
156.25
FPGA Link Clock (MHz) (5)
156.25
156.25
156.25
156.25
156.25
Character Replacement
Enabled
Enabled
Enabled
Enabled
Enabled
Data Pattern
Ramp
Ramp
Ramp
Ramp
Ramp
100
Arria 10 GX FPGA
Table 7: Parameter Settings for Arria 10 GX FPGA
Configuration
(4)
(5)
(6)
Setting
LMF
118
214
412
611
811
HD
0
0
0
1
1
S
4
4
4
4
4
N
16 (6)
16 (6)
16 (6)
12
12
N’
16
16
16
12
16
CS
0
0
0
0
0
CF
0
0
0
0
0
The device clock is used to clock the transceiver.
The frame clock and link clock is derived from the device clock using an internal PLL.
This 16-bit test pattern is an output from the JESD204X test pattern block in the AD9625 device.
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Test Results
Configuration
13
Setting
ADC Sampling Clock (MHz) 2500
2500
2500
2500
2500
FPGA Device Clock (MHz) (7) 625
625
625
625
625
FPGA Management Clock
(MHz)
100
100
100
100
FPGA Frame Clock (MHz) (5) 78.125
156.25
312.5
156.25
156.25
FPGA Link Clock (MHz) (5)
156.25
156.25
156.25
156.25
156.25
Lane Rate (Gbps)
6.25
6.25
6.25
6.25
6.25
Character Replacement
Enabled
Enabled
Enabled
Enabled
Enabled
Data Pattern (8)
PRBS-23
PRBS-23
PRBS-23
PRBS-23
PRBS-23
Ramp
Ramp
Ramp
Ramp
Ramp
100
Test Results
The following table contains the possible results and their definition.
Table 8: Results Definition
Result
Definition
PASS
The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments
The DUT was observed to exhibit conformant behavior. However, an additional
explanation of the situation is included, such as due to time limitations only a
portion of the testing was performed.
FAIL
The DUT was observed to exhibit non-conformant behavior.
Warning
The DUT was observed to exhibit behavior that is not recommended.
Refer to comments
From the observations, a valid pass or fail could not be determined. An
additional explanation of the situation is included.
Stratix V FPGA
The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1
with different values of L, M, F, K, subclass, data rate, sampling clock and link clock frequencies.
(7)
(8)
The device clock is used to clock the transceiver.
The ramp pattern is for deterministic latency measurement test cases DL.1, DL.2, DL.3 only.
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Test Results
Table 9: Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 (Stratix V FPGA)
Set
number
L
M
F
Subclass
SCR
K
Data rate
ADC
(Mbps) Sampling
Clock
(MHz)
FPGA
Link
Clock
(MHz)
Result
1
1
1
8
0
0
16
6250
156.25
156.25
Pass
2
1
1
8
0
1
16
6250
156.25
156.25
Pass
3
1
1
8
0
0
32
6250
156.25
156.25
Pass
4
1
1
8
0
1
32
6250
156.25
156.25
Pass
5
1
1
8
1
0
16
6250
156.25
156.25
Pass
6
1
1
8
1
1
16
6250
156.25
156.25
Pass
7
1
1
8
1
0
32
6250
156.25
156.25
Pass
8
1
1
8
1
1
32
6250
156.25
156.25
Pass
9
2
1
4
0
0
16
6250
625
156.25
Pass
10
2
1
4
0
1
16
6250
625
156.25
Pass
11
2
1
4
0
0
32
6250
625
156.25
Pass
12
2
1
4
0
1
32
6250
625
156.25
Pass
13
2
1
4
1
0
16
6250
625
156.25
Pass
14
2
1
4
1
1
16
6250
625
156.25
Pass
15
2
1
4
1
0
32
6250
625
156.25
Pass
16
2
1
4
1
1
32
6250
625
156.25
Pass
17
4
1
2
0
0
16
6250
1250
156.25
Pass
18
4
1
2
0
1
16
6250
1250
156.25
Pass
19
4
1
2
0
0
32
6250
1250
156.25
Pass
20
4
1
2
0
1
32
6250
1250
156.25
Pass
21
4
1
2
1
0
16
6250
1250
156.25
Pass
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Test Results
Set
number
L
M
F
Subclass
SCR
K
Data rate
ADC
(Mbps) Sampling
Clock
(MHz)
FPGA
Link
Clock
(MHz)
Result
22
4
1
2
1
1
16
6250
1250
156.25
Pass
23
4
1
2
1
0
32
6250
1250
156.25
Pass
24
4
1
2
1
1
32
6250
1250
156.25
Pass
25
6
1
1
0
0
20
6250
2500
156.25
Pass with
comments
26
6
1
1
0
1
20
6250
2500
156.25
Pass with
comments
27
6
1
1
0
0
32
6250
2500
156.25
Pass with
comments
28
6
1
1
0
1
32
6250
2500
156.25
Pass with
comments
29
6
1
1
1
0
20
6250
2500
156.25
Pass with
comments
30
6
1
1
1
1
20
6250
2500
156.25
Pass with
comments
31
6
1
1
1
0
32
6250
2500
156.25
Pass with
comments
32
6
1
1
1
1
32
6250
2500
156.25
Pass with
comments
33
8
1
1
0
0
20
6250
2500
156.25
Pass
34
8
1
1
0
1
20
6250
2500
156.25
Pass
35
8
1
1
0
0
32
6250
2500
156.25
Pass
36
8
1
1
0
1
32
6250
2500
156.25
Pass
37
8
1
1
1
0
20
6250
2500
156.25
Pass
38
8
1
1
1
1
20
6250
2500
156.25
Pass
39
8
1
1
1
0
32
6250
2500
156.25
Pass
40
8
1
1
1
1
32
6250
2500
156.25
Pass
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Test Results
Table 10: Results For Deterministic Latency Test (Stratix V FPGA)
Test
L
M
F
Subclass
K
Data rate
(Mbps)
ADC
Sampling
Clock
(MHz)
FPGA Link
Clock
(MHz)
Result
DL.1
1
1
8
1
32
6250
312.5
156.25
Pass
DL.2
1
1
8
1
32
6250
312.5
156.25
Pass
DL.3
1
1
8
1
32
6250
312.5
156.25
Pass with
comments.
Link clock
observed = 323
DL.1
2
1
4
1
32
6250
625
156.25
Pass
DL.2
2
1
4
1
32
6250
625
156.25
Pass
DL.3
2
1
4
1
32
6250
625
156.25
Pass with
comments.
Link clock
observed = 163
with FPGA
LMFC offset =
0x1C at IP core
register 0x54.
DL.1
4
1
2
1
32
6250
1250
156.25
Pass
DL.2
4
1
2
1
32
6250
1250
156.25
Pass
DL.3
4
1
2
1
32
6250
1250
156.25
Pass with
comments.
Link clock
observed = 99100 with ADC
LMFC offset
register set to
0x14.
DL.1
6
1
1
1
32
6250
2500
156.25
Pass
DL.2
6
1
1
1
32
6250
2500
156.25
Pass
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Test Results
Test
L
DL.3
6
M
1
F
1
Subclass
1
K
32
Data rate
(Mbps)
6250
ADC
Sampling
Clock
(MHz)
FPGA Link
Clock
(MHz)
2500
156.25
17
Result
Pass with
comments.
Link clock
observed = 67
with ADC
LMFC offset
register set to
0x02.
DL.1
8
1
1
1
32
6250
2500
156.25
Pass
DL.2
8
1
1
1
32
6250
2500
156.25
Pass
DL.3
8
1
1
1
32
6250
2500
156.25
Pass with
comments.
Link clock
observed = 67
with ADC
LMFC offset
register set to
0x02.
The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~
to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test
case). The clock count measures the first user data output latency.
Figure 9: Deterministic Latency Measurement Ramp Test Pattern Diagram (Stratix V FPGA)
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Test Results
Arria 10 GX FPGA
The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1
with different values of L, M, F, K, subclass, data rate, sampling clock,link clock, and SYSREF frequencies.
Table 11: Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 (Arria 10 GX FPGA)
Test
L
M
F
Subclass
SCR
K
Data
Rate
(Gbps)
Sampling
Clock
(GHz)
Link
Clock
(MHz)
Result
1
1
1
8
1
0
16
6.25
2.5
156.25
PASS
2
1
1
8
1
1
16
6.25
2.5
156.25
PASS
3
1
1
8
1
0
32
6.25
2.5
156.25
PASS
4
1
1
8
1
1
32
6.25
2.5
156.25
PASS
5
2
1
4
1
0
16
6.25
2.5
156.25
PASS
6
2
1
4
1
1
16
6.25
2.5
156.25
PASS
7
2
1
4
1
0
32
6.25
2.5
156.25
PASS
8
2
1
4
1
1
32
6.25
2.5
156.25
PASS
9
4
1
2
1
0
16
6.25
2.5
156.25
PASS
10
4
1
2
1
1
16
6.25
2.5
156.25
PASS
11
4
1
2
1
0
32
6.25
2.5
156.25
PASS
12
4
1
2
1
1
32
6.25
2.5
156.25
PASS
13
6
1
1
1
0
20
6.25
2.5
156.25
PASS with
comments
14
6
1
1
1
1
20
6.25
2.5
156.25
PASS with
comments
15
6
1
1
1
0
32
6.25
2.5
156.25
PASS with
comments
16
6
1
1
1
1
32
6.25
2.5
156.25
PASS with
comments
17
8
1
1
1
0
20
6.25
2.5
156.25
PASS
18
8
1
1
1
1
20
6.25
2.5
156.25
PASS
19
8
1
1
1
0
32
6.25
2.5
156.25
PASS
20
8
1
1
1
1
32
6.25
2.5
156.25
PASS
The following table lists the results for test cases DL.1, DL.2, DL.3 with different values of L, M, F, K,
subclass, data rate, sampling clock, link clock, and SYSREF frequencies
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Test Results
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Table 12: Results for Deterministic Latency Test (Arria 10 GX FPGA)
Test
L
M
F
Subclass
K
Data Rate
(Gbps)
Sampling Link Clock
Clock
(MHz)
(GHz)
Result
DL.1
1
1
8
1
32
6.25
2.5
156.25
PASS
DL.2
1
1
8
1
32
6.25
2.5
156.25
PASS
DL.3
1
1
8
1
32
6.25
2.5
156.25
PASS with
comments.
Link clock
observed = 319
with RBD offset
register set to 5.
DL.1
2
1
4
1
32
6.25
2.5
156.25
PASS
DL.2
2
1
4
1
32
6.25
2.5
156.25
PASS
DL.3
2
1
4
1
32
6.25
2.5
156.25
PASS with
comments.
Link clock
observed = 187
with RBD offset
register set to 9.
DL.1
4
1
2
1
32
6.25
2.5
156.25
PASS
DL.2
4
1
2
1
32
6.25
2.5
156.25
PASS
DL.3
4
1
2
1
32
6.25
2.5
156.25
PASS with
comments.
Link clock
observed = 99
with ADC
LMFC offset
register set to 0.
DL.1
6
1
1
1
32
6.25
2.5
156.25
PASS
DL.2
6
1
1
1
32
6.25
2.5
156.25
PASS
DL.3
6
1
1
1
32
6.25
2.5
156.25
PASS with
comments.
Link clock
observed = 67
with ADC
LMFC offset
register set to 0.
DL.1
8
1
1
1
32
6.25
2.5
156.25
PASS
DL.2
8
1
1
1
32
6.25
2.5
156.25
PASS
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Test Results
Test
L
DL.3
8
M
1
F
1
Subclass
1
K
32
Data Rate
(Gbps)
Sampling Link Clock
Clock
(MHz)
(GHz)
6.25
2.5
156.25
Result
PASS with
comments.
Link clock
observed = 67
with ADC
LMFC offset
register set to 0.
The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~
to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test
case). The clock count measures the first user data output latency.
Figure 10: Deterministic Latency Measurement Ramp Test Pattern Diagram (Arria 10 GX FPGA)
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Test Result Comments
21
Test Result Comments
In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until
user data phase. Except for LMF=611 test cases, no data integrity issue is observed by the ramp checker
and PRBS checker. For LMF=611 test cases, no data integrity check is performed because Altera transport
layer does not support N'=12 configuration.
In deterministic measurement test case DL.3, the link clock count in the FPGA depends on board layout
and the LMFC offset value set in the ADC register. The link clock count varies by only one link clock
when the FPGA and ADC are reset or power cycled. The link clock variation in the deterministic latency
measurement is caused by word alignment, where control characters fall into the next cycle of data some
time after realignment. This makes the duration of ILAS phase longer by one link clock some time after
reset or power cycle. For LMF=214 and LMF=118 test cases, the LMFC or RBD offset value is tuned at the
FPGA IP core instead of at the ADC for consistent latency.
AN 712 Document Revision History
Date
Version
Changes
June 2016
2016.06.13
• Added Arria 10 FPGA hardware setup and test results.
• Updated the Deterministic Latency Measurement Ramp
Test Pattern Diagram for Stratix V FPGA.
• Split the test results section to Stratix V and Arria 10 GX
FPGA.
October 2014
2014.10.13
Initial release.
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