AN-1334
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Impact of Adding a Neutral Attenuation Network in a 3P4W Wye System
by Hariharan Mani
INTRODUCTION
In a 3-phase 4-wire (3P4W) wye configuration, there are three
phase wires and one neutral wire. Each phase voltage is measured
with respect to the neutral. The phase voltages are typically
220 V rms or 110 V rms in magnitude. Each phase voltage is
120° phase-shifted with respect to the other phase voltages. A
common practice is to use attenuation networks on each of the
3-phase wires to step down the 220 V/110 V signals into signals
small enough to enter the ADExxxx metering IC. (ADExxxx refers
to Analog Devices, Inc., 3-phase AFEs such as the ADE7854,
ADE7858, ADE7868, ADE7878, ADE7854A, ADE7858A,
ADE7868A, ADE7878A, ADE7880, ADE7758, ADE7754,
ADE7762, and ADE7752A.) The neutral wire is typically used
as the ground reference for the ADExxxx IC. Figure 1 shows the
typical 3P4W wye configuration voltage attenuation network
setup.
However, in certain cases, the neutral cannot be treated as the
ground reference. In such situations, an attenuation network is
added to the neutral, thus forming a large resistance between
neutral and ADExxxx ground, as shown in Figure 3. This
application note analyses the performance impact of adding
a neutral attenuation network in a 3P4W wye system.
Rev. 0 | Page 1 of 11
AN-1334
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Standard 3P4W Configuration ........................................................6
Revision History ............................................................................... 2
3P4W Configuration with Neutral Series Resistance ...................7
Description of the Issue ................................................................... 3
Lab Tests .............................................................................................9
Voltage Channel ADCs .................................................................... 4
Simulation Test: Special Case........................................................ 10
Simulation Test Bench ..................................................................... 5
Conclusion....................................................................................... 11
Voltage Magnitude Imbalance ........................................................ 6
REVISION HISTORY
10/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 11
Application Note
AN-1334
PHASE A
DESCRIPTION OF THE ISSUE
PHASE B
Figure 1 shows the standard 3P4W wye configuration setup.
For simplicity, only the voltage channel connection is shown.
There are attenuation networks connected to all three phase
wires, and the neutral is considered to be the ground of the
ADExxxx IC.
PHASE C
NEUTRAL
ISOLATED POWER
SUPPLY
PHASE A
PHASE B
SENSING
AND
FILTERING
PHASE C
ADExxxx
IC
MCU
NEUTRAL
VAP
A
B
COMMUNICATION
MODULE
VBP
C
Figure 2. 3P4W Metering System Isolation Requirement
If these limitations cannot be overcome by means of any system
level changes, the meter designers typically install an attenuation
network on the neutral wire as well, which keeps the ground of
the system at a different potential than the neutral wire.
VCP
N
VAN
VBN
220V
220V
120°
VN
AGND
DGND
0°
–120°
12687-001
VCN 220V
The attenuation network resistors on the neutral wire create
a large resistance between the neutral and the ground of the
ADExxxx IC. This resistance is referred to as the neutral series
resistance. Figure 3 shows the voltage connection in the system
with the addition of neutral series resistance.
PHASE A
Figure 1. Standard 3P4W Wye Configuration Voltage Connection
PHASE B
In certain cases, the neutral cannot be treated as the ground
reference. There can be multiple reasons for this requirement.
Two of the main reasons are as follows:
1.
2.
12687-012
ADExxxx
Certain meters undergo a safety test during which one of
the phase wires is swapped with the neutral. If Phase A is
swapped with neutral, in Figure 1, the system ground
reference is now 220 V. The system components, such as
the power supply unit, are often not capable of handling
this situation. Therefore, treating neutral as the ground
reference is not a suitable option.
The communication module in a metering system is isolated
from the high voltages for safety purposes. There are different
types of isolation requirements based on application, meter
design, standards, and so on. If only one level of functional
isolation is required, it can be achieved by isolating the ground
of the system from neutral alone. It is assumed that current
sensors with isolation (such as current transformers) are used
in the system. Figure 2 shows a typical metering system. The
power supply is also isolated from neutral, in this case. There
are also cases where two levels of isolation are required in the
system: safety (galvanic) isolation and functional isolation.
The safety isolation is typically achieved by implementing a
sufficient amount of data and power isolation between the
MCU and communication module. The functional isolation is
achieved by separating neutral from the ground of the MCU.
PHASE C
ADExxxx
NEUTRAL
VAP
A
B
VBP
C
VCP
VN
N
AGND
VCN 220V
VAN
VBN
220V
220V
DGND
NEUTRAL ATTENUATION
NETWORK
120°
0°
–120°
12687-002
ATTENUATION NETWORK
ON THREE PHASE WIRES
Figure 3. 3P4W Wye Configuration Voltage Connection with
Attenuation Network on Neutral
Another common alternative to remain isolated from the high
voltages is the use of voltage transformers; however, voltage
transformers are less preferable because they make the meter
design expensive and large.
Rev. 0 | Page 3 of 11
AN-1334
Application Note
VOLTAGE CHANNEL ADCs
PHASE A
333kΩ
Voltage signals are typically single-ended signals in metering
applications. Therefore, the three voltage channel analog-to-digital
converters (ADCs) within an ADExxxx IC have a common input
terminal (the VN pin), as shown in Figure 4.
333kΩ
333kΩ
1kΩ
VA
VAP
2.2nF
PHASE B
333kΩ
1kΩ
VB
ADExxxx
PHASE C
333kΩ
VAP
333kΩ
333kΩ
VBP
VBP–VN
NEUTRAL
333kΩ
VBP
2.2nF
333kΩ
1kΩ
VC
VAP–VN
333kΩ
VCP
2.2nF
333kΩ
1kΩ
ADExxxx
VN
2.2nF
AGND
DGND
12687-005
333kΩ
VCP
12687-003
VCP–VN
VN
Figure 6. 3P4W Wye System: Neutral Series Resistance
Figure 4. Voltage Channel ADC Configuration in 3-Phase ADExxxx IC
In Figure 4, VAP, VBP, VCP, and VN represent the ADExxxx IC
input pins. The VAP, VBP, and VCP pins accept the steppeddown voltage signals from the phase wires, as shown in Figure 5
and Figure 6. The AGND and DGND pins of the ADExxxx IC,
shown in Figure 5 and Figure 6, are tied to the ground potential of
the system. If neutral is connected to ground, the VN pin of the
ADExxxx IC also stays at that potential, as shown in Figure 5. If
neutral is connected to an attenuation network, the stepped-down
version of the neutral signal is available at the VN pin, as shown in
Figure 6.
To obtain valid results from the ADExxxx IC, it is important to
understand the signal limitations at its input pins. The conditions
to be met, with respect to the input voltage pins, are as follows:
1.
2.
3.
PHASE A
333kΩ
333kΩ
333kΩ
1kΩ
VA
VAP
2.2nF
The third condition in the previous list is the most relevant
condition with respect to the use of neutral series resistance in
a 3P4W system. In a configuration like the one shown in Figure 5,
VN and AGND are at the same potential. However, when a
neutral series resistance exists in the system, as shown in Figure 6,
VN is not always equal to AGND. Any imbalance in the phase
voltages causes the VN − AGND potential difference to be
nonzero, thus leading to measurement errors.
PHASE B
333kΩ
333kΩ
1kΩ
VB
PHASE C
333kΩ
VC
VBP
2.2nF
ADExxxx
333kΩ
333kΩ
VCP
1kΩ
2.2nF
1kΩ
2.2nF
VN
NEUTRAL
AGND
DGND
12687-004
333kΩ
The ac potential difference between VAP/VBP/VCP and VN
must be no greater than ±500 mV peak (353.55 mV rms).
The ac potential difference between VAP/VBP/VCP and
AGND must be no greater than ±500 mV peak
(353.55 mV rms).
Similarly, the ac potential difference between VN and
AGND must be no greater than ±500 mV peak
(353.55 mV rms). Although VN can be as large as
±500 mV peak (353.55 mV rms) with respect to AGND,
it is desirable to keep VN equal to AGND, because VN is
common to all three voltage channel ADCs (see Figure 4).
Figure 5. 3P4W Wye System: Neutral Connected to Ground
Rev. 0 | Page 4 of 11
Application Note
AN-1334
SIMULATION TEST BENCH
12687-006
To understand the impact of having a series resistance on the
neutral, a simulation test bench was set up using the ADIsimPE
software. The simulation test bench, corresponding to Figure 5,
was set up as shown in Figure 7. The input impedance at the
voltage channel input pins of the ADExxxx IC was also taken
into consideration, as shown by the use of components R9 to
R12 and C5 to C8. The ADE7880 IC is taken as an example,
and its minimum input impedance is used for all simulations.
VA, VB, and VC in Figure 7 are the Phase A, Phase B, and
Phase C voltages, respectively. The voltage input pins of the
ADExxxx IC, VAP, VBP, VCP, and VN, are denoted as VAP_pin,
VBP_pin, VCP_pin, and VN_pin, respectively. The ground of
the ADExxxx IC is denoted as AGND_pin. The scopes that
measure the VAP − VN, VBP − VN, and VCP − VN potential
differences are denoted as VAN, VBN, and VCN, respectively.
The VAG, VBG, VCG, and VNG scopes measure the voltage
signals on the VAP, VBP, VCP, and VN pins, respectively, with
respect to ground.
Figure 7. Simulation Test Bench: Standard 3P4W Wye Setup
Rev. 0 | Page 5 of 11
AN-1334
Application Note
VOLTAGE MAGNITUDE IMBALANCE
The total magnitude imbalance is calculated as follows:
All three phase voltages, VA, VB, and VC, typically have the same
magnitude and are exactly 120° phase-shifted with respect to each
other (see Figure 8). In such a situation, the voltages are said to be
balanced, and their vector sum is equal to zero. However, in reality,
the loads are not balanced perfectly, thus causing imbalance in the
phase voltages. The voltage imbalance can be due to difference
in magnitude or phase or both. Voltage magnitude imbalance
occurs when the magnitude of the three phase voltages are not
equal to each other. Voltage phase imbalance occurs when the
phase voltages are not exactly 120° phase-shifted with respect
to each other. In this application note, only voltage magnitude
imbalance is considered.
VB
120°
120°
Total Magnitude Imbalance = 55 + 55 V
Total Magnitude Imbalance = 110 V
These two quantities are used hereafter in this application note
when referring to the amount of voltage magnitude imbalance
in the system.
STANDARD 3P4W CONFIGURATION
The standard 3P4W voltage channel configuration shown in
Figure 5 was simulated, and the amplitude and phase of the voltage
signals at the VAP, VBP, VCP, and VN pins were measured with
respect to AGND. The amplitude and phase of the VAP, VBP, and
VCP signals with respect to VN were also noted.
Each of the attenuation networks on the 3-phase wires is
comprised of three 333 kΩ resistors and one 1 kΩ resistor. This
arrangement, as shown in Figure 5, provides 1000:1 attenuation to
the phase voltages. The three phase voltages provided were
VC
12687-007
120°
VA
Total Magnitude Imbalance = |220 − 220| + |165 − 220| +
|275 − 220| V
|VA| = 220 V; ∠VA = 0°
Figure 8. Phasor Diagram Showing Three Phase Voltages
There are several definitions available for voltage imbalance.
For the purposes of this application note, two terms are defined:
% magnitude imbalance and total magnitude imbalance.
The % magnitude imbalance is defined as the absolute maximum
deviation from the average rms voltage as a percentage of the
average rms voltage.
% Magnitude Imbalance =
{
Max V MAX − V AVG , V MIN − V AVG
V AVG
|VB| = 220 V; ∠VB = −120°
|VC| = 220 V; ∠VC = +120°
These phase voltages are equal in magnitude and are 120° phaseshifted from the other voltages, which shows that the system is
balanced. The common node of the three voltage sources VA, VB,
and VC in Figure 5 represents the neutral wire in the 3P4W system.
The voltage signals at the input pins of the ADExxxx IC were
}× 100%
|VAP − VN| = 214.6 mV rms; ∠(VAP − VN) = 0°
|VBP − VN| = 214.6 mV rms; ∠(VBP − VN) = −120°
|VCP − VN| = 214.6 mV rms; ∠(VCP − VN) = +120°
where:
VMAX is the maximum magnitude of the three phase voltage rms
values VA, VB, and VC.
VMIN is the minimum magnitude of the three phase voltage rms
values VA, VB and VC.
VAVG is the average magnitude of the three phase voltage rms
values VA, VB and VC.
The signals at the input pins with respect to AGND potential were
|VAP − AGND| = 214.6mV rms; ∠(VAP − AGND) = 0°
|VBP − AGND| = 214.6mV rms; ∠(VBP − AGND) = −120°
|VCP − AGND| = 214.6 mV rms; ∠(VCP − AGND) = +120°
|VN − AGND| = 0 V; ∠(VN − AGND) = 0°
The total magnitude imbalance is defined as the sum of all
absolute deviations from the average rms voltage, in volts.
Total Magnitude Imbalance = |VA − VAVG| + |VB − VAVG| +
|VC − VAVG| V
For example, if |VA| = 220 V, |VB| = 165 V, and |VC| = 275 V,
the % magnitude imbalance is calculated as follows:
% Magnitude Imbalance =
{
Max 275 − 220 , 165 − 220
220
}× 100%
% Magnitude Imbalance = (55/220) × 100%
% Magnitude Imbalance = 25%
Rev. 0 | Page 6 of 11
Application Note
AN-1334
3P4W CONFIGURATION WITH NEUTRAL SERIES
RESISTANCE
These results mean that the ADExxxx IC measures the voltage
signals to be
The simulation test bench was modified to include the attenuation
network on the neutral wire of the system, as shown in Figure 6.
The same balanced phase voltage inputs provided for the standard
3P4W case were provided for this setup as well. The observed
voltage signals, VAP, VBP, and VCP with respect to VN and VAP,
VBP, VCP, and VN with respect to AGND, were the same as the
standard 3P4W case. This result shows that the addition of the
neutral series resistance has no notable impact on the system
performance when the system is balanced. To understand the
impact of neutral series resistance in an unbalanced system, the
following conditions were simulated:
Phase B and Phase C disconnected (floating)
Phase B and Phase C tied to neutral
|VA| = 220 V, |VB| = 240 V, |VC| = 240 V
|VA| = 220 V, |VB| = 20 V, |VC| = 20 V
Case 1: Phase B and Phase C Disconnected
When Phase B and Phase C were disconnected or floating, the
simulation test bench was similar to the one shown in Figure 9.
PHASE A
333kΩ
333kΩ
333kΩ
1kΩ
VA
333kΩ
333kΩ
VAP
2.2nF
333kΩ
1kΩ
333kΩ
When only Phase A was present, as shown in Case 1: Phase B
and Phase C Disconnected, and Phase B and Phase C were tied
to neutral instead of floating, most of the error observed in the
measurements of Phase B and Phase C were eliminated. Figure 10
shows the setup diagram.
1kΩ
333kΩ
333kΩ
VCP
2.2nF
333kΩ
NEUTRAL
1kΩ
VN
2.2nF
AGND
DGND
333kΩ
12687-008
333kΩ
To avoid getting invalid results on disconnected phases, monitor
the phase angle of the voltages every time a measurement is taken
to ensure that all the phase voltages are 120° phase-shifted with
respect to each other. In this case, the Phase B and Phase C voltage
signals were in-phase with the Phase A voltage signal, therefore
indicating that the voltage related measurements from Phase B
and Phase C must be discarded.
Case 2: Phase B and Phase C Tied to Neutral
VBP
2.2nF
ADExxxx
333kΩ
When only the Phase A voltage exists, the voltages present on the
VAP and VN pins are differential, antiphase signals. Because of
the configuration, a −0.2% gain error is observed in the Phase A
voltage measurement. Because the VN pin is common to all phase
voltages, the signal on the VN pin affects the Phase B and Phase C
voltage measurements of the ADExxxx IC. In this case, VN is not
equal to AGND, due to which the signal present on the VN pin
is phase-shifted by 180° and appears on the Phase B and Phase C
voltage measurements. In this case, the Phase B and Phase C
voltages computed by the ADExxxx IC contain large errors
because the signal on the VN pin consists of half of the voltage
signal of Phase A.
333kΩ
333kΩ
1kΩ
VA
333kΩ
333kΩ
VAP
2.2nF
333kΩ
VBP
Figure 9. Phase B and Phase C Disconnected, Case 1
1kΩ
2.2nF
ADExxxx
The voltage signal applied on Phase A was
333kΩ
|VA| = 220 V; ∠VA = 0°
333kΩ
333kΩ
1kΩ
The voltage signals at the input pins of the ADExxxx IC were
333kΩ
|VAP − VN| = 214.2 mV rms; ∠(VAP − VN) = 0°
333kΩ
VCP
2.2nF
333kΩ
1kΩ
|VBP − VN| = 106.9 mV rms; ∠(VBP − VN) = 0°
VN
2.2nF
AGND
|VCP − VN| = 106.9 mV rms; ∠(VCP − VN) = 0°
The signals at the input pins with respect to AGND potential were
|VAP − AGND| = 107.3 mV rms; ∠(VAP − AGND) = 0°
|VBP − AGND| = 0 V; ∠(VBP − AGND) = 0°
DGND
12687-009
1.
2.
3.
4.
Phase A voltage: 219.6 V, ∠0° (−0.2% gain error)
Phase B voltage: 109.8 V, ∠0° (expected: 0 V)
Phase C voltage: 109.8 V, ∠0° (expected: 0 V)
Figure 10. Phase B and Phase C Tied to Neutral, Case 2
The voltage signal applied on Phase A was
|VA| = 220 V; ∠VA = 0°
|VCP − AGND| = 0 V; ∠(VCP − AGND) = 0°
|VN − AGND| = 107.3 mV rms; ∠(VN − AGND) = 180°
The voltage signals at the input pins of the ADExxxx IC were
|VAP − VN| = 214.3 mV rms; ∠(VAP − VN) = 0°
|VBP − VN| = 0.21 mV rms; ∠(VBP − VN) = 180°
|VCP − VN| = 0.21 mV rms; ∠(VCP − VN) = 180°
Rev. 0 | Page 7 of 11
AN-1334
Application Note
The signals at the input pins with respect to AGND potential were
|VAP − AGND| = 160.9 mV rms; ∠(VAP − AGND) = 0°
|VBP − AGND| = 53.6 mV rms; ∠(VBP − AGND) = 180°
|VCP − AGND| = 53.6 mV rms; ∠(VCP − AGND) = 180°
|VN − AGND| = 53.4 mV rms; ∠(VN − AGND) = 180°
These results mean that the ADExxxx IC measures the voltage
signals to be
Phase A voltage: 219.8 V, ∠0°(−0.1% gain error)
Phase B voltage: 0.22 V, ∠180° (expected: 0 V)
Phase C voltage: 0.22 V, ∠180° (expected: 0 V)
These results mean that the ADExxxx IC measures the voltage
signals to be
Phase A voltage: 220 V, ∠0° (no error)
Phase B voltage: 240 V, ∠−119.9° (+0.1° phase error)
Phase C voltage: 240 V, ∠+120.1° (+0.1° phase error)
When an imbalance such as this was simulated, no notable gain
error was observed on the Phase A, Phase B, and Phase C
measurements; however, a minor phase error of 0.1° was
observed in the Phase B and Phase C voltages.
Case 4: |VA| = 220 V, |VB| = 20 V, |VC| = 20 V
Because the signals on Phase B, Phase C, and neutral have similar
signal path in this configuration, the Phase B and Phase C voltage
signals at the input pins of the ADExxxx IC were observed to be
closer to reality. Instead of observing half of the Phase A voltage
signal on Phase B and Phase C, like in the previous case, the
Phase B and Phase C voltage measurements in this configuration
represented a very small signal, that is, ~(VAP − VN)/1000. The
voltage signals on Phase B and Phase C were 180° out of phase with
the Phase A voltage. Because the Phase B and C voltages are not
120° phase-shifted in comparison to the Phase A voltage, the
phase angle of the Phase B and Phase C voltages can be used to
indicate that these phase voltages have been tied to neutral, in
the application. The gain error in the Phase A measurement was
−0.1% in this case.
In Case 4, a larger voltage magnitude imbalance was considered.
The applied voltage signals were
|VA| = 220 V; ∠VA = 0°
|VB| = 20 V; ∠VB = −120°
|VC| = 20 V; ∠VC = +120°
In this case, a 91% voltage magnitude imbalance was considered
with a total magnitude imbalance of 400 V. Although this amount
of imbalance is impractical, this case was simulated to understand
the impact of a large voltage magnitude imbalance in the system.
The simulation test bench was set up based on the configuration
shown in Figure 6.
The voltage signals at the input pins of the ADExxxx IC were
|VAP − VN| = 214.4 mV rms; ∠(VAP − VN) = 0°
Case 3: |VA| = 220 V, |VB| = 240 V, |VC| = 240 V
|VBP − VN| = 19.6 mV rms; ∠(VBP − VN) = −120.6°
In Case 3, instead of removing the phase voltages completely,
voltage magnitude imbalance was simulated by applying voltage
signals of different amplitudes to VB and VC compared to VA.
In this case, the applied voltage signals were
|VCP − VN| = 19.6 mV rms; ∠(VCP − VN) = +120.6°
The signals at the input pins with respect to AGND potential were
|VAP − AGND| = 165.8 mV rms; ∠(VAP − AGND) = 0°
|VA| = 220 V; ∠VA = 0°
|VBP − AGND| = 60.9 mV rms; ∠(VBP − AGND) = −164°
|VB| = 240 V; ∠VB = −120°
|VCP − AGND| = 60.9 mV rms; ∠(VCP − AGND) = +164°
|VC| = 240 V; ∠VC = +120°
|VN − AGND| = 48.6 mV rms; ∠(VN − AGND) = 180°
This condition represents a 9% voltage magnitude imbalance
with a total magnitude imbalance of 40 V. The simulation test
bench was set up based on the configuration shown in Figure 6.
The voltage signals at the input pins of the ADExxxx IC were
|VAP − VN| = 214.6 mV rms; ∠(VAP − VN) = 0°
These results mean that the ADExxxx IC measures the voltage
signals to be
|VBP − VN| = 234.1 mV rms; ∠(VBP − VN) = −119.9°
|VCP − VN| = 234.1 mV rms; ∠(VCP − VN) = +120.1°
The signals at the input pins with respect to AGND potential were
|VAP − AGND| = 219.5 mV rms; ∠(VAP − AGND) = 0°
|VBP − AGND| = 231.7 mV rms; ∠(VBP − AGND) = −119°
Phase A voltage: 219.8 V, ∠0° (−0.1% gain error)
Phase B voltage: 20.1 V, ∠−120.6° (+0.5% gain error;
−0.6° phase error)
Phase C voltage: 20.1 V, ∠+120.6° (+0.5% gain error;
+0.6° phase error)
When a large voltage magnitude imbalance such as this existed in
the system, the gain error observed on the Phase B and Phase C
voltages due to the configuration was 0.5%. These measurements
also had a phase error of 0.6°. The Phase A voltage measurement
had a gain error of −0.1%.
|VCP − AGND| = 231.7 mV rms; ∠(VCP − AGND) = +121°
|VN − AGND| = 4.86 mV rms; ∠(VN − AGND) = −118°
Rev. 0 | Page 8 of 11
Application Note
AN-1334
LAB TESTS
To verify the simulation results and to understand the impact of
real components, lab tests were conducted using the ADE7880,
a poly phase energy metering IC.
The ADE7880 evaluation board and a 3-phase Rotek accurate
source were used to conduct the lab tests. Refer to the ADE7880
evaluation board user guide, UG-356, for details on the ADE7880
evaluation board. To introduce the neutral series resistance in the
configuration, the following changes were made (see Figure 11):
•
•
The 1 kΩ resistor, R25 in Figure 11, was removed and
soldered on top of C25 on the evaluation board.
In the place of the 1 kΩ R25 resistor, a 1 MΩ resistor was
soldered.
The jumper status on the voltage channel connections of the
ADE7880 evaluation board were
•
•
•
1
VN_IN
1
VN
GRY
R25
1kΩ
2
B
12687-010
JP7N
A
COM
1 2 3
AGND
AGND
3PIN_JUMPER_TH
P7
1
P6
1
P5
1
1MΩ
VAP
1kΩ
2.2nF
1kΩ
2.2nF
1kΩ
2.2nF
1kΩ
2.2nF
1MΩ
VBP
1MΩ
VCP
1MΩ
Phase A = 1.001 MΩ; 1.009 kΩ
Phase B = 999 kΩ; 1.002 kΩ
Phase C = 1.002 Ω; 0.997 kΩ
Neutral = 950 kΩ; 1.01 kΩ
VN
12687-011
1
•
•
•
•
The simulation and lab results match closely, as seen in Table 1.
Observing the resistor values measured from the evaluation board,
all the resistors were 1% tolerant resistors, except for the 1 MΩ
resistor on the neutral wire (actually 950 kΩ), which was 5%
tolerant. This resistor is the major part of neutral series resistance
and is common to all phase voltage measurements. Therefore,
the loose tolerance specification of this resistor adversely impacted
the performance in all phases where voltage magnitude imbalance
exists. If the 1 MΩ resistor of Phase A is 5% tolerant, whereas all
other resistors are 1% tolerant, the impact due to the attenuation
network mismatch is severe only on the Phase A results, when
voltage magnitude imbalance exists.
Figure 11. Neutral Voltage Connection, ADE7880 Evaluation Board
P8
The 1 MΩ and 1 kΩ resistors placed on the signal path of all
phase and neutral wires were measured and found to be
The lab and simulation test results are shown in Table 1. The
balanced case measurements, with the neutral series resistance,
were considered as the reference, to compute the gain errors in
unbalanced cases.
VN
C25
2200pF
E3N
1500Ω
2
The voltage rms measurements from the ADE7880 IC were
recorded in each case to quantify the gain error observed.
Readings of 100 rms were recorded, and the results were
averaged to acquire an rms value in each case.
All the simulation cases were repeated by replacing the three
333 kΩ resistors in the signal path of each wire (see Figure 6),
with a single resistor on the signal path of each wire. Instead of
using 1 MΩ and 1 kΩ resistors in the schematic, resistors with
the measured values were used. The use of actual resistor values
is essential because the mismatch in the attenuation network ratios
causes more error when voltage magnitude imbalance exists.
JP7A, JP7B, JP7C, JP7N = open
JP9A, JP9B, JP9C = closed
JP8A, JP8B, JP8C = Pin 1 and Pin 2
P5
Pin 1 of the P8, P7, P6, and P5 connectors were connected to
the Phase A, Phase B, Phase C, and neutral wires, respectively,
as shown in Figure 12.
Figure 12. Final Representation of Voltage Channel Configuration
Table 1. Lab and Simulation Results Comparison
Unbalanced Case
Case 1: Phase B and Phase C Disconnected
Case 2: Phase B and Phase C Tied to Neutral
Case 3: |VA| = 220 V; |VB| = |VC| = 240 V
Case 4: |VA| = 220 V; |VB| = |VC| = 20 V
1
Lab
+2.00%
+0.96%
−0.10%
+1.17%
AVRMS
Simulation
+2.38%
+1.21%
−0.14%
+1.12%
Gain Error in RMS Measurement
BVRMS
Lab
Simulation
N/A 1
N/A1
N/A1
N/A1
+0.15%
+0.04%
−7.37%
−5.17%
Lab
N/A1
N/A1
+0.15%
−9.61%
CVRMS
Simulation
N/A1
N/A1
+0.25%
−5.42%
N/A = not applicable. The expected Phase B and Phase C voltages are 0 V in Case 1 and Case 2. Therefore, error is not shown in this table. Refer to the sections on each
individual case for details on erroneous Phase B and Phase C voltage signals in Case 1 and Case 2.
Rev. 0 | Page 9 of 11
AN-1334
Application Note
SIMULATION TEST: SPECIAL CASE
Because the simulation results closely matched the lab results,
further simulations were conducted to better understand the
errors observed in the 25% voltage magnitude imbalance
condition. When a 25% voltage magnitude imbalance exists,
with a total magnitude imbalance of 110 V, the gain and phase
errors were simulated on three different scenarios, and the
results are provided in Table 2. Resistors with 1% tolerance were
considered for these simulation cases. The resistors that formed
the attenuation network were
•
•
•
•
Phase A: Three 336.33 kΩ resistors and one 990 Ω resistor
Phase B: Three 329.67 kΩ resistors and one 1.01 kΩ resistor
Phase C: Three 333 kΩ resistors and one 1 kΩ resistor
Neutral: Three 333 kΩ resistors and one 1 kΩ resistor
Table 2. Simulation Results: 25% Voltage Magnitude Imbalance with 1% Tolerant Resistors
Unbalanced Case
|VA| = 275 V, |VB| = 220 V, |VC| = 165 V
|VA| = 165 V, |VB| = 275 V, |VC| = 220 V
|VA| = 220 V, |VB| = 165 V, |VC| = 275 V
Phase A Voltage
Gain Error
Phase Error
0.12%
0°
−0.14%
0°
0.00%
0°
Phase B Voltage
Gain Error
Phase Error
0.00%
−0.1°
−0.19%
−2.3°
0.26%
0°
Rev. 0 | Page 10 of 11
Phase C Voltage
Gain Error
Phase Error
0.03%
0°
0.00%
0°
−0.02%
0°
Application Note
AN-1334
CONCLUSION
4.
The performance impact analysis of using a neutral series
resistance in a 3P4W wye system, done with the help of
simulation and lab test results, reveal the following:
1.
2.
3.
When the phases are balanced, there is no performance
degradation observed, in comparison to the standard
3P4W configuration (see Figure 5 for the standard
configuration).
Calibrate the 3P4W wye meter setup by providing balanced
test voltage signals on all phases, even when calibrating
phases one by one.
When voltage magnitude imbalance exists, gain and phase
errors may be observed, depending on the amount of
imbalance and the attenuation network ratio mismatch.
5.
6.
7.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN12687-0-10/14(0)
Rev. 0 | Page 11 of 11
When 25% voltage magnitude imbalance exists, a maximum
gain error of 0.26% and a maximum phase error of −2.3°
can be expected, while using 1% tolerant resistors. If a single
voltage measurement has 0.26% gain error and −2.3° phase
error, the active energy measurement has an error of 0.18%
at PF of 1, −6.8% at PF of 0.5, and −20% at PF of 0.2.
Use resistors with tighter tolerance ratings for better
performance in unbalanced conditions.
The errors provided in this application note, based on lab and
simulation test results, do not take into account the
performance degradation over temperature.
Voltage phase imbalance (a condition where the phase
voltages are not exactly 120° phase-shifted with respect to
each other) is not common. The impact of the neutral series
resistance during such an imbalance is not considered in
this application note.