LT3992 - Monolithic Dual Tracking 3A Step-Down Switching Regulator

LT3992
Monolithic Dual Tracking
3A Step-Down Switching Regulator
Description
Features
Wide Input Range:
– Operation from 3V to 60V
n Independent Supply, Shutdown, Soft-Start, UVLO,
Programmable Current Limit and Programmable
Power Good for Each 3A Regulator
n Die Temperature Monitor
n Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 2MHz with Synchronized
Clock Output
n Independent Synchronized Switching Frequencies
Optimize Component Size
n Antiphase Switching
n Outputs Can Be Paralleled
n Flexible Output Voltage Tracking
n Low Dropout: 95% Maximum Duty Cycle
n5mm × 5mm QFN Package
n FMEA Compliant 38-Pin Exposed Pad TSSOP Package
The LT®3992 is a dual current mode PWM step-down
DC/DC converter with two internal 4.6A switches. Independent input voltage, shutdown, feedback, soft-start,
UVLO current limit and comparator pins for each channel
simplify complex power supply tracking and sequencing
requirements.
n
To optimize efficiency and component size, both converters have a programmable maximum current limit and are
synchronized to either a common external clock input, or
a resistor settable fixed 250kHz to 2MHz internal oscillator.
A frequency divider is provided for channel 1 to further
optimize component size. At all frequencies, a 180° phase
relationship between channels is maintained, reducing voltage ripple and component size. A clock output is available
for synchronizing multiple regulators.
Minimum input to output voltage ratios are improved by
allowing the switch to stay on through multiple clock cycles
only switching off when the boost capacitor needs recharging. Independent channel operation can be programmed
using the SHDN pin. Disabling both converters reduces
the total quiescent current to <10µA.
Applications
Automotive Supplies
Distributed Supply Regulation
n
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
12V and 5V 2-Stage Multi-Frequency Step-Down Converter
VIN1
15V TO 60V
4.7µF
VOUT2
VIN2
VIN1
SHDN1
22µH
0.1µF
VOUT1
12V
1A
400kHz
22µF
8.06k
113k
SHDN2
BST1
BST2
SW1
SW2
IND1
VOUT1
100k
LT3992
FB1
PG
680pF
CMPI2
CMPO1
CMPO2
100k
15k
DIV
SS2
ILIM2
VC2
48.7k
102k
CLKOUT
GND
CH1
400kHz
20V/DIV
2.2µH
0.1µF
VOUT2
CMPI1
RT/SYNC
33pF
IND2
42.2k
FB2
SS1
ILIM1
VC1
0.1µF
Independent Synchronized
Switching Frequencies Extend
Full Frequency Input Range
TJ
FB1
8.06k
VOUT2
5V
2A
47µF 1600kHz
CH2
1.6MHz
5V/DIV
VIN = 60V
CLKOUT
1600kHz
10nF
33pF
680pF
10k
500ns/DIV
3992 TA01b
0.1µF
60.4k
3992 TA01a
3992fa
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1
LT3992
Absolute Maximum Ratings
(Note 1)
VIN1/2, SHDN1/2, CMPO1/2........................................60V
SW1/2.....................................................................VIN1/2
BST1/2.......................................................................75V
BST1/2 Pin Above SW1/2...........................................25V
IND1/2, VOUT1/2..........................................................60V
FB1/2, CMPI1/2, SS1/2.................................................5V
RT/SYNC......................................................................5V
DIV, ILIM1/2..............................................................2.5V
VC1/2, TJ............................................................... ±100µA
Operating Junction Temperature Range (Note 2)
LT3992EUH......................................... –40°C to 125°C
LT3992IUH.......................................... –40°C to 125°C
LT3992EFE.......................................... –40°C to 125°C
LT3992IFE........................................... –40°C to 125°C
LT3992HFE......................................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
38 SW1
2
37 NC
NC
3
36 VIN1
VOUT1
4
35 SHDN1
32 31 30 29 28 27 26 25
NC
5
34 SS1
BST1
6
33 ILIM1
CMPO1
7
32 VC1
CMPI1
8
31 NC
FB1
9
VIN1
SW1
DNC*
IND1
DNC*
VOUT1
TOP VIEW
SHDN1
NC
IND1
SS1
TOP VIEW
1
BST1 1
24 ILIM1
CMPO1 2
23 VC1
22 RT/SYNC
CMPI1 3
FB1 4
21 CLKOUT
33
GND
30 RT/SYNC
20 TJ
NC 10
CMPI2 6
19 DIV
FB2 11
CMPO2 7
18 VC2
CMPI2 12
27 DIV
CMPO2 13
26 VC2
FB2 5
17 ILIM2
BST2 8
BST2 14
NC 15
SS2
SHDN2
VIN2
SW2
DNC*
IND2
DNC*
9 10 11 12 13 14 15 16
VOUT2
39
GND
VOUT2 16
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
NC 17
IND2 18
θJA = 44°C/W, θJC(PAD) = 7.3°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
*DO NOT CONNECT
NC 19
29 CLKOUT
28 TJ
25 ILIM2
24 SS2
23 SHDN2
22 VIN2
21 NC
20 SW2
FE PACKAGE
38-LEAD PLASTIC TSSOP
θJA = 17.5°C/W, θJC(PAD) = 10°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3992EUH#PBF
LT3992EUH#TRPBF
3992
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LT3992IUH#PBF
LT3992IUH#TRPBF
3992
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LT3992EFE#PBF
LT3992EFE#TRPBF
LT3992FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3992IFE#PBF
LT3992IFE#TRPBF
LT3992FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3992HFE#PBF
LT3992HFE#TRPBF
LT3992FE
38-Lead Plastic TSSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
3992fa
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LT3992
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 2)
PARAMETER
CONDITIONS
SHDN Voltage Threshold CH1/2
SHDN Input Current CH1/2
l
VSHDN = 1.35V
VIN1 Undervoltage Lockout (Note 3)
VIN1 Shutdown Current
VSHDN = 0V
l
VIN2 Shutdown Current
VSHDN = 0V
l
MIN
TYP
MAX
UNITS
1.24
1.32
1.4
V
–1
0
1
µA
2.6
2.9
3.2
V
6
13
µA
0.1
2
µA
VIN1 Quiescent Current
VFB1/2 = 2V
3
4.2
6
mA
VIN2 Quiescent Current
VFB1/2 = 2V
300
530
900
µA
Feedback Voltage CH1/2
VVC1/2 = 1V
l
786
806
824
mV
Feedback Voltage Regulation
VVIN1/2 = 4V to 60V
l
780
806
830
mV
Feedback Voltage Offset CH1 to CH2
VVC1/2 = 1V
l
–13
0
13
mV
l
0
85
300
Feedback Bias Current CH1/2
VVC1/2 = 1V
TJ Output Voltage (Note 4)
TJ = 25°C, ITJ = 25µA, Temperature = 25°C
ITJ = 25µA, Temperature = 125°C
ITJ = 25µA, Temperature = –40°C
TJ Error
Temperature = 25°C to 125°C
Error Amp gm CH1/2
VVC1/2 = 1V, IVC1/2 = ±10µA
250
1.23
–380
l
nA
mV
V
mV
–100
0
100
mV
250
350
450
µMho
Error Amp Source Current CH1/2
VFB1/2 = 0.7V, VVC1/2 = 1V
15
25
40
µA
Error Amp Sink Current CH1/2
VFB1/2 =0.9V, VVC1/2 = 1V
15
25
40
µA
Error Amp High Clamp CH1/2
VFB1/2 = 0.7V
1.7
1.9
2.1
V
0.8
1.0
1.2
V
9
13.5
17
µA
Error Amp Switching Threshold CH1/2
VFB1/2 = 0V
Soft-Start Source Current CH1/2
VFB1/2 = 2V, VSS1/2 = 0.07V
l
Soft-Start VOH CH1/2
VFB1/2 = 2.0V
1.9
2.15
2.4
Soft-Start Sink Current CH1/2
VFB1/2 = 0.7V, VSS1/2 = 2V
0.4
0.9
2
mA
Soft-Start VOL CH1/2
VFB1/2 = 0V
130
170
210
mV
Soft-Start to Feedback Offset CH1/2
VVC1/2 = 1V, VSS1/2 = 0.4V
16
0
16
mV
l
SS POR Threshold CH1/2
V
70
110
140
mV
Soft-Start Sink Current CH1/2 POR
VFB1/2 = 2V, VSS1/2 = 0.14V (Note 5)
150
450
600
µA
Soft-Start SW Disable CH1/2
VFB1/2 = 0V (Note 5)
80
115
150
mV
CMPI Bias Current CH1/2
VCMPI1/2 = 0.8V
CMPO Leakage CH1/2
VCMP1/2 = 0.8V, VCMPO1/2 = 60V
CMPI Threshold CH1/2
VCMPI1/2 Rising
CMPI Threshold CH1/2 of VFB1/2
VCMPI1/2 Rising (Note 6)
–100
l
0
100
nA
70
500
nA
690
725
760
mV
86
90
94
%
105
mV
CMPI Hysteresis CH1/2
VCMPI1/2
50
80
CMPO Sink Current CH1/2
VCMPI1/2 = 0.6V, VCMPO1/2 = 0.2V
150
250
RT/SYNC Reference Current
VRT/SYNC = 0.36V E- & I-Grade
l
11.3
12
RT/SYNC Reference Current
VRT/SYNC = 0.36V H-Grade
l
11.2
12
13
µA
Minimum Switching Frequency
RRT/SYNC =0Ω
50
110
150
kHz
Switching Frequency
RRT/SYNC = 28k
900
1000
1100
kHz
Maximum Switching Frequency
RRT/SYNC =100k
2.2
2.5
3.0
MHz
Switching Phase Angle CH1 ≥ CH2
µA
12.7
185
DIV Reference Current
VDIV = 1V
CH1 DIV 2 Threshold
RRT/SYNC = 0V
l
µA
Deg
10.7
12
13.3
µA
0.44
0.5
0.56
V
3992fa
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3
LT3992
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CH1 DIV 4 Threshold
RRT/SYNC = 0V
0.89
1.0
1.06
V
CH1 DIV 8 Threshold
RRT/SYNC = 0V
1.39
1.5
1.56
0.25
CLKOUT VOL
CLKOUT VOH
CLKOUT to SW1ON Delay ( tDCLKOSW1)
CLKOUT Rising
V
V
2
V
60
ns
CLKOUT to SW2ON Delay ( tDCLKOSW2)
CLKOUT Falling
30
ns
RT/SYNC to CLKOUT Delay ( tDRTSYNCH)
VRT/SYNC = 0V to 2V Rising Edge
300
ns
RT/SYNC to CLKOUT Delay ( tDRTSYNCL)
VRT/SYNC = 2V to 0V Falling Edge
150
ns
SYNC Frequency Range
SYNC Phase Angle CH1 to CH2
250
SYNC Frequency = 250kHz
2000
180
kHz
Deg
Minimum Switch On-Time CH1/2
160
ns
Minimum Switch Off-Time CH1/2
200
ns
Minimum Boost for 100% DC CH1/2 (Note 7)
1.6
IND + VOUT Current CH1/2
VVOUT1/2 = 0V
VVOUT1/2 = 5V
ILIM1/2 Reference Current
VILIM = 0V
IND to VOUT Maximum Current CH1/2
2.2
2.6
V
1.5
0.5
5
5
µA
µA
l
10
12
16
µA
VILIM1/2 = 0.5V, VVOUT = 1V (Note 8)
VILIM1/2 = 0.5V, VVOUT = 5V (Note 8)
VILIM1/2 = 1.5V, VVOUT = 1V (Note 8)
VILIM1/2 = 1.5V, VVOUT = 5V (Note 8)
l
l
0.5
0.7
3.5
3.5
1.5
1.8
4.6
4.6
3
3
6.4
6.4
A
A
A
A
Switch Leakage Current CH1/2
VSW1/2 = 0V
l
1
10
µA
Switch Saturation Voltage CH1/2
ISW1/2 = 500mA, VBST1/2 = 18V
ISW1/2 = 3A, VBST1/2 = 18V
Boost Current CH1/2
ISW1/2 = 500mA, VBST1/2 = 8V
ISW1/2 = 3A, VBST1/2 = 8V
5
35
8
55
25
85
mA
mA
Minimum Boost Voltage CH1/2 (Note 9)
ISW1/2 = 3A, VBST1/2 = 8V
1.0
2.2
3.0
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3992EUH/LT3992EFE is guaranteed to meet performance
specifications from 0°C to 125°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3992IUH/LT3992IFE is guaranteed over the full –40°C to 125°C
operating junction temperature range. The LT3992HFE is guaranteed
over the full –40°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes. Operating lifetime is
derated at junction temperatures greater than 125°C.
Note 3: VIN undervoltage lockout is defined as the voltage which the VIN
pin must exceed for operation. The threshold guarantees that internal bias
lines are regulated and switching frequency is constant. Actual minimum
input voltage to maintain a regulated output will depend upon output
voltage and load current. See the Applications Information section.
4
200
325
mV
mV
Note 4: The TJ output voltage represents the temperature at the center
of the die while dissipating quiescent power. Due to switch power
dissipation and temperature gradients across the die, the TJ output
voltage measurement does not guarantee that absolute maximum junction
temperature will not be exceeded.
Note 5: An internal power on reset (POR) latch is set on the positive
transition of the SHDN1/2 pin through its threshold, thermal shutdown or
overvoltage lockout. The output of the latch activates current sources on
each SS pin which typically sink 450µA and discharge the SS capacitor.
The latch is reset when both SS pins are driven below the soft-start POR
threshold or the SHDN pin is taken below its threshold.
Note 6: The threshold is expressed as a percentage of the feedback
reference voltage for the channel.
Note 7: To enhance dropout operation, the output switch will be turned off
for the minimum off-time only when the voltage across the boost capacitor
drops below the minimum boost for 100% duty cycle threshold.
Note 8: The IND to VOUT maximum current is defined as the value of
current flowing from the IND pin to the VOUT pin which resets the switch
latch when the VC pin is at its high clamp.
Note 9: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
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LT3992
Typical Performance Characteristics
3.5
6
CURRENT (µA)
SHUTDOWN
THRESHOLD VOLTAGE
IQ1
6
5
4
3
1.0
2
0.5
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
IQ2
0
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G01
TJ Output Voltage vs Temperature
RTJ = 30k TO –1V
–0.50
–50 –25
0
4
385
355
340
325
310
295
–1
–2
280
400
–3
–4
–50 –25
1800
SINK CURRENT AT VCMPO = 0.4V
FALLING THRESHOLD
25 50 75 100 125 150
TEMPERATURE (°C)
1400
3992 G07
250
200
150
1200
800
600
400
50
200
0
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G08
RRT/SYNC = 28.0k
1000
100
0
–50 –25
RRT/SYNC = 44.2k
1600
FREQUENCY (kHz)
CURRENT (µA)
660
25 50 75 100 125 150
TEMPERATURE (°C)
Switching Frequency
vs Temperature
300
700
670
0
3992 G06
350
710
0
0
3992 G05
RISING THRESHOLD
630
–50 –25
1
Comparator Sink Current
vs Temperature
680
VSS = 0.4V
2
370
Comparator Thresholds
vs Temperature
690
–8
25 50 75 100 125 150
TEMPERATURE (°C)
3
3992 G04
720
0
Soft-Start-to-Feedback Offset
vs Temperature
250
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
730
–4
3992 G03
265
25 50 75 100 125 150
TEMPERATURE (°C)
–2
CH1
800
–50 –25
VOLTAGE (mV)
TRANSCONDUCTANCE (µMho)
VOLTAGE (V)
0.25 RTJ = 30k
TO GND
0
–0.25
VOLTAGE (mV)
805
400
0.50
0
CH2
415
0.75
640
810
Error Amplifier Transconductance
vs Temperature
1.25
2
OFFSET
3992 G02
1.50
1.00
4
–6
1
0
–50 –25
815
OFFSET VOLTAGE (mV)
2.0
FEEDBACK VOLTAGE (mV)
8
7
1.5
8
9
MINIMUM
INPUT VOLTAGE
2.5
VOLTAGE (V)
820
10
3.0
650
FB Voltage and CH1-CH2 FB
Offset vs Temperature
Shutdown Quiescent Current
vs Temperature
Shutdown Threshold and Minimum
Input Voltage vs Temperature
0
–50 –25
RRT/SYNC = 13.0k
RRT/SYNC = 0k
0
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G09
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5
LT3992
Typical Performance Characteristics
CLKOUT-to-SW1 Delay
vs Temperature
160
450
193
150
400
191
140
130
187
120
185
183
110
100
300
200
150
90
179
80
100
177
70
50
60
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
DIV Voltage Threshold
vs Temperature
MAXIMUM RT/SYNC DUTY CYCLE
40
1.2
÷4
1.0
0.8
0.6
MINIMUM RT/SYNC DUTY CYCLE
÷2
0.4
10
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
5.0
90
4.5
4.0
70
3.5
PEAK CURRENT (A)
80
50
40
1A
20
10
0
–50 –25
0
3992 G16
6
3.00
25 50 75 100 125 150
TEMPERATURE (°C)
2.50
3.0
2.5
VILIM = 0.5V
2.0
1.5
0
–50 –25
ISW = 3A
2.75
VILIM = 1.5V
2.25
2.00
1.75
1.50
1.25
0.5
25 50 75 100 125 150
TEMPERATURE (°C)
0
Minimum Boost Voltage
vs Temperature
1.0
0.5A
ISW = 500mA
3992 G15
Switch Peak Current
vs Temperature
100
30
200
3992 G14
Boost Current vs Temperature
3A
ISW = 1A
250
100
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G13
60
300
150
0.2
0
–50 –25
ISW = 3A
350
VOLTAGE (mV)
VOLTAGE (V)
DUTY CYCLE (%)
÷8
1.4
50
20
400
1.6
70
30
Switch Saturation Voltage
vs Temperature
1.8
RT/SYNC FREQUENCY = 1MHz
60
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G12
VOLTAGE (V)
80
0
3992 G11
Synchronization Duty Cycles
vs Temperature
90
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G10
100
CLKOUT
250
181
0
SW1
350
DELAY (ns)
189
175
–50 –25
BOOST CURRENT (mA)
RT/SYNC-to-CLKOUT and SW1
Delay vs Temperature
195
DELAY (ns)
PHASE (DEG)
Switching Phase vs Temperature
0
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G17
1.00
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3992 G18
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LT3992
Typical Performance Characteristics
5V Efficiency
90
2250
85
2000
EFFICIENCY (%)
1500
1250
1000
750
85
VIN = 24V
VIN = 36V
75
70
65
10
20 30 40 50 60 70
RT/SYNC RESISTANCE (kΩ)
80
50
0
0.5
1.0 1.5 2.0 2.5
OUTPUT CURRENT (A)
5V Efficiency
90
85
85
80
80
75
75
70
65
60
50
fSW = 500kHz
CH1 = 5V
CH2 = 3.3V, 0A
45
40
0
0.5
1.0 1.5 2.0 2.5
OUTPUT CURRENT (A)
65
3.0
fSW = 1MHz
CH1 = 5V, 0A
CH2 = 3.3V
55
3.5
50
0
0.5
1.0 1.5 2.0 2.5
OUTPUT CURRENT (A)
3.0
3.5
3992 G21
3.3V Efficiency
90
55
70
3992 G20
3992 G19
EFFICIENCY (%)
0
VIN = 24V
75
60
fSW = 1MHz
CH1 = 5V
CH2 = 3.3V, 0A
55
250
VIN = 12V
80
60
500
0
VIN = 12V
80
1750
3.3V Efficiency
90
EFFICIENCY (%)
2500
EFFICIENCY (%)
CLKOUT FREQUENCY (kHz)
CLKOUT Frequency
vs RT/SYNC Resistance
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
3.0
70
65
60
55
50
fSW = 500kHz
CH1 = 5V, 0A
CH2 = 3.3V
45
3.5
40
0
0.5
3992 G22
1.0 1.5 2.0 2.5
OUTPUT CURRENT (A)
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
3.0
3.5
3992 G23
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7
LT3992
Pin Functions
BST1/2: The BST pin provides a higher than VIN base
drive to the power NPN to ensure a low switch drop. If the
voltage between the BST pin and the VIN pin is less than
the voltage required to fully turn on the power NPN, the
power switch is turned off to recharge the BST capacitor.
CMPI1/2: The CMPI pin is an input to a comparator with a
threshold of 725mV and 80mV of hysteresis. Connecting
the CMPI pin to the FB pin will generate a power good
signal when the output is within 90% of its regulated value.
CMPO1/2: The CMPO pin is an open-collector output that
sinks current when the CMPI pin falls below its threshold.
For a typical input voltage above 2.9V, its output state remains true, although during shutdown, VIN1 undervoltage
lockout or thermal shutdown, its current sink capability is
reduced. The COMPO pins can be left open circuit or tied
together to form a single power good signal.
DIV: The voltage present at the DIV pin determines the ratio
of channel 1 frequency to the master clock frequency set
by the RT/SYNC pin. The DIV pin is driven by an internal
current source with a typical value of 12µA which allows
a single resistor from the DIV pin to ground to set the
DIV voltage and resulting channel 1 frequency divider.
Ratios of 1, 2, 4 and 8 are available. See the Applications
Information section for more information.
DNC: Do Not Connect.
GND: The exposed pad pin is the only ground connection for the device. The exposed pad should be soldered
to a large copper area to reduce thermal resistance. The
GND pin is common to both channels and also serves as
small-signal ground. For ideal operation all small-signal
ground paths should connect to the GND pin at a single
point avoiding any high current ground returns.
FB1/2: The FB pin is the negative input to the error amplifier.
The output switches to regulate this pin to 806mV with
respect to the exposed ground pad. Bias current flows
out of the FB pin.
8
ILIM1/2: The voltage present at the ILIM pin determines
the peak inductor current for the channel. The ILIM pin is
driven by an internal current source with a typical value
of 12µA. A resistor from the ILIM pin to ground sets the
ILIM voltage; the resistor value must be between 42.2k
and 120k. The maximum current limit range is 4.8A to
1.8A when the ILIM voltages are 1V and 0.5V respectively.
IND1/2: The IND pin is the input to the internal sense resistor
that measures current flowing in the inductor. When the
current in the resistor exceeds the current dictated by the
VC pin, the SW latch is held in reset, disabling the output
switch. Bias current flows out of the IND pin.
RT/SYNC: The voltage present at the RT/SYNC pin determines the constant switching frequency. The RT/SYNC
pin is driven by an internal current source with a typical
value of 12µA which allows a single resistor from the RT/
SYNC pin to ground to set the RT/SYNC voltage and resulting switching frequency. Minimum switching frequency
is typically 110kHz when VRT/SYNC is 0V and maximum
switching frequency is typically 2.5MHz when VRT/SYNC
is above 950mV.
Driving the RT/SYNC pin with an external clock signal will
synchronize the switch to the applied frequency. Synchronization occurs on the rising edge of the clock signal after
the clock signal is detected. Each rising clock edge initiates
an oscillator ramp reset. A gain control loop servos the
oscillator charging current to maintain constant oscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode after
the synchronization detection circuitry times out. The clock
source impedance should be set such that the current out
of the RT/SYNC pin in resistor mode generates a frequency
roughly equivalent to the synchronization frequency. See
the Applications Information section for more information.
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LT3992
pin functions
SHDN1/2: The shutdown pin is used to control each
channel’s operation. In addition to controlling channel 1,
the SHDN1 pin also activates control circuitry for both
channels and must be present for channel 2 to operate.
When SHDN1 is below its threshold, quiescent current is
reduced to a typical value of 6µA. Independent channel
UVLO can be programmed by connecting the SHDN pin to
an input voltage divider. See the Applications Information
section for more information. If the shutdown features are
not used, the SHDN pin should be tied to VIN.
SS1/2: Current flowing out the SS pin into an external
capacitor defines the rise time of the output voltage. When
the SS pin is lower than the 0.806V reference, the feedback
is regulated to the SS voltage. When the SS pin exceeds
the reference voltage, the output will regulate the FB pin
voltage to 0.806V and the SS pin will continue to rise until
its clamp voltage. During an output overload, the VC pin is
driven above the maximum switch current level activating
its voltage clamp. When the VC clamp is activated, the SS
pin is discharged until the output reaches a regulation point
that the maximum output current can maintain. When the
overload condition is removed, the output soft starts from
that voltage. In the case of a SHDN or thermal shutdown
event, a power on reset latch ensures the capacitors on
both channels are fully discharged before either is released.
Connecting both SS pins together ensures the outputs
track together.
CLKOUT: The CLKOUT pin generates a square wave of 0V
to 2.5V which is synchronized to the internal oscillator. If
the switching frequency is set by an external resistor the
resultant clock duty cycle will be 50%. If the RT/SYNC pin
is driven by an external clock source, the resultant CLKOUT
duty cycle will mirror the external source.
TJ: The TJ pin outputs a voltage proportional to junction
temperature. The pin is 250mV for 25°C and has a slope
of 10mV/°C. See the Applications Information section for
more information.
VC1/2: The VC pin is the output of the error amplifier and the
input to the peak switch current comparator. It is normally
used for frequency compensation, but can also be used
as a current clamp or control loop override. If the error
amplifier drives VC above the maximum switch current
level, a voltage clamp activates. This indicates that the
output is overloaded and current is pulled from the SS
pin reducing the regulation point.
VIN1: The VIN1 pin powers the internal control circuitry
for both channels and is monitored by an undervoltage
lockout comparator. The VIN1 pin is also connected to the
collector of channel 1’s on-chip power NPN switch. The
VIN1 pin has high dI/dt edges and must be decoupled to
ground close to the pin of the device.
VIN2: The VIN2 pin powers the output stage for channel 2
and is monitored by an undervoltage lockout comparator.
VIN1 voltage must be greater than typically 2.9V for VIN2
operation. The VIN2 pin is also the collector of channel
2’s on-chip power NPN switch. The VIN2 pin has high dI/
dt edges and must be decoupled to ground close to the
pin of the device.
VOUT1/2: The VOUT pin is the output to the internal sense
resistor that measures current flowing in the inductor.
When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset disabling
the output switch. Bias current flows out of the VOUT pin.
SW1/2: The SW pin is the emitter of the internal power
NPN. At switch off, the inductor will drive this pin below
ground with a high dV/dt. An external Schottky catch
diode to ground, close to the SW pin and respective VIN
decoupling capacitor’s ground, must be used to prevent
this pin from excessive negative voltages.
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LT3992
Block Diagram
VIN1
1.32V
SHDN1
VIN1
+
–
CHANNEL 1
THERMAL
SHUTDOWN
2.5V
12µA
SS1
S
–
+
110mV
–
+
S
PRE
PRE
Q
R
DROPOUT
ENHANCEMENT
BST1
DRIVER
CIRCUITRY
SW1
D1
+
–
Q
R
IND1
VOUT1
VC1
R1
FB1
2.5V
ILIM1
RLIM
CMPI1
12µA
SLOPE
COMPENSATION
2.5V
2.5V
DIV
0.806V
0.72V
+
–
12µA
RT/SYNC
R3
+
+
–
R2
CMPO1
12µA
OSCILLATOR
AND AGC
CLK1
VIN1
MASTER CLOCK
2.9V
+
–
CLK2 TO CHANNEL 2
INTERNAL
REGULATOR
AND
REFERENCES
2.5V
TJ
CLKOUT
GND
RDIV
3992 F01
Figure 1. LT3992 Block Diagram
The LT3992 is a dual channel, constant frequency, current
mode buck converter with internal 4.6A switches. Each
channel can be independently controlled with the exception
that VIN1 must be above the typically 2.9V undervoltage
lockout threshold to power the common internal regulator,
oscillator and thermometer circuitry.
If the SHDN1 pin is taken below its 1.32V threshold the
LT3992 will be placed in a low quiescent current mode. In this
mode the LT3992 typically draws 6µA from VIN1 and <1µA
from VIN2. When the SHDN pin is driven above 1.32V, the
internal bias circuits turn on generating an internal regulated
voltage, 0.806VFB, 12µA RT/SYNC, DIV and ILIM current
references, and a POR signal which sets the soft-start latch.
Once the internal reference reaches its regulation point,
the internal oscillator will start generating a master clock
signal for the two regulators at a frequency determined by
the voltage present at the RT/SYNC pin. The channel 1 clock
10
is then divided by 1, 2, 4 or 8 depending on the voltage
present at the DIV pin. Channel 2’s clock runs at the master
clock frequency with a 180° phase shift from channel 1.
Alternatively, if a synchronization signal is detected by
the LT3992 the RT/SYNC pin, the master clock will be
generated at the incoming frequency on the rising edge
of the synchronization pulse with channel 1 in phase with
the synchronization signal. Frequency division and phase
remains the same as the internally generated master clock.
In addition, the internal slope compensation will be automatically adjusted to prevent subharmonic oscillation
during synchronization. In either mode of oscillator operation, a square wave with the master clock frequency,
synchronized to channel 1 is present at the CLKOUT pin.
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are controlled by an internal clock and two feedback loops that
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LT3992
Block Diagram
control the duty cycle of the power switch. In addition to
the normal error amplifier, there is a current sense amplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180° shift will occur. The current fed system will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
When, during power-up, an internal POR signal sets
the soft-start latch, both SS pins will be discharged to
ground to ensure proper start-up operation. When the SS
pin voltage drops below 110mV, the VC pin is driven low
disabling switching and the soft-start latch is reset. Once
the latch is reset the soft-start capacitor starts to charge
with a typical value of 12µA.
As the voltage rises above 110mV on the SS pin, the VC
pin will be driven high by the error amplifier. When the
voltage on the VC pin exceeds 1V, the clock set-pulse sets
the driver flip-flop, which turns on the internal power NPN
switch. This causes current from VIN, through the NPN
switch, inductor and internal sense resistor to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
VC pin, the flip-flop is reset and the internal NPN switch
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceeds the predetermined level at the start of a clock cycle,
the flip-flop will not be set resulting in a further decrease
in inductor current. Since the output current is controlled
by the VC voltage, output regulation is achieved by the
error amplifier continually adjusting the VC pin voltage.
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
either the SS pin or an internal 806mV reference. Compensation of the loop is easily achieved with a simple capacitor
or series resistor/capacitor from the VC pin to ground.
The regulators’ maximum output current occurs when
the VC pin is driven to its maximum clamp value by the
error amplifier. The value of the typical maximum switch
current can be programmed from 4.6A to 1.8A by placing
a resistor from the ILIM pin to ground.
Since the SS pin is driven by a constant current source, a
single capacitor on the soft-start pin will generate controlled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maximum current dictated by the VC pin clamp, the SS pin
will be discharged, lowering the regulation point until the
output voltage can be supported by the maximum current.
Once the overload condition is removed, the regulator will
soft-start from the overload regulation point.
Shutdown control or thermal shutdown will set the softstart latch, resulting in a complete soft-start sequence.
The switch driver operates from either the VIN or BST voltage. An external diode and capacitor are used to generate
a drive voltage higher than VIN to saturate the output NPN
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin comparator forces a minimum cycle off time, allowing the boost
capacitor to recharge.
A comparator with a threshold of 720mV and 80mV of
hysteresis is provided for detecting error conditions. The
CMPO output is an open-collector NPN that is off when
the CMPI pin is above the threshold allowing a resistor
to pull the CMPO pin to a desired voltage.
The voltage present at the TJ pin is proportional to the junction
temperature of the LT3992. The TJ pin will be 250mV for a
die temperature of 25°C and will have a slope of 10mV/°C.
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LT3992
Applications Information
Choosing the Output Voltage
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resistors according to:
⎛V
⎞
R1= R2 • ⎜ OUT – 1⎟
⎝ 0.806 ⎠
R2 should be 10k or less to avoid bias current errors. Reference designators refer to the Block Diagram in Figure 1.
To alleviate duty cycle restrictions due to minimum switchon times, channel 1’s switching frequency can be divided
from the master clock by 1, 2, 4 or 8 determined by resistor
RDIV in Figure 1. Channel 2’s switching frequency is not
affected by the DIV pin. The DIV pin is driven by a 12µA
current source. Setting resistor RDIV sets the voltage present at the DIV pin which determines the divisor as shown
in Table 1. The DIV pin doesn’t have any input hysteresis
near the ratio thresholds.
Table 1. Channel 1 Divisor vs VDIV
Choosing the Switching Frequency
TYPICAL DIV VOLTAGE
The LT3992 switching frequency is set by resistor R3 in
Figure 1. The RT/SYNC pin is driven by a 12µA current
source. Setting resistor R3 sets the voltage present at
the RT/SYNC pin which determines the master oscillator
frequency as illustrated in Figure 2. The R3 resistance
(in kΩ) may be calculated from the desired switching
frequency (in kHz) by the equation:
R3 = 1.86E-6 • fSW 2 + 2.81E-2 • fSW –1.76
for frequencies between 150kHz and 2000kHz. A 0V to
2.5V square wave with the same frequency as the master
oscillator and in phase with channel 1 is output via the
CLKOUT pin. The CLKOUT signal can be used to synchronize multiple switching regulators.
2500
RDIV (Ω)
VDIV < 0.5V
1
0
0.5V < VDIV < 1.0V
2
61.9k
1.0V < VDIV < 1.5V
4
102k
1.5V < VDIV
8
150k
The switching frequency is typically set as high as possible to reduce overall solution size. The LT3992 employs
techniques to enhance dropout at high frequencies but
efficiency and maximum input voltage decrease due to
switching losses and minimum switch on times.
The maximum recommended frequency can be approximated by the equation:
Frequency (Hz) =
VOUT + VD
1
•
VIN – VSW + VD tON(MIN)
where VD is the forward voltage drop of the catch diode (D1
Figure 1), VSW is the voltage drop of the internal switch,
and tON(MIN) in the minimum on-time of the switch.
2250
CLKOUT FREQUENCY (kHz)
FREQUENCY RATIO
2000
1750
1500
1250
1000
750
500
250
0
0
10
20 30 40 50 60 70
RT/SYNC RESISTANCE (kΩ)
80
3992 F02
Figure 2. Switching Frequency vs RT/SYNC Resistance
12
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LT3992
Applications Information
Table 2. Efficiency and Size Comparisons for Different RRT/SYNC Values, 3.3V Output
FREQUENCY (kHz)
RT/SYNC (kΩ)
EFFICIENCY
VVIN1/2 = 12V (%)
VIN(MAX) (V)†
L (µH)*
C (µF)*
C + L (Area, mm2)
250
5.90
88
60
15
120
59.8
500
13.0
87
43
8.2
60
54.6
1000
28.0
84
21
3.3
30
51.9
1500
44.2
82
14
2.2
22
46.9
2250
69.8
78
9
1
15
19.1
†
VIN(MAX) is defined as the highest typical input voltage that maintains constant output voltage ripple.
* Inductor and capacitor values chosen for stability and constant ripple current.
The following example along with the data in Table 2
illustrates the trade-offs of switch frequency selection for
a single input voltage system.
Example:
VIN = 25V, VOUT = 3.3V, IOUT = 2A, tON(MIN) = 180ns,
VD = 0.6V, VSW = 0.4V.
Max Frequency =
Forcing switch off for a minimum time will only occur at the
end of a clock cycle when the boost capacitor needs to be
recharged. This operation has the same effect as lowering the
clock frequency for a fixed off time, resulting in a higher duty
cycle and lower minimum input voltage. The resultant duty
cycle depends on the charging times of the boost capacitor
and can be approximated by the following equation:
3.3+ 0.6
1
•
~ 850kHz
25 – 0.4+ 0.6 180ns
DCMAX =
1
1+
1
B
RT/SYNC ~ 23.2kΩ (Figure 2 )
Input Voltage Range
where B is 3A divided by the typical boost current from
the Electrical Characteristics table.
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined. The
minimum input voltage is determined by either the LT3992’s
minimum operating voltage of ~2.9V, or by its maximum duty
cycle. The duty cycle is the fraction of time that the internal
switch is on during a clock cycle. Unlike most fixed frequency
regulators, the LT3992 will not switch off at the end of each
clock cycle if there is sufficient voltage across the boost
capacitor (C3 in Figure 1) to fully saturate the output switch.
This leads to a minimum input voltage of:
VIN(MIN) =
where VSW is the voltage drop of the internal switch.
Figure 4 shows a typical graph of minimum input voltage
vs load current for the 3.3V output shown in Figure 15.
6
tP
VOUT = 3.3V
5
START-UP
tP/2
VOLTAGE (V)
SW1
tP
SW2
tP/2
RUNNING
4
3
2
tP
1
CLKOUT
tDCLKOSW1
VOUT + VD
– VD + VSW
DCMAX
3992 F03
tDCLKOSW2
0
0
500 1000 1500 2000 2500 3000 3500
CURRENT (mA)
3992 F04
Figure 3. Timing Diagram RT/SYNC = 28.0k, tP = 1µs, VDIV = 0V
Figure 4. Minimum Input Voltage vs Load Current
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LT3992
Applications Information
The maximum input voltage is determined by the absolute
maximum ratings of the VIN and BST pins and by the
frequency and minimum duty cycle. The minimum duty
cycle is defined as:
DCMIN = tON(MIN) • Frequency
Maximum input voltage as:
VIN(MAX) =
VOUT + VD
– VD + VSW
DCMIN
Example:
Note that the LT3992 will regulate if the input voltage is
taken above the calculated maximum voltage as long as
maximum ratings of the VIN and BST pins are not violated.
However operation in this region of input voltage will
exhibit pulse skipping behavior.
Example:
VOUT = 3.3V, IOUT = 1A, frequency = 1MHz, temperature
= 25°C, VSW = 0.1V, B = 50 (from boost characteristics
specification), VD = 0.4V, tON(MIN) = 180ns:
DCMAX =
1
= 98%
1
50
3.3+ 0.4
– 0.4+ 0.1= 3.48V
VIN(MIN) =
0.98
DCMIN = tON(MIN) •Frequency = 0.18
1+
VIN(MAX) =
VIN1(MAX) =
3.3+ 0.4
– 0.4+ 0.1= >60V
0.045
Inductor Selection and Maximum Output Current
A good first choice for the LT3992 inductor value is:
L=
VOUT
f
With this value 3A of load current will be available over
the entire input voltage range. The inductor’s RMS current rating must be greater than your maximum load
current and its saturation current should be higher than
the maximum peak switch current, and will reduce the
output voltage ripple.
If the maximum load for a single channel is lower than
2.5A, then you can decrease the value of the inductor and
operate with higher ripple current, or you can adjust the
maximum switch current for the channel via the ILIM pin.
This allows you to use a physically smaller inductor, or one
with a lower DCR resulting in higher efficiency.
SW1
tP
SW2
tP
The peak inductor and switch current is:
CLKOUT
tDCLKOSW1
DCMIN1 = tON(MIN1) • Frequency/4 = 0.045
where f is frequency in MHz and L is in µH.
2 • tP
tP/2
VOUT = 3.3V, IOUT = 1A, frequency = 1MHz, temperature
= 25°C, VSW = 0.1V, B = 50 (from boost characteristics
specification), VD = 0.4V, tON(MIN) = 180ns. RDIV = 102kΩ.
3.3+ 0.4
– 0.4+ 0.1= 20.2V
0.18
1/(2 • tP)
In cases where multiple input voltages are present, or the
VIN /VOUT ratio for channel 1 is significantly different than
channel 2, channel 1’s frequency can be divided by a factor
of 2, 4 or 8 from the programmed value by setting the DIV
pin resistor to the appropriate value. Dividing channel 1’s
frequency will increase the maximum input voltage by the
same ratio. Channel 1’s external components will have to
be chosen according to the resulting frequency.
3992 F05
tDCLKOSW2
I SW(PK) =IL(PK) =IOUT +
ΔIL
2
Figure 5. Timing Diagram RT/SYNC = 28.0k,
tP = 1µs, VDIV = 0.75V
14
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LT3992
Applications Information
To maintain output regulation, this peak current must be
less than the LT3992’s switch current limit, ILIM. ILIM
can be set between 1.8A and 4.6A for each channel via
a resistor from the ILIM pin to ground. The ILIM pin is
driven by a 12µA current source. Setting resistor RLIM sets
the voltage present at the ILIM pin which determines the
maximum switch current as illustrated in Figure 6. The value
for RLIM must be greater than 42.2k. A capacitor from the
ILIM pin to ground, or a resistor divider from the output,
can be used to limit the peak current during start-up. If a
capacitor is used it must be discharged before power-up
to ensure proper operation.
Referring to Figure 6, as the peak current limit is reduced,
slope compensation further reduces the peak current with
increasing duty cycle.
When the ILIM pin is used to reduce the peak switch current, the equation for inductor choice becomes:
L=
50 • VOUT
f •RILIM
where f is frequency in MHz, L in µH and R in kΩ.
When the LT3992’s input supplies are operated at different
input voltages, an input capacitor sized for that channel
should be placed as close as possible to the respective
VIN pins.
A caution regarding the use of ceramic capacitors at the
input. A ceramic input capacitor can combine with stray
inductance to form a resonant tank circuit. If power is
applied quickly (for example by plugging the circuit into
a live power source) this tank can ring, doubling the input voltage and damaging the LT3992. The solution is to
either clamp the input voltage or dampen the tank circuit
by adding a lossy capacitor in parallel with the ceramic
capacitor. For details, see Application Note 88.
Output Capacitor Selection
Typically step-down regulators are easily compensated with
an output crossover frequency that is 1/10 of the switching frequency. This means that the time that the output
capacitor must supply the output load during a transient
step is ~2 or 3 switching periods. With an allowable 1%
drop in output voltage during the step, a good starting
value for the output capacitor can be expressed by:
4.5
PEAK SWITCH CURRENT (A)
4.0
3.5
Max Load Step
Frequency • 0.01• VOUT
Example:
3.0
VOUT = 3.3V, Frequency = 1MHz, Max Load Step = 2A.
2.5
2.0
1.5
1.0
C VOUT =
40
50
70
90
60
80
ILIM PIN RESISTOR (kΩ)
100
3992 F06
Figure 6. Peak Switch Current vs ILIM Resistor
Input Capacitor Selection
Bypass the inputs of the LT3992 circuit with a 4.7µF or
higher ceramic capacitor of X7R or X5R type. A lower
value or a less expensive Y5V type can be used if there
is additional bypassing provided by bulk electrolytic or
tantalum capacitors.
C VOUT =
2
= 60µF
1E6• 0.01• 3.3V
The calculated value is only a suggested starting value.
Increase the value if transient response needs improvement
or reduce the capacitance if size is a priority. The output
capacitor filters the inductor current to generate an output
with low voltage ripple. It also stores energy in order to
satisfy transient loads and to stabilize the LT3992’s control
loop. The switching frequency of the LT3992 determines
the value of output capacitance required. Also, the current
mode control loop doesn’t require the presence of output
capacitor series resistance (ESR). For these reasons, you
are free to use ceramic capacitors to achieve very low
output ripple and small circuit size.
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LT3992
Applications Information
You can also use electrolytic capacitors. The ESRs of most
aluminum electrolytics are too large to deliver low output
ripple. Tantalum and newer, lower ESR organic electrolytic
capacitors intended for power supply use, are suitable
and the manufacturers will specify the ESR. The choice of
capacitor value will be based on the ESR required for low
ripple. Because the volume of the capacitor determines
its ESR, both the size and the value will be larger than a
ceramic capacitor that would give you similar ripple performance. One benefit is that the larger capacitance may
give better transient response for large changes in load
current. Table 3 lists several capacitor vendors.
BST Pin Considerations
Table 3
VENDOR
TYPE
Taiyo Yuden
Ceramic X5R, X7R
SERIES
AVX
Ceramic X5R, X7R
Tantalum
Kemet
Tantalum
TA Organic
AL Organic
T491, T494, T495
T520
A700
Sanyo
TA/AL Organic
POSCAP
Panasonic
AL Organic
SP CAP
TDK
Ceramic X5R, X7R
Catch Diode
The diode D1 (Figure 1) conducts current only during
switch-off time. Use a Schottky diode to limit forward voltage drop to increase efficiency. The Schottky diode must
have a peak reverse voltage that is equal to regulator input
voltage and sized for average forward current in normal
operation. Average forward current can be calculated from:
ID(AVG) =
IOUT
• ( VIN – VOUT )
VIN
With a shorted condition, diode current will increase to the
typical value determined by the peak switch current limit
of the LT3992 set by the ILIM pin. This is safe for short
periods of time, but it would be prudent to check with the
diode manufacturer if continuous operation under these
conditions can be tolerated.
16
The capacitor and diode tied to the BST pin generate a
voltage that is higher than the input voltage. In most cases
a 0.47µF capacitor and a small Schottky diode (such as the
BAT41) will work well. To ensure optimal performance at
duty cycles greater than 80%, use a 0.5A Schottky diode
(such as a MBR0560). Almost any type of film or ceramic
capacitor is suitable, but the ESR should be <1Ω to ensure
it can be fully recharged during the off time of the switch.
The capacitor value can be approximated by:
C BST =
IOUT(MAX) • VOUT
5 • VIN ( VOUT – 2) • f
where IOUT(MAX) is the maximum load current.
Figure 7 shows four ways to arrange the boost circuit. The
BST pin must be more than 3V above the SW pin for full
efficiency. Generally, for outputs of 3.3V and higher the
standard circuit (Figure 7a) is the best. For lower output
voltages the boost diode can be tied to the input (Figure 7b). The circuit in Figure 7a is more efficient because
the BST pin current comes from a lower voltage source.
Figure 7c shows the boost voltage source from available
DC sources that are greater than 3V. The highest efficiency
is attained by choosing the lowest boost voltage above 3V.
For example, if you are generating 3.3V and 1.8V and the
3.3V is on whenever the 1.8V is on, the 1.8V boost diode
can be connected to the 3.3V output. In any case, you
must also be sure that the maximum voltage at the BST
pin is less than the maximum specified in the Absolute
Maximum Ratings section.
The boost circuit can also run directly from a DC voltage
that is higher than the input voltage by more than 3V, as
in Figure 7d. The diode is used to prevent damage to the
LT3992 in case VX is held low while VIN is present. The
circuit saves several components (both BST pins can be
tied to D2). However, efficiency may be lower and dissipation in the LT3992 may be higher. Also, if VX is absent, the
LT3992 will still attempt to regulate the output, but will do
so with very low efficiency and high dissipation because
the switch will not be able to saturate, dropping 1.5V to
2V in conduction.
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LT3992
Applications Information
D2
VIN
VIN
BST
C3
D2
VIN
SW
VIN
LT3992
IND
VOUT
VOUT
GND
(7b)
D2
VIN
D2
VX > VIN + 3V
VIN
BST
C3
VIN
SW
VIN
BST
SW
LT3992
LT3992
IND
VOUT
VBST – VSW = VX
VBST(MAX) = VIN + VX
VX(MIN) = 3V
VOUT < 3V
GND
VBST – VSW = VIN
VBST(MAX) = 2 • VIN
(7a)
VX = LOWEST VIN
OR VOUT > 3V
C3
SW
LT3992
IND
VOUT
VBST – VSW = VOUT
VBST(MAX) = VIN + VOUT
BST
IND
VOUT
VOUT < 3V
GND
VBST – VSW = VX
VBST(MAX) = VX
VX(MIN) = VIN + 3V
(7c)
VOUT < 3V
GND
3992 F07
(7d)
Figure 7. BST Pin Considerations
The minimum input voltage of an LT3992 application is
limited by the minimum operating voltage (typically 2.9V)
and by the maximum duty cycle as outlined above. For
proper start-up, the minimum input voltage is also limited
by the boost circuit. If the input voltage is ramped slowly,
or the LT3992 is turned on with its SS pin when the output
is already in regulation, then the boost capacitor may not
be fully charged. Because the boost capacitor is charged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on input
and output voltages, and on the arrangement of the boost
circuit. The Typical Performance Characteristics section
shows plots of the minimum load current to start and to
run as a function of input voltage for 3.3V outputs. In many
cases the discharged output capacitor will present a load
to the switcher which will allow it to start. The plots show
the worst-case situation where VIN is ramping very slowly.
Use a Schottky diode for the lowest start-up voltage.
Outputs Greater Than 6V
For outputs greater than 6V, add a resistor of 1k to 2.5k
across the inductor to damp the discontinuous ringing of
the SW node, preventing unintended SW current. The 24V
output circuit in the Typical Applications section shows
the location of this resistor.
Frequency Compensation
The LT3992 uses current mode control to regulate the
output. This simplifies loop compensation. In particular, the
LT3992 does not require the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
VC pin. Generally a capacitor and a resistor in series to
ground determine loop gain. In addition, there is a lower
value capacitor in parallel. This capacitor is not part of
the loop compensation but is used to filter noise at the
switching frequency.
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17
LT3992
Applications Information
Synchronization
Loop compensation determines the stability and transient
performance. Designing the compensation network is a bit
complicated and the best values depend on the application
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the compensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
The RT/SYNC pin can also be used to synchronize the
regulators to an external clock source. Driving the RT/SYNC
resistor with a clock source triggers the synchronization
detection circuitry. Once synchronization is detected, the
rising edge of SW1 will be synchronized to the rising edge
of the RT/SYNC signal and the rising edge of SW2 synchronized to the falling edge of the RT/SYNC signal (see
Figures 10 and 11). During synchronization, a 0V to 2.4V
square wave with the same frequency and duty cycle as
the synchronization signal is output via the CLKOUT pin
with a typical propagation delay of 250ns. In addition, an
internal AGC loop will adjust slope compensation to avoid
subharmonic oscillation. If the synchronization signal is
halted, the synchronization detection circuitry will timeout
in typically 10µs at which time the LT3992 reverts to the
free-running frequency based on the RT/SYNC pin voltage.
The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the
stability using a transient load.
Figure 8 shows an equivalent circuit for the LT3992 control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output current proportional to the voltage at the VC pin. Note that
the output capacitor integrates this current, and that the
capacitor on the VC pin (CC) integrates the error amplifier
output current, resulting in two poles in the loop. In most
cases a zero is required and comes from either the output
capacitor ESR or from a resistor in series with CC.
The synchronizing clock signal input to the LT3992 must
have a frequency between 200kHz and 2MHz, a duty cycle
between 20% and 80%, a low state below 0.5V and a high
state above 1.6V. Synchronization signals outside of these
parameters will cause erratic switching behavior. If the
RT/SYNC pin is held above 1.6V at any time, switching
will be disabled.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (CPL) across the feedback divider may improve
the transient response.
If the synchronization signal is not present during regulator start-up (for example, the synchronization circuitry
is powered from the regulator output) the RT/SYNC pin
must remain below 1V until the synchronization circuitry
is active for proper start-up operation.
LT3992
CURRENT MODE
POWER STAGE
gm = 4.8mho
OUTPUT
gm = 400µmho
3.6M
RC
CF
CC
+
–
VC
ERROR
AMP
R1
CPL
ESR
FB
C1
+
0.806V
R2
C1
CERAMIC
TANTALUM
OR
POLYMER
3992 F08
Figure 8. Model for Loop Response
18
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LT3992
Applications Information
If the synchronization signal powers up in an undetermined
state (VOL, VOH, Hi-Z), connect the synchronization clock
to the LT3992 as shown in Figure 9. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3992
will start up with a switching frequency determined by the
resistor from the RT/SYNC pin to ground.
If the synchronization signal powers up in a low impedance
state (VOL), connect a resistor between the RT/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the RT/SYNC pin to ground will set the startup frequency.
If the synchronization signal powers up in a high impedance state (Hi-Z), connect a resistor from the RT/SYNC
pin to ground. The equivalent resistance seen from the
RT/SYNC pin to ground will set the start-up frequency.
VOUT1
LT3992
PG1
RT/SYNC
tP
SW1
tP
tP/2
SW2
tP
tP/2
CLKOUT
tDCLKOSW1
tDCLKOSW2
tP/2
tP
RT/SYNC
3992 F10
tDRTSYNC
Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50%
tP
VCC
SYNCHRONIZATION
CIRCUITRY
SW1
CLK
tP
3992 F09
SW2
tPON
Figure 9. Synchronous Signal Powered from Regulator’s Output
tP
CLKOUT
tDCLKOSW1
tDCLKOSW2
tPON
tP
RT/SYNC
3992 F11
tDRTSYNCH
tDRTSYNCH
Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%
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19
LT3992
Applications Information
Reducing Input Ripple Voltage
Shutdown and Undervoltage/Overvoltage Lockout
Synchronizing the switches to the rising and falling edges
of the synchronization signal provides the unique ability to
reduce input ripple currents in systems where VIN1 and VIN2
are connected to the same supply. Decreasing the input
current ripple reduces the required input capacitance. For
example, the input ripple voltage shown in Figure 12 for
a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V
regulator is decreased from a peak of 472mV to 160mV
as shown in Figure 13 by driving the LT3992 with a 71%
duty cycle synchronization signal.
Typically, undervoltage lockout (UVLO) is used in situations where the input supply is current limited, or has a
relatively high source resistance. A switching regulator
draws constant power from the source, so source current increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating
at source voltages where these problems might occur.
SW1
SW2
An internal comparator will force both channels into shutdown below the minimum VIN1 of 2.9V. This feature can be
used to prevent excessive discharge of battery-operated
systems. In addition to the VIN1 undervoltage lockout, both
channels will be disabled when SHDN1 is less than 1.32V.
Programmable UVLO may be implemented using an input
voltage divider and one of the internal comparators (see
the Typical Applications section).
INPUT
RIPPLE V
RT/SYNC
3992 F12
Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase
When the SHDN pin is taken above 1.32V, its respective
channel is allowed to operate. When the SHDN pin is
driven below 1.32V, its channel is placed in a low quiescent
current state. There is no hysteresis on the SHDN pins.
Keep the connections from any series resistors to the SHDN
pins short and make sure that the interplane or surface
capacitance to switching nodes is minimized.
SW1
SW2
Soft-Start
INPUT
RIPPLE V
RT/SYNC
3992 F13
Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase
The output of the LT3992 regulates to the lowest voltage
present at either the SS pin or an internal 0.806V reference.
A capacitor from the SS pin to ground is charged by an
internal 12µA current source resulting in a linear output
ramp from 0V to the regulated output whose duration is
given by:
tRAMP =
CSS • 0.806V
12µA
At power-up, a reset signal sets the soft-start latch and
discharges both SS pins to approximately 0V to ensure
proper start-up. When both SS pins are fully discharged
the latch is reset and the internal 12µA current source
starts to charge the SS pin.
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LT3992
Applications Information
When the SS pin voltage is below 110mV, the VC pin is
pulled low which disables switching. This allows the SS
pin to be used as an individual shutdown for each channel.
As the SS pin voltage rises above 110mV, the VC pin is
released and the output is regulated to the SS voltage.
When the SS pin voltage exceeds the internal 0.806V
reference, the output is regulated to the reference. The
SS pin voltage will continue to rise until it is clamped at
typically 2.15V.
when the threshold is exceeded. The CMPO pin is active
(sink capability is reduced in shutdown and undervoltage
lockout mode) as long as the VIN1 pin voltage exceeds
typically 2.9V.
The comparators can be used to monitor input and output
voltages as well as die temperature. See the Typical Applications circuit collection for examples.
Output Tracking/Sequencing
In the event of a VIN1 undervoltage lockout, the soft-start
latch is set for both channels, triggering a full start-up
sequence. If a channel’s SHDN pin is driven below 1.32V,
its overvoltage lockout is enabled, or the internal die
temperature for its power switch exceeds its maximum
rating during normal operation, the soft-start latch is set
for that channel.
Complex output tracking and sequencing between channels
can be implemented using the LT3992’s SS and CMPO
pins. Figure 14 shows several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
In addition, if the load exceeds the maximum output switch
current, the output will start to drop causing the VC pin
clamp to be activated. As long as the VC pin is clamped,
the SS pin will be discharged. As a result, the output will
be regulated to the highest voltage that the maximum
output current can support. For example, if a 6V output is
loaded by 1Ω the SS pin will drop to 0.46V, regulating the
output at 4.6V ( 4.6A • 1Ω ). Once the overload condition
is removed, the output will soft start from the temporary
voltage level to the normal regulation point.
Ratiometric tracking is achieved in Figure 14b by connecting both SS pins together. In this configuration, the
SS pin source current is doubled (24µA) which must be
taken into account when calculating the output rise time.
Since the SS pin is clamped at typically 2.15V and has to
discharge to 0.806V before taking control of regulation,
momentary overload conditions will be tolerated without
a soft-start recovery. The typical time before the SS pin
takes control is:
t SS(CONTROL) =
CSS •1.2V
0.9mA
Open-Collector Comparators
The CMPO pin is the open-collector output of an internal
comparator. The comparator compares the CMPI pin voltage to 90% of the reference voltage (0.72V) with 80mV
of hysteresis.
The CMPO pin has a typical sink capability of 250µA when
the CMPI pin is below the threshold and can withstand 60V
Independent soft-start for each channel is shown in Figure 14a. The output ramp time for each channel is set by
the soft-start capacitor as described in the soft-start section.
By connecting a feedback network from VOUT1 to the SS2
pin with the same ratio that sets VOUT2 voltage, absolute
tracking shown in Figure 14c is implemented. The minimum value of the top feedback resistor (R1) should be set
such that the SS pin can be driven all the way to ground
with 0.9mA of sink current when VOUT1 is at its regulated
voltage. In addition, a small VOUT2 voltage offset will be
present due to the SS2 12µA source current. This offset
can be corrected for by slightly reducing the value of R2.
Figure 14d illustrates output sequencing. When VOUT1 is
within 10% of its regulated voltage, CMPO1 releases the
SS2 soft-start pin allowing VOUT2 to soft-start. In this case
CMPO1 will be pulled up to 2V by the SS pin. If a greater
voltage is needed for CMPO1 logic, a pull-up resistor to
VOUT1 can be used. This will decrease the soft-start ramp
time and increase tolerance to momentary shorts.
If precise output ramp up and down is required, drive the
SS pins as shown in Figure 14e. The minimum value of
resistor (R3) should be set such that the SS pin can be
driven all the way to ground with 0.9mA of sink current
during power-up and fault conditions.
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21
LT3992
Applications Information
Independent Start-Up
Ratiometric Start-Up
Absolute Start-Up
VOUT1
0.5V/DIV
VOUT1
0.5V/DIV
VOUT2
0.5V/DIV
VOUT2
0.5V/DIV
5ms/DIV
LT3992
FB1
CMPI1
+
–
0.1µF
12µA
0.72V
+
–
FB1
CMPI1
2.5V
12µA
0.72V
SS1
+
–
CMPO2
R2
2.5V
PG2
12µA
0.72V
SS2
12µA
PG1
0.72V
R4
R5
FB2
CMPI2
2.5V
PG2
12µA
0.72V
SS2
R8
0.22µF
(14a)
PG1
VOUT2
R6
CMPO2
+
–
+
–
R3
R2
CMPO1
0.1µF
R4
FB2
CMPI2
FB1
CMPI1
2.5V
VOUT2
R5
R1
SS1
R6
VOUT1
R3
CMPO1
0.1µF
FB2
CMPI2
SS2
R1
PG1
R4
LT3992
VOUT1
R3
R2
CMPO1
VOUT2
2.5V
10ms/DIV
LT3992
R1
0.72V
PG2
10ms/DIV
VOUT1
2.5V
VOUT2
0.5V/DIV
PG2
PG2
SS1
PG1
PG1
PG1
12µA
VOUT1
0.5V/DIV
CMPO2
+
–
R6
R5
PG2
R7
(14b)
(14c)
Output Sequencing
Controlled Power Up and Down
VOUT1
0.5V/DIV
VOUT1
0.5V/DIV
PG1/PG2
VOUT2
0.5V/DIV
VOUT2
0.5V/DIV
PG1
SS1/2
PG2
10ms/DIV
10ms/DIV
LT3992
LT3992
VOUT1
VOUT1
R1
FB1
CMPI1
2.5V
12µA
0.72V
SS1
+
–
0.1µF
R1
R2
2.5V
CMPO1
R4
12µA
SS2
0.72V
+
–
CMPO2
0.72V
SS1
+
–
VOUT2
2.5V
12µA
PG1
R5
FB2
CMPI2
FB1
CMPI1
+
–
R2
CMPO1
PG1
VOUT2
R4
R6
R5
FB2
CMPI2
2.5V
PG2
R3
12µA
SS2
0.72V
+
–
0.22µF
R6
R5
CMPO2
PG2
3992 F14
(14d)
(14e)
Figure 14. SS Pin Configurations
22
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LT3992
Applications Information
Application Optimization
For example, assume a maximum input of 60V:
In multiple channel applications requiring large VIN to
VOUT ratios, the maximum frequency and resulting inductor size is determined by the channel with the largest
ratio. The LT3992’s multi-frequency operation allows the
user to minimize component size for each channel while
maintaining constant frequency operation. The circuit in
Figure 15 illustrates this approach. A 2-stage step-down
approach coupled with multi-frequency operation will
further reduce external component size by allowing an
increase in frequency for the channel with the lower VIN
to VOUT ratio. The drawback to this approach is that the
output power capability for the first stage is determined by
the output power drawn from the second stage. The dual
step-down application in Figure 16 steps down the input
voltage (VIN1) to the highest output voltage then uses that
voltage to power the second output (VIN2). VOUT1 must be
able to provide enough current for its output plus VOUT2
maximum load. Note that the VOUT1 voltage must be above
VIN2’s minimum input voltage as specified in the Electrical
Characteristics (typically 2.9V) when the second channel
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing
with the CMP01 output.
VIN = 60V, VOUT1 = 3.3V at 1.5A and VOUT2 = 12V at 1.5A.
Frequency (Hz) =
L=
VOUT + VD
1
•
VIN – VSW + VD tON(MIN)
( VIN – VOUT ) • VOUT
VIN • f
Single Step-Down:
3.3+ 0.6
1
•
≅ 350kHz
60V – 0.4+ 0.6 180ns
(60V – 3.3) • 3.3 ≥ 9µH
L1=
60V • 350kHz
(60V – 12) •12 ≥ 27µH
L2 =
60V • 350kHz
Frequency (Hz) =
2-Stage Step-Down:
12+ 0.6
1
•
≅ 1MHz
60V – 0.4+ 0.6 180ns
(60V – 12) •12 ≥ 10µH
L1=
60V •1MHz
Frequency (Hz) =
L2 =
(12 – 3.3) • 3.3 ≥ 2.4µH
12 •1MHz
2-Stage Step-Down Multi-Frequency:
RDIV = 61.9k, FREQ1 = 900kHz, FREQ2 = 1800kHz.
L1=
(60V – 12) •12 ≥ 11µH
L2 =
(12 – 3.3) • 3.3 ≥ 1.3µH
60V • 900kHz
12 •1800kH z
In addition, RILIM2 = 52.3k reduces the peak current limit
on Channel 2 to 2.5A, which reduces inductor size and
catch diode requirements.
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23
LT3992
Applications Information
VIN1
15V TO 60V
4.7µF
4.7µF
VIN2
VIN1
SHDN1
VOUT1
3.3V
1.5A
200kHz
22µH
0.47µF
BST2
SW1
SW2
IND1
LT3992
VOUT1
100µF
×2
100k
24.9k
8.06k
SHDN2
BST1
FB1
PG1
1000pF
CMPO1
CMPO2
SS2
ILIM2
VC2
60.4k
13k
DIV
10k
0.22µF
113k
FB2
CMPI2
RT/SYNC
33pF
22µH
VOUT2
CMPI1
SS1
ILIM1
VC1
0.1µF
IND2
VOUT1
CLKOUT
TJ
GND
100k
PG2
ILIM1
CLKOUT
400kHz
10nF
61.9k
47µF
8.06k
VOUT2
12V
1.5A
400kHz
0.1µF
680pF
33pF
15k
3992 F15
Figure 15. 12V and 3.3V Dual Step-Down Multi-Frequency Converter
VIN1
15V TO 60V
4.7µF
VOUT2
VIN2
VIN1
SHDN1
22µH
0.1µF
VOUT1
12V
1A
400kHz
BST1
BST2
SW1
SW2
IND1
IND2
VOUT1
100k
10µF
8.06k
113k
SHDN2
LT3992
FB1
PG
0.1µF
60.4k
680pF
CMPO1
CMPO2
15k
DIV
48.7k
102k
24.9k
FB2
CMPI2
SS2
ILIM2
VC2
RT/SYNC
CLKOUT
GND
0.1µF
VOUT2
3.3V
2A
47µF 1600kHz
VOUT2
CMPI1
SS1
ILIM1
VC1
33pF
2.2µH
TJ
FB1
8.06k
ILIM1
CLKOUT
1600kHz
10nF
33pF
470pF
0.1µF
16k
3992 F16
Figure 16. 12V and 3.3V 2-Stage Multi-Frequency Step-Down Converter
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LT3992
Applications Information
Shorted and Reverse Input Protection
If the inductor is chosen so that it won’t saturate excessively, an LT3992 step-down regulator will tolerate a shorted
output. There is another situation to consider in systems
where the output will be held high when the input to the
LT3992 is absent. This may occur in battery charging
applications or in battery back-up systems where a battery
or some other supply is diode OR-ed with the LT3992’s
output. If the VIN1/2 pin is allowed to float and the SHDN
pin is held high (either by a logic signal or because it is
tied to VIN), then the LT3992’s internal circuitry will pull its
quiescent current through its SW pin. This is fine if your
system can tolerate a few mA in this state. If you ground
the SHDN pin, the SW pin current will drop to essentially
zero. However, if the VIN pin is grounded while the output
is held high, then parasitic diodes inside the LT3992 can
pull large currents from the output through the SW pin
and the VIN1/2 pin. Figure 17 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
at one location, ideally at the ground terminal of the output capacitor C2. Route all small signal analog returns
to the ground connection at the bottom of the package.
Additionally, the SW and BST traces should be kept as
short as possible.
VIN LT3992 SW
GND
(18a)
VIN LT3992 SW
GND
(18b)
VIN LT3992 SW
PARASITIC DIODE
D4
VIN1/2
GND
VIN
SW
VOUT1/2
(18c)
LT3992
3992 F17
Figure 17. Diode D4 Prevents a Shorted Input from Discharging a
Backup Battery Tied to the Output
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 18
shows the high di/dt paths in the buck regulator circuit.
Note that large switched currents flow in the power switch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit board and their connections should be made on that
layer. Place a local, unbroken ground plane below these
components, and tie this ground plane to system ground
3992 F18
Figure 18. Subtracting the Current When the Switch Is On (18a)
from the Current When the Switch Is Off (18b) Reveals the Path of
the High Frequency Switching Current (18c). Keep this Loop Small.
The Voltage on the SW and BST Traces Will Also Be Switched; Keep
These Traces As Short As Possible. Finally, Make Sure the Circuit
Is Shielded with a Local Ground Plane
Thermal Considerations
The PCB must also provide heat sinking to keep the LT3992
cool. The exposed metal on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to other copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3992.
Place additional vias near the catch diodes. Adding more
copper to the top and bottom layers and tying this copper
to the internal planes with vias can further reduce thermal
resistance. The topside metal and component outlines
in Figure 19 illustrate proper component placement and
trace routing.
3992fa
For more information www.linear.com/LT3992
25
LT3992
Applications Information
3992 F19
Figure 19. PCB Top Layer and Component Placement for TSSOP and QFN Packages
The LT3992’s powerful 4.6A switches allow the converter
to source large output currents. Depending on the converter’s operating conditions, the resulting internal power
dissipation can raise the junction temperature beyond
its maximum rating. Operating conditions include input
voltages, output voltages, switching frequencies, output
currents, and the ambient environmental temperature,
etc. An estimation of the junction temperature rise above
ambient temperature helps determine whether a given
design may exceed the maximum junction ratings for
specific operating conditions. However, temperature rise
depends on PCB design and the proximity to other heat
sources. The final converter design must be evaluated
on the bench.
as heat sources. After the operating conditions have been
determined, the individual power losses are calculated by:
⎛ V ⎞
PowerD1,2 = ⎜ 1− OUT ⎟ •IOUT • VFD
VIN ⎠
⎝
An estimation of the junction temperature rise begins by
determining which circuit components dissipate power.
In order to simplify the power loss estimation, only the
inductors, catch diodes, and the LT3992 will be considered
where:
26
PowerIND1,2 = RIND •IOUT 2
V
PowerCH1,2 = 0.1• OUT •I OUT 2 + 2•10 –3
VIN
IOUT • VOUT • VBOOST
•VIN +
+
40• VIN
⎛ VIN IOUT ⎞
VIN •IOUT • fSW •10 −6 • ⎜
+
⎝ 2.5 0.25 ⎟⎠
fSW = Switching Frequency in kHz
RIND =Inductor Resis tance
VFD = Catch Diode Forward Voltage Drop
VBOOST = Switch Boost Voltage
3992fa
For more information www.linear.com/LT3992
LT3992
Applications Information
For the LT3992 demo board using the TSSOP package,
the estimated junction temperature rise above ambient
temperature is found by:
TRISETSSOP ≈ 10•(PowerD1 +PowerD2 )+
12.3•(PowerIND1 +Power IND2)+17.5•
(PowerCH1 +PowerCH2 )
The estimated junction temperature rise above ambient
for the LT3992 QFN layout is:
TRISEQFN ≈ 8.5•(Power D1+Power D2)+
13•(Power IND1+Power IND2)+ 23•
(PowerCH1 +PowerCH2 )
For example, the typical application circuits listed in Table 4
are used to calculate the individual power loss contributions in Table 5. Table 6 shows the estimated power loss
and junction temperature rise above ambient temperature.
Note that the larger TSSOP package demonstrates better
thermal performance than the compact QFN package on
the LT3992 demo circuit boards. For LT3992 applications
that favor thermal performance, the TSSOP package is
the preferred package option.
Table 4
APPLICATION
VIN1 VIN2
(V) (V)
fSW
CH1
fSW
CH2
VOUT1 IOUT1 VOUT2 IOUT2
(V)
(A)
(V)
(A)
Front Page
48
12
400
1600
12
1.5
5
2
Back Page
48
48
300
300
5
2
3
2
Table 5
APPLICATION
PD1
(W)
PD2
(W)
PL1
(W)
PL2
(W)
PCH1
(W)
PCH2
(W)
Front Page
0.54
0.56
0.23
0.28
0.99
0.79
Back Page
0.88
0.92
0.28
0.2
0.95
0.91
Table 6
PLOSS (W)
TRISE TSSOP (°C)
TRISE QFN (°C)
rise. However, the LT3992 is a very versatile converter.
The combination of independent input voltages, output
voltages, output currents, switching frequencies, and
package selections for the LT3992 dictate that no power
loss estimation scheme can accommodate every possible
operating condition. As such, it is absolutely necessary to
evaluate a converter’s performance at the bench.
The power dissipation in the other power components such
as boost diodes, input and output capacitors, inductor
core loss, and trace resistances cause additional copper
heating and can further increase what the IC sees as ambient temperature. See the LT1767 data sheet’s Thermal
Considerations section.
Die Temperature and Thermal Shutdown
The LT3992 TJ pin outputs a voltage proportional to the
internal junction temperature. The TJ pin typically outputs
250mV for 25°C and has a slope of 10mV/°C. Without the
aid of external circuitry, the TJ pin output is valid from 20°C
to 150°C (200mV to 1.5V) with a maximum load of 100µA.
Full Temperature Range Measurement
To extend the operating temperature range of the TJ output below 20°C, connect a resistor from the TJ pin to a
negative supply as shown in Figure 20. The negative rail
voltage and TJ pin resistor may be calculated using the
following equations:
2 • TEMP(MIN)°C
100
|V |
R1 ≤ NEG
33µA
where:
VNEG ≤
TEMP(MIN)°C is the minimum temperature where a
valid TJ pin output is required.
VNEG = Regulated negative voltage supply.
APPLICATION
CALC
MEAS
CALC
MEAS
CALC
MEAS
Front Page
3.38
3.2
48.3
46.1
56.8
53.3
For example:
Back Page
4.14
4.2
56.4
53.0
64.3
62.9
TEMP(MIN)°C = –40°C
The power loss and temperature rise equations provided
in the Thermal Considerations section serve as a good
starting point for estimating the junction temperature
VNEG ≤ –0.8V
VNEG = –1, R1 ≤ |VNEG|/33µA = 30.2kΩ
3992fa
For more information www.linear.com/LT3992
27
LT3992
Applications Information
LT3992
TJ
R1
VNEG
GND
+
3992 F20
Figure 20. Circuit to Extend the TJ Pin Operating Range
TJ
LT3992
30k
330pF
Other Linear Technology Publications
D4
CLKOUT
GND
D3, D4: ZETEX BAT54S
0.1µF
D3
the CLKOUT pin, resulting in an output synchronization
clock signal phase delay. Figures 22 and 23 show the impact of capacitive loading on the CLKOUT signal rise and
fall times. Note that a typical 10:1 150MHz oscilloscope
probe contributes significant capacitance to the CLKOUT
node, necessitating a low capacitance probe for accurate
measurements. Applications requiring CLKOUT to generate
the negative supply voltage and provide the synchronization clock to other regulators may benefit from buffering
CLKOUT prior to the charge pump circuitry.
3992 F21
Figure 21. Circuit to Generate the Negative Voltage Rail to
Extend the TJ Pin Operating Range
Generating a Negative Regulated Voltage
The simple charge pump circuit in Figure 21 uses the
CLKOUT pin output to generate a negative voltage, eliminating the need for an external regulated supply. Surface
mount capacitors and dual-package Schottky diodes
minimize the board area needed to implement the negative voltage supply.
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note DN100
shows how to generate a dual (+ and –) output supply
using a buck regulator.
500mV/DIV
As a safeguard, the LT3992 has an additional thermal
shutdown threshold set at a typical value of 163°C for each
channel. Each time the threshold is exceeded, a power on
sequence for that channel will be initiated. The sequence
will then repeat until the thermal overload is removed.
It should be noted that the TJ pin voltage represents
a steady-state temperature and should not be used to
guarantee that maximum junction temperatures are
not exceeded. Instantaneous power along with thermal
gradients and time constants may cause portions of the
die to exceed maximum ratings and thermal shutdown
thresholds. Be sure to calculate die temperature rise for
steady state (>1Min) as well as impulse conditions.
CLKOUT Capacitive Loading
A minor drawback to generating a negative rail from the
CLKOUT pin is that the charge pump adds capacitance to
28
CHARGE PUMP
SCOPE PROBE: 15pF
SYNCHRONIZED LT3992
RT/SYNC PIN
FET PROBE: 2pF
40ns/DIV
FREQUENCY: 1.000MHz
3992 F22
Figure 22. CLKOUT Rise Time
CHARGE PUMP
SCOPE PROBE: 15pF
SYNCHRONIZED
LT3992 RT/SYNC PIN
500mV/DIV
FET PROBE: 2pF
20ns/DIV
FREQUENCY: 1.000MHz
3992 F23
Figure 23. CLKOUT Fall Time
3992fa
For more information www.linear.com/LT3992
VOUT1
5V
1.5A
300kHz
0.1µF
100k
33pF
11.8k
1000pF
8.06k
34.8k
42.2k
15µH
4.7µF
For more information www.linear.com/LT3992
102k
DIV
GND
TJ
CLKOUT
ILIM1
VC1
RT/SYNC
SS2
ILIM2
VC2
SS1
CMPO2
CMPO1
FB2
VOUT2
IND2
CMPI2
LT3992
SW2
SHDN2
BST2
VIN2
CMPI1
FB1
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
10nF
16.9k
2.2µH
33pF
100pF
0.1µF
16.9k
470pF
8.06k
1µF
47µF
42.2k
100k
8.06k
10k
0.1µF
CLOCKOUT
1200kHz
PG
VOUT2
2.5V
1A
1200kHz
8.06k
4.02k
VOUT3
1.2V
1A
1200kHz
42.2k
8.06k
100µF
0.1µF
33pF
4.02k
2.2µH
10k
470pF
100pF
1µF
DIV
SS2
ILIM2
VC2
TJ
CLKOUT
GND
RT/SYNC
ILIM1
VC1
SS1
CMPO2
CMPI2
FB2
VOUT2
IND2
SW2
SHDN2
BST2
VIN2
LT3992
CMPO1
CMPI1
FB1
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
10nF
10k
2.2µH
33pF
0.1µF
100pF
15k
470pF
8.06k
1µF
3992 TA02
42.2k
VOUT4
1.8V
47µF 1A
1200kHz
Typical Applications
47µF
0.47µF
VIN
7V TO 60V
Quad Output 5V, 2.5V, 1.8V and 1.2V Multi-Frequency Synchronized, 2-Stage
Converter with Output Sequencing, Absolute Tracking and Current Limiting
LT3992
29
3992fa
LT3992
TYPICAL APPLICATIONS
24V and 5V 2-Stage Dual Step-Down Converter
VIN1
25V TO 60V
4.7µF
VOUT2
VIN2
VIN1
SHDN1
BST1
22µH
0.1µF
VOUT1
24V
0.5A
1MHz
2k
SW1
SW2
IND1
IND2
VOUT1
100k
10µF
8.06k
232k
PG
SHDN2
BST2
LT3992
33pF
FB1
42.2k
28k
42.2k
FB2
CMPI1
CMPI2
CMPO1
CMPO2
SS2
ILIM2
VC2
RT/SYNC
470pF
0.1µF
DIV
VOUT2
5V
2A
47µF 1MHz
VOUT2
SS1
ILIM1
VC1
0.1µF
4.7µH
CLKOUT
TJ
GND
FB1
CLKOUT
1MHz
10nF
28k
8.06k
33pF
0.1µF
680pF
10k
100k
3992 TA03
3.3V/5A Single Output with UVLO and Power Good
VIN
5V TO 18V
60V TRANSIENT
4.7µF
×2
130k
374k
SHDN2
CMPI2
BST1
CMPO2
SW1
ILIM1
IND1
ILIM2
820pF
CLKOUT
1MHz
33pF
LT3992
20k
28k
10nF
VOUT2
SS2
BST2
VC1
SW2
VC2
IND2
CLKOUT
FB1
RT/SYNC
CMPI1
DIV
0.22µF
4.7µH
0.22µF
4.7µH
24.9k
8.06k
FB2
GND
VOUT
3.3V
47µF 5A
2MHz EFFECTIVE RIPPLE
×2
VOUT1
SS1
TJ
0.1µF
60.4k
VIN2
VIN1
SHDN1
CMPO1
100k
PG
3992 TA04
30
3992fa
For more information www.linear.com/LT3992
LT3992
TYPICAL APPLICATIONS
Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter
VIN1
12V
4.7µF
1µF
47.5k
13k
0.1µF
CLKOUT
2MHz
33pF
64.9k
61.9k
SHDN2
CMPI2
BST1
CMPO2
SW1
SS1
IND1
LT3992
VOUT2
LIM2
BST2
VC1
SW2
VC2
IND2
CLKOUT
FB1
RT/SYNC
CMPI1
0.22µF
2.2µH
47µF
VOUT
3.3V
4A
0.22µF
2.2µH
24.9k
8.06k
FB2
TJ
21k
SHDN1
VOUT1
LIM1
DIV
61.9k
42.2k
VIN2
VIN1
SHDN1
SS2
680pF
VIN2
5V
GND
10nF
CMPO1
3992 TA05
5V and 1.8V Dual 2-Stage Converter
VIN1
7V TO 60V
1µF
4.7µF
VIN1
VIN2
SHDN1
BST1
SHDN2
BST2
SW2
SW1
15µH
0.22µF
VOUT1
5V
1A
400kHz
IND1
LT3992
100k
42.2k
8.06k
PG
FB1
CMPI2
CMPO1
CMPO2
21k
13k
ILIM2
VC2
RT/SYNC
DIV
33pF
48.7k
102k
VOUT2
1.8V
1A
47µF 1600kHz
100pF
FB1
8.06k
SS2
ILIM1
VC1
0.1µF
0.22µF
10k
FB2
CMPI1
SS1
820pF
2.2µH
VOUT2
VOUT1
22µF
IND2
CLKOUT
GND
TJ
ILIM1
CLOCKOUT
1600kHz
33pF
0.1µF
470pF
10nF
21k
3992 TA06
3992fa
For more information www.linear.com/LT3992
31
32
22.1k
VIN
13V TO 60V
0.1µF
33pF
7.5k
28k
10nF
CLKOUT
1MHz
ON OFF
1300pF
2.2µF
×2
VOUT1
IND1
BST1
SW1
VIN2
GND
CMPO2
DIV
CMPI2
CMPO1
TJ
RT/SYNC
CMPI1
FB2
FB1
IND2
BST2
SW2
LT3992 VOUT2
CLKOUT
VC2
VC1
SS2
SS1
ILIM2
ILIM1
SHDN2
SHDN1
VIN1
22µH
22µH
133k
8.06k
0.22µF
0.22µF
VOUT2
0.1µF
113k
For more information www.linear.com/LT3992
OUT1
OUT2
MOD
GND
SET
LTC6908-1
V+
PG
200k
VOUT1
12V
0.5A
1MHz
22µF
×2
VOUT2
1.2V
3A
500kHz
VOUT3
0.1µF
100k
8.06k
100µF
×2
33pF
0.1µF
4.02k
2.2µH
SHDN1
7.68k
1000pF
100pF
1µF
61.9k
DIV
SS2
ILIM2
VC2
TJ
CLKOUT
GND
RT/SYNC
ILIM1
VC1
SS1
CMPO2
CMPI2
FB2
VOUT2
IND2
SW2
SHDN2
BST2
VIN2
LT3992
CMPO1
CMPI1
FB1
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
12V, 3.3V and 1.2V Triple Output with External Synchronization, Output Sequencing and Tracking
10nF
SS1
24.9k
2.2µH
SHDN1
33pF
1µF
16k
3992 TA07
470pF
8.06k
100pF
0.1µF
100k
VOUT3
3.3V
3A
100µF 1MHz
LT3992
TYPICAL APPLICATIONS
3992fa
LT3992
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1
0.25
REF
19
1.20
(.047)
MAX
0° – 8°
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AA) TSSOP REV C 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3992fa
For more information www.linear.com/LT3992
33
LT3992
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
34
0.25 ± 0.05
0.50 BSC
3992fa
For more information www.linear.com/LT3992
LT3992
Revision History
REV
DATE
DESCRIPTION
A
04/13
Clarified Typical Switching Frequency
PAGE NUMBER
3
Clarified Block Diagram
10
Clarified Figure 1 call out in last paragraph
Clarified Applications Information
12
14, 16
3992fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT3992
35
LT3992
Typical Application
FMEA Fault Tolerant 5V/2A and 3.3V/2A Dual Converter
VIN1
6V TO 60V
4.7µF
SHDN2
VOUT1
5V
2A
300kHz
15µH
0.47µF
249k
100µF
806Ω
4.22k
100k
PG
SS2
ILIM2
33pF
SHDN1
SHDN2
BST1
BST2
SW1
SW2
IND1
VOUT1
FB1
LT3992
10nF
11.8k
IND2
VOUT2
FB2
CMPI1
CMPI2
CMPO1
CMPO2
SS1
ILIM1
VC1
SS2
ILIM2
VC2
RT/SYNC
1000pF
DIV
4.7µF
100k
VIN2
VIN1
CLKOUT
GND
TJ
7.15k
10µH
0.47µF
2.49k
100k
806Ω
100µF
249k
VOUT2
3.3V
2A
300kHz
PG2
CLKOUT
300kHz
10nF
1000pF
12.1k
33pF
100nF
60.4k
3992 TA08
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LT3692/
LT3692A
36V, Dual 3.5A, 2.25MHz High Efficiency Step-Down
DC/DC Converter
VIN = 3V to 36V, VOUT(MIN) = 0.8V, IQ = 4mA, ISD < 10µA,
5mm × 5mm QFN-32, TSSOP-38E
LT3507/
LT3507A
36V, Triple 2.4A, 1.4A and 1.4A (IOUT), 2.5MHz, High
Efficiency Step-Down DC/DC Converter with LDO Controller
VIN = 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD = 1µA,
5mm × 7mm QFN-38
LT3508
36V with Transient Protection to 40V, Dual 1.4A (IOUT), 3MHz,
High Efficiency Step-Down DC/DC Converter
VIN = 3.7V to 37V, VOUT(MIN) = 0.8V, IQ = 4.6mA, ISD = 1µA,
4mm × 4mm QFN-24, TSSOP-16E
LT3680
36V, 3A, 2.4MHz High Efficiency Micropower Step-Down
DC/DC Converter
VIN = 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 75µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3693
36V, 3A, 2.4MHz High Efficiency Step-Down DC/DC Converter
VIN = 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 1.3mA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3480
36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode® Operation
VIN = 3.6V to 38V, Transients to 60V, VOUT(MIN) = 0.78V,
IQ = 70µA, ISD < 1µA, 3mm × 3mm DFN-10, MSOP-10E
LT3980
58V with Transient Protection to 80V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
VIN = 3.6V to 58V, Transients to 80V, VOUT(MIN) = 0.79V,
IQ = 75µA, ISD < 1µA, 3mm × 4mm DFN-16, MSOP-16E
LT3971
38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.8µA of Quiescent Current
VIN = 4.2V to 38V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3991
55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.8µA of Quiescent Current
VIN = 4.2V to 55V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
36 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT3992
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LT3992
3992fa
LT 0413 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2012