Application Notes

AN11060
TEA172X 5 W to 11 W Power Supply/USB charger
Rev. 1.2 — 8 June 2012
Application note
Document information
Info
Content
Keywords
Ultra-low standby power, constant output voltage, constant output current,
primary sensing, integrated high-voltage switch, integrated high-voltage
start-up, USB charger, standby supply, 5 W to 11 W supply.
Abstract
The TEA172X are primary sensing controllers for power supplies up to
5 W or 11 W (depending on version) with an integrated high-voltage
switch. No-load power is as low as 10 mW (depending on version) and
they surpass the Energy Star 5 level requirement (30 mW).
When the maximum output power is exceeded, the IC changes from
constant voltage mode to constant current mode, which is ideally suited for
battery charging.
AN11060
NXP Semiconductors
TEA172X 5 W to 11 W Power Supply/USB charger
Revision history
Rev
Date
Description
v.1.2
20120608
third issue
v.1.1
20120501
second issue
v.1
20120130
first issue
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
AN11060
Application note
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1. Introduction
The TEA172X family comprise a flyback controller with primary sensing and integrated
high-voltage switch. An advanced burst mode and integrated high-voltage start-up circuit
ensure a low no-load power consumption, depending on the version down to 10 mW.
When the maximum output power is reached, the constant output voltage control changes
to a constant output current control for use as a charger. Versions are available for
maximum output power of 5 W or 11 W.
The device is packaged in a space saving SO7 package with high-voltage spacer.
All values mentioned in this application note are typical values. The minimum and
maximum and spread figures can be found in the TEA172X data sheet.
2. Scope
This application note describes the functionality, the control functions and the basic
dimensioning of the circuit components of the TEA172X low-power adapter. Detailed
transformer calculation is available in a separate calculation sheet.
3. TEA172X low-power adapter
The TEA172X features enable power engineers to design reliable, cost-effective and
efficient adapter supplies with low no-load power consumption. These features result in
the TEA172X needing a minimum number of external components.
3.1 Key features
• Flyback controller with integrated 700 V MOSFET
• Available maximum output power of 5 W or 11 W
• No-load power consumption down to 10 mW at 5 W output power depending on the
version
• Primary sensed output voltage control, eliminating optocoupler for lower overall
system costs.
• High average efficiency above 75 % over the entire load range thanks to advanced
control modes.
• USB 1.1 and 1.2 compliant for mobile phone chargers
• Available in SO7 package with high-voltage spacer
3.1.1 Applications
• Mobile communications
– Mobile or smart phone charger
– Tablet PC charger
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• Home appliances
– Washing and drying machines
– Refrigerators and freezers
– Dish washers
– Induction cookers
– Air conditioners
• Computing and consumer
– E-readers
– Portable audio/video equipment
– Set-top boxes
– PC peripherals
• Industrial and residential
– Smart metering
– Lighting
– Home and building automation
– Heating, Ventilation, Air Conditioning (HVAC) equipment
– Industrial automation and control
3.2 Basic application schematic
Rpreload
Rinrush
+
VOUT
-
VCC
FB
DRAIN
TEA172x
GND
SOURCE
aaa-000872
Fig 1.
AN11060
Application note
Basic application schematic
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4. Pin description
7
DRAIN
3
6
SOURCE
4
5
VCC
GND1
1
GND2
2
GND3
FB
TEA172x
aaa-001539
Fig 2.
Table 1.
Pinning diagram SO7 TEA172X
Pinning description
Pin
Name
Description
1
GND1
2
GND2
3
GND3
Ground connection from driver and control part. Pins GND1 and
GND3 are thermally connected to the MOSFET and must be
connected to a copper plane for efficient cooling.
4
FB
Feedback input. Senses the voltage on the auxiliary winding via a
resistive divider during the secondary stroke. The sense voltage
represents the voltage on the output winding
At constant output voltage, the sensed voltage is regulated at 2.5 V.
When the sensed voltage drops below 2.5 V, the regulation changes
to Constant Current (CC) mode. The OverVoltage Protection (OVP)
level is 3.2 V
Demagnetization detection guarantees discontinuous operation. It
checks that the voltage of the auxiliary winding drops below 50 mV
after the secondary stroke.
AN11060
Application note
5
VCC
Supply voltage. At start-up, an internal current source charges the
capacitor until VCC(startup). VCC(startup) level is around 17 V. The device
starts switching and the auxiliary winding takes over the supply. The
VCC(stop) level on the VCC pin is 8.5 V.
6
SOURCE
SOURCE connection of the internal MOSFET. The current through
the MOSFET is monitored using a resistor from the SOURCE pin to
ground. The peak level in burst mode is around 120 mV. The peak
level in other modes varies between 120 mV and 600 mV. (Exact
values depend on the dV/dt value of the SOURCE pin.
7
DRAIN
DRAIN connection of the internal MOSFET. The breakdown voltage is
700 V. The high-voltage start-up current source is connected to the
DRAIN pin.
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5. System description
5.1 Introduction
Throughout this section, refer to the basic application schematic, Figure 1
5.2 Supply
At start-up, an internal current source, connected to the DRAIN charges the capacitor
connected to the VCC pin see Figure 3.
When the voltage level reaches 17 V (VCC(startup)), the internal current source is switched
off and the IC starts switching. The IC now runs using the charge on the capacitor
connected to the VCC pin.
When the internal MOSFET starts switching, the voltage, generated at the auxiliary supply
winding of the transformer provides the supply, see Figure 4. Under some circumstances,
the IC does not start switching (due to protection) or the auxiliary winding does not provide
the supply voltage. The result is, the capacitor VCC pin voltage drops to 8.5 V (VCC(stop)),
and the internal current source is enabled. The internal current source now charges the
capacitor up to 17 V (VCC(startup)). The sequence is repeated, see Figure 5
It is possible to supply the IC externally, however the supply voltage must be above 17 V
(VCC(startup)) with some margin to guarantee start-up. The rise time of the external supply
voltage must be below 0.1 V/μs. If steeper, use a filter of for example, a 220 Ω series
resistor and a 1 μF decoupling capacitor on the VCC pin. The example used is based
upon a 20 V external supply.
Rpreload
Rinrush
+
VOUT
-
(1)
VCC
(2)
DRAIN
FB
TEA172x
GND
SOURCE
aaa-000889
(1) Auxiliary winding also provides VCC
(2) Primary sensing via auxiliary winding
Fig 3.
AN11060
Application note
Charging the VCC capacitor
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Rpreload
Rinrush
+
VOUT
-
(1)
VCC
(2)
DRAIN
TEA172x
FB
GND
SOURCE
aaa-000890
(1) Auxiliary winding also provides VCC
(2) Primary sensing via auxiliary winding
Fig 4.
Rectified voltage of the auxiliary winding takes over the VCC supply
VCC
(2)
(2)
VCC(startup)
17 V
VCC(stop)
8.5 V
(1)
(3)
(4)
(1)
aaa-000891
(1) HV current source on
(2) HV current source off
(3) Switching start, VAUX builds up
(4) VAUX takes over VCC
Fig 5.
AN11060
Application note
Voltage on the VCC pin
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5.3 Operating modes
From no-load to maximum load and in CC mode, the TEA172X uses different operating
modes as follows.
Rpreload
Rinrush
+
VOUT
Lp
VCC
FB
DRAIN
TEA172x
GND
SOURCE
lpk
I
aaa-000892
Fig 6.
Basic circuit and relevant parameters
The regulation of a flyback converter is based upon regulating the transferred energy
according to Equation 1.
2
P o = 0.5 × L p × I pk × f sw × η
(1)
Where:
•
•
•
•
•
Po = Output power
Lp = Primary inductance of the transformer
Ipk = The peak value of the primary current at switch-off from the MOSFET
fsw = Switching frequency
η = Efficiency convertor
The output power is equal to the energy, stored per stroke, times the number of strokes
per second times the efficiency. Though not accurate, the basic formula is enough to
understand the control modes.
The different operating modes include:
•
•
•
•
•
AN11060
Application note
Constant Voltage Burst mode (CVB) regulation control
Constant Voltage peak Current mode (CVC) regulation control
Constant Voltage Frequency mode (CVF) regulation control
Constant Current Frequency mode (CCF) regulation control
Constant Current peak Current mode (CCC) regulation control
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5.3.1 Burst mode
Figure 7 shows burst mode with energy saving.
At fixed time intervals, the burst period is started. Each burst period starts with one stroke
at a fixed Ipk level. After the stroke, the voltage is sensed at the FB pin near the end of the
secondary stroke. If the sensed voltage is equal or above 2.5 V, no additional strokes are
made. The IC now enters energy save mode until the next burst period. If the sensed
voltage at the FB pin is below 2.5 V, additional strokes are made. This action continues
until the sensed voltage level on the FB pin rises above 2.5 V. Thereafter, the IC goes into
energy save mode until the next burst period.
(1)
(2)
Iprim
(3)
0.08 A
1
2
3
1
44 μs = tswitch
1.13 ms = tburst
VOUT
(4)
(5)
5.10 V
Isupply
600 μA
130 μA
(6)
aaa-000893
(7)
(1) Start of burst
(2) End of burst
(3) Minimum supply current for energy save. Only the oscillator active
(4) VOUT(pk) reaches control value in 1 or 2 cycles
(5) IC switches to minimum supply current, energy save
(6) IC switches to nominal supply just before new burst start.
Timing and currents given are for TEA1721BT version with a fburst = 885 Hz
Fig 7.
Burst mode with energy saving
The fixed time interval between the start of the burst period enables the calculation of the
required output capacitor to fulfill the load step of the USB 1.1 specification (VOUT > 4.1 V
for IOUT load step from 0 => 0.5 A). The primary sensing concept cannot detect any
changes on secondary side while the IC is not switching. During the time between burst
periods, the output capacitor has to manage the load changes.
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Iprim
1
1
1.13 ms = tburst
Iload
0.50 A
0.00 A
VOUT
4.85 V
4.85 V
4.10 V
4.10 V
130 μA
600 μA
(1)
aaa-000895
Timing and currents given are for TEA1721BT version with a fburst = 885 Hz
Fig 8.
VOUT for load step occurring between burst periods
First when the next burst starts, the output voltage is monitored and the mode changes to
provide for the increased load.
To speed up the change from burst mode to a higher power mode, the IC immediately
switches from CVB mode to CVC mode once the release threshold voltage on the FB pin
(Vth(rel)FB) is less than 2.4 V.
Low no-load power is achieved by:
• A low burst period repetition rate
• Switching the IC to energy saving mode between the burst periods. This action
reduces current consumption by a factor of 5.
Reduced audible noise is achieved by:
• Selecting the minimum Ipk (Ipk(min)) for burst mode
• Using a 22.5 kHz repetition rate of the strokes within the burst period. This frequency
is above the audible limit.
No-load power decreases as a longer time interval between burst periods is selected.
However, using longer time intervals the output capacitor increases to compensate for the
load steps that occur between burst periods.
An overview of available burst frequencies, no-load power and output capacitor value is
given in Table 2 fburst versus Cout and PIN(no-load).
When the output load increases, more strokes per burst period are added to transfer
enough energy. Finally, the whole burst period is filled with strokes and the IC is switching
continuously. When the load increases further, the IC goes into the next mode, CVC.
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Po in burst mode is calculated using Equation 2
2
P o = 0.5 × L p × I pk ( min ) × f burst × average number of strokes × η
(2)
Where:
• fburst = the fixed burst frequency, determining the fixed time between bursts
• Ipk(min) = the fixed minimum Ipk level in burst
The level of Ipk is determined by measuring the voltage over the resistor from SOURCE
pin to ground. The peak level, when measured in an application with an oscilloscope, is
approximately 120 mV. This measured level includes internal propagation delay and
differs from the value, given in the data sheet.
Remark: When the number of strokes in the burst period increases, the exact quantity of
strokes can vary per burst period. This state is normal behavior in this mode. The average
number of strokes over more burst periods is regulated to deliver the required output
power.
5.3.2 CVC mode
CVC mode starts immediately after burst mode ends. The IC continuously switches at
22.5 kHz = fmin and peak current is equal to Ipk(min). fmin is the minimum switching
frequency in continuous mode.
When more output power is needed, switching frequency fmin (22.5 kHz) is maintained
constant and the Ipk level is increased to deliver more power.
Iprim
Ipk(max)
Ipk(min)
44 μs
44 μs
VOUT
5.00 V
aaa-000897
Remark: The on-time (ton) increases with the amplitude of Ipk, which is not shown on these
simplified graphs.
Fig 9.
CVC mode with Ipk control
In this mode, the peak voltage level on the SOURCE pin increases from 120 mV to
565 mV. (Levels measured in an application with an oscilloscope, inclusive of propagation
delay. Differs from the data sheet).
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Po in CVC mode is calculated using Equation 3.
2
P o = 0.5 × L p × I pk × f min × η
(3)
Where:
• Ipk = Varying from Ipk(min) to Ipk(max), a result of VSOURCE(pk) changing from 120 mV to
565 mV on the SOURCE pin.
• fmin = Minimum switching frequency in continuous mode (22.5 kHz)
At Ipk(max), the IC switches to CVF mode.
5.3.3 CVF mode
In CVF mode, Ipk is maintained constant on Ipk(max) and the frequency is increased to
deliver the additional required power.
Iprim
Ipk(max)
44 μs
40 μs
30 μs
19.4 μs
VOUT
5.00 V
aaa-000902
Fig 10. CVF mode with frequency regulation
The switching frequency increases in this mode from fmin (22.5 kHz) to fmax (51.5 kHz).
Output power is calculated using Equation 4
2
P o = 0.5 × L p × I pk ( max ) × f sw × η
(4)
Where:
• Ipk(max) = Fixed maximum Ipk (VSOURCE(pk) on SOURCE pin 565 mV)
• fsw = Switching frequency varies from fmin (22.5 kHz) to fmax (51.5 kHz)
Maximum output power is calculated using Equation 5
2
P o ( max ) = 0.5 × L p × I pk ( max ) × f max × η
(5)
This formula is useful for dimensioning the circuit as used in Section 6.3. When the
maximum power is exceeded, the IC switches to CCF mode.
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5.3.4 CCF mode
CCF mode is the first Constant Current (CC) mode. In CC mode, the current is kept
constant at IOUT(max). VOUT varies with the equivalent resistive load value. For a linear
decreasing resistive value of the load, VOUT also decreases linearly. The CC mode is
intended to charge batteries.
(1)
(2)
Iprim
Ipk(max)
19.4 μs
44 μs
30 μs
8.7 μs
17.4 μs
VOUT
(3)
5V
Icp
2.5 V
1A
aaa-000903
(1) Primary current, hot side
(2) Secondary current, cold side
(3) The converter operates in CCF for VOUT from 5.3 V to 2.5 V and delivers 1 A to the charging port
Fig 11. CCF mode regulation by frequency
The output power formula is the same as for CVF mode, see Equation 6
2
P o = 0.5 × L p × I pk ( max ) × f sw × η
(6)
Now fsw is used to maintain IOUT constant, while VOUT becomes the voltage over the load
at IOUT(max). fsw drops from fmax (51.5 kHz) to fmin (22.5 kHz) while decreasing the resistive
value of the load.
When fmin is reached, the IC switches to CCC mode.
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5.3.5 CCC mode
In CCC mode, the switching frequency is maintained constant while the Ipk value is
reduced. The Ipk value is regulated to maintain IOUT(max) constant.
Ipk(p)
0.39 A
(1)
(2)
44 μs
44 μs
VOUT
(3)
2.5 V
Icp
1A
0V
aaa-000904
(1) Primary current, hot side
(2) Secondary current, cold side
(3) In most applications, the converter operates in start-stop cycles for VOUT < 1 V because the
auxiliary winding VCC < VCC(stop).
Fig 12. CCC mode regulation by Ipk
Output power is calculated using Equation 7
2
P o = 0.5 × L p × I pk × f min × η
(7)
To keep IOUT(max) constant, Ipk is reduced from Ipk(max) to Ipk(min) while the resistive value of
the load is further decreased.
Reducing the resistive value of the load reduces VOUT. The auxiliary winding voltage,
which is related to VOUT, also drops. When the auxiliary winding voltage, supplying VCC,
drops below VCC(stop), the IC stops and performs a restart. The IC remains in hiccup mode
until the resistive value of the load is high enough to enable VCC supply above VCC(stop).
The moment VCC(stop) is reached, depends on the transformer construction and the supply
circuit.
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5.3.6 Overview control modes
Figure 13 summarizes the control modes.
CVB
CVC
fsw
fmax = 51.5 kHz
CP
CVF
CCF
CCC
(3)
Ipk
0.39 A
(1)
fmin = 22.5 kHz
0 kHz/0 W
TEA1721 (5 W) 0.12 W
TEA1723 (11 W) 0.26 W
Vcp
5V
0.08 A
Pcp
2.0 W
4.4 W
5.0 W
11 W
~2.0 W
~4.4 W
~1.0 W
~2.2 W
0W
0W
Icp
1A
(2)
2V
0 V/∞ Ω
TEA1721 (5 W) 200 Ω
TEA1723 (11 W) 91 Ω
Rload
12.5 Ω
5.7 Ω
5.0 Ω
2.25 Ω
~2.0 Ω ~1.0 Ω 0 Ω
~0.91 Ω ~0.45 Ω 0 Ω
aaa-000905
(1) Ipk and fsw as a function of Pcp (power to charging port)
(2) Vcp and Icp as a function of Rload (load impedance to charging port)
(3) When VOUT gets very low, VCC drops below VCC(stop) and IC enters hiccup mode
Fig 13. Overview control modes
The control graph is symmetrical, with both VOUT on the left and IOUT on the right constant.
5.4 Relationship between no-load and max load
As most of the parameters are fixed inside the IC, the different control modes and output
power are all interdependent. The following summarizes the relevant formulas.
Burst mode:
2
P o = 0.5 × L p × I pk ( min ) × f burst × average number of strokes per burst × η
(8)
CVF mode (Po(max) is reached for fmax)
2
P o = 0.5 × L p × I pk ( mdx ) × f sw × η
(9)
For burst mode, PIN(min) is calculated using Equation 10. PIN(min) is reached at one stroke
per burst period, excluding the efficiency:
2
P IN = 0.5 × L p × I pk ( min ) × f burst
(10)
For CVF Po(max) is defined as:
2
P o = 0.5 × L p × I pk ( max ) × f max × η
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Except for Lp and the value for Ipk, all parameters (fburst, fmax, ratio Ipk(min), Ipk(max)) are
fixed in the IC. Therefore, the ratio between Po(max) and PIN(min) is fixed. As Po(max) is a
spec point, start with selecting Lp and Ipk(max) so that Po(max) can be reached.
PIN(min) follows from the values chosen for Po(max) = η × P IN ( max ) .
P o ( max )
Using P IN ( max ) = ----------------- Equation 12 can be written.
η
2
P IN ( min ) = ( P o ( max ) ÷ η ) × ( I pk ( min ) ÷ I pk ( max ) ) × ( f burst ÷ f max )
(12)
Example:
In the following example, the results from a 5 W charger with an efficiency of 75 % are
used.
Main parameter:
•
•
•
•
Lp = 1.75 mH
Ipk(max) = 0.39 A => Ipk(min) / 4.9 = 0.080 A
fmax = 51.5 kHz
fburst = 885 Hz
(13)
2
P o ( max ) = 0.5 × L p × I pk ( max ) × f max × η = 0.5 × 1.75 × 10
–3
2
3
× 0.39 × 51.5 × 10 × 0.75 = 5.14 W
For a no-load condition, input power PIN(min) is of interest.
2
P IN ( min ) = 0.5 × L p × I pk ( min ) × f burst = 0.5 × 1.75 × 10
–3
2
× 0.080 × 885 = 0.005 W
(14)
To remain in regulation, occasional additional strokes are made in the burst period. In
practice PIN(min) is about 40 % higher, at approximately 7 mW.
Remark: The total PIN(min) is higher due to additional losses in the circuit. These losses
are described in Section 5.5.
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5.5 Total input power at no-load
The calculated input power PIN(min) at no-load is only from the converter and at a minimum
input voltage. In an actual application, there are additional losses present. All no-load
losses are shown in Figure 14.
Rpreload
(8)
Rinrush
+
220 pF
(1)
100 kΩ
(5)
(7) VOUT
-
470 Ω
(2)
(6)
(4)
(3)
VCC
DRAIN
TEA172x
FB
GND
SOURCE
aaa-000906
(1) Rectifier 0.1 µA (40 °C), 325 V, 2 × 0.1 mW
(2) Electrolytic capacitor 10u 400 V 10 µA, 375 V (estimation) 3.5 mW
(3) FB sensing, only dissipating during pri + sec stroke, 0.1 mW
(4) VCC = 12 V, I = 0.1 mA, 3 mW
(5) Snubber 2 mW
(6) Leakage HV current source, 1 µA, 375 V, 0.4 mW
(7) Vsec = 5 V, I = 0.8 mA, 4 mW
(8) The minimum transferred energy (fburst × 0.5 × Lp × Ipk(min)2, only one cycle per burst) is divided
between the VCC supply and the preload.
Fig 14. No-load losses
The input power is higher in practice due to the additional losses:
• Increase of Ipk at higher input voltage (IC has no VIN compensation). The difference
between 85 V (AC) and 264 V (AC) is about an additional 2 mW
• Leakage main electrolytic capacitor (3.5 mW)
• Leakage bridge diodes, leakage high-voltage start-up current source (0.5 mW)
• Snubber losses (2 mW)
Combining the additional losses, PIN(min)tot at no-load for fburst = 885 Hz equals:
PIN(min)tot = 7 + 2 + 3.5 + 0.5 + 2 = 15 mW
fburst determines the value of PIN(min), a lower fburst leads to a lower PIN(min). However, other
losses including, electrolytic capacitor leakage, diode bridge leakage must be minimized
to achieve low no-load power.
For the lowest burst frequency of 420 Hz, the calculation is as Equation 15:
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2
P IN ( min ) = 0.5 × L p × I pk ( min ) × f burst = 0.5 × 1.75 × 10
–3
2
× 0.080 × 420 = 0.0024 W
(15)
Practical value (in regulation) PIN(min) is 40 % higher at 3.4 mW.
The additional losses are lower when they are related to fburst:
• Increase of Ipk at higher input voltage (IC has no VIN compensation). The difference
between 85 V (AC) and 264 V (AC) is about an additional 1 mW
• Leakage main electrolytic capacitor (3.5 mW)
• Leakage bridge diodes, high-voltage start-up current source (0.5 mW)
• Snubber losses (1 mW)
PIN(min)tot = 3.4 + 1 + 3.5 + 0.5 + 1 = 9.4 mW
For an overview of burst frequencies, see Table 2
5.6 Relationship between fburst and output capacitor
The USB 1.1 specification (see Section 7.1.1) requires that VOUT remains above 4.1 V for
a load step of 0 A => 0.5 A. This condition is critical in burst mode as the primary sensing
concept is "blind" of conditions on the secondary side while the IC is in energy save mode.
Iprim
Ipk(min)
1
1
1.13 ms = tburst
Iload
0.50 A
0.00 A
VOUT
4.85 V
4.85 V
4.10 V
4.10 V
130 μA
600 μA
aaa-000909
Fig 15. fburst and output capacitor
The worst case is when the load step occurs as the IC enters energy save mode. The
maximum time the capacitor has to maintain the output voltage is 1/fburst.
The capacitor value can be calculated using Equation 16:
C = I load ÷ ( f burst × V drop )
(16)
Where:
• Iload = current after load step
• Vdrop = VOUT at the beginning of load step −4.1 V
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The formula indicates the relationship between burst frequency fburst. and the output
capacitor. A lower fburst leads to a lower PIN(min)tot at no-load, but needs a larger output
capacitor to fulfill the load step requirement.
Example:
Due to the internal load line, VOUT drops when the load increases. VOUT must remain
higher than 4.75 V. Therefore, VOUT at no or low load during burst is always higher than
the specified minimum VOUT voltage of 4.75 V. In practice, the lowest VOUT in burst where
no-load step is detected, is 4.85 V.
As a result, the voltage on the output capacitor can drop from 4.85 V to 4.1 V.
• Vdrop = 0.75 V
• Iload = 0.5 A
Equation 17 show the calculated value of Cout for an fburst of 885 Hz:
C out ( min ) = 0.5 ÷ ( 885 × 0.75 ) = 753 × 10
–6
(17)
The results in Equation 17 represents the minimal required value for the capacitor (C). As
most electrolytic capacitors have a tolerance of −20 % on the low-side, divide the
calculated value by 0.8 to obtain the nominal value. See Equation 18
C out ( nom ) = 753 × 10
–6
÷ 0.8 = 941 × 10
–6
(18)
Table 2 provides an overview of the (nominal) output capacitor value related to the burst
frequency and no-load PIN.
Table 2.
fburst
fburst as a function of Cout and PIN(no-load)
Cout(nom)
PIN(no-load)
TEA1721
TEA1723
420 Hz
2 × 1000 μF
< 10 mW
< 17 mW
885 Hz
2 × 470 μF
< 16 mW
< 26 mW
1260 Hz
680 μF
< 22 mW
< 35 mW
1750 Hz
2 × 820 μF
< 33 mW
< 50 mW
The version with fburst = 1750 Hz with large output capacitance is intended for applications
with high requirements for the load step behavior.
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5.7 Feedback
In a primary sensed system, the output voltage is regulated by measuring the voltage of
an auxiliary winding on primary side.
Rpreload
Rinrush
+
VOUT
-
(2)
VCC
(1)
DRAIN
TEA172x
FB
(3)
GND
SOURCE
aaa-000910
(1) Primary sensing via auxiliary winding
(2) Auxiliary winding also provides VCC
(3) Regulation level on FB pin is 2.5 V
Fig 16. Feedback from auxiliary winding
For optimal matching of the auxiliary winding voltage and the output voltage, tightly couple
the transformer auxiliary winding to the secondary winding.
Due to the primary sensing concept, the secondary voltage is regulated before the
secondary diode. Changes in voltage drop over the diode are not corrected and are
reflected in the VOUT level.
Figure 17 shows the waveform on the auxiliary winding.
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(1)
(2)
Vs
(3)
VAUX
-VDC / NAUX
Is
Ipks = Ipk(p)/n
aaa-000911
(1) No accurate measurement possible during ringing
(2) Voltage drops due to decreasing voltage over the secondary diode with decreasing current
(3) Measurements done towards the end of the secondary stroke at minimal secondary current to
increase accuracy and avoid ringing.
Fig 17. Auxiliary winding waveform
VOUT is measured during the secondary stroke. To increase the accuracy, VOUT is
sampled near the end of the secondary stroke. This timing minimizes the influence of the
voltage drop over the secondary diode because the diode current is close to zero. It also
minimizes the error, due to ringing.
As the secondary stroke time varies with the value of Ipk (the higher Ipk, the longer the
secondary stroke time), the sample time is adapted accordingly.
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Vs
VAUX
-VDC/NAUX
(1)
Ip
Ipk(p)
ls
aaa-000912
(1) To increase measurement accuracy, the position of the measurement pulse is adapted to the
duration of the secondary current. A measurement is taken near the end of the stroke where the
secondary stroke is close to zero and ringing is minimal
Fig 18. Adaptive sample time
Configure the resistive divider on the FB pin to deliver 2.5 V at the FB pin near the end of
the secondary stroke in burst mode. Take into account that the voltage near the end of the
secondary stroke is VOUT + Vdiode.
5.8 Demagnetization protection
The signal of the auxiliary winding on the FB pin is also used for demagnetization
protection. That is, to determine if the secondary stroke has ended and all stored energy
in the transformer is transferred to secondary winding.
To release the demagnetization protection, the voltage on the FB pin must drop below
50 mV after the secondary stroke has started. When no demagnetization is detected, the
next primary stroke is prohibited until demagnetization is true. This condition guarantees
discontinuous operation.
5.9 Supply from the auxiliary winding
The supply of the IC is supplied from an auxiliary winding. It is possible to use the
feedback auxiliary winding or a separate winding.
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Rpreload
Rinrush
+
VOUT
-
(2)
VCC
(1)
DRAIN
TEA172x
FB
GND
SOURCE
aaa-000913
(1) Primary sensing via auxiliary winding
(2) Auxiliary winding also provides VCC
Fig 19. Supply from the auxiliary winding
When designing the auxiliary winding, consider the waveforms on the winding as shown in
Figure 20:
(1)
VAUX
(2)
VCC
-VDC/NAUX
Ip
Ipk(p)
ls
aaa-000914
(1) Actual VCC, resulting from peak rectification of the ringing
(2) VCC, expected from the transformer calculations using winding ratio’s
Fig 20. VCC higher than anticipated due to ringing
As the power consumption of the IC is low, the rectified voltage of the auxiliary winding
follows the peak of the ringing (peak rectification). Therefore, the supply voltage is much
higher than anticipated.
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The amount of ringing depends on the coupling of the auxiliary winding with the primary
and secondary winding. As necessary, adapt the number of auxiliary windings to obtain
the correct supply voltage.
The supply voltage range is large, approximately 8.5 V to 35 V. For optimum efficiency
and no-load input power, design VCC for 10 V to 12 V at no-load.
As the ringing increases for higher loads, demo board VCC rises from 12 V at no-load to
22 V at maximum load.
5.10 Soft start
To reduce stress at start-up, the IC starts in CC mode with reduced Ipk. The output current
is limited to 1 A during start-up. Charging of the output capacitor of 2 × 470 μF takes less
than 5 ms.
5.11 Load line compensation
For stable regulation, it is necessary that the voltage on the FB pin drops for higher loads.
This leads to a load line from zero load to full load of 450 mV. The IC has a built-in load
line compensation that limits the load line from zero to full load below 200 mV.
5.12 Jitter
To improve ElectroMagnetic Interference (EMI), the switching frequency varies around the
center value. This results in reduced peak levels around the switching frequency. Jitter is
present in all modes and amounts approximately ±8 %. The jitter frequency is between
100 Hz to 400 Hz. To keep Po constant while varying fsw, Ipk is adapted accordingly as can
be derived using Equation 19.
2
P o = 0.5 × L p × I pk × f sw × η
(19)
5.13 Protective features
The following protective features are implemented:
•
•
•
•
•
UnderVoltage Protection (UVP) on the VCC pin
OverVoltage Protection (OVP) VOUT (via FB pin)
OverTemperature Protection (OTP)
Demagnetization protection
Open/short circuit protection on the FB pin
The IC can also handle a short-circuit on the secondary side in a safe way. The behavior
is described in Section 6.5.
5.13.1 UnderVoltage Protection (UVP) on the VCC pin
The UVP on the VCC pin prevents unpredictable behavior when the supply voltage drops
below the minimum level needed for operation. The UVP level and action taken are as
follows:
• UVP: VCC < 8.5 V restarts the IC
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Restart causes switching to stop and the high-voltage current source is enabled to charge
the VCC capacitor. When VCC rises above 17 V (VCC(startup)), the high-voltage current
source is disabled and switching restarts.
If an error persists, the sequence repeats itself. This condition is known as “hiccup mode”.
5.13.2 OverVoltage Protection (OVP) on VOUT
The voltage on secondary side is monitored using VFB (measured on the FB pin). Under
normal operation, the VFB is approximately 2.5 V when sampled during the secondary
stroke. If VFB > 3.2 V, a forced restart is performed.
• OVP secondary side: Sampled voltage on pin FB > 3.2 V causes the IC to restart
When the sampled voltage on pin FB > 3.2 V, switching stops. The auxiliary winding no
longer provides the VCC supply and VCC drops. When required, the IC waits until the
VCC supply < 8.5 V before enabling the high-voltage current source to charge the VCC
capacitor.
When VCC(startup) > 17 V, the high-voltage current source is switched off and the switching
is re-enabled. If the error persists and the sampled voltage on pin FB > 3.2 V, switching
stops, the sequence repeats itself. This condition is known as “Hiccup mode”.
The level of overvoltage is calculated as follows:
• Sampled voltage FB pin for VOUT = 5 V: 2.5 V
• Voltage on secondary winding before the diode: 5.3 V
• Ratio voltage secondary winding divided by the sampled voltage the FB
pin = 5.3 V / 2.5 V = 2.12
• Voltage (secondary winding) for the sampled voltage FB = 3.2 V: 3.2 V × 2.12 = 6.8 V
The output voltage must rise above 6.8 V before OVP is triggered. In practice, OVP
triggers at an output voltage between 6.5 V and 6.8 V. However, it depends on the
steepness of the VOUT increase.
5.13.3 OverTemperature Protection (OTP)
When the temperature of the IC increases above 150 °C, OTP is activated. The IC stops
switching and VCC drops. When VCC falls below the VCC(stop) of 8.5 V, the high-voltage
current source charges the VCC capacitor until 17 V (VCC(startup)). The IC does not start
switching until the die temperature drops < 100 °C. During the waiting time, VCC cycles
between charging to VCC(startup) then discharges to VCC(stop).
The hysteresis from 150 °C to 100 °C ensures that no dangerous situations occur.
5.13.4 Demagnetization protection
Demagnetization protection is implemented to check that the secondary stroke has ended
before enabling the next primary stroke. This condition ensures discontinuous operation
and prevents stress in overload conditions.
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5.13.5 FB pin open and short-circuit protection
The FB pin detects if there is an AC voltage present on the pin. When the voltage on the
pin does not alternate below and above 50 mV, switching is stopped. This action prevents
the presence of an uncontrolled output voltage when the FB pin is open or shorted to
ground.
5.13.6 Protection features overview table
Table 3.
Protection feature overview
Protection feature
Level
Action
VCC UVP
8.5 V
restart
VOUT OVP
VFB pin > 3.2 V
restart
OTP
150°
stop switching until T < 100 °C
Demagnetization
VFB < 50 mV
hold next primary stroke until demagnetization has
occurred
FB pin open or
short-circuit
AC detection FB pin
stop switching
6. Application
6.1 Application diagram
Figure 21 shows the demo board schematic configured as a 5 W charger application.
Following the schematic each component from the AC input to the output stage is
explained. At the end of this section the schematic of an 11 W charger is given. Also the
main differences with the 5 W application are described.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
1
T1
C4
2.2 nF
50 V
D8
6
NXP Semiconductors
AN11060
Application note
L1
R9
100 Ω
+
1.5 mH
3
C9
220 pF
500 V
R1
D1
1N4007
1000 V
J1
L
4
C1
4.7 μF
400 V
C2
4.7 μF
400 V
R4
470 Ω
R10
5.5 kΩ
5V
Transformer
Wurth T4
D5
1N4007
1000 V
10 Ω
C5
470 μF
10 V
-
5
D2
1N4007
1000 V
RF1
R3
100 kΩ
C6
470 μF
10 V
D7
PMLL4148L
90 V (AC) to
265 V (AC)
IC1
J2
N
GND1
GND2
GND3
C7
D3
1N4007
1000 V
D4
1N4007
1000 V
10 pF
50 V
R2
FB
8
1
2
TEA1721BT
3
6
4
5
DRAIN
Rsense
1.65 Ω
R6
12 Ω
SOURCE
VCC
C8
10 nF
50 V
C3
10 μF
50 V
RFB1
19.5 kΩ
10 kΩ
RFB2
5.73 kΩ
aaa-000918
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Fig 21. Demo board schematic (5 W)
L2
1.5 mH
TEA172X 5 W to 11 W Power Supply/USB charger
Rev. 1.2 — 8 June 2012
All information provided in this document is subject to legal disclaimers.
10 kΩ
SL44
4A
40 V
8
AN11060
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6.1.1 Input and EMI filter
Figure 21 shows fuse resistor RF1 that is part of the input circuit. RF1 is a 2 W fusible
resistor designed to limit the inrush current and provides primary side short-circuit
protection. For mains rectification, standard diodes are used, however the use of a diode
bridge is also possible. Capacitors C1 and C2 form the main electrolytic capacitor, C1, C2,
L1, L2, R1, and R2 form the damping filter for conducted EMI.
6.1.2 Clamp
Diode D5, R4, R3 and C9 are designed to dampen the ringing after switch-off of the
integrated MOSFET switch. D5 must be a slow diode for ringing damping. Figure 22 and
Figure 23 show damping using fast and a slow diode.
aaa-000920
CH1 (Orange): Drain primary switch
CH2 (Green): Cathode clamp diode
Fig 22. Damping using a slow diode (1N4007)
Using a slow diode, the diode conducts after the drain signal reaches its peak and the
clamping circuit remains parallel to the primary. This action leads to the fast damping of
the ringing. The ringing frequency is 1.1 MHz, damping time is 2 µs.
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aaa-000922
CH1 (Orange): Drain primary switch
CH2 (Green): Cathode clamp diode
Fig 23. Damping using a fast diode (BYW26CV)
Using a fast diode, the clamping capacitor remains charged after reaching a peak, the
clamping circuit is not active and does not provide further damping. The oscillation
frequency is 2.2 MHz and the damping time increases to 4 µs. Quick damping of the
oscillation is important to ensure proper measurement of the voltage on the FB pin at the
end of the secondary stroke.
The value of R4 controls the damping and is a compromise of the damping speed and the
additional dissipation of the clamp. The values shown are a good starting point for a 5 W
application.
6.1.3 Source resistor
The source resistor between SOURCE pin and ground comprise three SMD resistors in
parallel. Parallel configuration allows the use of standard SMD resistors for accurate
tuning. The value of the source resistor is calculated as follows:
RSOURCE = VSOURCE(pk)max / Ipk(p)max
VSOURCE(pk)max = 0.565 V and Ipk(p)max is the peak current required to deliver full power as
in the following calculation:
PIN(max) = 0.5 × Lp × Ipk(max)2 × fmax
In practice, RSOURCE can be about 5 % larger as the real Ipk continues to increase after
switch-off from the MOSFET.
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(6)
Ipri in coil of transformer
(1)
(2)
Isec.ns/np
(3)
tprop
Vgate
trise
0A
11 V
tcomm
t
t
0V
(4)
Vcomm
(5)
np/ns.Vsec
VIN
0V
VFB VFB(sec)
0V
VFB(pri)
Vint Vint(max)
0V
t
t
t
aaa-000924
(1) Ipk (VDRAIN = VIN)
(2) Ip (VGATE = 0 V
(3) Ip (VSOURCE = Vpk)
(4) VIN + nVsec + Vcomm
(5) VIN + nVsec
(6) Isec ns/np in secondary coil of transformer
Fig 24. Detail rise of the primary circuit
After reaching the internal Vpk level of the control loop, there is an internal delay
(tPD = propagation delay) before the gate is turned off. The value shown for
VSOURCE(pk)max is taking this propagation delay into account, as it is measured in a
practical application.
After the gate is turned off, Ip increases until the voltage over the primary coil is zero.
Under theses conditions, the voltage on the drain equals VIN.
The exact amount of overshoot of Ipk depends on the steepness of the primary current
rise. Some tuning of Rsense could be necessary.
6.1.4 Auxiliary winding supply
The auxiliary winding of the transformer supplies the IC VCC voltage via D7, R6 and C3.
The peak of the ringing (peak rectification) determines the VCC level and not the average
level of the secondary stroke. Resistor R6 is used to prevent a too heavy short load of the
auxiliary winding under no-load conditions. A short load can disturb the sampling of the
voltage at the FB pin. If the output voltage drops below 1 V, resistor R6 can be trimmed to
ensure the IC switches off when in current mode. As VCC runs on peak rectification, it is
possible the IC continues operating up to an output voltage of 0 V.
Remark: Install capacitor C10 as close to the IC as possible to suppress disturbances.
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6.1.5 Auxiliary winding: Feedback
The auxiliary winding is fed to the FB pin. The resistive divider consists of R7, R8, R13
and R14. To set an accurate division factor, use two resistors in parallel. Capacitor C7 is
added for spike suppression. Select a low value for C7 (around 10 pF) to avoid a
disruption of the waveform at the FB pin. A low value for C7 provides accurate sampling of
the voltage.
6.1.6 Secondary side
On the secondary side, Schottky diode D8 is used for rectification. Despite a 1 A rated
output current, the peak current can be higher than 4.5 A. Therefore, for efficiency select a
diode able to manage a current higher than 4.5 A. Capacitor C4 and R9 suppress the
switching spikes of the diode.
The output capacitors C5 and C6 manage the load step in burst mode. For output ripple
and load step behavior, use capacitors with low Equivalent Series Resistance (ESR).
Table 4 summarizes the relationship between the value of the output capacitor, burst
frequency and no-load power for a 5 W and 11 W application:
Table 4.
fburst
fburst versus Cout and PIN(no-load)
Cout(nom)
PIN(no-load)
TEA1721
TEA1723
420 Hz
2 × 1000 μF
< 10 mW
< 17 mW
885 Hz
2 × 470 μF
< 16 mW
< 26 mW
1260 Hz
680 μF
< 22 mW
< 35 mW
1750 Hz
2 × 820 μF
< 33 mW
< 50 mW
Resistor R10 is the preload resistor. The preload resistor serves two purposes:
• A small load on secondary side ensures proper regulation of the output voltage at
no-load condition.
• The preload resistor dissipates any excess of energy above the IC supply and the
auxiliary divider generated in no-load conditions by the fixed burst frequency. If
excess energy is not dissipated, the output voltage rises up to the OVP level.
6.2 Layout considerations
Layout is not critical, however for the best result the following items are taken into
account:
•
•
•
•
Separation of large signal and small signal path
Copper area at ground pins for cooling
Routing input filter
Short connection secondary diode to transformer and output capacitor
Figure 25 show the layout of the demo board:
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Fig 25. Demo board layout (5 W)
Both components on top side and bottom side are shown for reference. The ground plane
is emphasized with a transparent light blue color. For recognition, the internal switch of the
IC between pin 7 and 6 is drawn. Figure 21 shows the circuit diagram.
6.2.1 Separation large and small signal path
The area above the IC carries the large currents and high voltages and the area below the
IC is the small signal area. The negative pole of C2 acts as star ground where all grounds
(large signal, small signal, AC input) merge.
The loop of the large signal current is kept small. When the internal switch is closed, the
current flows from the plus terminal of C2 to the primary winding. Thereafter, the current
flows via the internal switch between pins 7, 6 and the source resistor R5, 11,12 back to
the minus terminal of C2, star ground. When the internal switch is off, the current of the
primary winding flows into the clamp via diode D5, R4, R3 and C11 back to the positive
terminal of C2 and (during rise of the drain voltage) via the parasitic capacitance of the
internal switch and the source resistor to ground.
The small signal ground is positioned below the IC. Here the auxiliary winding is
grounded. Via D7, R6, C3, a bridge wire and C8 the auxiliary winding supplies the VCC on
pin 5. Via the resistive divider R8, R13 and R7, R14, C7 the signal of the auxiliary winding
is fed to FB pin 4.
6.2.2 Cooling the IC
IC pins 1 to 3 are connected to a copper plane, and used for cooling the IC. The heat of
the internal switch is conducted from the IC via pin 1 and 3. The heat transfer from the IC
pins is optimized by using a contiguous copper plane underneath the pins. The holes in
the silk screen create the solder islands for the IC pins. The size of the copper plane is
10 mm × 8 mm. This plane provides sufficient cooling of an enclosed 5 W application up
to 45 °C.
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6.2.3 Input filter
The input part is routed such that interference from switching cannot reach the mains
connection without passing through the filter L1, L2 and C1. Crosstalk directly to the
mains connections is avoided by creating sufficient spacing.
6.2.4 Secondary side
On the secondary side, a rectifier diode is placed as close as possible to the winding to
improve EMI. In addition, the connection from cathode to output capacitor is as short as
possible. R9 and C4 are added to suppress switching spikes. The position of preload
resistor R10 is not critical.
6.3 Transformer
For proper functioning of the primary sensing concept, attention is needed for the correct
transformer construction.
The considerations are as follows:
•
•
•
•
Lp and Ipk in relation to input voltage and power
Secondary stroke must be long enough for proper sampling of VOUT
Transformer construction of windings
Safety
The following outlines the basics of transformer selection:
6.3.1 Calculation of Lp and Ipk
Figure 26 shows a calculation example for a 5 W application. Only the main items, which
determine the transformer are calculated, the primary inductance Lp and the peak current
Ipk at maximum output power.
At the right-hand side, the explanation of parameters and used formulas are given. Below
some additional details of Figure 26 are described.
fmains
fmains the lowest mains frequency selected for this application is 60 Hz and not 50 Hz. The
reason is 50 Hz mains have nominal voltages of 220 V or higher. A drop to 85 V is not
realistic at these voltage levels.
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Selection nVOUT
The value of nVOUT (the output voltage multiplied by the ratio of the number of primary
windings and number of secondary windings) influences two design parameters:
• The peak voltage on the primary switch
• The secondary stroke time
The formula for the peak voltage on the primary switch when turned off is:
Vpk(p) = Velcap(max) + nVOUT + Vpk(ringing)
Where:
Vpk(p) has to remain below the maximum breakdown voltage of the switch.
Velcap(max) is reached for maximum AC input voltage 264 V (AC) and is about 375 V (DC).
Vpk(ringing) can run up to about 100 V.
By selecting nVOUT not too high, Vpk(p) can be maintained at a safe level.
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Input value
Calculated
Fill in the required
parameters in the
green fields
Values, pending on design
Vout
Iout
Vf
Cmains
Vmains_min
Fmains
nVout
The other values are
fixed for this design
5.00 Vdc
1.00 A
0.60 V
9.40E-06 F
85.00 Vac
60.00 Hz
72.00 V
Output voltage converter @ max load
Maximum output current converter
Forward voltage secondary diode
Value total elcap behind rectifier
Lowest specified mains input voltage for full performance
Frequency mains voltage @ minimal input voltage
Practical value between 60 and 80 Volt, select highest value for which Tsec_min = 1.9 us
Values, fixed by IC design
eff
Switch frequency at max power
Tdead_min_perc
0.75
5.20E+04 Hz
0.05
Tdead_min
9.62E-07
Tdead_min = 1/Fsw * Tdead_min_perc
Fsw_max
Converter efficiency
1/Fsw = Tprim + Tsec + Tdead_min, Tdead_min to guarantee discontinuous operation
Pin
Vpeak_elcap
Vmin_elcap
6.67 W
118.81 V
74.71 V
Pin = Vout * Iout_max / eff
Vpeak_elcap = Vmains_min * SQRT(2) - 2 * drop over bridge diodes (0.7V / diode)
Vmin_elcap is where the dropping voltage of the elcap meets the rising mains voltage
For the elcap voltage we can write for Tm, where Tm is the time after reching the Vpeak_elcap:
0.5 * Cmains * (Vpeak^2 - Velcap^2) = Pin * Tm =>
Velcap = SQRT((Vpeak^2) - ((Pin * Tm)/(0.5 * Cmains)))
For the rising voltage of the mains the formula is:
Vmains = Vpeak * sin (2*pi*Fmains*(Tm - 1/(4*Fmains)))
Calculation Ipk, Lp
Derivation:
1 Pin = Fsw_max * 0.5 * Lp * Ipk^2
2 Pin = Pout/eff.
3 Ipk = Vmin_elcap * Tprim / Lp
4 Ipk = nVout * Tsec / Lp
5 Tprim + Tsec + Tdead_min = 1/Fsw_max
Substitute 3 and 4 in 5
(Lp*Ipk)/Vmin_elcap + (Lp*Ipk)/nVout + Tdead_min = 1/Fsw_max
Lp*Ipk = (1/Fsw_max - Tdead_min)(1/(1/Vmin_elcap + 1/nVout) = (1/Fsw_max)(1-Tdead_min_perc)(1/(1/Vmin_elcap + 1/nVout)
Substitute Lp*Ip in 1
Ipk
Tsec_max
Tsec_min
Ipk = (2 * Pin * (Vmin_elcap + nVout)) / ((Vmin_elcap * nVout) * (1-Tdead_min_perc))
9.30E-06
1.90E-06
Tsec = Lp * Ipk / (nVout)
Lp = (1/Fsw_max - Tdead_min) * 1 / (1/Vmin_elcap + 1/nVout) * 1/Ipk
Tsec_min = Tsec_max * (Ipk_min/Ipk_max) = Tsec_max / 4.9
aaa-001523
Fig 26. Lp and Ipk calculations (5 W)
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Lp
3.83E-01 A
1.75E-03 H
TEA172X 5 W to 11 W Power Supply/USB charger
Rev. 1.2 — 8 June 2012
All information provided in this document is subject to legal disclaimers.
Calculation minimal DC voltage at converter input
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6.3.2 Secondary stroke time
The sampling timing during the secondary stroke time is related to the output power.
The secondary stroke time is also related to the output power, it is important that the
sampling timing fits within the secondary stroke time. Figure 27 shows some basic signals
and the relationship between secondary stroke time and the transformer.
VDC + nVOUT
VDC
+ VDC
Ls
n : 1 Vs
Ip
+ VOUT
Vp
Is
Lp
Ipk(p)
Vp
lp
Ip = (VDC / Lp) * t
VOUT
t
Vs
(2)
lpks = n * lpk(p)
ls
Is = n * Ipk(p) - (VOUT * n ^ 2 / Lp) * t
t
aaa-000930
(1) Ipk(p) = primary peak current.
(2) Ipk(s) = secondary peak current.
Graphs valid for discontinuous mode when neglecting secondary diode drop
Fig 27. Waveforms to calculate secondary stroke time
During primary stroke time, the Ipk primary increases linear with the slope of the DC
voltage over the primary VDC divided by the inductance Lp. The current on the secondary
side (Is) starts with the transformed current to secondary side, Ipk(p) * n. The decay is linear
to zero with a slope of the output voltage VOUT divided by the primary inductance,
transferred to secondary side Lp / n2.
The secondary stroke time ts can be derived from the secondary current Equation 20, as
shown in Equation 21.
2
I s = n × I pk ( p ) – ( V OUT ÷ ( L p ÷ ( n ) ) ) × t
(20)
The secondary stroke time ts is reached when Is = 0:
t s = L p × I pk ( p ) ÷ ( n × V OUT )
(21)
For correct sampling, the minimum secondary stroke time ts(min) for Ipk = Ipk(min) = 1.9 µs.
The ratio between Ipk(min) and Ipk(max) is 4.9.
When the calculated ts(min) is too short, the time can be increased by lowering nVOUT in
the calculation and recalculate the Lp and Ipk.
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6.3.3 Winding construction
Figure 28 show a suitable set-up of the winding scheme.
S
Aux
P
P
Shield
Core
Core
aaa-000931
Fig 28. Transformer winding configuration
The first winding called the Shield is a shielding winding that must be one full layer.
Connect one side to ground or to the DC voltage side of the main electrolytic capacitor.
The primary winding (P) normally needs two or three layers.
The auxiliary winding additional serves as shielding between primary and secondary. For
primary sensing, the auxiliary winding needs a tight coupling with the secondary. In this
position it also has a good coupling with the primary, leading to more ringing on the
auxiliary winding. For optimal performance, the auxiliary winding must be on top of the
secondary winding. However, some shielding is needed between the primary and
secondary for EMI protection. The TEA172X demo board uses the construction discussed
thus far with auxiliary winding between the primary and secondary. This type of
construction gives the demo board satisfactory performance.
The secondary winding (S) must be Triple Isolated (TRISO) wire to meet the safety
standards.
6.3.4 Safety requirements
As the output power is low, it is possible to use small cores for the transformer, for
example, the EE13 and EE16. However, with these transformer sizes, consider the safety
requirements for mains isolation. The use of TRISO wire for the secondary winding
maintains a small construction size.
Typically the pins of the bobbins for EE13 and EE16 cores are not spaced far enough
apart to fulfill the safety distance between hot and cold. Therefore, the solution is to use
flying leads to connect the secondary windings far enough from the primary pins at the
bobbin. Flying leads are however not convenient for production.
Some bobbins for EE13 and EE16 are designed with the required safety distance by
extending the footprint of the secondary side. This type of construction increases the
footprint (larger size), but eases production.
6.4 Differences between 11 W and 5 W applications
The following provides a list of differences between the 11 W and 5 W applications.
Figure 29 shows the schematic of the 11 W demo board.
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1
T1
9,10
C4
2.2 nF
50 V
D8
NXP Semiconductors
AN11060
Application note
L1
R9
33 Ω
1.5 mH
12, 13 SBR10U45SP5
3
C9
470 pF
500 V
R1
J1
L
C1
10 μF
400 V
C2
10 μF
400 V
10 Ω
R4
180 Ω
Transformer
Wurth
11W
D5
1N4007
1000 V
90 V (AC) to
265 V (AC)
C6
470 μF
10 V
R10
2.2 kΩ
C122
2 μF
10 V
J3
5V
GND1
GND2
GND3
C7
D4
1N4007
1000 V
10 pF
50 V
FB
8
1
2
C10
2.2 nF
2 kV
D7
PMLL4148L
IC1
J2
N
D3
1N4007
1000 V
C5
470 μF
10 V
6
D2
1N4007
1000 V
RF1
10 A
40 V
4
TEA1723BT
3
6
4
5
DRAIN
Rsense
0.78 Ω
R6
12 Ω
SOURCE
VCC
C8
10 nF
50 V
C3
10 μF
50 V
RFB1
19.5 kΩ
RFB2
aaa-001978
5.45 kΩ
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Fig 29. Demo board schematic (11 W)
TEA172X 5 W to 11 W Power Supply/USB charger
Rev. 1.2 — 8 June 2012
All information provided in this document is subject to legal disclaimers.
10 kΩ
D1
1N4007
1000 V
R3
100 kΩ
AN11060
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6.4.1 Input filter and EMI
The configuration for EMI suppression is slightly different. A 2.2 nF Y-cap used over the
transformer and the coil in the ground connection of C1 and C2 is replaced by a
short-circuit. The EMI suppression is at the limit, to improve the reserve an additional
common mode choke before the diode bridge could be added.
6.4.2 Clamp
The values of the components are adapted to match the higher power.
6.4.3 Source resistor
The value of the resistor is adapted to match the higher current.
6.4.4 Secondary side
The value of the output capacitors can remain the same to fulfill the USB 1.1 spec.
To reduce the output ripple, a 22 µF ceramic capacitor can be added in parallel to the
output capacitors. In addition, the value of the preload resistor is adapted to match the
higher no-load power.
6.4.5 Layout considerations
The layout setup for the 11 W version is identical to the 5 W version. Only the cooling is
increased to cope with the higher power. The dimension of the copper area is 15 × 10 mm
for the 11 W version. The dimension of the copper area for the 5 W version is 8 × 10 mm.
aaa-001989
Fig 30. Demo board layout (11 W)
6.4.6 Calculation Lp and Ipk
Figure 31 shows a calculation example for an 11 W application.
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Application note
Direcons for use
Definition:
Physical constants
mu_r
mu_o
ro
ro_increase_per_degree
1.00
1.26E-06
1.75E-08
4.30E-03
Permeability core
1.00E-04 m
2.00E-05 m
Use wire tables, available from manufacturers, e.g. Electrisola
Permeability vacuum
Copper resistance
For a temperature increase of 100 degrees, the copper resistance increases with 43%
Values for transformer calculaon
Isolation thickness triso
Isolation thickness lacquer
Use wire tables, available from manufacturers, e.g. Electrisola, use for isolation grade 2
Input value
Calculated
Fill in the required
parameters in the
green fields
Values, pending on design
Vout
Iout
Vf
Cmains
Vmains_min
The other values are
fixed for this design
Output voltage converter @ max load
Maximum output current converter
Forward voltage secondary diode
Value total elcap behind rectifier, usual 2 μF per watt output power.
Lowest specified mains input voltage for full performance
Frequency mains voltage @ minimal input voltage
Practical value between 60 and 80 Volt, select highest value for which Tsec_min = 1.9 us
Values, fixed by IC design
0.75
5.20E+04 Hz
0.05
Switch frequency at max power
Tdead_min_perc
eff
Tdead_min
9.62E-07
Tdead_min = 1/Fsw * Tdead_min_perc
Fsw_max
Converter efficiency
1/Fsw = Tprim + Tsec + Tdead_min, Tdead_min to guarantee discontinuous operation
Calculation minimal DC voltage at converter input
Pin
Vpeak_elcap
Vmin_elcap
13.33 W
118.81 V
77.63 V
Pin = Vout * Iout_max / eff
Vpeak_elcap = Vmains_min * SQRT(2) - 2 * drop over bridge diodes (0.7V / diode)
Vmin_elcap is where the dropping voltage of the elcap meets the rising mains voltage
For the elcap voltage we can write for Tm, where Tm is the time after reching the Vpeak_elcap:
0.5 * Cmains * (Vpeak^2 - Velcap^2) = Pin * Tm =>
Velcap = SQRT((Vpeak^2) - ((Pin * Tm)/(0.5 * Cmains)))
For the rising voltage of the mains the formula is:
Vmains = Vpeak * sin (2*pi*Fmains*(Tm - 1/(4*Fmains)))
Calculation Ipk, Lp
Derivation:
1 Pin = Fsw_max * 0.5 * Lp * Ipk^2
2 Pin = Pout/eff.
3 Ipk = Vmin_elcap * Tprim / Lp
4 Ipk = nVout * Tsec / Lp
5 Tprim + Tsec + Tdead_min = 1/Fsw_max
Substitute 3 and 4 in 5
(Lp*Ipk)/Vmin_elcap + (Lp*Ipk)/nVout + Tdead_min = 1/Fsw_max
Lp*Ipk = (1/Fsw_max - Tdead_min)(1/(1/Vmin_elcap + 1/nVout) = (1/Fsw_max)(1-Tdead_min_perc)(1/(1/Vmin_elcap + 1/nVout)
Lp
Tsec_max
Tsec_min
Fig 31. Lp and Ipk calculations (11 W)
7.51E-01 A
9.08E-04 H
9.48E-06
1.93E-06
Ipk = (2 * Pin * (Vmin_elcap + nVout)) / ((Vmin_elcap * nVout) * (1-Tdead_min_perc))
Lp = (1/Fsw_max - Tdead_min) * 1 / (1/Vmin_elcap + 1/nVout) * 1/Ipk
Tsec = Lp * Ipk / (nVout)
Tsec_min = Tsec_max * (Ipk_min/Ipk_max) = Tsec_max / 4.9
aaa-002013
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Substitute Lp*Ip in 1
Ipk
TEA172X 5 W to 11 W Power Supply/USB charger
Rev. 1.2 — 8 June 2012
All information provided in this document is subject to legal disclaimers.
Fmains
nVout
5.00 Vdc
2.00 A
0.60 V
2.00E-05 F
85.00 Vac
60.00 Hz
72.00 V
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6.5 Short-circuit behavior
The TEA172x can handle a short-circuit on the secondary side in a safe way.
In Figure 32 the relevant signals are given during a short.
(1) IOUT in short-circuit condition.
(2) VCC.
(3) VDRAIN.
(4) VOUT.
Fig 32. Signals during a short circuit of VOUT
When the output is short circuited, the TEA172x runs in current mode.
During a short circuit (VOUT = 0), the VOUT related auxiliary winding voltage Vaux and VCC
drop below the VCC(stop) level (8.5 V). The high-voltage current source is enabled and
charges the capacitor connected to pin on VCC. When the VCC voltage > 17 V
(VCC(startup)), switching is started and the circuit delivers current to the short-circuit.
Switching continues until the VCC supply < VCC(stop) trigger level (8.5 V) causing the
sequence to repeat.
Looking in more detail at the waveforms, the TEA172x triggers demagnetization
protection when the output is short circuited (See Figure 33).
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(1) IOUT in short-circuit condition.
(2) VDRAIN.
(3) VOUT.
Fig 33. Detailed waveforms while switching during a short circuit
After building up energy during primary stroke, the energy is delivered to the secondary
diode and the short circuited output. The demagnetization requirement (VFB < 50 mV) is
only valid when all energy is delivered to secondary side. Once this occurs, switching is
released. The demagnetization protection now determines the switching frequency
ensuring the energy delivered during the short-circuit is limited.
The primary power, taken during the hiccup mode with VOUT short circuited, is measured
for the TEA172x application boards as given in Table 5.
Table 5.
Input power with VOUT short circuited
The TEA1721XT are 5 W versions and the TEA1723XT are 11 W versions.
AC VIN RMS (V)
TEA1721XT (W)
TEA1723XT (W)
90
0.26
0.42
115
0.29
0.45
230
0.39
0.59
265
0.43
0.62
The primary power is low enough for the circuit to survive a short-circuit for an indefinite
time
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7. Appendix
7.1 USB specification
The TEA172X is designed to fulfill the USB specification for chargers. Currently, USB 1.1
is used, however USB 1.2 is advancing. The most important requirements are as follows.
7.1.1 USB 1.1
Figure 34 shows a graph of the static voltage versus current requirement for a USB 1.1
charger.
1
2
3
4
0.5 A
1.5 A
5.25 V
5.0
4.75 V
5
4.0
Dedicated
Charging
Port shall
operate
here
Dedicated
Charging
Port shall
not operate
here
Voltage
(V)
3.0
2.0 V
2.0
6
1.0
7
0
0
0.5
1.0
1.5
Current (A)
aaa-000932
(1) CVB: Burst mode with energy saving: no-load 10 mW to low load of 120 mW.
(2) CVC: 120 mW up to 2 W.
(3) CVF: 2 W up to 5 W.
(4) CP: 5 W with transition from CV to CC.
(5) CCF: 5 W down to 2.5 W
(6) CCC: Constant voltage with burst mode. 2.5 down to 1 W
(7) Start-up and UVLO. No power conversion.
Generally, the graph is valid for a quasi-stationary load and is without jitter and without spread.
Fig 34. USB 1.1 static behavior and TEA172X operation modes
Figure 34 shows the voltage versus current for a 5 W USB charger using the TEA1721.
The USB 1.1 specification requires precise voltage regulation (5 V ± 5 % or
4.75 V - 5.25 V) up to 0.5 A. Higher than 0.5 A, the requirement is that the output current
remains between 0.5 A and 1.5 A. The output voltage must remain lower than 5.25 V.
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If VOUT drops below 2 V, the power supply is allowed to shut down, that is, it starts to
“Hiccup”. Alternatively, the power supply can continue to deliver current for as long as the
output current remains lower than 1.5 A. The characteristic of most chargers is to maintain
the output voltage between 4.75 V and 5.25 V until maximum output power is reached.
Thereafter, switch to current mode for charging.
Current mode has to work at least until an output voltage of 2 V. Lower than 2 V, behavior
is not critical unless the output current increases higher than 1.5 A. For the USB 1.1
characteristic the different operating modes of the TEA172X are indicated.
Figure 35 shows the dynamic behavior requirements of USB 1.1.
IOUT
I max A
0.5 A
0.0 A
VOUT
6.00 V
5.25 V
4.75 V
4.10 V
(1)
(2)
aaa-000933
(1) Load step 0 A => 0.5 A. Requirements:
- VOUT must remain above 4.1 V
- VOUT average (over 1 s) must remain between 4.75 V and 5.25 V
No time limits for recovery
(2) Load step I max A => 0 A. Requirement:
- VOUT must remain below 6 V
- VOUT average (over 1 s) must remain between 4.75 V and 5.25 V
No time limit for recovery
Fig 35. USB 1.1 dynamic behavior
For any load step between 0 A and 0.5 A, VOUT is not allowed to drop below 4.1 V. This
requirement is used to calculate the size of the output capacitors, see Section 5.6.
For any load step between IOUT(max) and 0 A, the output voltage must not rise higher than
6 V. The output voltage must remain between 4.75 V and 5.25 V when averaged over 1
second.
7.1.2 USB 1.2
Figure 36 shows the static behavior for USB 1.2, which is less demanding on a number of
aspects compared to USB 1.1.
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5.25
5.0
4.75
all curves
allowed
4.0
(1)
Voltage
(V)
(2)
3.0
VBUS
turned
off
2.0
1.0
0
(3)
0
0.5
1.0
1.5
(4)
2.0
5.0
Current
(A) aaa-000934
(1) Charging port operation not allowed
(2) Required operating range for Dedicated Charging Port (DCP)
(3) Valid load curve must cross either line
(4) Continuous current regulation allowed. Current limit trip operation allowed.
Generally, the specification for the output voltage remains narrow until an output current of 0.5 A
(4.75 V to 5.25 V). No requirement for current limitation or minimal required VOUT (VBUS).
Fig 36. USB 1.2 static behavior
The USB 1.2 specification is identical to USB 1.1 up to an output current of 0.5 A. At 0.5 A,
VOUT must remain between 4.75 V and 5.25 V. Above 0.5 A, there are no requirements
except that the output voltage must remain below 5.25 V and the output current must
remain below 5 A.
At output currents <1.5 A, the device must operate until the output voltage is 2 V. Below
an output voltage of 2 V or an output current > 1.5 A, the device can shut down, “Hiccup”
or deliver any current < 5 A. In practice, most customers do not allow currents in this
mode above the nominal charge current to avoid excessive dissipation.
A major relaxation of USB 1.2 related to dynamic behavior are load steps. Load steps
have been divided into two ranges and three current levels. See Table 6
Table 6.
Load steps
IDCP
Min
Max
Unit
Low
0
0.03
A
Mid
0.03
0.1
A
High
0.5
-
A
Load steps are divided into the three Dedicated Charging Port (DCP) current ranges:
• IDCP Low => IDCP Mid
• IDCP Mid => IDCP High
• IDCP Low => IDCP High
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The additional IDCP Mid level allows for relaxation of the undershoot requirements for
primary sensed chargers with low standby power, provided the USB device is designed
for USB 1.2. The requirements for undershoot during current steps from Low to Mid and
Mid to High are as shown in Figure 37:
IOUT
0.5 A
0.1 A
0.0 A
VOUT
6.00 V
< 10 ms
< 10 ms
5.25 V
4.75 V
4.10 V
> 20 ms
aaa-000935
Fig 37. USB dynamic undershoot 1
For load steps between:
• IDCP Low => IDCP Mid (0 A => 0.03 A to 0.10 A) and IDCP Mid => IDCP High (0.03 A to
0.10 A => 0.5 A)
the following applies:
• VOUT must remain above 4.1 V
• Duration undershoot VOUT < 4.75 V must be < 10 ms
• Minimum time between load step 0 A => 0.03 A to 0.10 A and
0.03 A to 0.10 A => 0.5 A is 20 ms.
The requirements for undershoot during a current step from Low to High are as shown in
Figure 38
AN11060
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 8 June 2012
© NXP B.V. 2012. All rights reserved.
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AN11060
NXP Semiconductors
TEA172X 5 W to 11 W Power Supply/USB charger
IOUT
0.5 A
0.0 A
VOUT
< 10 ms
6.00 V
5.25 V
4.75 V
4.10 V
(1)
aaa-000936
(1) Load voltage attached PD (USB PD)
Fig 38. USB dynamic undershoot 2
For any load step between:
• IDCP Low => High (0 A to 0.03 A => 0.5 A)
the following applies:
• VOUT can drop to the battery voltage of the attached Portable Device (PD)
• Undershoot (VOUT < 4.75 V) must be < 10 ms
The requirement for load steps from high to low is the same as for USB 1.1. See Figure 39
IOUT
1A
0A
VOUT
6.00 V
5.25 V
4.75 V
4.10 V
(1)
aaa-000937
(1) Load step 1 A => 0 A (or any other load step down). Requirement, VOUT must not exceed 6 V.
Fig 39. USB 1.2 dynamic overshoot
In general, the output voltage must not rise above 6 V for any load step, during switch-on
or during switch-off.
AN11060
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 8 June 2012
© NXP B.V. 2012. All rights reserved.
47 of 50
AN11060
NXP Semiconductors
TEA172X 5 W to 11 W Power Supply/USB charger
8. Abbreviations
Table 7.
Abbreviations
Acronym
Description
CC
Constant Current
CCC
Constant Current with Current mode
CCF
Constant Current with Frequency mode
CP
Constant Power
CVB
Constant Current with Burst mode
CVC
Constant Voltage with Current mode
CVF
Constant Voltage with Frequency mode
CV
Constant Voltage
DCP
Dedicated Charging Port
EMI
ElectroMagnetic Interference
ESR
Equivalent Series Resistance
HVAC
Heating, Ventilating and Air Conditioning
MOSFET
Metal-Oxide Semiconductor Field-Effect Transistor
OVP
OverVoltage Protection
PD
Portable Device
UVLO
UnderVoltage Lockout
UVP
UnderVoltage Protection
9. References
AN11060
Application note
[1]
TEA1721AT\BT\DT\FT — data sheets: Ultra-low standby SMPS controller with
integrated power switch
[2]
TEA1723AT\BT\DT\FT — data sheets: Ultra-low standby SMPS controller with
integrated power switch data sheet
[3]
UM10520 — TEA1721 Isolated 3-phase universal mains flyback converter
demo board user manual
[4]
UM10521 — TEA1721 isolated universal mains flyback converter demo
board user manual
[5]
UM10522 — TEA1721 non-isolated universal mains buck and buck/boost
converter demo board user manual
[6]
UM10523 — TEA1721 universal mains white goods flyback SMPS demo
board user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 8 June 2012
© NXP B.V. 2012. All rights reserved.
48 of 50
AN11060
NXP Semiconductors
TEA172X 5 W to 11 W Power Supply/USB charger
10. Legal information
10.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
10.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express, implied
or statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of this
product remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business, business
interruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort
(including negligence), strict liability, breach of contract, breach of warranty or
any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoing limitations, exclusions
and disclaimers shall apply to the maximum extent permitted by applicable
law, even if any remedy fails of its essential purpose.
10.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
AN11060
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 8 June 2012
© NXP B.V. 2012. All rights reserved.
49 of 50
AN11060
NXP Semiconductors
TEA172X 5 W to 11 W Power Supply/USB charger
11. Contents
1
2
3
3.1
3.1.1
3.2
4
5
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.13.1
5.13.2
5.13.3
5.13.4
5.13.5
5.13.6
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.2.1
6.2.2
6.2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TEA172X low-power adapter. . . . . . . . . . . . . . . 3
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Basic application schematic . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 5
System description . . . . . . . . . . . . . . . . . . . . . . 6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 8
Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CVC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CVF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CCF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CCC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overview control modes . . . . . . . . . . . . . . . . . 15
Relationship between no-load and max load . 15
Total input power at no-load . . . . . . . . . . . . . . 17
Relationship between fburst and output
capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Demagnetization protection . . . . . . . . . . . . . . 22
Supply from the auxiliary winding . . . . . . . . . . 22
Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Load line compensation . . . . . . . . . . . . . . . . . 24
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Protective features . . . . . . . . . . . . . . . . . . . . . 24
UnderVoltage Protection (UVP) on the
VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
OverVoltage Protection (OVP) on VOUT . . . . . 25
OverTemperature Protection (OTP) . . . . . . . . 25
Demagnetization protection . . . . . . . . . . . . . . 25
FB pin open and short-circuit protection . . . . . 26
Protection features overview table . . . . . . . . . 26
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Application diagram . . . . . . . . . . . . . . . . . . . . 26
Input and EMI filter . . . . . . . . . . . . . . . . . . . . . 28
Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Source resistor . . . . . . . . . . . . . . . . . . . . . . . . 29
Auxiliary winding supply . . . . . . . . . . . . . . . . . 30
Auxiliary winding: Feedback . . . . . . . . . . . . . . 31
Secondary side . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout considerations. . . . . . . . . . . . . . . . . . . 31
Separation large and small signal path. . . . . . 32
Cooling the IC . . . . . . . . . . . . . . . . . . . . . . . . . 32
Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2.4
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.5
7
7.1
7.1.1
7.1.2
8
9
10
10.1
10.2
10.3
11
Secondary side . . . . . . . . . . . . . . . . . . . . . . .
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of Lp and Ipk . . . . . . . . . . . . . . . . .
Secondary stroke time . . . . . . . . . . . . . . . . . .
Winding construction . . . . . . . . . . . . . . . . . . .
Safety requirements . . . . . . . . . . . . . . . . . . . .
Differences between 11 W and 5 W
applications . . . . . . . . . . . . . . . . . . . . . . . . . .
Input filter and EMI. . . . . . . . . . . . . . . . . . . . .
Clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source resistor. . . . . . . . . . . . . . . . . . . . . . . .
Secondary side . . . . . . . . . . . . . . . . . . . . . . .
Layout considerations . . . . . . . . . . . . . . . . . .
Calculation Lp and Ipk . . . . . . . . . . . . . . . . . . .
Short-circuit behavior . . . . . . . . . . . . . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB specification. . . . . . . . . . . . . . . . . . . . . .
USB 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
36
37
37
37
39
39
39
39
39
39
41
43
43
43
44
48
48
49
49
49
49
50
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 June 2012
Document identifier: AN11060