SRDA05 4R2 D

SRDA05-4R2
Low Capacitance Surface
Mount TVS for High-Speed
Data Interfaces
The SRDA05-4 transient voltage suppressor is designed to protect
equipment attached to high speed communication lines from ESD,
EFT, and lightning.
Features
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SO-8 LOW CAPACITANCE
VOLTAGE SUPPRESSOR
500 WATTS PEAK POWER
6 VOLTS
•SO-8 Package
•Peak Power - 500 Watts 8 x 20 mS
•ESD Rating:
IEC 61000-4-2 (ESD) 15 kV (air) 8 kV (contact)
IEC 61000-4-4 (EFT) 40 A (5/50 ns)
IEC 61000-4-5 (lightning) 23 (8/20 ms)
•UL Flammability Rating of 94 V-0
•Pb-Free Package is Available
PIN CONFIGURATION
AND SCHEMATIC
I/O 1 1
8 REF 2
Typical Applications
REF 1 2
7 I/O 4
•High Speed Communication Line Protection
REF 1 3
6 I/O 3
I/O 2 4
5 REF 2
MAXIMUM RATINGS
Rating
Peak Power Dissipation
8 x 20 mS @ TA = 25°C (Note 1)
Junction and Storage Temperature Range
Lead Solder Temperature Maximum 10 Seconds Duration
Symbol
Value
Unit
Ppk
500
W
SOIC-8
CASE 751
PLASTIC
8
1
TJ, Tstg
- 55 to +150
°C
TL
260
°C
MARKING DIAGRAM
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Non-repetitive current pulse 8 x 20 mS exponential decay waveform
8
SRDA5
AYWWG
G
1
SRDA5 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
SRDA05-4R2
SO-8
2500/Tape & Reel
SO-8
(Pb-Free)
2500/Tape & Reel
SRDA05-4R2G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2007
June, 2007 - Rev. 5
1
Publication Order Number:
SRDA05-4R2/D
SRDA05-4R2
ELECTRICAL CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Reverse Breakdown Voltage @ It = 1.0 mA
Characteristic
VBR
6.0
-
-
V
Reverse Leakage Current @ VRWN = 5.0 V
IR
N/A
-
10
mA
Maximum Clamping Voltage @ IPP = 1.0 A, 8 x 20 mS
VC
N/A
-
9.8
V
Maximum Clamping Voltage @ IPP = 10 A, 8 x 20 mS
VC
N/A
-
12
V
Between I/O Pins and Ground @ VR = 0 V, 1.0 MHz
Capacitance
-
10
15
pF
Between I/O Pins @ VR = 0 Volts, 1.0 MHz
Capacitance
-
5
8
pF
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
UNIDIRECTIONAL (Circuit tied to Pins 1 and 3 or 2 and 3)
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
QVBR
IF
VC VBR VRWM
IR VF
IT
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
Test Current
IPP
Maximum Temperature Coefficient of VBR
IF
Forward Current
VF
Forward Voltage @ IF
ZZT
Maximum Zener Impedance @ IZT
IZK
Reverse Current
ZZK
Maximum Zener Impedance @ IZK
Uni-Directional TVS
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2
V
SRDA05-4R2
9
8
8
7
IR, REVERSE LEAKAGE (mA)
VZ, REVERSE BREAKDOWN (V)
TYPICAL CHARACTERISTICS
7
6
5
4
3
2
1
0
-100
-50
0
50
100
T, TEMPERATURE (°C)
150
6
5
4
3
2
1
0
-100
200
VC, CLAMPING VOLTAGE (V)
% OF PEAK PULSE CURRENT
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
200
35
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
150
100
Figure 2. Reverse Leakage versus
Temperature
PEAK VALUE IRSM @ 8 ms
tr
90
50
T, TEMPERATURE (°C)
Figure 1. Reverse Breakdown versus
Temperature
100
0
-50
60
30
25
20
15
10
5
0
80
0
10
20
30
40
50
60
70
80
IPP, PEAK PULSE CURRENT (A)
t, TIME (ms)
Figure 3. 8 x 20 ms Pulse Waveform
Figure 4. Clamping Voltage versus Peak Pulse
Current
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3
90
SRDA05-4R2
APPLICATIONS INFORMATION
Option 2
Protection of four data lines with bias and power supply
isolation resistor.
The SRDA05-4R2 is a low capacitance TVS diode array
designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the SRDA05-4R2 offers surge rated, low
capacitance steering diodes and a TVS diode integrated in a
single package (SO-8). If a transient condition occurs, the
steering diodes will drive the transient to the positive rail of
the power supply or to ground. The TVS device protects the
power line against overvoltage conditions avoiding damage
to the power supply and other downstream components.
I/O 1
I/O 2
VCC
10 K
1
8
2
7
3
6
4
5
I/O 3
SRDA05-4R2 Configuration Options
The SRDA05-4R2 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or Vcc+Vf).
The diodes will force the transient current to bypass the
sensitive circuit.
Data lines are connected at pins 1, 4, 6 and 7. The negative
reference is connected at pins 5 and 8. These pins must be
connected directly to ground using a ground plane to
minimize the PCB's ground inductance. It is very important
to reduce the PCB trace lengths as much as possible to
minimize parasitic inductances.
I/O 4
Figure 6.
The SRDA05-4R2 can be isolated from the power supply
by connecting a series resistor between pins 2 and 3 and Vcc.
A 10 kW resistor is recommended for this application. This
will maintain a bias on the internal TVS and steering diodes,
reducing their capacitance.
Option 3
Protection of four data lines using the internal TVS diode
as reference.
I/O 1
I/O 2
Option 1
Protection of four data lines and the power supply using
Vcc as reference.
I/O 1
I/O 2
VCC
1
8
I/O 3
2
7
I/O 4
3
6
4
5
1
8
NC
2
7
NC
3
6
4
5
Figure 7.
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal TVS can be used as the reference. For
these applications, pins 2 and 3 are not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
the TVS plus one diode drop (Vc=Vf + VTVS).
I/O 3
I/O 4
Figure 5.
For this configuration, connect pins 2 and 3 directly to the
positive supply rail (Vcc). The data lines are referenced to
the supply voltage. The internal TVS diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.
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4
SRDA05-4R2
ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes reduces
their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
Power
Supply
IESDpos
VCC
Protected Data Line
Device
L diESD/dt factor. A relatively small trace inductance can result
in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board layout.
Taking care to minimize the effects of parasitic inductance
will provide significant benefits in transient immunity.
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD events
across datalines and the supply rail. Discrete diodes with good
transient power capability will have larger die and therefore
higher capacitance. This capacitance becomes problematic as
transmission frequencies increase. Reducing capacitance
generally requires reducing die size. These small die will have
higher forward voltage characteristics at typical ESD
transient current levels. This voltage combined with the
smaller die can result in device failure.
The ON Semiconductor SRDA05- 4R2 was developed to
overcome the disadvantages encountered when using discrete
diodes for ESD protection. This device integrates a TVS
diode within a network of steering diodes.
D1
IESDpos
IESDneg
D2
IESDneg
VF + VCC
-VF
Figure 8.
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a negative
ESD condition occurs. For slower transient conditions, this
system may be approximated as follows:
For positive pulse conditions:
Vc = Vcc + VfD1
For negative pulse conditions:
Vc = -VfD2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect of
parasitic inductance must be considered. A pictorial
representation of this is shown below.
Power
Supply
D5
D7
D2
D4
D6
D8
Figure 10. SRDA05-4R2 Equivalent Circuit
During an ESD condition, the ESD current will be driven
to ground through the TVS diode as shown below.
IESDpos
D1
D3
0
Power
Supply
VCC
Protected
Device
D1
IESDpos
VCC
IESDneg
D1
Data Line
D2
Protected
Device
VC = VCC + Vf + (L diESD/dt)
IESDneg
IESDpos
Data Line
D2
VC = -Vf - (L diESD/dt)
Figure 9.
Figure 11.
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = Vcc + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = -Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
The resulting clamping voltage on the protected IC will
be:
Vc = VFD1 + VTVS.
The clamping voltage of the TVS diode is provided in
Figure 4 and depends on the magnitude of the ESD current.
The steering diodes are fast switching devices with unique
forward voltage and low capacitance characteristics.
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5
SRDA05-4R2
TYPICAL APPLICATIONS
UPSTREAM
USB PORT
VBUS
VBUS
VBUS
VBUS
D+
RT
D+
RT
D-
VBUS
GND
USB
Controller
D-
VBUS
SRDA05-4R2
CT CT
DOWNSTREAM
USB PORT
GND
VBUS
VBUS
NUP2201MR6
RT
D+
RT
DGND
DOWNSTREAM
USB PORT
CT CT
Figure 12. ESD Protection for USB Port
RJ45
Connector
TX+
TX+
TXTXPHY
Ethernet
(10/100)
Coupling
Transformers
RX+
RX+
RXRXSRDA05-4R2
VCC
GND
N/C
N/C
Figure 13. Protection for Ethernet 10/100 (Differential Mode)
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SRDA05-4R2
R1
RTIP
R3
R2
RRING
T1
VCC
T1/E1
TRANCEIVER
SRDA05-4R2
R4
TTIP
R5
TRING
T2
Figure 14. TI/E1 Interface Protection
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7
SRDA05-4R2
PACKAGE DIMENSIONS
SOIC-8 NB
CASE 751-07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
-XA
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
-YG
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
-Z-
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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SRDA05-4R2/D