PIC18F85J11 Family Data Sheet Errata

PIC18F85J11 FAMILY
PIC18F85J11 Family
Silicon Errata and Data Sheet Clarification
The PIC18F85J11 family devices that you have received
conform functionally to the current Device Data Sheet
(DS39774D), except for the anomalies described in this
document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18F85J11 family silicon.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A6).
Note:
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
2.
3.
4.
Note:
Data Sheet clarifications and corrections start on page 5,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
The DEVREV values for the various PIC18F85J11
family silicon revisions are shown in Table 1.
Revision ID for Silicon Revision(2)
Device ID(1)
PIC18F63J11
390Xh
PIC18F64J11
392Xh
PIC18F65J11
396Xh
PIC18F83J11
398Xh
PIC18F84J11
39AXh
PIC18F85J11
39EXh
2:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
SILICON DEVREV VALUES
Part Number
Note 1:
Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the development tool used, the part number and Device
Revision ID value appear in the Output window.
A3
A4
A5
A6
3h
4h
5h
6h
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the “PIC18F6XJXX/8XJXX Family Flash Microcontroller Programming Specification” (DS39644)
for detailed information on Device and Revision IDs for your specific device.
 2011 Microchip Technology Inc.
DS80383F-page 1
PIC18F85J11 FAMILY
TABLE 2:
Module
SILICON ISSUE SUMMARY
Feature
Item
Number
Affected Revisions(1)
Issue Summary
A3
A4
A5
A6
Reset
BOR
1.
BOR and POR may occur at the same
time.
X
X
X
X
MSSP
I2C™
Slave
2.
If the SSPBUF register is not read within
a window after the SSPIF interrupt, the
module may not receive the correct data.
X
X
X
X
MSSP
I2C Master
3.
The clock may get narrow if the slave
performs a clock stretch.
X
X
X
X
EUSART
Enable/
Disable
4.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 TCY
delay.
X
X
X
X
Timer1/3 Counter
5.
Timer1/3 in Internal Counter mode will
not increment in the instruction count
where the timer is disabled.
X
X
X
X
Timer1/3 Prescale
6.
Timer1/3 prescale will take an additional
count to switch when prescaler value is
changed.
X
X
X
X
7.
The TRMT bit may not indicate when the
TSR register is empty.
X
X
X
X
8.
The Two-Speed Start-up (IESO,
CONFIG2L<7>) and the Fail-Safe Clock
Monitor (FCMEN, CONFIG2L<6>) bits
will not work correctly.
X
X
X
X
EUSART
Synchronous
mode
POR
Two-Speed
Start-up/Fail-Safe
Clock Monitor
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80383F-page 2
 2011 Microchip Technology Inc.
PIC18F85J11 FAMILY
Silicon Errata Issues
Note:
3. Module: MSSP (I2C™ Master)
When in I2C Master mode, if the slave performs
clock stretching, the first clock pulse after the
slave releases the SCL line may be narrower
than the configured clock width. This may result
in the slave missing the first clock in the next
transmission/reception.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A6).
Work around
1. Module: Reset
The clock pulse will be the normal width if the slave
does not perform clock stretching.
When a Brown-out Reset (BOR) occurs and the
BOR bit is reset, the Power-on Reset (POR) bit
may also be reset. The resulting state matches
that of the RCON register following a Power-on
Reset event.
Affected Silicon Revisions
Consequently, an application may not be able to
detect whether a BOR or POR event has occurred.
Work around
None.
Affected Silicon Revisions
A3
A4
A5
A6
X
X
X
X
Work around
The issue can be resolved in either of these ways:
• Prior to the I2C slave reception, enable the
clock stretching feature. This is done by
setting the SEN bit (SSPCON2<0>).
• Each time the SSPxIF bit is set, read the
SSPBUF before the first rising clock edge of
the next byte being received.
Affected Silicon Revisions
A3
A4
A5
A6
X
X
X
X
 2011 Microchip Technology Inc.
A4
A5
A6
X
X
X
X
4. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTAx<7> = 0)
• The EUSART is re-enabled (RCSTAx<7> = 1)
2. Module: MSSP (I2C™ Slave)
In extremely rare cases, when configured for
I2C™ slave reception, the MSSP module may
not receive the correct data. This occurs only if
the Serial Receive/Transmit Buffer register
(SSPBUF) is not read within a window after the
SSPIF interrupt (PIR1<3>) has occurred.
A3
• A two-cycle instruction is executed
Work around
Add a 2 TCY delay after re-enabling the EUSART.
1.
2.
3.
4.
5.
Disable receive interrupts
(RCxIE bit, PIEx<5>) = 0).
Disable the EUSART (RCSTA<7> = 0).
Re-enable the EUSART (RCSTA<7> = 1).
Re-enable receive interrupts (PIEx<5> = 1).
(This is the first TCY delay.)
Execute a NOP instruction.
(This is the second TCY delay.)
Affected Silicon Revisions
A3
A4
A5
A6
X
X
X
X
DS80383F-page 3
PIC18F85J11 FAMILY
5. Module: Timer 1/3
When either Timer1 or Timer3 is configured for
the internal clock source (FOSC/4, TxCON<1>
(TMRxCS) = 0) and in the 8/16-Bit Counter mode
(TxCON<7>(RD16) = 0 or 1), TMRxH and TMRxL
will not increment on the instruction that turns off
the counter (TxCON<0> (TMRxON) = 0).
Work around
None.
Affected Silicon Revisions
A3
A4
A5
A6
X
X
X
X
6. Module: Timer 1/3
When either Timer1 or Timer3 is in the 8/16-Bit
Counter mode (TxCON<7> (RD16) = 0 or 1),
incrementing the prescale value (TxCON<5:4>
(TXCKPS<1:0>)) will take an additional count at
the previous value before the prescale value is
updated.
7. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In Synchronous Slave Transmission mode, the
TRMT bit (TXSTAx<1> may not indicate when
the TSR register is empty.
Work around
Instead of polling the TRMT bit to determine the
status of the EUSART, poll the TXxIF flag
(PIRx<4>) to determine when new data can be
written to the TXREG register.
Affected Silicon Revisions
A3
A4
A5
A6
X
X
X
X
8. Module: POR
The Two-Speed Start-up (IESO, CONFIG2L<7>)
and the Fail-Safe Clock Monitor (FCMEN,
CONFIG2L<6>) bits will not work correctly. The
Two-Speed Start-up and Fail-Safe Clock Monitor
are always enabled after initial power-up.
For example, changing the prescale value from
1:4 to 1:8 will occur four instruction cycles after
the execution of the instruction to update the
prescaler.
The Two-Speed Start-up and the Fail-Safe
Clock Monitor will work correctly after a WDT/
MCLR/Reset instruction, RESET, and will also
work correctly after a wake-up from Sleep.
Work around
Work around
None.
None.
Affected Silicon Revisions
Affected Silicon Revisions
A3
A4
A5
A6
A3
A4
A5
A6
X
X
X
X
X
X
X
X
DS80383F-page 4
 2011 Microchip Technology Inc.
PIC18F85J11 FAMILY
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS39774D):
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
Note:
1. Module: Guidelines for Getting Started
with PIC18FJ Microcontrollers
Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)” has been
replaced with a new and more detailed section.
The entire text follows:
2.4
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 26.0 “Electrical
Characteristics” for additional information.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 26.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
Note that the “LF” versions of some low pin count
PIC18FJ parts (e.g., the PIC18LF45J10) do not have
the ENVREG pin. These devices are provided with the
voltage regulator permanently disabled; they must
always be provided with a supply voltage on the
VDDCORE pin.
FIGURE 2-3
Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables the
regulator, while tying it to ground disables the regulator.
Refer to Section 23.3.2 “On-Chip Regulator and
BOR” for details on connecting and using the on-chip
regulator.
ESR ()
1
0.1
0.01
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The VCAP/
VDDCORE pin must not be connected to VDD and must
use a capacitor of 10 µF connected to ground. The type
can be ceramic or tantalum. Suitable examples of
capacitors are shown in Table 2-1 Capacitors with
equivalent specifications can be used.
0.001
0.01
Note:
0.1
1
10
100
Frequency (MHz)
1000 10,000
Typical data measurement at 25°C, 0V DC bias.
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
.
TABLE 2-1
SUITABLE CAPACITOR EQUIVALENTS
Make
Part #
Nominal
Capacitance
Base Tolerance
Rated Voltage
Temp. Range
TDK
C3216X7R1C106K
10 µF
±10%
16V
-55 to 125ºC
TDK
C3216X5R1C106K
10 µF
±10%
16V
-55 to 85ºC
Panasonic
ECJ-3YX1C106K
10 µF
±10%
16V
-55 to 125ºC
Panasonic
ECJ-4YB1C106K
10 µF
±10%
16V
-55 to 85ºC
Murata
GRM32DR71C106KA01L
10 µF
±10%
16V
-55 to 125ºC
Murata
GRM31CR61C106KC31L
10 µF
±10%
16V
-55 to 85ºC
 2011 Microchip Technology Inc.
DS80383F-page 5
PIC18F85J11 FAMILY
CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface
mount ceramic capacitors have become very cost
effective in sizes up to a few tens of microfarad. The
low-ESR, small physical size and other properties
make ceramic capacitors very attractive in many types
of applications.
Ceramic capacitors are suitable for use with the
VDDCORE voltage regulator of this microcontroller.
However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance
over the intended operating range of the application.
Typical low cost, 10 µF ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit
satisfactory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer's data
sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 µF nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum VDDCORE voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
Vddcore regulator if the application must operate over a
wide temperature range.
DS80383F-page 6
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very significant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type and Y5V type capacitors is shown in
Figure 2-4.
FIGURE 2-4
Capacitance Change (%)
2.4.1
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
10
0
-10
16V Capacitor
-20
-30
-40
10V Capacitor
-50
-60
-70
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC Bias Voltage (VDC)
When selecting a ceramic capacitor to be used with the
VDDCORE voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at
16V for the 2.5V VDDCORE voltage. Suggested
capacitors are shown in Table 2-1.
 2011 Microchip Technology Inc.
PIC18F85J11 FAMILY
2. Module: Electrical Characteristics
Changes shown in bold have been made to the D005
parameter in Section 26.1 “DC Characteristics: Supply Voltage PIC18F85J11 Family (Industrial)”. The
updated table is shown below:
26.1
DC Characteristics: Supply Voltage PIC18F85J11 Family (Industrial)
PIC18F85J90 Family
(Industrial)
Param
No.
D001
Symbol
VDD
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C < TA < +85°C for Industrial
Characteristic
Supply Voltage
D001B VDDCORE External Supply for
Microcontroller Core
Min
Typ
Max
Units
VDDCORE
2.0
—
—
3.6
3.6
V
V
ENVREG tied to Vss
ENVREG tied to VDD
2.0
—
2.70
V
ENVREG tied to Vss
V
D001C AVDD
Analog Supply Voltage
VDD – 0.3
—
VDD + 0.3
D001D AVSS
Analog Ground Potential VSS – 0.3
—
VSS + 0.3
V
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Start Voltage to
Ensure Internal
Power-on Reset Signal
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
D005
VBOR
Brown-out Reset Voltage
1.75(2)
2.0
2.4
Note 1:
2:
See Section 5.3 “Power-on
Reset (POR)” for details
V/ms See Section 5.3 “Power-on
Reset (POR)” for details
V
This is the limit to which VDDCORE can be lowered in Sleep mode, or during a device Reset, without losing
RAM data.
When the BOR is enabled, the part will continue to operate until the BOR occurs. This is valid
although VDD may be below the minimum voltage.
3. Module: I/O Ports
In Section 11.6 “PORTE, TRISE and LATE
Registers”, the following changes are made.
The changes are shown in bold text.
11.6
Conditions
PORTE, TRISE and LATE
Registers
PORTE is a 7-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are
TRISE and LATE. All pins on PORTE are digital only.
PORTE<7:3> can tolerate voltages up to 5.5V and
PORTE<2:0> are only VDD level tolerant.
 2011 Microchip Technology Inc.
4. Module: I/O Ports
In Section 11.8 “PORTG, TRISG and LATG
Registers”, the following changes are made.
The changes are shown in bold text.
11.8
PORTG, TRISG and LATG
Registers
PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are
TRISG and LATG. All pins on PORTG are digital
only. PORTG<4> and PORTG<1> can tolerate voltages up to 5.5V. PORTG<3:2> and PORTG<0> are
VDD level tolerant only.
DS80383F-page 7
PIC18F85J11 FAMILY
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev D Document (12/2010)
Initial release of the combined, silicon errata/data
sheet clarification document. New data sheet
clarifications 1 (Guidelines for Getting Started with
PIC18FJ Microcontrollers), 2 (Electrical Characteristics)
and 3-5 (I/O Ports).
This document replaces these errata documents:
• DS80318A, “PIC18F85J11 Family Rev. A3 Silicon
Errata”
• DS80423A, “PIC18F85J11 Family Rev. A4 Silicon
Errata”
• DS80383C, “PIC18F85J11 Family Data Sheet
Errata”
Rev E Document (9/2011)
Updated data sheet clarification 2 (Electrical
Characteristics).
Rev F Document (10/2011)
Added new silicon issue 8 (POR).
DS80383F-page 8
 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
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PIC32 logo, rfPIC and UNI/O are registered trademarks of
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© 2011, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
ISBN: 978-1-61341-705-8
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 2011 Microchip Technology Inc.
DS80383F-page 9
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China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS80383F-page 10
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
08/02/11
 2011 Microchip Technology Inc.