PIC18F87J11 FAMILY PIC18F87J11 Family Silicon Errata and Data Sheet Clarification The PIC18F87J11 family of devices that you have received conform functionally to the current Device Data Sheet (DS39778E), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. The errata described in this document will be addressed in future revisions of the PIC18F87J11 family silicon. 4. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A6 or C2, respectively). Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB IDE project. Configure the MPLAB IDE project for the appropriate device and hardware debugger. Based on the version of MPLAB IDE you are using, do one of the following: a) For MPLAB IDE 8, select Programmer > Reconnect. b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool Status icon ( ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. 5. Data Sheet clarifications and corrections start on page 6, following the discussion of silicon issues. Note: The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: The DEVREV values for the various PIC18F87J11 family silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Revision ID for Silicon Revision(2) Device ID(1) A1 PIC18F66J11 444h PIC18F66J16 446h PIC18F67J11 448h PIC18F86J11 44Eh PIC18F86J16 450h PIC18F87J11 452h Note 1: 2: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. 1h A2 2h A4 4h A5 5h A6 C1 C2 10h 13h 6h The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format “DEVID DEVREV”. Refer to the “PIC18F6XJXX/8XJXX Flash Microcontroller Programming Specification” (DS39644) for detailed information on Device and Revision IDs for your specific device. 2010-2015 Microchip Technology Inc. DS80000495G-page 1 PIC18F87J11 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Affected Revisions(1) Item Num Issue Summary X X X A1 A2 A4 A5 A6 C1 C2 Master Synchronous Serial Port (MSSPx) I2C Slave Reception 1. When configured for I2C slave reception, the MSSPx module may not receive the correct data if the SSPxBUF register is not read within a window after an SSPxIF interrupt occurs. Oscillator Configurations (PLL) PLL 2. When Phase Lock Loop (PLL) is enabled, if the PLL input frequency is higher than 8 MHz, there may be problems accessing the RAM. X X X X X X X Voltage Regulator VDDCORE 3. If VDDCORE drops below approximately 2.45V, while the on-chip core voltage regulator is enabled and operating in Voltage Tracking mode, the REGSLP bit (WDTCON <7>) will be automatically cleared. SRAM Read/Write 4. Any read or write access to SRAM will increase the current consumption of the device – varying with how often the SRAM is accessed. X Low-Voltage Detect LVDSTAT 5. The LVDSTAT VDDCORE Status bit is not implemented in the cited revision of silicon. X MSSPx (I2C Master) I2C Master mode 6. In Master mode, the first clock may become narrower than the configuration width if the slave performs a clock stretch and release. X X X X X X X X X X X X X X X X X X X X Enhanced Universal Synchronous Asynchronous Synchronous Receiver Transmitter Mode (EUSART) 7. Timer1/3 8. Note 1: Interrupt The TRMT bit may not indicate when the TSR register is empty. When the timer is operated in Asynchronous External Input mode, unexpected interrupt flag generation may occur. Only those issues indicated in the last column apply to the current silicon revision. DS80000495G-page 2 2010-2015 Microchip Technology Inc. PIC18F87J11 FAMILY 3. Module: Voltage Regulator Silicon Errata Issues This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A6 or C2, respectively). If VDDCORE drops below approximately 2.45V while the on-chip core voltage regulator is enabled, and operating in Voltage Tracking mode, the REGSLP bit (WDTCON <7>) will be automatically cleared. The REGSLP bit cannot be set again by firmware until VDDCORE rises back above the 2.45V approximate threshold. 1. Module: Master Synchronous Serial Port (MSSPx) Additionally, the REGSLP bit retains its previous state upon all Resets except POR. Note: When configured for I2C slave reception, the MSSPx module may not receive the correct data, in extremely rare cases. This occurs only if the Serial Receive/Transmit Buffer Register (SSPxBUF) is not read within a window after the SSPxIF interrupt (PIRx<3>) has occurred. Work around None. Affected Silicon Revisions A1 A2 A4 A5 A6 C1 C2 X Work around The issue can be resolved in either of these ways: • Prior to the I2C slave reception, enable the clock stretching feature. This is done by (SSPxCON2<0>). setting the SEN bit • Each time the SSPxIF is set, read the SSPxBUF before the first rising clock edge of the next byte being received. Affected Silicon Revisions A1 A2 A4 A5 A6 C1 C2 X X X X X X X 2. Module: Oscillator Configurations (PLL) When Phase Lock Loop (PLL) is enabled, if the PLL input frequency is higher than 8 MHz, there may be problems accessing the RAM. Work around Limit the PLL input frequency from 4 MHz to 8 MHz. This will cause the system clock to operate from 16 MHz to 32 MHz. If it is necessary to run the device above 32 MHz, do not enable PLL and use the EC mode. Affected Silicon Revisions A1 A2 X X A4 A5 A6 2010-2015 Microchip Technology Inc. C1 C2 DS80000495G-page 3 PIC18F87J11 FAMILY 4. Module: SRAM 5. Module: Low-Voltage Detect Any access to SRAM, either in the form of read or write operations, will increase the current consumption of the device, depending on how often the SRAM is accessed. A small current increase is normal, but in this cited silicon revision, the difference may be significant and of particular concern for low-power applications. The LVDSTAT, VDDCORE Status bit (WDTCON<6>), is not implemented in this revision of silicon. Work around None. Affected Silicon Revisions For further details, see Table 3. A1 TABLE 3: TYPICAL CURRENT CONSUMPTION A4 A5 A6 C1 C2 X 6. Module: MSSPx (I2C Master) Case 1: Voltage Regulator Enabled Temperature = +25°C SEC_RUN mode using 32 kHz Timer1 Crystal Condition A2 IDD (A) VDD (V) If the module is in I2C Master mode, and the slave performs clock stretching, the first clock pulse after the slave releases the SCLx line may be narrower than the configured clock width. This may result in the slave missing the first clock in the next transmission/reception. No RAM access(1) 59 3.3 Typ RAM access(2) 201 3.3 Work around Extreme RAM access(3) 906 3.3 If the module is in I2C Master mode, do not allow the slave to perform clock stretching. Alternately, the master can slow down the SCLx clock frequency to a level where the slave can detect the narrowed clock pulse. Case 2: Voltage Regulator Disabled VDDCORE is tied to VDD Temperature = +25°C SEC_RUN mode using 32 kHz Timer1 Crystal Condition IDD (A) VDD (V) VDDCORE (V) 20 2.5 2.5 132 2.5 2.5 723 2.5 2.5 No RAM access(1) Typ RAM access(2) Extreme RAM access(3) Note 1: 2: 3: Affected Silicon Revisions Code execution patterns where no instructions access SRAM. Code execution that accesses SRAM, once every seven instruction cycles. Code execution where every instruction cycle executes an instruction that accesses SRAM. A1 A2 A4 A5 A6 C1 X X X X X X C2 7. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In Synchronous Slave Transmission mode, the TRMT bit (TXSTA<1>) may not indicate when the TSR register is empty. Work around Work around Instead of polling the TRMT bit to determine the status of the EUSART, poll the TXIF flag (PIR1<4>) to determine when new data can be written to the TXREG register. None. Affected Silicon Revisions Affected Silicon Revisions A1 A2 A4 A5 A6 C1 C2 A1 A2 A4 A5 A6 C1 C2 X X X X X X X X DS80000495G-page 4 2010-2015 Microchip Technology Inc. PIC18F87J11 FAMILY 8. Module: Timer1/3 When Timer1 or Timer3 is operated in Asynchronous External Input mode, unexpected interrupt flag generation may occur if an external clock edge arrives too soon following a firmware write to the TMRxH:TMRxL registers. An unexpected interrupt flag event may also occur when enabling the module or switching from Synchronous to Asynchronous mode. Work around This issue only applies when operating the timer in Asynchronous mode. Whenever possible, operate the timer module in Synchronous mode to avoid spurious timer interrupts. If Asynchronous mode must be used in the application, potential strategies to mitigate the issue may include any of the following: EXAMPLE 1: • Design the firmware so it does not rely on the TMRxIF flag or keep the respective interrupt disabled. The timer still counts normally and does not reset to 0x0000 when the spurious interrupt flag event is generated. • Design the firmware so that it does not write to the TMRxH:TMRxL registers or does not periodically disable/enable the timer, or switch modes. Reading from the timer does not trigger the spurious interrupt flag events. • If the firmware must use the timer interrupts and must write to the timer (or disable/enable, or mode switch the timer), implement code to suppress the spurious interrupt event, should it occur. This can be achieved by following the process shown in Example 1. ASYNCHRONOUS TIMER MODE WORK AROUND TO AVOID SPURIOUS INTERRUPT //Timer1 update procedure in asynchronous mode //The code below uses Timer1 as example T1CONbits.TMR1ON = 0; PIE1bits.TMR1IE = 0; TMR1H = 0x00; TMR1L = 0x00; T1CONbits.TMR1ON = 1; //Stop timer from incrementing //Temporarily disable Timer1 interrupt vectoring //Update timer value //Turn on timer //Now wait at least two full T1CKI periods + 2TCY before re-enabling Timer1 interrupts. //Depending upon clock edge timing relative to TMR1H/TMR1L firmware write operation, //a spurious TMR1IF flag event may sometimes assert. If this happens, to suppress //the actual interrupt vectoring, the TMR1IE bit should be kept clear until //after the "window of opportunity" (for the spurious interrupt flag event has passed). //After the window is passed, no further spurious interrupts occur, at least //until the next timer write (or mode switch/enable event). while(TMR1L < 0x02); //Wait for 2 timer increments more than the Updated Timer //value (indicating more than 2 full T1CKI clock periods elapsed) //Wait two more instruction cycles NOP(); NOP(); PIR1bits.TMR1IF = 0; PIE1bits.TMR1IE = 1; //Clear TMR1IF flag, in case it was spuriously set //Now re-enable interrupt vectoring for timer 1 Affected Silicon Revisions A1 A2 A4 A5 A6 C1 C2 X X X X X X X 2010-2015 Microchip Technology Inc. DS80000495G-page 5 PIC18F87J11 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39778E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: I/O Ports PORTE pin RE3 is not +5.5V tolerant as indicated in the data sheet. The pin diagrams should be corrected to read as follows: DS80000495G-page 6 2010-2015 Microchip Technology Inc. PIC18F87J11 FAMILY RD7/PMD7/SS2 RD6/PMD6/SCK2/SCL2 RD5/PMD5/SDI2/SDA2 RD4/PMD4/SDO2 RD3/PMD3 RD2/PMD2 RD1/PMD1 VSS VDD RE7/PMA9/ECCP2(1)/P2A(1) RD0/PMD0 RE6/PMA10/P1B RE5/PMA11/P1C RE4/PMA12/P3B RE3/PMA13/P3C/REFO RE2/PMBE/P2B 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/PMWR/P2C RE0/PMRD/P2D RG0/PMA8/ECCP3/P3A RG1/PMA7/TX2/CK2 RG2/PMA6/RX2/DT2 RG3/PMCS1/CCP4/P3D MCLR RG4/PMCS2/CCP5/P1D VSS VDDCORE/VCAP RF7/SS1 RF6/AN11/C1INA RF5/AN10/C1INB/CVREF RF4/AN9/C2INA RF3/AN8/C2INB RF2/PMA5/AN7/C1OUT 48 47 46 45 44 43 1 2 3 4 5 6 7 PIC18F6XJ11 8 9 10 11 12 13 PIC18F6XJ16 14 15 16 RB0/INT0/FLT0 RB1/INT1/PMA4 RB2/INT2/PMA3 RB3/INT3/PMA2 RB4/KBI0/PMA1 42 41 40 RB5/KBI1/PMA0 RB6/KBI2/PGC VSS OSC2/CLKO/RA6 39 38 OSC1/CLKI/RA7 VDD 37 36 35 RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 34 33 RC3/SCK1/SCL1 RC2/ECCP1/P1A Legend: Note 1: RC7/RX1/DT1 RC6/TX1/CK1 RC1/T1OSI/ECCP2(1)/P2A(1) RC0/T1OSO/T13CKI RA4/T0CKI RA5/AN4 VDD VSS RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ AVSS AVDD ENVREG RF1/AN6/C2OUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Shaded pins indicate pins that are tolerant up to +5.5V. The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting. 2010-2015 Microchip Technology Inc. DS80000495G-page 7 PIC18F87J11 FAMILY RD1/AD1/PMD1(3) RD2/AD2/PMD2(3) RD3/AD3/PMD3(3) RD4/AD4/PMD4(3)/SDO2 RD5/AD5/PMD5(3)/SDI2/SDA2 RD6/AD6/PMD6(3)/SCK2/SCL2 RD7/AD7/PMD7(3)/SS2 RJ0/ALE RJ1/OE RE7/AD15/PMA9/ECCP2(1)/P2A(1) RD0/AD0/PMD0(3) VDD VSS RE2/AD10/PMBE(3)/P2B RE3/AD11/PMA13/P3C(2)/REFO RE4/AD12/PMA12/P3B(2) RE5/AD13/PMA11/P1C(2) RE6/AD14/PMA10/P1B(2) RH1/A17 RH0/A16 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/A18/PMD7(3) 1 60 RJ2/WRL RH3/A19/PMD6(3) 2 RE1/AD9/PMWR(3)/P2C RE0/AD8/PMRD(3)/P2D RG0/PMA8/ECCP3/P3A 3 4 5 6 7 59 58 57 RJ3/WRH RB0/INT0/FLT0 RB1/INT1/PMA4 56 55 RB2/INT2/PMA3 51 50 12 13 14 49 48 47 46 45 15 16 17 18 RA4/PMD5(3)/T0CKI 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 RB3/INT3/PMA2/ECCP2(1)/P2A(1) RB4/KBI0/PMA1 RB5/KBI1/PMA0 RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 VDD RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A RJ7/UB RJ6/LB RC1/T1OSI/ECCP2(1)/P2A(1) RC0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RJ4/BA0 RJ5/CE 20 RA5/PMD4(3)/AN4 RH6/PMRD(3)/AN14/ P1C(2)/C1INC RA0/AN0 VSS VDD 19 44 43 42 41 RH5/PMBE(3)/AN13/P3B(2)/C2IND RH4/PMD3(3)/AN12/P3C(2)/C2INC RF1/AN6/C2OUT ENVREG AVDD RH7/PMWR(3)/AN15/P1B(2) Legend: Note 1: 2: 3: 54 53 52 PIC18F8XJ11 PIC18F8XJ16 10 11 RA2/AN2/VREFRA1/AN1 RF7/PMD0(3)/SS1 RF6/PMD1(3)/AN11/C1INA RF5/PMD2(3)/AN10/ C1INB/CVREF RF4/AN9/C2INA RF3/AN8/C2INB RF2/PMA5/AN7/C1OUT 8 9 AVSS RA3/AN3/VREF+ RG1/PMA7/TX2/CK2 RG2/PMA6/RX2/DT2 RG3/PMCS1/CCP4/P3D MCLR RG4/PMCS2/CCP5/P1D VSS VDDCORE/VCAP Shaded pins indicate pins that are tolerant up to +5.5V. The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings. P1B, P1C, P3B, and P3C pin placement depends on the ECCPMX Configuration bit setting. PMP pin placement depends on the PMPMX Configuration bit setting. DS80000495G-page 8 2010-2015 Microchip Technology Inc. PIC18F87J11 FAMILY 2. Module: Input Voltage Levels Table 11-1 in Section 11.1.1 should be corrected to read as follows: TABLE 11-1: Port or Pin PORTA<7:0> INPUT VOLTAGE LEVELS Tolerated Input Description VDD Only VDD input levels are tolerated. 5.5V Tolerates input levels above VDD, useful for most standard logic. PORTC<1:0> PORTE<3> PORTF<6:1> PORTH<7:4>(1) PORTB<7:0> PORTC<7:2> PORTD<7:0> PORTE<7:4> PORTE<2:0> PORTF<7> PORTG<4:0> PORTH<3:0>(1) PORTJ<7:0>(1) Note 1: These ports are not available on PIC18F6XJ1X devices. 2010-2015 Microchip Technology Inc. DS80000495G-page 9 PIC18F87J11 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev G Document (9/2015) Data Sheet Clarifications: Added Modules 1 and 2. Rev A Document (2/2010) Combined existing silicon and data sheet errata documents into the new, single document format. Added the A6 silicon revision, but no issues or clarifications. This document replaces these errata documents: • DS80418A, “PIC18F87J11 Family Rev. A5 Silicon Errata” • DS80417A, “PIC18F87J11 Family Rev. A4 Silicon Errata” • DS80344A, “PIC18F87J11 Family Rev. A2 Silicon Errata” • DS80305B, “PIC18F87J11 Family Rev. A1 Silicon Errata” • DS80408B, “PIC18F87J11 Family Data Sheet Errata” Rev B Document (7/2010) Added silicon issue 6 (MSSPx I2C™ Master). Added data sheet clarifications 10 and 11 (Memory Organization). Rev C Document (8/2010) Added silicon revision B0; includes existing silicon issues 1 (Master Synchronous Serial Port – MSSPx) and 6 (MSSPx – I2C Master). No new data sheet clarifications added. Rev D Document (2/2011) Replaced silicon revision B0 with revision C1 for lower pin count devices. Added silicon issue 12 (Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). Removed data sheet clarification 12 (Electrical Characteristics). Rev E Document (9/2011) Removed data sheet clarification 12 (Guidelines for Getting Started). Added new data sheet clarification 12 (Electrical Specification). Added new silicon revision (C2). Rev F Document (7/2014) Added MPLAB X IDE; Added Module 8, Timer1/3 to Silicon Errata Issues. Data Sheet Clarifications: Removed Modules 1 through 12. DS80000495G-page 10 2010-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-852-9 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2010-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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