dm00119316

RM0383
Reference manual
STM32F411xC/E advanced ARM®-based 32-bit MCUs
Introduction
This Reference manual targets application developers. It provides complete information on
how to use the memory and the peripherals of the STM32F411xC/E microcontroller.
STM32F411xC/E is part of the family of microcontrollers with different memory sizes,
packages and peripherals.
For ordering information, mechanical and electrical device characteristics refer to the
datasheets.
For information on the ARM® Cortex®-M4 with FPU core, refer to the Cortex®-M4 with FPU
Technical Reference Manual.
Related documents
Available from STMicroelectronics web site (http://www.st.com):
• STM32F411xC/E datasheet
For information on the ARM®-M4 core with FPU, refer to the STM32F3xx/F4xxx Cortex®M4 with FPU-M4 programming manual (PM0214).
July 2014
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Contents
RM0383
Contents
1
2
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3
Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.1
I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1.2
D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1.3
S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1.4
DMA memory bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1.5
DMA peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1.6
BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1.7
AHB/APB bridges (APB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.1
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.3.2
Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.3
Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3
Embedded Flash memory in STM32F411xC/E . . . . . . . . . . . . . . . . . . . . 43
3.4
Read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5
2/836
2.1.1
2.2
2.4
3
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.1
Relation between CPU clock frequency and Flash memory read time . 44
3.4.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 45
Erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5.1
Unlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5.2
Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5.3
Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5.4
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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3.5.5
3.6
4
5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6.1
Description of user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6.2
Programming user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6.3
Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6.4
Write protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.6.5
Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 56
3.7
One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.8
Flash interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.8.1
Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 58
3.8.2
Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.8.3
Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 59
3.8.4
Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.8.5
Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.8.6
Flash option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . . . . 62
3.8.7
Flash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.1
CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.4
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.1
Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.2
Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.3
Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4.4
CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Power controller (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1
5.2
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.1
Independent A/D converter supply and reference voltage . . . . . . . . . . . 70
5.1.2
Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.2.1
Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 72
5.2.2
Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.3
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 73
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5.3
5.4
5.5
6
5.3.1
Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.2
Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.3
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.4
Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.5
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.6
Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4.1
PWR power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4.2
PWR power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . 85
PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Reset and clock control (RCC) for STM32F411xC/E . . . . . . . . . . . . . . 87
6.1
6.2
6.3
4/836
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.1
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.2
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.1.3
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.2.1
HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.2.2
HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2.3
PLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.2.4
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2.5
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2.6
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2.7
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2.8
RTC/AWU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.2.9
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2.10
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2.11
Internal/external clock measurement using TIM5/TIM11 . . . . . . . . . . . . 96
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.1
RCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.2
RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 101
6.3.3
RCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 103
6.3.4
RCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.5
RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 108
6.3.6
RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 110
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6.3.7
RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . . . . 110
6.3.8
RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 112
6.3.9
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 114
6.3.10
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 115
6.3.11
RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 115
6.3.12
RCC APB2 peripheral clock enable register
(RCC_APB2ENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.13
RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.14
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.15
RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.16
RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.17
RCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 126
6.3.18
RCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 127
6.3.19
RCC spread spectrum clock generation register (RCC_SSCGR) . . . . 129
6.3.20
RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 130
6.3.21
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) . . 132
6.3.22
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 136
7.1
I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.2
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.2.1
SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 136
7.2.2
SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 137
7.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2.6
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2.7
Compensation cell control register (SYSCFG_CMPCR) . . . . . . . . . . . 140
7.2.8
SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.1
GPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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8.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.4
9
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
8.3.2
I/O pin multiplexer and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
8.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8.3.8
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8.3.10
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.3.11
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.3.12
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8.3.13
Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15
port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8.3.14
Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . 152
8.3.15
Selection of RTC additional functions . . . . . . . . . . . . . . . . . . . . . . . . . 152
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.4.1
GPIO port mode register (GPIOx_MODER) (x = A..E and H) . . . . . . . 153
8.4.2
GPIO port output type register (GPIOx_OTYPER)
(x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
8.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
8.4.5
GPIO port input data register (GPIOx_IDR) (x = A..E and H) . . . . . . . 156
8.4.6
GPIO port output data register (GPIOx_ODR) (x = A..E and H) . . . . . 157
8.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H) . . . . 157
8.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
8.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H) 159
8.4.10
GPIO alternate function high register (GPIOx_AFRH)
(x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
8.4.11
GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.1
6/836
8.3.1
DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
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9.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.3
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
9.3.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
9.3.2
DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
9.3.3
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
9.3.4
Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
9.3.5
DMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
9.3.6
Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 168
9.3.7
Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
9.3.8
Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
9.3.9
Double buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.3.10
Programmable data width, packing/unpacking, endianess . . . . . . . . . 173
9.3.11
Single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.3.12
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.3.13
DMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9.3.14
DMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
9.3.15
Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
9.3.16
Summary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 180
9.3.17
Stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
9.3.18
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
9.4
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
9.5
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
9.5.1
DMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 183
9.5.2
DMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 184
9.5.3
DMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 185
9.5.4
DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 186
9.5.5
DMA stream x configuration register (DMA_SxCR) (x = 0..7) . . . . . . . 187
9.5.6
DMA stream x number of data register (DMA_SxNDTR) (x = 0..7) . . . 190
9.5.7
DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) . 191
9.5.8
DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) 191
9.5.9
DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) 191
9.5.10
DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) . . . . . . 192
9.5.11
DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
10.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 198
10.1.1
NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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10.2
10.3
11
10.1.2
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
10.1.3
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 198
10.2.1
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
10.2.2
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.2.3
Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.2.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.2.5
External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 204
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
10.3.1
Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
10.3.2
Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
10.3.3
Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 206
10.3.4
Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 206
10.3.5
Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 207
10.3.6
Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
10.3.7
EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
11.1
ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
11.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
11.3
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.3.1
ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.3.2
ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.3.3
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.3.4
Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.3.5
Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.3.6
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.3.7
Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.3.8
Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.3.9
Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8/836
11.4
Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
11.5
Channel-wise programmable sampling time . . . . . . . . . . . . . . . . . . . . . 217
11.6
Conversion on external trigger and trigger polarity . . . . . . . . . . . . . . . . 218
11.7
Fast conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.8
Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
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11.9
11.8.1
Using the DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.8.2
Managing a sequence of conversions without using the DMA . . . . . . 220
11.8.3
Conversions without DMA and without overrun detection . . . . . . . . . . 221
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.10 Battery charge monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 229
11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 229
11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . 230
11.12.7 ADC watchdog higher threshold register (ADC_HTR) . . . . . . . . . . . . . 230
11.12.8 ADC watchdog lower threshold register (ADC_LTR) . . . . . . . . . . . . . . 231
11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 231
11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 232
11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 232
11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 233
11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 233
11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 234
11.12.15 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . . 235
11.12.16 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
12
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
12.1
TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
12.2
TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
12.3
TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
12.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
12.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.3.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.3.4
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
12.3.5
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
12.3.6
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
12.3.7
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.3.8
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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12.3.9
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
12.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
12.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 262
12.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
12.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 266
12.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
12.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
12.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
12.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
12.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
12.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 274
12.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
12.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
12.4
TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
12.4.1
TIM1 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 278
12.4.2
TIM1 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 279
12.4.3
TIM1 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . 282
12.4.4
TIM1 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 284
12.4.5
TIM1 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
12.4.6
TIM1 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 287
12.4.7
TIM1 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 289
12.4.8
TIM1 capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 292
12.4.9
TIM1 capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 293
12.4.10 TIM1 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
12.4.11 TIM1 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
12.4.12 TIM1 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 297
12.4.13 TIM1 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . . . . . . 298
12.4.14 TIM1 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 298
12.4.15 TIM1 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 299
12.4.16 TIM1 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 299
12.4.17 TIM1 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 300
12.4.18 TIM1 break and dead-time register (TIMx_BDTR) . . . . . . . . . . . . . . . 300
12.4.19 TIM1 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 302
12.4.20 TIM1 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 303
12.4.21 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
13
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General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 306
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13.1
TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
13.2
TIM2 to TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
13.3
TIM2 to TIM5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
13.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
13.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
13.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
13.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
13.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
13.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
13.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
13.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
13.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
13.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
13.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 329
13.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
13.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
13.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 333
13.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
13.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
13.4
TIM2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
13.4.1
TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 342
13.4.2
TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 344
13.4.3
TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 345
13.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 348
13.4.5
TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
13.4.6
TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 351
13.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 352
13.4.8
TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 355
13.4.9
TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 356
13.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
13.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
13.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 358
13.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 358
13.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 359
13.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 359
13.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 360
13.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 360
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13.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 361
13.4.19 TIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
13.4.20 TIM5 option register (TIM5_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
13.4.21 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
14
General-purpose timers (TIM9 to TIM11) . . . . . . . . . . . . . . . . . . . . . . . 366
14.1
TIM9/10/11 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.2
TIM9/10/11 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.3
14.2.1
TIM9 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.2.2
TIM10/TIM11 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
TIM9 to TIM11 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
14.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
14.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
14.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
14.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
14.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
14.3.6
PWM input mode (only for TIM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
14.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
14.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
14.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
14.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.3.11 TIM9 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 382
14.3.12 Timer synchronization (TIM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
14.3.13 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
14.4
TIM9 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
14.4.1
TIM9 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 385
14.4.2
TIM9 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . 387
14.4.3
TIM9 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . . . 388
14.4.4
TIM9 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
14.4.5
TIM9 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 390
14.4.6
TIM9 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 392
14.4.7
TIM9 capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 395
14.4.8
TIM9 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
14.4.9
TIM9 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
14.4.10 TIM9 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 396
14.4.11 TIM9 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 397
14.4.12 TIM9 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 397
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14.4.13 TIM9 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.5
TIM10/11 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
14.5.1
TIM10/11 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . 400
14.5.2
TIM status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
14.5.3
TIM event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . 401
14.5.4
TIM10/11 capture/compare mode register 1
(TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
14.5.5
TIM10/11 capture/compare enable register
(TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
14.5.6
TIM10/11 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
14.5.7
TIM10/11 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
14.5.8
TIM10/11 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 406
14.5.9
TIM10/11 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 407
14.5.10 TIM11 option register 1 (TIM11_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . 407
14.5.11 TIM10/11 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
15
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.1
IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.3
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.4
16
15.3.1
Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.3.2
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.3.3
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
15.4.1
Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
15.4.2
Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
15.4.3
Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
15.4.4
Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
15.4.5
IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
16.1
WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
16.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
16.3
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
16.4
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 418
16.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
16.6
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
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16.6.1
Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
16.6.2
Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 421
16.6.3
Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
16.6.4
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
17.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
17.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
17.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
17.3.1
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
17.3.2
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
17.3.3
Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
17.3.4
Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
17.3.5
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
17.3.6
Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
17.3.7
Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
17.3.8
RTC synchronization
17.3.9
RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
17.3.10 RTC coarse digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
17.3.11 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
17.3.12 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
17.3.13 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
17.3.14 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
17.3.15 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
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RTC and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
17.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
17.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
17.6.1
RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
17.6.2
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
17.6.3
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
17.6.4
RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 443
17.6.5
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 445
17.6.6
RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 446
17.6.7
RTC calibration register (RTC_CALIBR) . . . . . . . . . . . . . . . . . . . . . . . 446
17.6.8
RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 447
17.6.9
RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 448
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17.6.10 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 449
17.6.11 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 450
17.6.12 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 451
17.6.13 RTC time stamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 451
17.6.14 RTC time stamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 452
17.6.15 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . . 453
17.6.16 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 453
17.6.17 RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
17.6.18 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 456
17.6.19 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 457
17.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 459
17.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
18
Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 462
18.1
I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
18.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
18.3
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
18.3.1
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
18.3.2
I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
18.3.3
I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
18.3.4
Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
18.3.5
Programmable noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
18.3.6
SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
18.3.7
SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
18.3.8
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
18.3.9
Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
2
18.4
I C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
18.5
I2C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
18.6
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
18.6.1
I2C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
18.6.2
I2C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
18.6.3
I2C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 487
18.6.4
I2C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 487
18.6.5
I2C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
18.6.6
I2C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
18.6.7
I2C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
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18.6.8
I2C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 493
18.6.9
I2C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
18.6.10 I2C FLTR register (I2C_FLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
18.6.11 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
19
Universal synchronous asynchronous receiver
transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
19.1
USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
19.2
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
19.3
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
19.3.1
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
19.3.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
19.3.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
19.3.4
Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
19.3.5
USART receiver tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . 521
19.3.6
Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
19.3.7
Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
19.3.8
LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 524
19.3.9
USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
19.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 528
19.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
19.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
19.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 533
19.3.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
20
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19.4
USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
19.5
USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
19.6
USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
19.6.1
Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
19.6.2
Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
19.6.3
Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
19.6.4
Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
19.6.5
Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
19.6.6
Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
19.6.7
Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 547
19.6.8
USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
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20.1
SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
20.2
SPI and I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
20.3
20.2.1
SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
20.2.2
I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
20.3.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
20.3.2
Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
20.3.3
Configuring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 558
20.3.4
Configuring the SPI for half-duplex communication . . . . . . . . . . . . . . . 560
20.3.5
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 560
20.3.6
CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
20.3.7
Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
20.3.8
Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
20.3.9
SPI communication using DMA (direct memory addressing) . . . . . . . 571
20.3.10 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
20.3.11 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
20.4
I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
20.4.1
I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
20.4.2
I2S full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
20.4.3
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
20.4.4
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
20.4.5
I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
20.4.6
I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
20.4.7
Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
20.4.8
Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
20.4.9
I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
20.4.10 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
20.5
SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
20.5.1
SPI control register 1 (SPI_CR1)(not used in I2S mode) . . . . . . . . . . . 593
20.5.2
SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
20.5.3
SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
20.5.4
SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
20.5.5
SPI CRC polynomial register (SPI_CRCPR)(not used in I2S
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
20.5.6
SPI RX CRC register (SPI_RXCRCR)(not used in I2S mode) . . . . . . . 598
20.5.7
SPI TX CRC register (SPI_TXCRCR)(not used in I2S mode) . . . . . . . 598
20.5.8
SPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 599
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20.5.9
SPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 600
20.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
21
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 603
21.1
SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
21.2
SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
21.3
SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
21.4
21.3.1
SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
21.3.2
SDIO APB2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
21.4.1
Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
21.4.2
Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
21.4.3
Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
21.4.4
Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
21.4.5
Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
21.4.6
Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
21.4.7
Stream access, stream write and stream read
(MultiMediaCard only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
21.4.8
Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . 622
21.4.9
Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
21.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
21.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
21.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
21.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
21.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
21.5
21.6
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Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
21.5.1
R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
21.5.2
R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
21.5.3
R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
21.5.4
R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
21.5.5
R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
21.5.6
R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
21.5.7
R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
21.5.8
R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
21.6.1
SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 641
21.6.2
SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 642
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21.7
21.6.3
SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
21.6.4
SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
21.7.1
Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 642
21.7.2
Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 643
21.7.3
CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
21.7.4
Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
21.8
HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
21.9
SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
21.9.1
SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 643
21.9.2
SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . 644
21.9.3
SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 645
21.9.4
SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 646
21.9.5
SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 647
21.9.6
SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 647
21.9.7
SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 648
21.9.8
SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 648
21.9.9
SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 649
21.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . . 650
21.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
21.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 652
21.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
21.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 656
21.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 657
21.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
22
USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 659
22.1
OTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
22.2
OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
22.3
22.4
22.2.1
General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
22.2.2
Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
22.2.3
Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
22.3.1
OTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
22.3.2
Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
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22.5
22.6
22.7
22.4.1
ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
22.4.2
HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
22.4.3
SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
22.5.1
SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
22.5.2
Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
22.5.3
Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
22.6.1
SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
22.6.2
USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
22.6.3
Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
22.6.4
Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
22.7.1
Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
22.7.2
Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
22.8
Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
22.9
Dynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . . 676
22.10 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
22.11 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
22.11.1 Peripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
22.11.2 Peripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
22.12 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
22.12.1 Host Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
22.12.2 Host Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
22.13 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
22.13.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
22.13.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
22.14 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
22.15 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
22.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
22.16.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
22.16.2 OTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
22.16.3 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
22.16.4 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
22.16.5 OTG_FS power and clock gating control register
(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
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22.16.6 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
22.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
22.17.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
22.17.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
22.17.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
22.17.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
22.17.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
22.17.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
22.17.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
22.17.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
23
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
23.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
23.2
Reference ARM® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
23.3
SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . 798
23.3.1
23.4
Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . . 799
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
23.4.1
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
23.4.2
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
23.4.3
Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . 801
23.4.4
Using serial wire and releasing the unused debug pins as GPIOs . . . 802
23.5
STM32F411xC/E JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . 802
23.6
ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
23.6.1
MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
23.6.2
Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
23.6.3
Cortex®-M4 with FPU TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
23.6.4
Cortex®-M4 with FPU JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . 805
23.7
JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
23.8
SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
23.8.1
SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
23.8.2
SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
23.8.3
SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 808
23.8.4
DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
23.8.5
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
23.8.6
SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
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RM0383
23.9
AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .811
23.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
23.11 Capability of the debugger host to connect under system reset . . . . . . 813
23.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
23.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
23.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . 814
23.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
23.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . . 814
23.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
23.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
23.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
23.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
23.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
23.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
23.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 817
23.16.2 Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 818
23.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
23.16.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . . 819
23.16.5 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . . . . . . 820
23.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
23.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
23.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
23.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
23.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . . 825
23.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . . 825
23.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
23.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
23.17.8 TRACECLKIN connection inside the STM32F411xC/E . . . . . . . . . . . . 826
23.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
23.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
23.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
24
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Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
24.1
Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
24.2
Flash size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
DocID026448 Rev 1
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
STM32F411xC/E register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Memory mapping vs. Boot mode/physical remap in STM32F411xC/E. . . . . . . . . . . . . . . . 41
Flash module organization (STM32F411xC/E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . 44
Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Access versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
OTP area organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CRC calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Sleep-now entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Sleep-on-exit entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Stop operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Stop mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Standby mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RCC register map and reset values for STM32F411xC/E . . . . . . . . . . . . . . . . . . . . . . . . 133
SYSCFG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
RTC additional functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DMA1 request mapping (STM32F411xC/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DMA2 request mapping (STM32F411xC/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Source and destination address registers in Double buffer mode (DBM=1). . . . . . . . . . . 173
Packing/unpacking & endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . . . 174
Restriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
FIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Possible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Vector table for STM32F411xC/E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 208
ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
External trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
ADC register map and reset values for each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
ADC register map and reset values (common ADC registers) . . . . . . . . . . . . . . . . . . . . . 237
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
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RM0383
TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Output control bits for complementary OCx and OCxN channels with
break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
TIM2 to TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
TIM9 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
TIM10/11 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Min/max IWDG timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Effect of low power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . . . . . . . . . . . . . . . . . . 475
SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,
oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
USART receiver’s tolerance when DIV fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
USART receiver tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . . 521
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . . . . . . . . . . . . . . . . . 586
DocID026448 Rev 1
RM0383
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
List of tables
I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 807
Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Cortex®-M4 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
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List of tables
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
26/836
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Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
DocID026448 Rev 1
RM0383
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Flash memory interface connection inside system architecture
(STM32F411xC/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Sequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
PCROP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Frequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . 97
Frequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 98
Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Selecting an alternate function onSTM32F411xC/E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
System implementation of the two DMA controllers( STM32F411xC/E) . . . . . . . . . . . . . 165
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Right alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Left alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Left alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 221
Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 241
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 241
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 243
Counter timing diagram, update event when ARPE=1
DocID026448 Rev 1
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List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
28/836
RM0383
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Counter timing diagram, update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 247
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 248
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 249
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 249
Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 250
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 251
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 254
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 255
Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 255
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 262
Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 263
Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 271
Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 271
Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 277
General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 308
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 309
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 311
Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 312
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
DocID026448 Rev 1
RM0383
Figure 98.
Figure 99.
Figure 100.
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
Figure 117.
Figure 118.
Figure 119.
Figure 120.
Figure 121.
Figure 122.
Figure 123.
Figure 124.
Figure 125.
Figure 126.
Figure 127.
Figure 128.
Figure 129.
Figure 130.
Figure 131.
Figure 132.
Figure 133.
Figure 134.
Figure 135.
Figure 136.
Figure 137.
Figure 138.
Figure 139.
Figure 140.
Figure 141.
Figure 142.
Figure 143.
Figure 144.
Figure 145.
Figure 146.
Figure 147.
List of figures
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 315
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 316
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 317
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 317
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 318
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 320
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 321
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 332
Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 332
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
General-purpose timer block diagram (TIM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
General-purpose timer block diagram (TIM10/11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 370
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 370
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 374
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 375
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
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List of figures
Figure 148.
Figure 149.
Figure 150.
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Figure 152.
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Figure 154.
Figure 155.
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Figure 173.
Figure 174.
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Figure 178.
Figure 179.
Figure 180.
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Figure 183.
Figure 184.
Figure 185.
Figure 186.
Figure 187.
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Figure 189.
Figure 190.
Figure 191.
Figure 192.
Figure 193.
Figure 194.
Figure 195.
Figure 196.
Figure 197.
Figure 198.
Figure 199.
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RM0383
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 376
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 525
Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 526
USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
IrDA data modulation (3/16) -Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
TI mode - Slave mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
TI mode - Slave mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
TI mode - master mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
TI mode - master mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and
DocID026448 Rev 1
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List of figures
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 200. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 201. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in
case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 202. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of
continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Figure 203. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of
continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Figure 204. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of
discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 205. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Figure 206. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Figure 207. TI mode frame format error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Figure 208. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Figure 209. I2S full duplex block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Figure 210. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 578
Figure 211. I2S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 578
Figure 212. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Figure 213. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Figure 214. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 579
Figure 215. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 216. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 580
Figure 217. MSB Justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 218. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . 581
Figure 219. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 220. LSB Justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 221. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 222. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 223. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 583
Figure 224. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 583
Figure 225. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Figure 226. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 584
Figure 227. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Figure 228. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Figure 229. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Figure 230. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Figure 231. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Figure 232. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Figure 233. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Figure 234. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Figure 235. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Figure 236. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Figure 237. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Figure 238. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Figure 239. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Figure 240. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Figure 241. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Figure 242. OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Figure 243. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Figure 244. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 245. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
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List of figures
RM0383
Figure 246.
Figure 247.
Figure 248.
Figure 249.
Figure 250.
Figure 251.
Figure 252.
Figure 253.
Figure 254.
Figure 255.
Figure 256.
Figure 257.
Figure 258.
Figure 259.
Figure 260.
Figure 261.
Figure 262.
Figure 263.
Figure 264.
Figure 265.
Figure 266.
SOF connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Updating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 677
Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . . 678
Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 757
Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Block diagram of STM32 MCU and Cortex®-M4 with FPU-level
debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 267. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Figure 268. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Figure 269. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
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Documentation conventions
1
Documentation conventions
1.1
List of abbreviations for registers
The following abbreviations are used in register descriptions:
read/write (rw)
Software can read and write to these bits.
read-only (r)
Software can only read these bits.
write-only (w)
Software can only write to this bit. Reading the bit returns the reset
value.
read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has
no effect on the bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has
no effect on the bit value.
read/clear by read Software can read this bit. Reading this bit automatically clears it to ‘0’.
(rc_r)
Writing ‘0’ has no effect on the bit value.
read/set (rs)
Software can read as well as set this bit. Writing ‘0’ has no effect on the
bit value.
read-only write
trigger (rt_w)
Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no
effect on the bit value.
toggle (t)
Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.
Reserved (Res.)
Reserved bit, must be kept at reset value.
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Documentation conventions
1.2
RM0383
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
The CPU core integrates two debug ports:
–
JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
–
SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, please refer to the Cortex®-M4 with FPU
Technical Reference Manual
1.3
•
Word: data/instruction of 32-bit length.
•
Half word: data/instruction of 16-bit length.
•
Byte: data of 8-bit length.
•
Double word: data of 64-bit length.
•
IAP (in-application programming): IAP is the ability to reprogram the Flash memory of a
microcontroller while the user program is running.
•
ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
•
I-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction
interface. Prefetch is performed on this bus.
•
D-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU
to the Flash data interface.
•
Option bytes: product configuration bits stored in the Flash memory.
•
OBL: option byte loader.
•
AHB: advanced high-performance bus.
•
CPU: refers to the Cortex®-M4 with FPU core.
Peripheral availability
For information on the availability and the number of instances of each peripheral, refer to
the STM32F411xC/E datasheet.
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Memory and bus architecture
2
Memory and bus architecture
2.1
System architecture
In STM32F411xC/E, the main system consists of 32-bit multilayer AHB bus matrix that
interconnects:
•
•
Six masters:
–
Cortex®-M4 with FPU core I-bus, D-bus and S-bus
–
DMA1 memory bus
–
DMA2 memory bus
–
DMA2 peripheral bus
Five slaves:
–
Internal Flash memory ICode bus
–
Internal Flash memory DCode bus
–
Main internal SRAM
–
AHB1 peripherals including AHB to APB bridges and APB peripherals
–
AHB2 peripherals
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1.
Figure 1. System architecture
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Memory and bus architecture
2.1.1
RM0383
I-bus
This bus connects the Instruction bus of the Cortex®-M4 with FPU core to the BusMatrix.
This bus is used by the core to fetch instructions. The target of this bus is a memory
containing code (internal Flash memory/SRAM).
2.1.2
D-bus
This bus connects the databus of the Cortex®-M4 with FPU to the BusMatrix. This bus is
used by the core for literal load and debug access. The target of this bus is a memory
containing code or data (internal Flash memory/SRAM).
2.1.3
S-bus
This bus connects the system bus of the Cortex®-M4 with FPU core to a BusMatrix. This
bus is used to access data located in a peripheral or in SRAM. Instructions may also be
fetch on this bus (less efficient than ICode). The targets of this bus are the internal SRAM,
the AHB1 peripherals including the APB peripherals and the AHB2 peripherals.
2.1.4
DMA memory bus
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal Flash memory, internal SRAM and additionally for S4 the AHB1/AHB2 peripherals
including the APB peripherals.
2.1.5
DMA peripheral bus
This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is
used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.
The targets of this bus are the AHB and APB peripherals plus data memories: Flash
memory and internal SRAM.
2.1.6
BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
round-robin algorithm.
2.1.7
AHB/APB bridges (APB)
The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between
the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.
Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies,
and to Table 1 for the address mapping of AHB and APB peripherals.
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash
memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR or RCC_APBxENR register.
Note:
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When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
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2.2
Memory and bus architecture
Memory organization
Program memory, data memory, registers and I/O ports are organized within the same linear
4 Gbyte address space.
The bytes are coded in memory in little endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte, the word’s
most significant.
For the detailed mapping of peripheral registers, please refer to the related chapters.
The addressable memory space is divided into 8 main blocks, each of 512 MB.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”). Refer to the memory map figure in the product datasheet.
2.3
Memory map
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map. Table 1 gives the boundary addresses of the peripherals available in
STM32F411xC/E device.
Table 1. STM32F411xC/E register boundary addresses
Boundary address
Peripheral
Bus
0x5000 0000 - 0x5003 FFFF
USB OTG FS
AHB2
0x4002 6400 - 0x4002 67FF
DMA2
0x4002 6000 - 0x4002 63FF
DMA1
0x4002 3C00 - 0x4002 3FFF
Flash interface
register
0x4002 3800 - 0x4002 3BFF
RCC
0x4002 3000 - 0x4002 33FF
CRC
0x4002 1C00 - 0x4002 1FFF
GPIOH
0x4002 1000 - 0x4002 13FF
GPIOE
0x4002 0C00 - 0x4002 0FFF
GPIOD
0x4002 0800 - 0x4002 0BFF
GPIOC
0x4002 0400 - 0x4002 07FF
GPIOB
0x4002 0000 - 0x4002 03FF
GPIOA
Register map
Section 22.16.6: OTG_FS register map on
page 744
Section 9.5.11: DMA register map on page 194
Section 3.8: Flash interface registers on page 58
Section 6.3.22: RCC register map on page 133
Section 4.4.4: CRC register map on page 68
AHB1
Section 8.4.11: GPIO register map on page 160
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Memory and bus architecture
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Table 1. STM32F411xC/E register boundary addresses (continued)
Boundary address
Peripheral
0x4001 5000 - 0x4001 53FFF
SPI5/I2S5
0x4001 4800 - 0x4001 4BFF
TIM11
0x4001 4400 - 0x4001 47FF
TIM10
Section 14.5.11: TIM10/11 register map on
page 407
0x4001 4000 - 0x4001 43FF
TIM9
Section 14.4.13: TIM9 register map on page 397
0x4001 3C00 - 0x4001 3FFF
EXTI
Section 10.3.7: EXTI register map on page 208
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x4001 3400 - 0x4001 37FF
SPI4/I2S4
0x4001 3000 - 0x4001 33FF
SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF
SDIO
Section 21.9.16: SDIO register map on page 657
0x4001 2000 - 0x4001 23FF
ADC1
Section 11.12.16: ADC register map on page 235
0x4001 1400 - 0x4001 17FF
USART6
0x4001 1000 - 0x4001 13FF
USART1
0x4001 0000 - 0x4001 03FF
TIM1
Section 12.4.21: TIM1 register map on page 304
0x4000 7000 - 0x4000 73FF
PWR
Section 5.5: PWR register map on page 86
0x4000 5C00 - 0x4000 5FFF
I2C3
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
I2S3ext
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3400 - 0x4000 37FF
I2S2ext
0x4000 3000 - 0x4000 33FF
IWDG
0x4000 2C00 - 0x4000 2FFF
WWDG
0x4000 2800 - 0x4000 2BFF
RTC & BKP Registers
0x4000 0C00 - 0x4000 0FFF
TIM5
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
2.3.1
Bus
Register map
Section 20.5.10: SPI register map on page 602
Section 7.2.8: SYSCFG register map
APB2
Section 20.5.10: SPI register map on page 602
Section 19.6.8: USART register map on page 548
Section 18.6.11: I2C register map on page 496
Section 19.6.8: USART register map on page 548
Section 20.5.10: SPI register map on page 602
APB1
Section 15.4.5: IWDG register map on page 415
Section 16.6.4: WWDG register map on page 422
Section 17.6.21: RTC register map on page 459
Section 13.4.21: TIMx register map on page 364
Embedded SRAM
STM32F411xC/E devices feature 128 Kbytes of system SRAM.
The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state.
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Memory and bus architecture
The CPU can access the embedded SRAM through the System Bus or through the ICode/D-Code buses when boot from SRAM is selected or when physical remap is selected
(Section 7.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG
controller). To get the max performance on SRAM execution, physical remap should be
selected (boot or software selection).
2.3.2
Flash memory overview
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
The Flash memory is organized as follows:
•
A main memory block divided into sectors.
•
System memory from which the device boots in System memory boot mode
•
512 OTP (one-time programmable) bytes for user data.
•
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Refer to Section 3: Embedded Flash memory interface for more details.
2.3.3
Bit banding
The Cortex®-M4 with FPU memory map includes two bit-band regions. These regions map
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32F4xx devices both the peripheral registers and the SRAM are mapped to a bitband region, so that single bit-band write and read operations are allowed. The operations
are only available for Cortex®-M4 with FPU accesses, and not from other bus masters (e.g.
DMA).
A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)
where:
–
bit_word_addr is the address of the word in the alias memory region that maps to
the targeted bit
–
bit_band_base is the starting address of the alias region
–
byte_offset is the number of the byte in the bit-band region that contains the
targeted bit
–
bit_number is the bit position (0-7) of the targeted bit
Example
The following example shows how to map bit 2 of the byte located at SRAM address
0x20000300 to the alias region:
0x22006008 = 0x22000000 + (0x300*32) + (2*4)
Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM address 0x20000300.
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Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM
address 0x20000300 (0x01: bit set; 0x00: bit reset).
For more information on bit-banding, please refer to the Cortex®-M4 with FPU programming
manual (see Related documents on page 1).
2.4
Boot configuration
Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed
through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex®-M4 with FPU CPU always
fetches the reset vector on the ICode bus, which implies to have the boot space available
only in the code area (typically, Flash memory). STM32F4xx microcontrollers implement a
special mechanism to be able to boot from other memories (like the internal SRAM).
In the STM32F4xx, three different boot modes can be selected through the BOOT[1:0] pins
as shown in Table 2.
Table 2. Boot modes
Boot mode selection pins
Boot mode
Aliasing
BOOT1
BOOT0
x
0
Main Flash memory Main Flash memory is selected as the boot space
0
1
System memory
System memory is selected as the boot space
1
1
Embedded SRAM
Embedded SRAM is selected as the boot space
The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It
is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot
mode.
BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been
sampled, the corresponding GPIO pin is free and can be used for other purposes.
The BOOT pins are also resampled when the device exits the Standby mode. Consequently,
they must be kept in the required Boot mode configuration when the device is in the Standby
mode. After this startup delay is over, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.
Note:
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When the device boots from SRAM, in the application initialization code, you have to
relocate the vector table in SRAM using the NVIC exception table and the offset register.
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Memory and bus architecture
Embedded bootloader
The embedded bootloader mode is used to reprogram the Flash memory using one of the
following serial interfaces:
•
USART1 (PA9/PA10)
•
USART2 (PD5/PD6)
•
I2C1 (PB6/PB7)
•
I2C2 (PB10/PB3)
•
I2C3 (PA8/PB4)
•
SPI1 (PA4/PA5/PA6/PA7)
•
SPI2 (PB12/PB13/PB14/PB15)
•
SPI3 (PA15/PC10/PC11/PC12)
•
USB OTG FS (PA11/12) in Device mode (DFU: device firmware upgrade).
The USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency, while the
USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to 26 MHz).
The embedded bootloader code is located in system memory. It is programmed by ST
during production. For additional information, refer to application note AN2606.
Physical remap in STM32F411xC/E
Once the boot pins are selected, the application software can modify the memory
accessible in the code area (in this way the code can be executed through the ICode bus in
place of the System bus). This modification is performed by programming the Section 7.2.1:
SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.
The following memories can thus be remapped:
•
Main Flash memory
•
System memory
•
Embedded SRAM1
Table 3. Memory mapping vs. Boot mode/physical remap in STM32F411xC/E
Addresses
Boot/Remap in main
Flash memory
Boot/Remap in
embedded SRAM
Boot/Remap in
System memory
0x2000 0000 - 0x2002 0000
SRAM1 (128 KB)
SRAM1 (128KB)
SRAM1 (128KB)
0x1FFF 0000 - 0x1FFF 77FF
System memory
System memory
System memory
0x0804 0000 - 0x1FFE FFFF
Reserved
Reserved
Reserved
0x0800 0000 - 0x0807 FFFF
Flash memory
Flash memory
Flash memory
0x0400 000 - 0x07FF FFFF
Reserved
Reserved
Reserved
SRAM1 (128 KB)
Aliased
System memory
(30 KB) Aliased
0x0000 0000 - 0x0007 FFFF(1) Flash (512 KB) Aliased
1. Even when aliased in the boot memory space, the related memory is still accessible at its original memory
space.
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Embedded Flash memory interface
3.1
Introduction
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2
Main features
•
Flash memory read operations
•
Flash memory program/erase operations
•
Read / write protections
•
Prefetch on I-Code
•
64 cache lines of 128 bits on I-Code
•
8 cache lines of 128 bits on D-Code
Figure 2 shows the Flash memory interface connection inside the system architecture.
Figure 2. Flash memory interface connection inside system architecture
(STM32F411xC/E)
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3.3
Embedded Flash memory interface
Embedded Flash memory in STM32F411xC/E
The Flash memory has the following main features:
•
Capacity up to 512 KBytes for STM32F411xC/E
•
128 bits wide data read
•
Byte, half-word, word and double word write
•
Sector and mass erase
•
Memory organization
The Flash memory is organized as follows:
–
A main memory block divided into 4 sectors of 16 KBytes, 1 sector of 64 KBytes, 3
sectors of 128 Kbytes (STM32F411xC/E).
–
System memory from which the device boots in System memory boot mode
–
512 OTP (one-time programmable) bytes for user data
The OTP area contains 16 additional bytes used to lock the corresponding OTP
data block.
–
•
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Low-power modes (for details refer to the Power control (PWR) section of the reference
manual)
Table 4. Flash module organization (STM32F411xC/E)
Block
Name
Block base addresses
Size
Sector 0
0x0800 0000 - 0x0800 3FFF
16 Kbytes
Sector 1
0x0800 4000 - 0x0800 7FFF
16 Kbytes
Sector 2
0x0800 8000 - 0x0800 BFFF
16 Kbytes
Sector 3
0x0800 C000 - 0x0800 FFFF
16 Kbytes
Sector 4
0x0801 0000 - 0x0801 FFFF
64 Kbytes
Sector 5
0x0802 0000 - 0x0803 FFFF
128 Kbytes
Sector 6
0x0804 0000 - 0x0805 FFFF
128 Kbytes
Sector 7
0x0806 0000 - 0x0807 FFFF
128 Kbytes
System memory
0x1FFF 0000 - 0x1FFF 77FF
30 Kbytes
OTP area
0x1FFF 7800 - 0x1FFF 7A0F
528 bytes
Option bytes
0x1FFF C000 - 0x1FFF C00F
16 bytes
Main memory
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3.4
Read interface
3.4.1
Relation between CPU clock frequency and Flash memory read time
To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
The prefetch buffer must be disabled when the supply voltage is below 2.1 V. The
correspondence between wait states and CPU clock frequency is given in Table 5.
- when VOS[1:0] = 0x01, the maximum value of fHCLK = 64 MHz.
- when VOS[1:0] = 0x10, the maximum value of fHCLK = 84 MHz.
- when VOS[1:0] = 0x11, the maximum value of fHCLK = 100 MHz.
Table 5. Number of wait states according to CPU clock (HCLK) frequency
HCLK (MHz)
Wait states (WS)
Voltage range
Voltage range
Voltage range
Voltage range
2.7 V - 3.6 V
2.4 V - 2.7 V
2.1 V - 2.4 V
1.71 V - 2.1 V
0 WS (1 CPU cycle)
0 < HCLK≤ 30
0 < HCLK ≤ 24
0 < HCLK ≤ 18
0 < HCLK ≤ 16
1 WS (2 CPU cycles)
30 < HCLK ≤ 64
24 < HCLK ≤ 48
18 < HCLK ≤ 36
16 <HCLK ≤ 32
2 WS (3 CPU cycles)
64 < HCLK ≤ 90
48 < HCLK ≤ 72
36 < HCLK ≤ 54
32 < HCLK ≤ 48
3 WS (4 CPU cycles)
90 < HCLK ≤ 100
72 < HCLK ≤ 96
54 < HCLK ≤ 72
48 < HCLK ≤ 64
4 WS (5 CPU cycles)
-
96 < HCLK ≤ 100
72 < HCLK ≤ 90
64 < HCLK ≤ 80
5 WS (6 CPU cycles)
-
-
90 < HCLK ≤ 100
80 < HCLK ≤ 96
6 WS (7 CPU cycles)
-
-
-
96 < HCLK ≤ 100
(LATENCY)
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states needed to access the Flash memory with the CPU frequency.
Increasing the CPU frequency
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1.
Program the new number of wait states to the LATENCY bits in the FLASH_ACR
register
2.
Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register
3.
Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4.
If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5.
Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
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Embedded Flash memory interface
Decreasing the CPU frequency
1.
Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
2.
If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
3.
Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register
4.
Program the new number of wait states to the LATENCY bits in FLASH_ACR
5.
Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register
Note:
A change in CPU clock configuration or wait state (WS) configuration may not be effective
straight away. To make sure that the current CPU clock frequency is the one you have
configured, you can check the AHB prescaler factor and clock source status values. To
make sure that the number of WS you have programmed is effective, you can read the
FLASH_ACR register.
3.4.2
Adaptive real-time memory accelerator (ART Accelerator™)
The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard ARM® Cortex®-M4 with FPU processors. It balances the inherent
performance advantage of the ARM® Cortex®-M4 with FPU over Flash memory
technologies, which normally requires the processor to wait for the Flash memory at higher
operating frequencies.
To release the processor full performance, the accelerator implements an instruction
prefetch queue and branch cache which increases program execution speed from the 128bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the
ART accelerator is equivalent to 0 wait state program execution from Flash memory at a
CPU frequency up to 100 MHz.
Instruction prefetch
Each Flash memory read operation provides 128 bits from either four instructions of 32 bits
or 8 instructions of 16 bits according to the program launched. So, in case of sequential
code, at least four CPU cycles are needed to execute the previous read instruction line.
Prefetch on the I-Code bus can be used to read the next sequential instruction line from the
Flash memory while the current instruction line is being requested by the CPU. Prefetch is
enabled by setting the PRFTEN bit in the FLASH_ACR register. This feature is useful if at
least one wait state is needed to access the Flash memory.
Figure 3 shows the execution of sequential 32-bit instructions with and without prefetch
when 3 WSs are needed to access the Flash memory.
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Figure 3. Sequential 32-bit instruction execution
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When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
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Embedded Flash memory interface
Instruction cache memory
To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction
cache memory. This feature can be enabled by setting the instruction cache enable (ICEN)
bit in the FLASH_ACR register. Each time a miss occurs (requested data not present in the
currently used instruction line, in the prefetched instruction line or in the instruction cache
memory), the line read is copied into the instruction cache memory. If some data contained
in the instruction cache memory are requested by the CPU, they are provided without
inserting any delay. Once all the instruction cache memory lines have been filled, the LRU
(least recently used) policy is used to determine the line to replace in the instruction memory
cache. This feature is particularly useful in case of code containing loops.
Data management
Literal pools are fetched from Flash memory through the D-Code bus during the execution
stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested
literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB
databus D-Code have priority over accesses through the AHB instruction bus I-Code.
If some literal pools are frequently used, the data cache memory can be enabled by setting
the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the
instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.
Note:
Data in user configuration sector are not cacheable.
3.5
Erase and program operations
For any Flash memory program operation (erase or program), the CPU clock frequency
(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a
device reset occurs during a Flash memory operation.
Any attempt to read the Flash memory on STM32F4xx while it is being written or erased,
causes the bus to stall. Read operations are processed correctly once the program
operation has completed. This means that code or data fetches cannot be performed while
a write/erase operation is ongoing.
3.5.1
Unlocking the Flash control register
After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1.
Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2.
Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)
Any wrong sequence will return a bus error and lock up the FLASH_CR register until the
next reset.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
Note:
The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR
register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall
until the BSY bit is cleared.
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3.5.2
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Program/erase parallelism
The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It
represents the number of bytes to be programmed each time a write operation occurs to the
Flash memory. PSIZE is limited by the supply voltage and by whether the external VPP
supply is used or not. It must therefore be correctly configured in the FLASH_CR register
before any programming/erasing operation.
A Flash memory erase operation can only be performed by sector, or for the whole Flash
memory (mass erase). The erase time depends on PSIZE programmed value. For more
details on the erase time, refer to the electrical characteristics section of the device
datasheet.
Table 6 provides the correct PSIZE values.
Table 6. Program/erase parallelism
Voltage range 2.7 - 3.6 V
with External VPP
Voltage range
2.7 - 3.6 V
Parallelism size
x64
x32
x16
x8
PSIZE(1:0)
11
10
01
00
Note:
Voltage range
2.4 - 2.7 V
Voltage range
2.1 - 2.4 V
Voltage range
1.7 V - 2.1 V
Any program or erase operation started with inconsistent program parallelism/voltage range
settings may lead to unpredicted results. Even if a subsequent read operation indicates that
the logical value was effectively written to the memory, this value may not be retained.
To use VPP, an external high-voltage supply (between 8 and 9 V) must be applied to the VPP
pad. The external supply must be able to sustain this voltage range even if the DC
consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on
the factory line. The VPP supply must not be applied for more than an hour, otherwise the
Flash memory might be damaged.
3.5.3
Erase
The Flash memory erase operation can be performed at sector level or on the whole Flash
memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration
sector.
Sector Erase
To erase a sector, follow the procedure below:
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Set the SER bit and select the sector out of the 7 sectors (STM32F411xC/E) in the
main memory block you wish to erase (SNB) in the FLASH_CR register
3.
Set the STRT bit in the FLASH_CR register
4.
Wait for the BSY bit to be cleared
Mass Erase
To perform Mass Erase, the following sequence is recommended:
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Note:
Embedded Flash memory interface
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Set the MER bit in the FLASH_CR register
3.
Set the STRT bit in the FLASH_CR register
4.
Wait for the BSY bit to be cleared
If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.
If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may
occur without generating any error flag. This condition should be forbidden.
3.5.4
Programming
Standard programming
The Flash memory programming sequence is as follows:
1.
Check that no main Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2.
Set the PG bit in the FLASH_CR register
3.
Perform the data write operation(s) to the desired memory address (inside main
memory block or OTP area):
4.
Note:
–
Byte access in case of x8 parallelism
–
Half-word access in case of x16 parallelism
–
Word access in case of x32 parallelism
–
Double word access in case of x64 parallelism
Wait for the BSY bit to be cleared.
Successive write operations are possible without the need of an erase operation when
changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.
If an erase and a program operation are requested simultaneously, the erase operation is
performed first.
Programming errors
It is not allowed to program data to the Flash memory that would cross the 128-bit row
boundary. In such a case, the write operation is not performed and a program alignment
error flag (PGAERR) is set in the FLASH_SR register.
The write access type (byte, half-word, word or double word) must correspond to the type of
parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and a
program parallelism error flag (PGPERR) is set in the FLASH_SR register.
If the standard programming sequence is not respected (for example, if there is an attempt
to write to a Flash memory address when the PG bit is not set), the operation is aborted and
a program sequence error flag (PGSERR) is set in the FLASH_SR register.
Programming and caches
If a Flash memory write access concerns some data in the data cache, the Flash write
access modifies the data in the Flash memory and the data in the cache.
If an erase operation in Flash memory also concerns data in the data or instruction cache,
you have to make sure that these data are rewritten before they are accessed during code
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execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the FLASH_CR register.
Note:
The I/D cache should be flushed only when it is disabled (I/DCEN = 0).
3.5.5
Interrupts
Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables
interrupt generation when an erase or program operation ends, that is when the busy bit
(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this
case, the end of operation (EOP) bit in the FLASH_SR register is set.
If an error occurs during a program, an erase, or a read operation request, one of the
following error flags is set in the FLASH_SR register:
•
PGAERR, PGPERR, PGSERR (Program error flags)
•
WRPERR (Protection error flag)
In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_SR register, an
interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.
Note:
If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
Table 7. Flash interrupt request
Interrupt event
Event flag
Enable control bit
EOP
EOPIE
WRPERR
ERRIE
PGAERR, PGPERR, PGSERR
ERRIE
End of operation
Write protection error
Programming error
3.6
Option bytes
3.6.1
Description of user option bytes
The option bytes are configured by the end user depending on the application requirements.
Table 8 shows the organization of these bytes inside the user configuration sector.
Table 8. Option byte organization
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Address
[63:16]
[15:0]
0x1FFF C000
Reserved
ROP & user option bytes (RDP & USER)
0x1FFF C008
Reserved
Write protection nWRP bits for sectors 0 to 7
(STM32F411xC/E)
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Embedded Flash memory interface
Table 9. Description of the option bytes
Option bytes (word, address 0x1FFF C000)
RDP: Read protection option byte.
The read protection is used to protect the software code stored in Flash memory.
0xAA: Level 0, no protection
Bit 15:8
0xCC: Level 2, chip protection (debug and boot from RAM features
disabled)
Others: Level 1, read protection of memories (debug features limited)
USER: User option byte
This byte is used to configure the following features:
Select the watchdog event: Hardware or software
Reset event when entering the Stop mode
Reset event when entering the Standby mode
Bit 7
nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generated
Bit 6
nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated
Bit 5
WDG_SW
0: Hardware watchdog
1: Software watchdog
Bit 4
0x0: Not used. Always readout as “0”.
Bits 3:2
BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset.
They can be written to program a new BOR level value into Flash memory.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
For full details on BOR characteristics, refer to the Electrical characteristics
section of the product datasheet.
Bits 1:0
0x1: Not used
Option bytes (word, address 0x1FFF C008)
Bit 15
SPRMOD: Selection of Protection Mode of nWPRi bits
0: nWPRi bits used for sector i write protection (Default)
1: nWPRi bits used for sector i PCROP protection (Sector)
Bits 14:6
Reserved
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Table 9. Description of the option bytes (continued)
nWRP: Flash memory write protection option bytes
Sector 0 to 7 (STM32F411xC/E) can be write protected.
Bits 5:0
3.6.2
nWRPi
If SPRMOD is reset (default value) :
0: Write protection active on sector i.
1: Write protection not active on sector i.
If SPRMOD is set (active):
0: PCROP protection not active on sector i.
1: PCROP protection active on sector i.
Programming user option bytes
To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option
control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have
to perform the following sequence:
1.
Write OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)
2.
Write OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)
The user option bytes can be protected against unwanted erase/program operations by
setting the OPTLOCK bit by software.
Modifying user option bytes
To modify the user option value, follow the sequence below:
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Write the desired option value in the FLASH_OPTCR register.
3.
Set the option start bit (OPTSTRT) in the FLASH_OPTCR register
4.
Wait for the BSY bit to be cleared.
Note:
The value of an option is automatically modified by first erasing the user configuration sector
and then programming all the option bytes with the values contained in the FLASH_OPTCR
register.
3.6.3
Read protection (RDP)
The user area in the Flash memory can be protected against read operations by an
entrusted code. Three read protection levels are defined:
•
Level 0: no read protection
When the read protection level is set to Level 0 by writing 0xAA into the read protection
option byte (RDP), all read/write operations (if no write protection is set) from/to the
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Flash memory are possible in all boot configurations (Flash user boot, debug or boot
from RAM).
•
Level 1: read protection enabled
It is the default read protection level after option byte erase. The read protection Level
1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and
Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:
–
No access (read, erase, program) to Flash memory can be performed while the
debug feature is connected or while booting from RAM or system memory
bootloader. A bus error is generated in case of read request.
–
When booting from Flash memory, accesses (read, erase, program) to Flash
memory from user code are allowed.
When Level 1 is active, programming the protection option byte (RDP) to Level 0
causes the Flash memory to be mass-erased. As a result the user code area is cleared
before the read protection is removed. The mass erase only erases the user code area.
The other option bytes including write protections remain unchanged from before the
mass-erase operation. The OTP area is not affected by mass erase and remains
unchanged. Mass erase is performed only when Level 1 is active and Level 0
requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass
erase.
•
Level 2: debug/chip read protection disabled
The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When
the read protection Level 2 is set:
–
All protections provided by Level 1 are active.
–
Booting from RAM or system memory bootloader is no more allowed.
–
JTAG, SWV (single-wire viewer), ETM, and boundary scan are disabled.
–
User option bytes can no longer be changed.
–
When booting from Flash memory, accesses (read, erase and program) to Flash
memory from user code are allowed.
Memory read protection Level 2 is an irreversible operation. When Level 2 is activated,
the level of protection cannot be decreased to Level 0 or Level 1.
Note:
The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a
consequence, boundary scan cannot be performed. STMicroelectronics is not able to
perform analysis on defective parts on which the Level 2 protection has been set.
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--
Memory area
RM0383
Table 10. Access versus read protection level
Protection
Level
Debug features, Boot from RAM or
from System memory bootloader
Read
Main Flash Memory
Option Bytes
OTP
Level 1
Write
Erase
Booting from Flash memory
Read
Write
NO(1)
NO
YES
Level 2
NO
YES
Level 1
YES
YES
Level 2
NO
NO
Level 1
NO
NA
YES
NA
Level 2
NO
NA
YES
NA
1. The main Flash memory only erased when the RDP changes from level 1 to 0. The OTP area remains unchanged.
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Erase
DocID026448 Rev 1
RM0383
Embedded Flash memory interface
Figure 4 shows how to go from one RDP level to another.
Figure 4. RDP levels
2$0!!H##H
/THERSOPTIONSMODIFIED
,EVEL
2$0!!H
2$0##H
DEFAULT
7RITEOPTIONS
INCLUDING
2$0##H
7RITEOPTIONSINCLUDING
2$0##H!!H
, EV E L 2 $ 0 # # H
7RITEOPTIONS
INCLUDING
2$0!!H
, EV E L 7RITEOPTIONS
INCLUDING
2$0##H
/PTIONSWRITE2$0LEVELINCREASEINCLUDES
/PTIONSERASE
.EWOPTIONSPROGRAM
/PTIONSWRITE2$0LEVELDECREASEINCLUDES
-ASSERASE
/PTIONSERASE
.EWOPTIONSPROGRAM
2 $ 0 ! ! H
2$0!!H
/THERSOPTIONSMODIFIED
/PTIONSWRITE2$0LEVELIDENTICALINCLUDES
/PTIONSERASE
.EWOPTIONSPROGRAM
AI
3.6.4
Write protections
Up to 7 (STM32F411xC/E) user sectors in Flash memory can be protected against
unwanted write operations due to loss of program counter contexts. When the non-write
protection nWRPi bit (0 ≤i ≤7) in the FLASH_OPTCR registers is low, the corresponding
sector cannot be erased or programmed. Consequently, a mass erase cannot be performed
if one of the sectors is write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted
(sector protected by write protection bit, OTP part locked or part of the Flash memory that
can never be written like the ICP), the write protection error flag (WRPERR) is set in the
FLASH_SR register.
Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.
Write protection error flag
If an erase/program operation to a write protected area of the Flash memory is performed,
the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.
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If an erase operation is requested, the WRPERR bit is set when:
•
Mass, bank, sector erase are configured (MER and SER = 1)
•
A sector erase is requested and the Sector Number SNB field is not valid
•
A mass erase is requested while at least one of the user sector is write protected by
option bit (MER = 1 and nWRPi = 0 with 0 ≤i ≤7 bits in the FLASH_OPTCRx register
•
A sector erase is requested on a write protected sector. (SER = 1, SNB = i and
nWRPi = 0 with 0 ≤i ≤7 bits in the FLASH_OPTCRx register)
•
The Flash memory is readout protected and an intrusion is detected.
If a program operation is requested, the WRPERR bit is set when:
3.6.5
•
A write operation is performed on system memory or on the reserved part of the user
specific sector.
•
A write operation is performed to the user configuration sector
•
A write operation is performed on a sector write protected by option bit.
•
A write operation is requested on an OTP area which is already locked
•
The Flash memory is read protected and an intrusion is detected.
Proprietary code readout protection (PCROP)
Flash memory user sectors (0 to7) can be protected against D-bus read accesses by using
the proprietary readout protection (PCROP).
The PCROP protection is selected as follows, through the SPRMOD option bit in the
FLASH_CR register:
•
SPRMOD = 0: nWRPi control the write protection of respective user sectors
•
SPRMOD = 1: nWRPi control the read and write protection (PCROP) of respective
user sectors.
When a sector is readout protected (PCROP mode activated), it can only be accessed for
code fetch through ICODE Bus on Flash interface:
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•
Any read access performed through the D-bus triggers a RDERR flag error.
•
Any program/erase operation on a PCROPed sector triggers a WRPERR flag error.
DocID026448 Rev 1
RM0383
Embedded Flash memory interface
Figure 5. PCROP levels
7RITEOPTIONS
30-/$ACTIVE
ANDVALIDN720I
,EVEL
2$0X!!
2$0X##
DEFAULT
7RITEOPTIONS
30-/$ACTIVE
ANDVALIDN720I
7RITEOPTIONS
30-/$ACTIVE
ANDVALIDN720I
.ORESTRICTIONON
7RITEOPTIONS
,EVEL
,EVEL
2$0X##
2$0X!!
7RITEOPTIONS
30-/$ACTIVE
ANDVALIDN720I
7RITEOPTIONS
30-/$ACTIVE
ANDVALIDN720I
5SEROPTIONSECTORERASE
0ROGRAMNEWOPTIONS
'LOBALMASSERASE
5SEROPTIONSECTIONERASE
0ROGRAMNEWOPTIONS
6ALIDN720IMEANSTHATNONEOFTHEN720BITSSETCANBERESETTRANSITIONFROMTO
-36
The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can
only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not
respected, the user option byte modification is cancelled and the write error WRPERR flag
is set. The modification of the users option bytes (BOR_LEV, RST_STDBY, ..) is allowed
since none of the active nWRPi bits is reset and SPRMOD is kept active.
Note:
The active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
If SPRMOD = 1 and nWRPi =1, then user sector i of bank 1, respectively bank 2 is
read/write protected (PCROP).
3.7
One-time programmable bytes
Table 11 shows the organization of the one-time programmable (OTP) part of the OTP area.
Table 11. OTP area organization
Block
0
1
.
.
.
[128:96]
[95:64]
[63:32]
[31:0]
Address byte 0
OTP0
OTP0
OTP0
OTP0
0x1FFF 7800
OTP0
OTP0
OTP0
OTP0
0x1FFF 7810
OTP1
OTP1
OTP1
OTP1
0x1FFF 7820
OTP1
OTP1
OTP1
OTP1
0x1FFF 7830
.
.
.
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.
.
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RM0383
Table 11. OTP area organization (continued)
Block
[128:96]
[95:64]
[63:32]
[31:0]
Address byte 0
OTP15
OTP15
OTP15
OTP15
0x1FFF 79E0
OTP15
OTP15
OTP15
OTP15
0x1FFF 79F0
LOCKB15 ...
LOCKB12
LOCKB11 ...
LOCKB8
LOCKB7 ...
LOCKB4
LOCKB3 ...
LOCKB0
0x1FFF 7A00
15
Lock block
The OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16
bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes
LOCKBi (0 ≤i ≤15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP
data block can be programmed until the value 0x00 is programmed in the corresponding
OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP
bytes might not be taken into account correctly.
3.8
Flash interface registers
3.8.1
Flash access control register (FLASH_ACR)
The Flash access control register is used to enable/disable the acceleration features and
control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Reserved
15
14
Reserved
13
12
11
DCRST ICRST
rw
w
10
9
8
DCEN
ICEN
PRFTEN
rw
rw
rw
7
Reserved
Bits 31:13 Reserved, must be kept cleared.
Bit 12 DCRST: Data cache reset
0: Data cache is not reset
1: Data cache is reset
This bit can be written only when the D cache is disabled.
Bit 11 ICRST: Instruction cache reset
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the I cache is disabled.
Bit 10 DCEN: Data cache enable
0: Data cache is disabled
1: Data cache is enabled
Bit 9 ICEN: Instruction cache enable
0: Instruction cache is disabled
1: Instruction cache is enabled
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rw
rw
rw
rw
RM0383
Embedded Flash memory interface
Bit 8 PRFTEN: Prefetch enable
0: Prefetch is disabled
1: Prefetch is enabled
Bits 7:4 Reserved, must be kept cleared.
Bits 3:0 LATENCY: Latency
These bits represent the ratio of the CPU clock period to the Flash memory access time.
0000: Zero wait state
0001: One wait state
0010: Two wait states
1110: Fourteen wait states
1111: Fifteen wait states
3.8.2
Flash key register (FLASH_KEYR)
The Flash key register is used to allow access to the Flash control register and so, to allow
program and erase operations.
Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
28
27
26
25
24
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
w
w
w
w
w
w
w
w
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
KEY[31:16]
KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 FKEYR: FPEC key
The following values must be programmed consecutively to unlock the FLASH_CR register
and allow programming/erasing it:
a) KEY1 = 0x45670123
b) KEY2 = 0xCDEF89AB
3.8.3
Flash option key register (FLASH_OPTKEYR)
The Flash option key register is used to allow program and erase operations in the user
configuration sector.
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
w
w
w
w
w
w
w
OPTKEYR[31:16
w
w
w
w
w
w
w
w
w
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Embedded Flash memory interface
15
14
13
12
11
10
RM0383
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OPTKEYR[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 OPTKEYR: Option byte key
The following values must be programmed consecutively to unlock the FLASH_OPTCR
register and allow programming it:
a) OPTKEY1 = 0x08192A3B
b) OPTKEY2 = 0x4C5D6E7F
3.8.4
Flash status register (FLASH_SR)
The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Reserved
15
14
13
12
Reserved
11
10
9
8
7
r
6
5
4
RDERR PGSERR PGPERR PGAERR WRPERR
rw
rc_w1
16
BSY
rc_w1
rc_w1
rc_w1
3
2
Reserved
1
0
OPERR
EOP
rc_w1
rc_w1
Bits 31:17 Reserved, must be kept cleared.
Bit 16 BSY: Busy
This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a
Flash memory operation and cleared when the operation finishes or an error occurs.
0: no Flash memory operation ongoing
1: Flash memory operation ongoing
Bits 15:9 Reserved, must be kept cleared.
Bit 8 RDERR: Read Protection Error (pcrop)
Set by hardware when an address to be read through the Dbus belongs to a read protected
part of the flash.
Reset by writing 1.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the code while
the control register has not been correctly configured.
Cleared by writing 1.
Bit 6 PGPERR: Programming parallelism error
Set by hardware when the size of the access (byte, half-word, word, double word) during the
program sequence does not correspond to the parallelism configuration PSIZE (x8, x16,
x32, x64).
Cleared by writing 1.
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Embedded Flash memory interface
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same 128-bit Flash
memory row.
Cleared by writing 1.
Bit 4 WRPERR: Write protection error
Set by hardware when an address to be erased/programmed belongs to a write-protected
part of the Flash memory.
Cleared by writing 1.
Bits 3:2 Reserved, must be kept cleared.
Bit 1 OPERR: Operation error
Set by hardware when a flash operation (programming / erase /read) request is detected and
can not be run because of parallelism, alignment, or write protection error. This bit is set only
if error interrupts are enabled (ERRIE = 1).
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operations (program/erase) has/have
completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =
1).
Cleared by writing a 1.
3.8.5
Flash control register (FLASH_CR)
The Flash control register is used to configure and start Flash memory operations.
Address offset: 0x10
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
LOCK
27
26
Reserved
rs
15
28
14
13
12
Reserved
11
10
25
24
ERRIE
EOPIE
rw
rw
9
8
PSIZE[1:0]
rw
rw
23
22
21
20
19
18
17
Reserved
7
Res.
6
5
4
rs
3
SNB[3:0]
rw
rw
rw
16
STRT
rw
2
1
0
MER
SER
PG
rw
rw
rw
Bit 31 LOCK: Lock
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 30:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is
set to 1.
0: Error interrupt generation disabled
1: Error interrupt generation enabled
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Bit 24 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes
to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bits 23:17 Reserved, must be kept cleared.
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bits 15:10 Reserved, must be kept cleared.
Bits 9:8 PSIZE: Program size
These bits select the program parallelism.
00 program x8
01 program x16
10 program x32
11 program x64
Bit 7 Reserved, must be kept cleared.
Bits 6:3 SNB: Sector number
These bits select the sector to erase.
0000 sector 0
0001 sector 1
...
0101 sector 5
0110 sector 6
0111 sector 7
1000 not allowed
...
1011 not allowed
1100 user specific sector
1101 user configuration sector
1110 not allowed
1111 not allowed
Bit 2 MER: Mass Erase
Erase activated for all user sectors.
Bit 1 SER: Sector Erase
Sector Erase activated.
Bit 0 PG: Programming
Flash programming activated.
3.8.6
Flash option control register (FLASH_OPTCR)
The FLASH_OPTCR register is used to modify the user option bytes.
Address offset: 0x14
Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at
reset release.
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Embedded Flash memory interface
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
28
SPR
MOD
27
26
25
24
21
14
13
12
11
rw
rw
rw
10
9
8
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
nRST_ nRST_
STDBY STOP
rw
20
nWRP[7:0]
RDP[7:0]
rw
22
Reserved
rw
15
23
rw
rw
rw
rw
rw
WDG_
SW
rw
Reserv
ed
BOR_LEV
rw
rw
OPTST OPTLO
RT
CK
rs
rs
Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits
0: PCROP disabled, nWPRi bits used for Write Protection on sector i
1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i
Bits 30:24 Reserved, must be kept cleared.
Bits 23:16 nWRP[7:0]: Not write protect
These bits contain the value of the write-protection option bytes of sectors after reset. They
can be written to program a new write protect value into Flash memory.
0: Write protection active on selected sector
1: Write protection not active on selected sector
These bits contain the value of the write-protection and read-protection (PCROP) option
bytes for sectors 0 to 5 after reset. They can be written to program a new write-protect or
PCROP value into Flash memory.
If SPRMOD is reset:
0: Write protection active on sector i
1: Write protection not active on sector i
If SPRMOD is set:
0: PCROP protection not active on sector i
1: PCROP protection active on sector i
Bits 15:8 RDP: Read protect
These bits contain the value of the read-protection option level after reset. They can be
written to program a new read protection value into Flash memory.
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, read protection of memories active
Bits 7:5 USER: User option bytes
These bits contain the value of the user option byte after reset. They can be written to
program a new user option byte value into Flash memory.
Bit 7: nRST_STDBY
Bit 6: nRST_STOP
Bit 5: WDG_SW
Note: When changing the WDG mode from hardware to software or from software to
hardware, a system reset is required to make the change effective.
Bit 4 Reserved, must be kept cleared. Always read as “0”.
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Embedded Flash memory interface
RM0383
Bits 3:2 BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level. By default, BOR is off. When the supply voltage (VDD)
drops below the selected BOR level, a device reset is generated.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
Note: For full details about BOR characteristics, refer to the “Electrical characteristics” section
in the device datasheet.
Bit 1 OPTSTRT: Option start
This bit triggers a user option operation when set. It is set only by software and cleared when
the BSY bit is cleared.
Bit 0 OPTLOCK: Option lock
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked.
This bit is cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
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3.8.7
Embedded Flash memory interface
Flash interface register map
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reset value
0
0
0
STRT
FLASH_OPTCR
EOPIE
1
ERRIE
LOCK
Reset value
Reserved
Reserved
0
nWRP[7:0]
Reserved
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
OPTKEYR[15:0]
Reserved
FLASH_CR
0
1
1
1
1
0
0
1
0
RDP[7:0]
1
1
DocID026448 Rev 1
1
0
1
0
1
0
SNB[3:0]
0
0
1
1
1
0
0
0
0
0
0
0
1
0
1
EOP
0
0
OPERR
FLASH_SR
0
0
PG
0
0
SER
0
0
OPTSTRT
0
0
OPTLOCK
0
0
Reserved
0
0
MER
0
0
BOR_LEV
0
PGAERR
0
0
WRPERR
0
0
Reserved
0
0
PGPERR
0
WDG_SW
0
0
PGSERR
0
Reserved
0
nRST_STOP
0
OPTKEYR[31:16]
SPRMOD
0x14
0
KEY[15:0]
Reset value
0x10
0
nRST_STDBY
0x0C
0
FLASH_
OPTKEYR
Reset value
0
LATENCY
Reserved
RDERR
0x08
0
PSIZE[1:0]
Reset value
0
KEY[31:16]
FLASH_KEYR
BSY
0x04
ICEN
Reset value
PRFTEN
Reserved
DCEN
FLASH_ACR
ICRST
0x00
Register
DCRST
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 12. Flash register map and reset values
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CRC calculation unit
RM0383
4
CRC calculation unit
4.1
CRC introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
4.2
CRC main features
•
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
–
•
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
Single input/output 32-bit data register
•
CRC computation done in 4 AHB clock cycles (HCLK)
•
General-purpose 8-bit register (can be used for temporary storage)
The block diagram is shown in Figure 6.
Figure 6. CRC calculation unit block diagram
AHB bus
32-bit (read access)
Data register (output)
CRC computation (polynomial: 0x4C11DB7)
32-bit (write access)
Data register (input)
ai14968
4.3
CRC functional description
The CRC calculation unit mainly consists of a single 32-bit data register, which:
•
is used as an input register to enter new data in the CRC calculator (when writing into
the register)
•
holds the result of the previous CRC calculation (when reading the register)
Each write operation into the data register creates a combination of the previous CRC value
and the new one (CRC computation is done on the whole 32-bit data word, and not byte per
byte).
The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses.
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CRC calculation unit
The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the
CRC_CR register. This operation does not affect the contents of the CRC_IDR register.
4.4
CRC registers
The CRC calculation unit contains two data registers and a control register.The peripheral
The CRC registers have to be accessed by words (32 bits).
4.4.1
Data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DR [31:16]
DR [15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 Data register bits
Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.
4.4.2
Independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
IDR[7:0]
Reserved
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 General-purpose 8-bit data register bits
Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register.
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CRC calculation unit
4.4.3
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Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6
5
4
3
2
1
16
Reserved
15
14
13
12
11
10
9
8
7
0
RESET
Reserved
w
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 RESET bit
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.
This bit can only be set, it is automatically cleared by hardware.
4.4.4
CRC register map
The following table the CRC register map and reset values.
Table 13. CRC calculation unit register map and reset values
Offset
0x00
Register
31-24
23-16
15-8
7
6
Data register
Reset
value
0xFFFF FFFF
Reset
value
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Reset
value
3
2
1
0
Independent data register
Reserved
0x00
RESET
CRC_CR
0x08
4
CRC_DR
CRC_IDR
0x04
5
Reserved
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Power controller (PWR)
5
Power controller (PWR)
5.1
Power supplies
There are two main power supply schemes:
•
VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal regulator disabled,
provided externally through VDD pins. Requires the use of an external power supply
supervisor connected to the VDD and PDR_ON pins.
•
VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
The real-time clock (RTC) and the RTC backup registers can be powered from the VBAT
voltage when the main VDD supply is powered off.
Note:
Depending on the operating power supply range, some peripheral may be used with limited
functionality and performance. For more details refer to section "General operating
conditions" in STM32F4xx datasheets.
Figure 7. Power supply overview
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1. VDDA and VSSA must be connected to VDD and VSS, respectively.
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5.1.1
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Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.
•
The ADC voltage supply input is available on a separate VDDA pin.
•
An isolated supply ground connection is provided on pin VSSA.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF. The voltage on VREF ranges from 1.7 V to VDDA.
5.1.2
Battery backup domain
Backup domain description
To retain the content of the RTC backup registers and supply the RTC when VDD is turned
off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by
another source.
To allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT
pin powers the following blocks:
•
The RTC
•
The LSE oscillator
•
PC13 to PC15 I/Os
The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset
block.
Warning:
During tRSTTEMPO (temporization at VDD startup) or after a PDR
is detected, the power switch between VBAT and VDD remains
connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect the VBAT pin to
VDD with a 100 nF external decoupling ceramic capacitor in parallel.
When the backup domain is supplied by VDD (analog switch connected to VDD), the
following functions are available:
Note:
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•
PC14 and PC15 can be used as either GPIO or LSE pins
•
PC13 can be used as a GPIO or additional functions can be configured (refer to
Table 25: RTC additional functions for more details about this pin configuration)
Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 are restricted: only one I/O at a time can be used as an output, the
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Power controller (PWR)
speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be
used as a current source (e.g. to drive an LED).
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
•
PC14 and PC15 can be used as LSE pins only
•
PC13 can be used as the RTC additional function pin (refer to Table 25: RTC additional
functions for more details about this pin configuration)
Backup domain access
After reset, the backup domain (RTC registers and RTC backup register) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
•
Access to the RTC and RTC backup registers
1.
Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see Section 6.3.11: RCC APB1 peripheral clock enable register
(RCC_APB1ENR))
2.
Set the DBP bit in the Section 5.4.1 to enable access to the backup domain
3.
Select the RTC clock source: see Section 6.2.8: RTC/AWU clock
4.
Enable the RTC clock by programming the RTCEN [15] bit in the Section 6.3.17: RCC
Backup domain control register (RCC_BDCR)
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)
which are reset when a tamper detection event occurs. For more details refer to Section 17:
Real-time clock (RTC).
5.1.3
Voltage regulator
An embedded linear voltage regulator supplies all the digital circuitries except for the backup
domain and the Standby circuitry. The regulator output voltage is around 1.2 V.
This voltage regulator requires one or two external capacitors to be connected to one or two
dedicated pins, VCAP_1 and for some packages VCAP_2. Specific pins must be connected
either to VSS or VDD to activate or deactivate the voltage regulator. These pins depend on
the package.
When activated by software, the voltage regulator is always enabled after Reset. It works in
three different modes depending on the application modes.
•
In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can
be scaled by software to different voltage values:
Scale 1, scale 2, or scale 3 can be configured through the VOS[1:0] bits of the
PWR_CR register. After reset the VOS register is set to scale 2. When the PLL is
OFF, the voltage regulator is set to scale 3 independently of the VOS register
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content. The VOS register content is only taken into account once the PLL is
activated and the HSI or HSE is selected as clock source.
The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency.
•
In Stop mode, the main regulator or the low-power regulator supplies low power to the
1.2 V domain, thus preserving the content of registers and internal SRAM. The voltage
regulator can be put either in main regulator mode (MR) or in low-power mode (LPR).
The programmed voltage scale remains the same during Stop mode:
Voltage scale 3 is automatically selected when the microcontroller enters Stop
mode (see Section 5.4.1: PWR power control register (PWR_CR)).
•
In Standby mode, the regulator is powered down. The content of the registers and
SRAM are lost except for the Standby circuitry and the backup domain.
Note:
For more details, refer to the voltage regulator section in the STM32F411xC/E datasheet.
5.2
Power supply supervisor
5.2.1
Power-on reset (POR)/power-down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting
from 1.8 V.
To use the device below 1.8 V, the internal power supervisor must be switched off using the
PDR_ON pin (please refer to section Power supply supervisor of the
STM32F411xC/Edatasheet).The device remains in Reset mode when VDD/VDDA is below a
specified threshold, VPOR/PDR, without the need for an external reset circuit. For more
details concerning the power on/power-down reset threshold, refer to the electrical
characteristics of the datasheet.
Figure 8. Power-on reset/power-down reset waveform
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HYSTERESIS
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4EMPORIZATION
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2ESET
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5.2.2
Power controller (PWR)
Brownout reset (BOR)
During power on, the Brownout reset (BOR) keeps the device under reset until the supply
voltage reaches the specified VBOR threshold.
VBOR is configured through device option bytes. By default, BOR is off. 3 programmable
VBOR threshold levels can be selected:
Note:
•
BOR Level 3 (VBOR3). Brownout threshold level 3.
•
BOR Level 2 (VBOR2). Brownout threshold level 2.
•
BOR Level 1 (VBOR1). Brownout threshold level 1.
For full details about BOR characteristics, refer to the "Electrical characteristics" section in
the device datasheet.
When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is
generated.
The BOR can be disabled by programming the device option bytes. In this case, the
power-on and power-down is then monitored by the POR/ PDRor by an external power
supervisor if the PDR is switched off through the PDR_ON pin (see Section 5.2.1: Power-on
reset (POR)/power-down reset (PDR)).
The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the
supply voltage).
Figure 9. BOR thresholds
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5.2.3
Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
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A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate
if VDD is higher or lower than the PVD threshold. This event is internally connected to the
EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD
output interrupt can be generated when VDD drops below the PVD threshold and/or when
VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge
configuration. As an example the service routine could perform emergency shutdown tasks.
Figure 10. PVD thresholds
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HYSTERESIS
06$OUTPUT
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5.3
Low-power modes
By default, the microcontroller is in Run mode after a system or a power-on reset. In Run
mode the CPU is clocked by HCLK and the program code is executed. Several low-power
modes are available to save power when the CPU does not need to be kept running, for
example when waiting for an external event. It is up to the user to select the mode that gives
the best compromise between low-power consumption, short startup time and available
wakeup sources.
The devices feature three low-power modes:
•
Sleep mode (Cortex®-M4 with FPU core stopped, peripherals kept running)
•
Stop mode (all clocks are stopped)
•
Standby mode (1.2 V domain powered off)
In addition, the power consumption in Run mode can be reduce by one of the following
means:
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•
Slowing down the system clocks
•
Gating the clocks to the APBx and AHBx peripherals when they are unused.
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Table 14. Low-power mode summary
Mode name
Sleep
(Sleep now or
Sleep-on-exit)
Stop
Standby
5.3.1
Entry
Wakeup
WFI
Any interrupt
WFE
Wakeup event
SLEEPDEEP bit
+ WFI or WFE
Effect on 1.2 V
domain clocks
Effect on
VDD
domain
clocks
Voltage regulator
CPU CLK OFF
no effect on other
clocks or analog
clock sources
None
ON
Any EXTI line (configured
in the EXTI registers,
internal and external lines)
WKUP pin rising edge,
RTC alarm (Alarm A or
PDDS bit +
Alarm B), RTC Wakeup
SLEEPDEEP bit event, RTC tamper events,
+ WFI or WFE
RTC time stamp event,
external reset in NRST
pin, IWDG reset
HSI and
All 1.2 V domain
HSE
clocks OFF
oscillators
OFF
Main regulator or
Low-Power
regulator (depends
on PWR power
control register
(PWR_CR)
OFF
Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 6.3.3: RCC clock configuration register (RCC_CFGR).
5.3.2
Peripheral clock gating
In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be
stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB1 peripheral clock enable register
(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR) (see
Section 6.3.9: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR),
Section 6.3.10: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
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Sleep mode
Entering Sleep mode
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex®-M4 with FPU System Control register:
•
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon
as WFI or WFE instruction is executed.
•
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as
it exits the lowest priority ISR.
Refer to Table 15 and Table 16 for details on how to enter Sleep mode.
Exiting Sleep mode
If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wakeup event can be generated either by:
•
Enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex®-M4 with FPU System Control register. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
•
Or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
Refer to Table 15 and Table 16 for more details on how to exit Sleep mode.
Table 15. Sleep-now entry and exit
Sleep-now mode
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Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex®-M4 with FPU System Control register.
Mode exit
If WFI was used for entry:
Interrupt: Refer to Table 37: Vector table for STM32F411xC/E
If WFE was used for entry
Wakeup event: Refer to Section 10.2.3: Wakeup event management
Wakeup latency
None
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Table 16. Sleep-on-exit entry and exit
Sleep-on-exit
5.3.4
Description
Mode entry
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex®-M4 with FPU System Control register.
Mode exit
Interrupt: refer to Table 37: Vector table for STM32F411xC/E
Wakeup latency
None
Stop mode
The Stop mode is based on the Cortex®-M4 with FPU deepsleep mode combined with
peripheral clock gating. The voltage regulator can be configured either in normal or lowpower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI
and the HSE RC oscillators are disabled. Internal SRAM and register contents are
preserved.
Some settings in the PWR_CR register allow to further reduce the power consumption.
When the Flash memory is in power-down mode, an additional startup delay is incurred
when waking up from Stop mode (see Table 17: Stop operating modes and Section 5.4.1:
PWR power control register (PWR_CR)).
Normal mode
Table 17. Stop operating modes
Stop mode
MRLV bit
LPLV bit
FPDS bit
LPDS bit
Wakeup latency
STOP MR
0
-
0
0
HSI RC startup time
STOP MRFPD
0
-
1
0
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode
STOP LP
0
0
0
1
HSI RC startup time +
regulator wakeup time from LP
mode
1
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
regulator wakeup time from LP
mode
0
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
Main regulator from low voltage
mode
1
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
regulator wakeup time from Low
Voltage LP mode
STOP LPFPD
STOP MRLV
STOP LPLV
-
1
-
0
-
1
1
-
-
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Entering Stop mode
Refer to Table 18 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the PWR power control register
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 15.3 in Section 15: Independent watchdog (IWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the Section 6.3.17: RCC
Backup domain control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
Section 6.3.18: RCC clock control & status register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Section 6.3.17: RCC Backup domain control register (RCC_BDCR).
The ADC can also consume power during the Stop mode, unless it is disabled before
entering it. To disable it, the ADON bit in the ADC_CR2 register must be written to 0.
Note:
If the application needs to disable the external clock before entering Stop mode, the HSEON
bit must first be disabled and the system clock switched to HSI.
Otherwise, if the HSEON bit is kept enabled while the external clock (external oscillator) can
be removed before entering stop mode, the clock security system (CSS) feature must be
enabled to detect any external oscillator failure and avoid a malfunction behavior when
entering stop mode.
Exiting Stop mode
Refer to Table 18 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
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Table 18. Stop mode entry and exit
Stop mode
5.3.5
Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex®-M4 with FPU System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR.
Note: To enter the Stop mode, all EXTI Line pending bits (in Pending
register (EXTI_PR)), all peripheral interrupts pending bits, the RTC Alarm
(Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time stamp
flags, must be reset. Otherwise, the Stop mode entry procedure is ignored
and program execution continues.
Mode exit
If WFI was used for entry:
All EXTI lines configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 37: Vector
table for STM32F411xC/E.
If WFE was used for entry:
All EXTI Lines configured in event mode. Refer to Section 10.2.3:
Wakeup event management on page 202
Wakeup latency
Table 17: Stop operating modes
Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex®-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V
domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are
also switched off. SRAM and register contents are lost except for registers in the backup
domain (RTC registers and RTC backup register), and Standby circuitry (see Figure 7).
Entering Standby mode
Refer to Table 19 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 15.3 in Section 15: Independent watchdog (IWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
backup domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG
Reset, a rising edge on WKUP pin, an RTC alarm, a tamper event, or a time stamp event is
detected. All registers are reset after wakeup from Standby except for PWR power
control/status register (PWR_CSR).
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After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the PWR
power control/status register (PWR_CSR) indicates that the MCU was in Standby mode.
Refer to Table 19 for more details on how to exit Standby mode.
Table 19. Standby mode entry and exit
Standby mode
Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP in Cortex®-M4 with FPU System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
– Clear the RTC flag corresponding to the chosen wakeup source (RTC
Alarm A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags)
Mode exit
WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time stamp event, external reset in NRST pin, IWDG reset.
Wakeup latency
Reset phase.
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except for:
•
Reset pad (still available)
•
RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC
clock calibration out
•
WKUP pin (PA0), if enabled
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex®-M4 with
FPU core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 23.16.1: Debug support for low-power modes.
5.3.6
Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes
The MCU can be woken up from a low-power mode by an RTC alternate function.
The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC
tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and Standby lowpower modes.
The system can also wake up from low-power modes without depending on an external
interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.
The RTC provides a programmable time base for waking up from the Stop or Standby mode
at regular intervals.
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Power controller (PWR)
For this purpose, two of the three alternate RTC clock sources can be selected by
programming the RTCSEL[1:0] bits in the Section 6.3.17: RCC Backup domain control
register (RCC_BDCR):
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with a very low-power consumption
(additional consumption of less than 1 µA under typical conditions)
•
Low-power internal RC oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC oscillator is designed to use minimum power.
RTC alternate functions to wake up the device from the Stop mode
•
•
•
To wake up the device from the Stop mode with an RTC alarm event, it is necessary to:
a)
Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC Alarm Interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC alarm
To wake up the device from the Stop mode with an RTC tamper or time stamp event, it
is necessary to:
a)
Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper
interrupt in the RTC_TAFCR register
c)
Configure the RTC to detect the tamper or time stamp event
To wake up the device from the Stop mode with an RTC wakeup event, it is necessary
to:
a)
Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC wakeup interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC Wakeup event
RTC alternate functions to wake up the device from the Standby mode
•
•
•
To wake up the device from the Standby mode with an RTC alarm event, it is necessary
to:
a)
Enable the RTC alarm interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC alarm
To wake up the device from the Standby mode with an RTC tamper or time stamp
event, it is necessary to:
a)
Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper
interrupt in the RTC_TAFCR register
b)
Configure the RTC to detect the tamper or time stamp event
To wake up the device from the Standby mode with an RTC wakeup event, it is
necessary to:
a)
Enable the RTC wakeup interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC wakeup event
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Safe RTC alternate function wakeup flag clearing sequence
If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared,
it will not be detected on the next event as detection is made once on the rising edge.
To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit
correctly from the Stop and Standby modes, it is recommended to follow the sequence
below before entering the Standby mode:
•
•
When using RTC alarm to wake up the device from the low-power modes:
a)
Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)
b)
Clear the RTC alarm (ALRAF/ALRBF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC alarm interrupt
e)
Re-enter the low-power mode
When using RTC wakeup to wake up the device from the low-power modes:
a)
•
•
b)
Clear the RTC Wakeup (WUTF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC Wakeup interrupt
e)
Re-enter the low-power mode
When using RTC tamper to wake up the device from the low-power modes:
a)
Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)
b)
Clear the Tamper (TAMP1F/TSF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC tamper interrupt
e)
Re-enter the low-power mode
When using RTC time stamp to wake up the device from the low-power modes:
a)
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Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register)
Disable the RTC time stamp interrupt (TSIE bit in RTC_CR)
b)
Clear the RTC time stamp (TSF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC TimeStamp interrupt
e)
Re-enter the low-power mode
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Power controller (PWR)
5.4
Power control registers
5.4.1
PWR power control register (PWR_CR)
Address offset: 0x00
Reset value: 0x0000 8000 (reset by wakeup from Standby mode)
31
30
29
28
27
26
25
24
23
22
21
20
19
FISSR
FMSSR
rw
rw
5
4
3
2
1
0
PVDE
CSBF
CWUF
PDDS
LPDS
rw
w
w
rw
rw
Reserved
15
14
VOS
rw
13
ADCDC1
rw
rw
18
17
16
Reserved
12
11
10
9
8
Res
MRLV
DS
LPLV
DS
FPDS
DBP
rw
rw
rw
rw
7
6
PLS[2:0]
rw
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 FISSR: Flash Interface Stop while System Run
0: Flash Interface clock run (Default value).
1: Flash Interface clock off.
Note: This bit could not be set while executing with the Flash itself. It should be done with
specific routine executed from RAM.
Bit 20 FMSSR: Flash Memory Sleep System Run.
0: Flash standard mode (Default value)
1: Flash forced to be in STOP or DeepPower Down mode (depending of FPDS value bit) by
hardware.
Note: This bit could not be set while executing with the Flash itself. It should be done with
specific routine executed from RAM.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection
These bits control the main internal voltage regulator output voltage to achieve a trade-off
between performance and power consumption when the device does not operate at the
maximum frequency (refer to the corresponding datasheet for more details).
These bits can be modified only when the PLL is OFF. The new value programmed is active
only when the PLL is ON. When the PLL is OFF, the voltage regulator is set to scale 3
independently of the VOS register content.
00: Reserved (Scale 3 mode selected)
01: Scale 3 mode <= 64 MHz
10: Scale 2 mode (reset value) <= 84 MHz
11: Scale 1 mode <= 100 MHz
Bit 13 ADCDC1:
0: No effect.
1: Refer to AN4073 for details on how to use this bit.
Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when
the Prefetch is OFF.
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Bit 12 Reserved, must be kept at reset value.
Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep
0: Main regulator in Voltage scale 3 when the device is in Stop mode.
1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is
in Stop mode.
Bit 10 LPLVDS: Low-power regulator Low Voltage in Deep Sleep
0: Low-power regulator on if LPDS bit is set when the device is in Stop mode.
1: Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is
set when device is in Stop mode.
Bit 9 FPDS: Flash power-down in Stop mode
When set, the Flash memory enters power-down mode when the device enters Stop mode.
This allows to achieve a lower consumption in stop mode but a longer restart time.
0: Flash memory not in power-down when the device is in Stop mode
1: Flash memory in power-down when the device is in Stop mode
Bit 8 DBP: Disable backup domain write protection
In reset state, the RCC_BDCR register, the RTC registers (including the backup registers),
and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This
bit must be set to enable write access to these registers.
0: Access to RTC and RTC Backup registers.
1: Access to RTC and RTC Backup registers.
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
000: 2.2 V
001: 2.3 V
010: 2.4 V
011: 2.5 V
100: 2.6 V
101: 2.7 V
110: 2.8 V
111: 2.9 V
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect.
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect.
1: Clear the WUF Wakeup Flag after 2 System clock cycles.
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Power controller (PWR)
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
Bit 0 LPDS: Low-power deepsleep
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode.
1: Low-power Voltage regulator on during Stop mode.
5.4.2
PWR power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Res
VOS
RDY
BRE
EWUP
rw
rw
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
BRR
PVDO
SBF
WUF
r
r
r
r
Reserved
r
Reserved
7
Reserved
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
0: Not ready
1: Ready
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 BRE: Backup regulator enable
When set, the Backup regulator (used to maintain the backup domain content) is enabled. If
BRE is reset, the backup regulator is switched off. Once set, the application must wait that
the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the
backup registers will be maintained in the Standby and VBAT modes.
0: Backup regulator disabled
1: Backup regulator enabled
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
or by a power reset.
Bit 8 EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
the device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bits 7:4 Reserved, must be kept at reset value.
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Bit 3 BRR: Backup regulator ready
Set by hardware to indicate that the Backup Regulator is ready.
0: Backup Regulator not ready
1: Backup Regulator ready
Note: This bit is not reset when the device wakes up from Standby mode or by a system reset
or power reset.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits.
1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR_CR register.
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in
the PWR_CR register.
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
EWUP bit) when the WKUP pin level is already high.
5.5
PWR register map
The following table summarizes the PWR registers.
Refer to Table 1 on page 37 for the register boundary addresses.
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0
0
LPDS
0
0
PDDS
Reserved
0
0
0
0
0
0
SBF
0
WUF
DBP
0
CSBF
FPDS
0
CWUF
LPLVDS
0
PVDO
MRLVDS
0
PVDE
Reset value
1
PLS[2:0]
BRR
Reserved
1
EWUP
PWR_CSR
0
BRE
0x004
0
ADCDC1
Reset value
Reser
ved
VOS[1:0]
Reserved
VOSRDY
PWR_CR
FISSR
0x000
Register
FMSSR
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 20. PWR - register map and reset values
0
0
0
0
0
Reserved
RM0383
Reset and clock control (RCC) for STM32F411xC/E
6
Reset and clock control (RCC) for STM32F411xC/E
6.1
Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
6.1.1
System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain.
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2.
Window watchdog end of count condition (WWDG reset)
3.
Independent watchdog end of count condition (IWDG reset)
4.
A software reset (SW reset) (see Software reset)
5.
Low-power management reset (see Low-power management reset)
Software reset
The reset source can be identified by checking the reset flags in the RCC clock control &
status register (RCC_CSR).
The SYSRESETREQ bit in Cortex®-M4 with FPU Application Interrupt and Reset Control
Register must be set to force a software reset on the device. Refer to the Cortex®-M4 with
FPU technical reference manual for more details.
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Low-power management reset
There are two ways of generating a low-power management reset:
1.
Reset generated when entering the Standby mode:
This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.
In this case, whenever a Standby mode entry sequence is successfully executed, the
device is reset instead of entering the Standby mode.
2.
Reset when entering the Stop mode:
This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.
In this case, whenever a Stop mode entry sequence is successfully executed, the
device is reset instead of entering the Stop mode.
For further information on the user option bytes, refer to the STM32F411xC/E Flash
programming manual available from your ST sales office.
6.1.2
Power reset
A power reset is generated when one of the following events occurs:
1.
Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset
2.
When exiting the Standby mode
A power reset sets all registers to their reset values except the Backup domain.
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
Figure 11. Simplified diagram of the reset circuit
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6.1.3
Reset and clock control (RCC) for STM32F411xC/E
Backup domain reset
The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset
values.
A backup domain reset is generated when one of the following events occurs:
6.2
1.
Software reset, triggered by setting the BDRST bit in the RCC Backup domain control
register (RCC_BDCR).
2.
VDD or VBAT power on, if both supplies have previously been powered off.
Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
•
HSI oscillator clock
•
HSE oscillator clock
•
Main PLL (PLL) clock
The devices have the two following secondary clock sources:
•
32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and,
optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.
•
32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
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Figure 12. Clock tree
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1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
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Reset and clock control (RCC) for STM32F411xC/E
The clock controller provides a high degree of flexibility to the application in the choice of the
external crystal or the oscillator to run the core and peripherals at the highest frequency
and, guarantee the appropriate frequency for peripherals that need a specific clock like USB
OTG FS, I2S and SDIO.
Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is
100 MHz. The maximum allowed frequency of the high-speed APB2 domain is 100 MHz.
The maximum allowed frequency of the low-speed APB1 domain is 50 MHz
All peripheral clocks are derived from the system clock (SYSCLK) except for:
•
The USB OTG FS clock (48 MHz) and the SDIO clock (≤48 MHz) which are coming
from a specific output of PLL (PLL48CLK)
•
The I2S clock
To achieve high-quality audio performance, the I2S clock can be derived either from a
specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For
more information about I2S clock frequency and precision, refer to Section 20.4.4:
Clock generator.
The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick control and status register.
The timer clock frequencies for STM32F411xC/E are automatically set by hardware. There
are two cases:
1.
If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2.
Otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
The timer clock frequencies are automatically set by hardware. There are two cases
depending on the value of TIMPRE bit in RCC_DCKCFGR register:
•
If TIMPRE bit is reset:
If the APB prescaler is configured to a division factor of 1, the timer clock frequencies
(TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies are twice the
frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.
•
If TIMPRE bit is set:
If the APB prescaler is configured to a division factor of 1 or 2, the timer clock
frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four
times the frequency of the APB domain to which the timers are connected: TIMxCLK =
4xPCLKx.
FCLK acts as Cortex®-M4 with FPU free-running clock. For more details, refer to the
Cortex®-M4 with FPU technical reference manual.
6.2.1
HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
•
HSE external crystal/ceramic resonator
•
HSE external user clock
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The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 13. HSE/ LSE clock sources
Hardware configuration
OSC_OUT
External clock
(HI-Z)
External
source
OSC_IN OSC_OUT
Crystal/ceramic
resonators
CL1
Load
capacitors
CL2
External source (HSE bypass)
In this mode, an external clock source must be provided. You select this mode by setting the
HSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock
signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the
OSC_OUT pin should be left HI-Z. See Figure 13.
External crystal/ceramic resonator (HSE crystal)
The HSE has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Figure 13. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control
register (RCC_CR).
6.2.2
HSI clock
The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used
directly as a system clock, or used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
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Reset and clock control (RCC) for STM32F411xC/E
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock
control register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the RCC clock control register (RCC_CR).
The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the RCC clock control
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 94.
6.2.3
PLL configuration
The STM32F411xC/E devices feature two PLLs:
•
•
A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different
output clocks:
–
The first output is used to generate the high speed system clock (up to 100 MHz)
–
The second output is used to generate the clock for the USB OTG FS (48 MHz)
and the SDIO (≤50 MHz).
A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality
audio performance on the I2S interface.
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is
recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as
PLL clock source, and configuration of division factors M, P, Q and multiplication factor N).
The PLLI2S uses the same input clock as the main PLL (HSI or HSE). However, the PLLI2S
has dedicated enable/disable and division factors configuration bits. Refer to Section 6.3.1:
RCC clock control register (RCC_CR), Section 6.3.2: RCC PLL configuration register
(RCC_PLLCFGR) and Section 6.3.20: RCC PLLI2S configuration register
(RCC_PLLI2SCFGR). Once the PLLI2S is enabled, the configuration parameters cannot be
changed.
The two PLLs are disabled by hardware when entering Stop and Standby modes, or when
an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC
PLL configuration register (RCC_PLLCFGR) and RCC clock configuration register
(RCC_CFGR) can be used to configure PLL and PLLI2S, respectively.
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6.2.4
RM0383
LSE clock
The LSE clock is generated using a 32.768kHz low speed external crystal or ceramic
resonator. It has the advantage providing a low-power but highly accurate clock source to
the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain
control register (RCC_BDCR).
The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock
interrupt register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC Backup
domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left HI-Z. See Figure 13.
6.2.5
LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 32 kHz. For more details, refer to the electrical characteristics
section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the RCC clock control &
status register (RCC_CSR).
The LSIRDY flag in the RCC clock control & status register (RCC_CSR) indicates if the lowspeed internal oscillator is stable or not. At startup, the clock is not released until this bit is
set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
6.2.6
System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as the system clock. When a clock source
is used directly or through PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source is ready. Status bits in the RCC clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as the system clock.
6.2.7
Clock security system (CSS)
The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock
failure event is sent to the break inputs of advanced-control timer TIM1, and an interrupt is
generated to inform the software about the failure (clock security system interrupt CSSI),
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allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M4 with
FPU NMI (non-maskable interrupt) exception vector.
Note:
When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt,
which causes the automatic generation of an NMI. The NMI is executed indefinitely unless
the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the
CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register
(RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that
it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is
detected, then the system clock switches to the HSI oscillator and the HSE oscillator is
disabled.
If the HSE oscillator clock was the clock source of PLL used as the system clock when the
failure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also
disabled when the HSE fails.
6.2.8
RTC/AWU clock
Once the RTCCLK clock source has been selected, the only possible way of modifying the
selection is to reset the power domain.
The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable
prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits
in the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC
clock configuration register (RCC_CFGR). This selection cannot be modified without
resetting the Backup domain.
If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the
system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not
guaranteed if the system supply disappears. If the HSE oscillator divided by a value
between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup
or the system supply disappears.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a
consequence:
•
If LSE is selected as the RTC clock:
–
•
If LSI is selected as the Auto-wakeup unit (AWU) clock:
–
•
The AWU state is not guaranteed if the VDD supply is powered off. Refer to
Section 6.2.5: LSI clock on page 94 for more details on LSI calibration.
If the HSE clock is used as the RTC clock:
–
Note:
The RTC continues to work even if the VDD supply is switched off, provided the
VBAT supply is maintained.
The RTC state is not guaranteed if the VDD supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.2 V domain).
To read the RTC calendar register when the APB1 clock frequency is less than seven times
the RTC clock frequency (fAPB1 < 7xfRTCLCK), the software must read the calendar time and
date registers twice. The data are correct if the second read access to RTC_TR gives the
same result than the first one. Otherwise a third read access must be performed.
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6.2.9
RM0383
Watchdog clock
If the independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
6.2.10
Clock-out capability
Two microcontroller clock output (MCO) pins are available:
•
MCO1
You can output four different clock sources onto the MCO1 pin (PA8) using the
configurable prescaler (from 1 to 5):
–
HSI clock
–
LSE clock
–
HSE clock
–
PLL clock
The desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in
the RCC clock configuration register (RCC_CFGR).
•
MCO2
You can output four different clock sources onto the MCO2 pin (PC9) using the
configurable prescaler (from 1 to 5):
–
HSE clock
–
PLL clock
–
System clock (SYSCLK)
–
PLLI2S clock
The desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the
RCC clock configuration register (RCC_CFGR).
For the different MCO pins, the corresponding GPIO port has to be programmed in alternate
function mode.
The selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O
speed).
6.2.11
Internal/external clock measurement using TIM5/TIM11
It is possible to indirectly measure the frequencies of all on-board clock source generators
by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 14
and Figure 15.
Internal/external clock measurement using TIM5 channel4
TIM5 has an input multiplexer which allows choosing whether the input capture is triggered
by the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits
in the TIM5_OR register.
The primary purpose of having the LSE connected to the channel4 input capture is to be
able to precisely measure the HSI (this requires to have the HSI used as the system clock
source). The number of HSI clock counts between consecutive edges of the LSE signal
provides a measurement of the internal clock period. Taking advantage of the high precision
of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency
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with the same resolution, and trim the source to compensate for manufacturing-process
and/or temperature- and voltage-related frequency deviations.
The HSI oscillator has dedicated, user-accessible calibration bits for this purpose.
The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the
precision is therefore tightly linked to the ratio between the two clock sources. The greater
the ratio, the better the measurement.
It is also possible to measure the LSI frequency: this is useful for applications that do not
have a crystal. The ultralow-power LSI oscillator has a large manufacturing process
deviation: by measuring it versus the HSI clock source, it is possible to determine its
frequency with the precision of the HSI. The measured value can be used to have more
accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an
IWDG timeout with an acceptable accuracy.
Use the following procedure to measure the LSI frequency:
1.
Enable the TIM5 timer and configure channel4 in Input capture mode.
2.
Set the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI clock
internally to TIM5 channel4 input capture for calibration purposes.
3.
Measure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.
4.
Use the measured LSI frequency to update the prescaler of the RTC depending on the
desired time base and/or to compute the IWDG timeout.
Figure 14. Frequency measurement with TIM5 in Input capture mode
4)-
4)?2-0;=
'0)/
24#?7AKE5P?)4
,3%
,3)
4)
AI6
Internal/external clock measurement using TIM11 channel1
TIM11 has an input multiplexer which allows choosing whether the input capture is triggered
by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in
the TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is
connected to channel 1 input capture to have a rough indication of the external crystal
frequency. This requires that the HSI is the system clock source. This can be useful for
instance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be
able to determine harmonic or subharmonic frequencies (–50/+100% deviations).
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Figure 15. Frequency measurement with TIM11 in Input capture mode
4)-
4)?2-0;=
'0)/
4)
(3%?24#-(Z
AI
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6.3
RCC registers
Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
6.3.1
RCC clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX81 where X is undefined.
Access: no wait state, word, half-word and byte access
31
30
29
28
14
13
26
25
24
23
22
PLLI2S PLLI2S
PLLRDY PLLON
RDY
ON
Reserved
15
27
12
r
rw
r
rw
11
10
9
8
r
r
r
r
20
Reserved
7
6
HSICAL[7:0]
r
21
5
4
19
18
17
16
CSS
ON
HSE
BYP
HSE
RDY
HSE ON
rw
rw
r
rw
3
2
1
0
Res.
HSI
RDY
HSION
r
rw
HSITRIM[4:0]
r
r
r
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 PLLI2SRDY: PLLI2S clock ready flag
Set by hardware to indicate that the PLLI2S is locked.
0: PLLI2S unlocked
1: PLLI2S locked
Bit 26 PLLI2SON: PLLI2S enable
Set and cleared by software to enable PLLI2S.
Cleared by hardware when entering Stop or Standby mode.
0: PLLI2S OFF
1: PLLI2S ON
Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
Set by hardware to indicate that PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL (PLL) enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL
clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if an oscillator failure is detected.
0: Clock security system OFF (Clock detector OFF)
1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)
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Bit 18 HSEBYP: HSE clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: HSE oscillator not bypassed
1: HSE oscillator bypassed with an external clock
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared,
HSERDY goes low after 6 HSE oscillator clock cycles.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: Internal high-speed clock ready flag
Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI clock cycles.
0: HSI oscillator not ready
1: HSI oscillator ready
Bit 0 HSION: Internal high-speed clock enable
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in
case of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit
cannot be cleared if the HSI is used directly or indirectly as the system clock.
0: HSI oscillator OFF
1: HSI oscillator ON
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6.3.2
RCC PLL configuration register (RCC_PLLCFGR)
Address offset: 0x04
Reset value: 0x2400 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLL clock outputs according to the formulas:
31
30
•
f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
•
f(PLL general clock output) = f(VCO clock) / PLLP
•
f(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ
29
28
Reserved
15
Reserv
ed
14
13
27
26
25
24
PLLQ1
PLLQ0
rw
rw
rw
10
9
8
PLLQ3 PLLQ2
rw
12
11
23
22
7
6
PLLN
rw
rw
rw
rw
rw
21
Reserv PLLSRC
ed
rw
20
19
18
Reserved
5
4
3
2
PLLM5 PLLM4 PLLM3 PLLM2
rw
rw
rw
rw
rw
rw
rw
rw
17
16
PLLP1
PLLP0
rw
rw
1
0
PLLM1
PLLM0
rw
rw
Bit 31:28 Reserved, must be kept at reset value.
Bits 27:24 PLLQ: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator
clocks
Set and cleared by software to control the frequency of USB OTG FS clock, the random
number generator clock and the SDIO clock. These bits should be written only if PLL is
disabled.
Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the
random number generator need a frequency lower than or equal to 48 MHz to work
correctly.
USB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤PLLQ ≤15
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 15
Bit 23 Reserved, must be kept at reset value.
Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written
only when PLL and PLLI2S are disabled.
0: HSI clock selected as PLL and PLLI2S clock entry
1: HSE oscillator clock selected as PLL and PLLI2S clock entry
Bits 21:18 Reserved, must be kept at reset value.
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Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock
Set and cleared by software to control the frequency of the general PLL output clock. These
bits can be written only if PLL is disabled.
Caution: The software has to set these bits correctly not to exceed 100 MHz on this domain.
PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8
00: PLLP = 2
01: PLLP = 4
10: PLLP = 6
11: PLLP = 8
Bits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can
be written only when PLL is disabled. Only half-word and word accesses are allowed to
write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output
frequency is between 100 and 432 MHz. (check also Section 6.3.20: RCC PLLI2S
configuration register (RCC_PLLI2SCFGR))
VCO output frequency = VCO input frequency × PLLN with 50 ≤PLLN ≤432
000000000: PLLN = 0, wrong configuration
000000001: PLLN = 1, wrong configuration
...
000110010: PLLN = 50
...
001100011: PLLN = 99
001100100: PLLN = 100
...
110110000: PLLN = 432
110110001: PLLN = 433, wrong configuration
...
111111111: PLLN = 511, wrong configuration
Note: Multiplication factors possible for VCO input frequency higher than 1 MHz but care
must be taken to fulfill the minimum VCO output frequency as specified above.
Bits 5:0 PLLM: Division factor for the main PLL (PLL) input clock
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.
These bits can be written only when the PLL and PLLI2S are disabled.
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLM with 2 ≤PLLM ≤63
000000: PLLM = 0, wrong configuration
000001: PLLM = 1, wrong configuration
000010: PLLM = 2
000011: PLLM = 3
000100: PLLM = 4
...
111110: PLLM = 62
111111: PLLM = 63
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6.3.3
RCC clock configuration register (RCC_CFGR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.
31
30
29
MCO2
26
14
rw
25
24
23
22
I2SSC
R
MCO1 PRE[2:0]
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
PPRE1[2:0]
rw
rw
rw
rw
Reserved
21
20
rw
18
17
16
RTCPRE[4:0]
5
rw
rw
rw
rw
rw
4
3
2
1
0
SWS1
SWS0
SW1
SW0
r
r
rw
rw
HPRE[3:0]
rw
19
MCO1
rw
PPRE2[2:0]
rw
27
MCO2 PRE[2:0]
rw
15
28
rw
rw
Bits 31:30 MCO2[1:0]: Microcontroller clock output 2
Set and cleared by software. Clock source selection may generate glitches on MCO2. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and the PLLs.
00: System clock (SYSCLK) selected
01: PLLI2S clock selected
10: HSE oscillator clock selected
11: PLL clock selected
Bits 29:27 MCO2PRE: MCO2 prescaler
Set and cleared by software to configure the prescaler of the MCO2. Modification of this
prescaler may generate glitches on MCO2. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLLs.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
Bits 26:24 MCO1PRE: MCO1 prescaler
Set and cleared by software to configure the prescaler of the MCO1. Modification of this
prescaler may generate glitches on MCO1. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLL.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
Bit 23 I2SSRC: I2S clock selection
Set and cleared by software. This bit allows to select the I2S clock source between the
PLLI2S clock and the external clock. It is highly recommended to change this bit only after
reset and before enabling the I2S module.
0: PLLI2S clock used as I2S clock source
1: External clock mapped on the I2S_CKIN pin used as I2S clock source
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Bits 22:21 MCO1: Microcontroller clock output 1
Set and cleared by software. Clock source selection may generate glitches on MCO1. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and PLL.
00: HSI clock selected
01: LSE oscillator selected
10: HSE oscillator clock selected
11: PLL clock selected
Bits 20:16 RTCPRE: HSE division factor for RTC clock
Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock
for RTC.
Caution: The software has to set these bits correctly to ensure that the clock supplied to the
RTC is 1 MHz. These bits must be configured if needed before selecting the RTC
clock source.
00000: no clock
00001: no clock
00010: HSE/2
00011: HSE/3
00100: HSE/4
...
11110: HSE/30
11111: HSE/31
Bits 15:13 PPRE2: APB high-speed prescaler (APB2)
Set and cleared by software to control APB high-speed clock division factor.
Caution: The software has to set these bits correctly not to exceed 84 MHz on this domain.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE2 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
Bits 12:10 PPRE1: APB Low speed prescaler (APB1)
Set and cleared by software to control APB low-speed clock division factor.
Caution: The software has to set these bits correctly not to exceed 42 MHz on this domain.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE1 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
Bits 9:8 Reserved, must be kept at reset value.
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Bits 7:4 HPRE: AHB prescaler
Set and cleared by software to control AHB clock division factor.
Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
HPRE write.
Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
0xxx: system clock not divided
1000: system clock divided by 2
1001: system clock divided by 4
1010: system clock divided by 8
1011: system clock divided by 16
1100: system clock divided by 64
1101: system clock divided by 128
1110: system clock divided by 256
1111: system clock divided by 512
Bits 3:2 SWS: System clock switch status
Set and cleared by hardware to indicate which clock source is used as the system clock.
00: HSI oscillator used as the system clock
01: HSE oscillator used as the system clock
10: PLL used as the system clock
11: not applicable
Bits 1:0 SW: System clock switch
Set and cleared by software to select the system clock source.
Set by hardware to force the HSI selection when leaving the Stop or Standby mode or in
case of failure of the HSE oscillator used directly or indirectly as the system clock.
00: HSI oscillator selected as system clock
01: HSE oscillator selected as system clock
10: PLL selected as system clock
11: not allowed
6.3.4
RCC clock interrupt register (RCC_CIR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
CSSC
Reserved
22
Reserved
w
15
14
Reserved
13
12
11
10
PLLI2S
PLL
HSE
HSI
RDYIE RDYIE RDYIE RDYIE
rw
rw
rw
rw
9
8
7
LSE
RDYIE
LSI
RDYIE
CSSF
rw
rw
r
6
Reserved
DocID026448 Rev 1
21
20
19
18
17
16
PLLI2S
RDYC
PLL
RDYC
HSE
RDYC
HSI
RDYC
LSE
RDYC
LSI
RDYC
w
w
w
w
w
w
5
4
3
2
1
0
PLLI2S
RDYF
PLL
RDYF
HSE
RDYF
HSI
RDYF
LSE
RDYF
LSI
RDYF
r
r
r
r
r
r
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RM0383
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22 Reserved, must be kept at reset value.
Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear
This bit is set by software to clear the PLLI2SRDYF flag.
0: No effect
1: PLLI2SRDYF cleared
Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLLI2S lock.
0: PLLI2S lock interrupt disabled
1: PLLI2S lock interrupt enabled
Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
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RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 6 Reserved, must be kept at reset value.
Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag
Set by hardware when the PLLI2S locks and PLLI2SRDYDIE is set.
Cleared by software setting the PLLRI2SDYC bit.
0: No clock ready interrupt caused by PLLI2S lock
1: Clock ready interrupt caused by PLLI2S lock
Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
Set by hardware when PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 3 HSERDYF: HSE ready interrupt flag
Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
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Reset and clock control (RCC) for STM32F411xC/E
RM0383
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
6.3.5
RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
Reserved
15
14
13
Reserved
12
CRCRST
11
10
9
8
7
GPIOH
RST
Reserved
rw
22
21
DMA2
RST
DMA1
RST
rw
rw
6
5
Reserved
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2RST: DMA2 reset
Set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Bit 21 DMA1RST: DMA1 reset
Set and cleared by software.
0: does not reset DMA1
1: resets DMA1
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: does not reset CRC
1: resets CRC
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRST: IO port H reset
Set and cleared by software.
0: does not reset IO port H
1: resets IO port H
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 GPIOERST: IO port E reset
Set and cleared by software.
0: does not reset IO port E
1: resets IO port E
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20
19
18
17
16
Reserved
4
3
2
1
GPIOE GPIOD GPIOC GPIOB
RST
RST
RST
RST
rw
rw
rw
rw
0
GPIOA
RST
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 3 GPIODRST: IO port D reset
Set and cleared by software.
0: does not reset IO port D
1: resets IO port D
Bit 2 GPIOCRST: IO port C reset
Set and cleared by software.
0: does not reset IO port C
1: resets IO port C
Bit 1 GPIOBRST: IO port B reset
Set and cleared by software.
0: does not reset IO port B
1:resets IO port B
Bit 0 GPIOARST: IO port A reset
Set and cleared by software.
0: does not reset IO port A
1: resets IO port A
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Reset and clock control (RCC) for STM32F411xC/E
6.3.6
RM0383
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
17
16
Reserved
15
14
13
12
11
10
9
8
7
OTGFS
RST
Reserved
Reserved
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 6:0 Reserved, must be kept at reset value.
6.3.7
RCC APB1 peripheral reset register for (RCC_APB1RSTR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
PWR
RST
Reserved
26
25
24
Reserved
23
22
21
I2C3
RST
I2C2
RST
I2C1
RST
rw
rw
rw
7
6
5
rw
15
14
SPI3
RST
SPI2
RST
rw
rw
13
12
Reserved
11
10
9
8
WWDG
RST
Reserved
rw
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: does not reset the power interface
1: resets the power interface
Bits 27:24 Reserved, must be kept at reset value.
Bit 23 I2C3RST: I2C3 reset
Set and cleared by software.
0: does not reset I2C3
1: resets I2C3
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: does not reset I2C2
1: resets I2C2
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20
19
18
USART2
ReserRST
ved
rw
Reserved
4
3
2
1
0
TIM5
RST
TIM4
RST
TIM3
RST
TIM2
RST
rw
rw
rw
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: does not reset I2C1
1: resets I2C1
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: does not reset USART2
1: resets USART2
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: does not reset SPI3
1: resets SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: does not reset SPI2
1: resets SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: does not reset the window watchdog
1: resets the window watchdog
Bits 10:4 Reserved, must be kept at reset value.
Bit 3 TIM5RST: TIM5 reset
Set and cleared by software.
0: does not reset TIM5
1: resets TIM5
Bit 2 TIM4RST: TIM4 reset
Set and cleared by software.
0: does not reset TIM4
1: resets TIM4
Bit 1 TIM3RST: TIM3 reset
Set and cleared by software.
0: does not reset TIM3
1: resets TIM3
Bit 0 TIM2RST: TIM2 reset
Set and cleared by software.
0: does not reset TIM2
1: resets TIM2
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6.3.8
RM0383
RCC APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
SPI5
RST
Reserved
rw
15
14
SYSCFG
ReserRST
ved
rw
13
12
11
SPI4
RST
SPI1
RST
SDIO
RST
rw
rw
rw
10
9
8
ADC1
RST
Reserved
7
6
Reserved
rw
5
USART6 USART1
RST
RST
rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 SPI5RST: SPI5RST
This bit is set and cleared by software.
0: does not reset SPI5
1: resets SPI5
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Set and cleared by software.
0: does not reset TIM11
1: resets TIM11
Bit 17 TIM10RST: TIM10 reset
Set and cleared by software.
0: does not reset TIM10
1: resets TIM10
Bit 16 TIM9RST: TIM9 reset
Set and cleared by software.
0: does not reset TIM9
1: resets TIM9
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
Set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Bit 13 SPI4RST: SPI4 reset
Set and reset by software.
0: does not reset SPI4
1: resets SPI4
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: does not reset SPI1
1: resets SPI1
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4
rw
19
18
TIM11
Reser- RST
ved
rw
3
2
Reserved
17
16
TIM10
RST
TIM9
RST
rw
rw
1
0
TIM1
RST
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 11 SDIORST: SDIO reset
Set and cleared by software.
0: does not reset the SDIO module
1: resets the SDIO module
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADC1RST: ADC interface reset
Set and cleared by software.
0: does not reset the ADC interface
1: resets the ADC interface
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6RST: USART6 reset
Set and cleared by software.
0: does not reset USART6
1: resets USART6
Bit 4 USART1RST: USART1 reset
Set and cleared by software.
0: does not reset USART1
1: resets USART1
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TIM1RST: TIM1 reset
Set and cleared by software.
0: does not reset TIM1
1: resets TIM1
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6.3.9
RM0383
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
Reserved
15
14
13
Reserved
12
CRCEN
11
22
10
9
8
7
GPIOH
EN
Reserved
rw
rw
rw
6
5
Reserved
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 21 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: IO port H clock enable
Set and reset by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 GPIOEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 3 GPIODEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
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21
20
19
DMA2EN DMA1EN
DocID026448 Rev 1
18
17
16
1
0
Reserved
4
3
2
GPIOD GPIOC GPIOB GPIOA
GPIOEEN
EN
EN
EN
EN
rw
rw
rw
rw
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
6.3.10
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
17
16
Reserved
15
14
13
12
11
10
9
8
7
OTGFS
EN
Reserved
Reserved
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bits 6:0 Reserved, must be kept at reset value.
6.3.11
RCC APB1 peripheral clock enable register (RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
PWR
EN
Reserved
26
25
24
Reserved
rw
15
14
SPI3
EN
SPI2
EN
rw
rw
13
12
Reserved
11
WWDG
EN
10
9
8
23
22
21
I2C3
EN
I2C2
EN
I2C1
EN
rw
rw
rw
7
6
5
Reserved
rw
DocID026448 Rev 1
20
19
18
USART2
ReserEN
ved
rw
Reserved
4
3
2
1
0
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw
rw
rw
rw
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Bits 31:29 Reserved, must be kept at reset value.
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bits 27:24 Reserved, must be kept at reset value.
Bit 23 I2C3EN: I2C3 clock enable
Set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Set and cleared by software.
0: SPI3 clock disabled
1: SPI3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:4 Reserved, must be kept at reset value.
Bit 3 TIM5EN: TIM5 clock enable
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
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RM0383
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 2 TIM4EN: TIM4 clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
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6.3.12
RM0383
RCC APB2 peripheral clock enable register
(RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
14
13
SYSCF
Reser- G EN SPI4EN
ved
rw
rw
12
11
SPI1
EN
SDIO
EN
rw
rw
10
9
8
ADC1
EN
Reserved
7
6
Reserved
rw
5
rw
Bit 20 SPI5EN:SPI5 clock enable
This bit is set and cleared by software
0: SPI5 clock disabled
1: SPI5 clock enabled
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Bit 17 TIM10EN: TIM10 clock enable
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
Bit 16 TIM9EN: TIM9 clock enable
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGEN: System configuration controller clock enable
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Bit 13 SPI4EN: SPI4 clock enable
Set and reset by software.
0: SPI4 clock disabled
1: SPI4 clock enable
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
DocID026448 Rev 1
4
USART6 USART1
EN
EN
Bits 31:21 Reserved, must be kept at reset value.
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SPI5EN Reserved
rw
Reserved
15
20
rw
3
18
17
16
TIM11
EN
TIM10
EN
TIM9
EN
rw
rw
rw
2
1
Reserved
0
TIM1
EN
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 11 SDIOEN: SDIO clock enable
Set and cleared by software.
0: SDIO module clock disabled
1: SDIO module clock enabled
Bit 8 ADC1EN: ADC1 clock enable
Set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock disabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 clock enable
Set and cleared by software.
0: USART6 clock disabled
1: USART6 clock enabled
Bit 4 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TIM1EN: TIM1 clock enable
Set and cleared by software.
0: TIM1 clock disabled
1: TIM1 clock enabled
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6.3.13
RM0383
RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x0061 900F
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
Reserved
15
FLITF
LPEN
rw
14
13
Reserved
12
CRC
LPEN
11
10
9
Reserved
8
22
21
DMA2
LPEN
DMA1
LPEN
rw
rw
6
5
7
GPIOH
LPEN
rw
Reserved
rw
20
4
rw
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
Set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode
Set and reset by software.
0: IO port H clock disabled during sleep mode
1: IO port H clock enabled during sleep mode
Bits 6:5 Reserved, must be kept at reset value.
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GPIOE GPIOD
LPEN
LPEN
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
Set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
Bits 11:8 Reserved, must be kept at reset value.
17
16
SRAM1
LPEN
rw
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
18
Reserved
Bits 31:23 Reserved, must be kept at reset value.
Bits 14:13 Reserved, must be kept at reset value.
19
rw
2
GPIOC
LPEN
rw
1
0
GPIOB GPIOA
LPEN LPEN
rw
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode
Set and cleared by software.
0: IO port E clock disabled during Sleep mode
1: IO port E clock enabled during Sleep mode
Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode
Set and cleared by software.
0: IO port D clock disabled during Sleep mode
1: IO port D clock enabled during Sleep mode
Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode
Set and cleared by software.
0: IO port C clock disabled during Sleep mode
1: IO port C clock enabled during Sleep mode
Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode
Set and cleared by software.
0: IO port B clock disabled during Sleep mode
1: IO port B clock enabled during Sleep mode
Bit 0 GPIOALPEN: IO port A clock enable during sleep mode
Set and cleared by software.
0: IO port A clock disabled during Sleep mode
1: IO port A clock enabled during Sleep mode
6.3.14
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR)
Address offset: 0x54
Reset value: 0x0000 0080
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Reserved
15
14
13
12
11
Reserved
10
9
8
7
OTGFS
LPEN
Reserved
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode
Set and cleared by software.
0: USB OTG FS clock disabled during Sleep mode
1: USB OTG FS clock enabled during Sleep mode
Bits 6:0 Reserved, must be kept at reset value.
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Reset and clock control (RCC) for STM32F411xC/E
6.3.15
RM0383
RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0x10E2 C80F
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
PWR
LPEN
Reserved
26
25
24
Reserved
rw
15
14
SPI3
LPEN
SPI2
LPEN
rw
rw
13
12
Reserved
11
WWDG
LPEN
10
9
23
22
21
I2C3
LPEN
I2C2
LPEN
I2C1
LPEN
rw
rw
rw
7
6
5
8
20
4
Reserved
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Power interface clock disabled during Sleep mode
1: Power interface clock enabled during Sleep mode
Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode
Set and cleared by software.
0: I2C3 clock disabled during Sleep mode
1: I2C3 clock enabled during Sleep mode
Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode
Set and cleared by software.
0: I2C2 clock disabled during Sleep mode
1: I2C2 clock enabled during Sleep mode
Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode
Set and cleared by software.
0: I2C1 clock disabled during Sleep mode
1: I2C1 clock enabled during Sleep mode
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2LPEN: USART2 clock enable during Sleep mode
Set and cleared by software.
0: USART2 clock disabled during Sleep mode
1: USART2 clock enabled during Sleep mode
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3LPEN: SPI3 clock enable during Sleep mode
Set and cleared by software.
0: SPI3 clock disabled during Sleep mode
1: SPI3 clock enabled during Sleep mode
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18
17
16
USART2
ReserLPEN
ved
rw
Reserved
rw
Bits 27:24 Reserved, must be kept at reset value.
19
3
2
1
0
TIM5
LPEN
TIM4
LPEN
TIM3
LPEN
TIM2
LPEN
rw
rw
rw
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode
Set and cleared by software.
0: SPI2 clock disabled during Sleep mode
1: SPI2 clock enabled during Sleep mode
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode
Set and cleared by software.
0: Window watchdog clock disabled during sleep mode
1: Window watchdog clock enabled during sleep mode
Bits 10:4 Reserved, must be kept at reset value.
Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode
Set and cleared by software.
0: TIM5 clock disabled during Sleep mode
1: TIM5 clock enabled during Sleep mode
Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode
Set and cleared by software.
0: TIM4 clock disabled during Sleep mode
1: TIM4 clock enabled during Sleep mode
Bit 1 TIM3LPEN: TIM3 clock enable during Sleep mode
Set and cleared by software.
0: TIM3 clock disabled during Sleep mode
1: TIM3 clock enabled during Sleep mode
Bit 0 TIM2LPEN: TIM2 clock enable during Sleep mode
Set and cleared by software.
0: TIM2 clock disabled during Sleep mode
1: TIM2 clock enabled during Sleep mode
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Reset and clock control (RCC) for STM32F411xC/E
6.3.16
RM0383
RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0007 7930
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
SPI5
LPEN
Reserved
rw
15
12
11
SYSC
SPI4LP
FG
ReserEN
LPEN
ved
14
13
SPI1
LPEN
SDIO
LPEN
rw
rw
rw
rw
10
9
Reserved
8
ADC1
LPEN
7
6
Reserved
5
4
USART6 USART1
LPEN
LPEN
rw
rw
19
Reserved
3
18
17
16
TIM11
LPEN
TIM10
LPEN
TIM9
LPEN
rw
rw
rw
2
1
0
Reserved
rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
This bit is set and cleared by software
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
Set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
Set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
Bit 13 SPI4LPEN: SPI4 clock enable during sleep mode
Set and reset by software.
0: SPI4 clock disabled during sleep mode
1: SPI4 clock enabled during sleep mode
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TIM1
LPEN
rw
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode
Set and cleared by software.
0: SPI1 clock disabled during Sleep mode
1: SPI1 clock enabled during Sleep mode
Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode
Set and cleared by software.
0: SDIO module clock disabled during Sleep mode
1: SDIO module clock enabled during Sleep mode
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode
Set and cleared by software.
0: ADC1 clock disabled during Sleep mode
1: ADC1 clock disabled during Sleep mode
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6LPEN: USART6 clock enable during Sleep mode
Set and cleared by software.
0: USART6 clock disabled during Sleep mode
1: USART6 clock enabled during Sleep mode
Bit 4 USART1LPEN: USART1 clock enable during Sleep mode
Set and cleared by software.
0: USART1 clock disabled during Sleep mode
1: USART1 clock enabled during Sleep mode
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode
Set and cleared by software.
0: TIM1 clock disabled during Sleep mode
1: TIM1 clock enabled during Sleep mode
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Reset and clock control (RCC) for STM32F411xC/E
6.3.17
RM0383
RCC Backup domain control register (RCC_BDCR)
Address offset: 0x70
Reset value: 0x0000 0000, reset by Backup domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control
register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are
write-protected and the DBP bit in the PWR power control register (PWR_CR) has to be set
before these can be modified. Refer to Section 5.1.2 on page 70 for further information.
These bits are only reset after a Backup domain Reset (see Section 6.1.3: Backup domain
reset). Any internal or external Reset will not have any effect on these bits.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Reserved
15
RTCEN
rw
14
13
12
Reserved
11
10
9
8
rw
7
RTCSEL[1:0]
rw
16
BDRST
rw
6
5
Reserved
4
3
2
1
0
LSEMO LSEBYP LSERDY LSEON
D
rw
r
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.
00: No clock
01: LSE oscillator clock used as the RTC clock
10: LSI oscillator clock used as the RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC
clock
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 LSEMOD: External low-speed oscillator bypass
Set and reset by software to select crystal mode for low speed oscillator. Two power modes
are available.
0: LSE oscillator “low power” mode selection
1: LSE oscillator “high drive” mode selection
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RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the LSE clock is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: External low-speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: LSE clock not ready
1: LSE clock ready
Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: LSE clock OFF
1: LSE clock ON
6.3.18
RCC clock control & status register (RCC_CSR)
Address offset: 0x74
Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31
30
LPWR WWDG
RSTF RSTF
29
28
27
26
25
24
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
BORRS
TF
RMVF
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
1
0
Reserved
7
6
5
Reserved
4
3
2
LSIRDY LSION
r
rw
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Low-power management
reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
Set by hardware when an independent watchdog reset from VDD domain occurs.
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
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Reset and clock control (RCC) for STM32F411xC/E
RM0383
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 BORRSTF: BOR reset flag
Cleared by software by writing the RMVF bit.
Set by hardware when a POR/PDR or BOR reset occurs.
0: No POR/PDR or BOR reset occurred
1: POR/PDR or BOR reset occurred
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.
0: LSI RC oscillator not ready
1: LSI RC oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
Set and cleared by software.
0: LSI RC oscillator OFF
1: LSI RC oscillator ON
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RM0383
Reset and clock control (RCC) for STM32F411xC/E
6.3.19
RCC spread spectrum clock generation register (RCC_SSCGR)
Address offset: 0x80
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
The spread spectrum clock generation is available only for the main PLL.
The RCC_SSCGR register must be written either before the main PLL is enabled or after
the main PLL disabled.
Note:
For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to
the “Electrical characteristics” section in your device datasheet.
31
30
SSCG
EN
SPR
EAD
SEL
rw
rw
15
14
29
28
27
26
25
24
23
13
12
rw
21
20
19
18
17
16
INCSTEP
Reserved
rw
rw
rw
11
10
9
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
8
INCSTEP
rw
22
MODPER
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 SSCGEN: Spread spectrum modulation enable
Set and cleared by software.
0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)
1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)
Bit 30 SPREADSEL: Spread Select
Set and cleared by software.
To write before to set CR[24]=PLLON bit.
0: Center spread
1: Down spread
Bits 29:28 Reserved, must be kept at reset value.
Bits 27:13 INCSTEP: Incrementation step
Set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile amplitude.
Bits 12:0 MODPER: Modulation period
Set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile period.
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Reset and clock control (RCC) for STM32F411xC/E
6.3.20
RM0383
RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
Address offset: 0x84
Reset value: 0x2400 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLI2S clock outputs according to the formulas:
•
f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLI2SM)
•
f(PLL I2S clock output) = f(VCO clock) / PLLI2SR
31
30
29
28
Reserved
PLLI2S
R2
PLLI2S
R1
PLLI2S
R0
rw
rw
rw
14
13
12
15
Reserved
27
26
25
24
23
22
21
20
6
5
4
rw
rw
18
17
16
3
2
1
0
rw
rw
Reserved
11
10
9
8
7
PLLI2SN[8:0]
rw
19
rw
rw
PLLI2SM[5:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks
Set and cleared by software to control the I2S clock frequency. These bits should be written
only if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler
values inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0%
error with audio crystals. For more information about I2S clock frequency and precision,
refer to Section 20.4.4: Clock generator in the I2S chapter.
Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.
I2S clock frequency = VCO frequency / PLLR with 2 ≤PLLR ≤7
000: PLLR = 0, wrong configuration
001: PLLR = 1, wrong configuration
010: PLLR = 2
...
111: PLLR = 7
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RM0383
Reset and clock control (RCC) for STM32F411xC/E
Bits 27:15 Reserved, must be kept at reset value.
Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can
be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed
to write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output
frequency is between 100 and 432 MHz. With VCO input frequency ranges from 1
to 2 MHz (refer to Figure 13 and divider factor M of the RCC PLL configuration
register (RCC_PLLCFGR))
VCO output frequency = VCO input frequency × PLLI2SN with 50 ≤PLLI2SN ≤432
000000000: PLLI2SN = 0, wrong configuration
000000001: PLLI2SN = 1, wrong configuration
...
001100010: PLLI2SN = 50
...
001100011: PLLI2SN = 99
001100100: PLLI2SN = 100
001100101: PLLI2SN = 101
001100110: PLLI2SN = 102
...
110110000: PLLI2SN = 432
110110000: PLLI2SN = 433, wrong configuration
...
111111111: PLLI2SN = 511, wrong configuration
Note: Between 50 and 99 multiplication factors are possible for VCO input frequency higher
than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency
as specified above.
Bits 5:0 PLLI2SM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.
These bits can be written only when the PLL and PLLI2S are disabled.
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
ranges from 1 to 2 MHz.It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLI2SM with 2≤PLLI2SM ≤63
000000: PLLI2SM = 0, wrong configuration
000001: PLLI2SM = 1, wrong configuration...
000010: PLLI2SM = 2
000011: PLLI2SM = 3
000100: PLLI2SM = 4
.......
111110: PLLI2SM = 62
111111: PLLI2SM = 63
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Reset and clock control (RCC) for STM32F411xC/E
6.3.21
RM0383
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
Reserved
15
14
13
12
24
23
22
21
TIMPRE
10
9
8
19
18
17
16
2
1
0
Reserved
rw
11
20
7
6
5
4
3
Reserved
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TIMPRE: Timers clocks prescalers selection
Set and reset by software to control the clock frequency of all the timers connected to APB1
and APB2 domain.
0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, TIMxCLK = HCKL . Otherwise, the timer clock frequencies are set to
twice to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 2xPCLKx.
1:If the APB prescaler ( PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1 or 2, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set to
four times to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 4xPCLKx.
Bits 23: 0 Reserved, must be kept at reset value.
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RCC_
APB1RSTR
0x24
RCC_
APB2RSTR
Reserved
0x28
Reserved
Reserved
0x2C
Reserved
Reserved
0x30
RCC_
AHB1ENR
0x34
RCC_
AHB2ENR
0x38
Reserved
Reserved
0x3C
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DocID026448 Rev 1
Reserved
TIM2RST
GPIOAEN
TIM1RST
TIM3RST
GPIOBEN
TIM4RST
GPIOCEN
Reserved
WWDGRST
Reserved
Reserved
TIM5RST
USART1RST
USART6RST
Reserved
ADC1RST
Reserved
SDIORST
SPI1RST
Reserved
CRCRST
GPIOARST
GPIOBRST
GPIOCRST
LSIRDYF
LSERDYF
HSIRDYF
SW 0
SW 1
SWS 0
SWS 1
PLLM 0
PLLM 1
PLLM 2
PLLM 3
HPRE 0
PLLRDYF
GPIOERST
HSERDYF
PLLM 4
HPRE 1
GPIODRST
PLLN 0
PLLM 5
HPRE 2
Reserved
PLLN 1
PLLN 2
HPRE 3
Reserved
PLLN 3
PLLN 4
CSSF
LSIRDYIE
LSERDYIE
PPRE1 0
PLLN 5
PPRE1 1
HSERDYIE
HSIRDYIE
PLLN 6
PPRE1 2
PLLRDYIE
PLLN 7
HSION
HSIRDY
Reserved
HSITRIM 0
HSITRIM 1
HSITRIM 2
HSITRIM 3
HSITRIM 4
HSICAL 0
HSICAL 1
HSICAL 2
HSICAL 3
HSICAL 4
HSICAL 5
HSICAL 6
PLLN 8
PPRE2 0
PPRE2 1
PLLI2SRDYIE
Reserved
HSEON
HSERDY
Reserved HSICAL 7
PLLP 0
RTCPRE 0
CSSON
HSEBYP
PPRE2 2
PLLP 1
RTCPRE 1
RTCPRE 2
LSIRDYC
RTCPRE 3
HSIRDYC
LSERDYC
RTCPRE 4
PLLRDYC
PLLI2SRDYF
OTGFSRST GPIOHRST
PLLSRC
MCO1 0
MCO1 1
PLL ON
Reserved
MCO1PRE0 PLLQ 0
I2SSRC
PLL RDY
MCO1PRE1 PLLQ 1
HSERDYC
DMA1RST PLLI2SRDYC
DMA2RST
CSSC
PLL I2SON
MCO1PRE2 PLLQ 2
MCO2PRE0 PLLQ 3 PLL I2SRDY
MCO2PRE1
MCO2PRE2
MCO2 0
Reser
ved
GPIODEN
GPIOEEN
0x20
SP45RST
Reserved
Reserved
Reserved
Reserved
OTGFSEN GPIOHEN
Reserved
Reserved
Reserved
Reserved
CRCEN
Reserved
SPI2RST
RCC_
AHB2RSTR
SYSCFGRST
0x14
Reserved
SPI3RST
RCC_
AHB1RSTR
Reserved
0x10
Reserved
Reserved
RCC_CIR
TIM9RST
0x0C
Reserved
TIM10RST USART2RST
RCC_CFGR
TIM11RST
0x08
SPI5RST
Reserved
Reserved
Reserved
RCC_
PLLCFGR
I2C1RST
0x04
I2C2RST
Reserved
DMA1EN
RCC_CR
I2C3RST
0x00
DMA2EN
0x18
0x1C
PWRRST
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Addr.
offset
MCO2 1
6.3.22
Reserved
RM0383
Reset and clock control (RCC) for STM32F411xC/E
RCC register map
Table 21 gives the register map and reset values
Table 21. RCC register map and reset values for STM32F411xC/E
Reserved
Reserved
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Reserved
Reserved
Reserved
Reserved
0x80
RCC_SSCGR
SSCGEN
SPREADSEL
0x68
Reserved
Reserved
0x6C
Reserved
Reserved
0x70
RCC_BDCR
0x74
RCC_CSR
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RMVF
BORRSTF
PADRSTF
PORRSTF
SFTRSTF
WDGRSTF
Reserved
0x60
RCC_APB1L
PENR
0x64
RCC_APB2L
PENR
Reserved
SPI2LPEN
SYSCFGLPEN
0x84
RCC_PLLI2S
CFGR
PLLI2SRx
Reserved
DocID026448 Rev 1
Reserved
INCSTEP
PLLI2SNx
Reserved
Reserved
LSERDY
LSEON
LSIRDY
LSION
Reserved
TIM1LPEN
Reserved
MODPER
PLLI2SMx
TIM2LPEN
TIM3LPEN
TIM4LPEN
TIM3EN
TIM2EN
TIM1EN
GPIOALPEN
TIM4EN
GPIOBLPEN
TIM5EN
Reserved
WWDGEN
GPIOCLPEN
USART1EN
USART6EN
Reserved
ADC1EN
Reserved
SDIOEN
SPI1EN
GPIODLPEN
GPIOELPEN
Reserved
SPI2EN
Reserved
SPI3EN
SYSCFGEN
SPI4EN
Reserved
Reserved
USART2EN
Reserved
I2C1EN
TIM9EN
TIM10EN
TIM11EN
Reserved
SPI5EN
I2C2EN
I2C3EN
Reserved
LSEBYP
TIM5LPEN
CRCLPEN
Reserved
FLITFLPEN
SRAM1LPEN
OTGFSLPEN GPIOHLPEN
Reserved
USART1LPEN
Reserved
DMA1LPEN
DMA2LPEN
Reserved
USART6LPEN
ADC1LPEN
RTCSEL 0
Reserved
WWDGLPEN
RCC_AHB2L
PENR
SDIOLPEN
0x54
SPI1LPEN
RCC_AHB1L
PENR
Reserved
SPI3LPEN
Reserved
0x50
SPI4LPEN
Reserved
Reserved
Reserved
TIM9LPEN
Reserved
Reserved
LSEMOD
Reserved
TIM10LPEN USART2LPEN
TIM11LPEN
Reserved
SPI5LPEN
Reserved
I2C1LPEN
Reserved
Reserved
I2C2LPEN
0x48
0x4C
RTCSEL 1
Reserved
Reserved
I2C3LPEN
Reserved
RTCEN
Reserved
Reserved
PWREN
Reserved
BDRST
0x58
0x5C
PWRLPEN
RCC_APB2E
NR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x44
Reserved
RCC_APB1E
NR
Reserved
0x40
LPWRRSTF
Register
name
WWDGRSTF
Addr.
offset
Reserved
0x78
0x7C
Reserved
Reset and clock control (RCC) for STM32F411xC/E
RM0383
Table 21. RCC register map and reset values for STM32F411xC/E (continued)
Reserved
RM0383
Reset and clock control (RCC) for STM32F411xC/E
Addr.
offset
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 21. RCC register map and reset values for STM32F411xC/E (continued)
0x8C
Reserved
RCC_DCKCF
GR
Reserved
TIMPRE
0x88
Reserved
Refer to Table 3 on page 41 for the register boundary addresses.
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135
System configuration controller (SYSCFG)
7
RM0383
System configuration controller (SYSCFG)
The system configuration controller is mainly used to remap the memory accessible in the
code area and manage the external interrupt line connection to the GPIOs.
7.1
I/O compensation cell
By default the I/O compensation cell is not used. However when the I/O output buffer speed
is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell
for slew rate control on I/O tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
supply.
When the compensation cell is enabled, a READY flag is set to indicate that the
compensation cell is ready and can be used. The I/O compensation cell can be used only
when the supply voltage ranges from 2.4 to 3.6 V.
7.2
SYSCFG registers
7.2.1
SYSCFG memory remap register (SYSCFG_MEMRMP)
This register is used for specific configurations on memory remap:
•
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the BOOT
pins.
•
After reset these bits take the value selected by the BOOT pins. When booting from
main Flash memory with BOOT0 pin set to 0 this register takes the value 0x00.
In remap mode, the CPU can access the external memory via ICode bus instead of System
bus which boosts up the performance.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)
)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Reserved
15
14
13
12
11
10
9
8
7
Reserved
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MEM_MODE
rw
rw
RM0383
System configuration controller (SYSCFG)
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE: Memory mapping selection
Set and cleared by software. This bit controls the memory internal mapping at
address 0x0000 0000. After reset these bits take the value selected by the Boot
pins .
00: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
11: Embedded SRAM mapped at 0x0000 0000
Note: Refer to Section 2.3: Memory map for details about the memory mapping at
address 0x0000 0000.
7.2.2
SYSCFG peripheral mode configuration register (SYSCFG_PMC)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADC1D
C2
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 ADCxDC2:
0: No effect.
1: Refer to AN4073 on how to use this bit .
Note: These bits can be set only if the following conditions are met:
- ADC clock higher or equal to 30 MHz.
- Only one ADCxDC2 bit must be selected if ADC conversions do not start
at the same time and the sampling times differ.
- These bits must not be set when the ADCDC1 bit is set in PWR_CR
register.
Bits 15:0 Reserved, must be kept at reset value.
7.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
19
6
5
4
3
18
17
16
2
1
0
Reserved
EXTI3[3:0]
rw
rw
rw
7
EXTI2[3:0]
rw
rw
rw
EXTI1[3:0]
rw
rw
rw
rw
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rw
EXTI0[3:0]
rw
rw
rw
rw
rw
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System configuration controller (SYSCFG)
RM0383
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx
external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: Reserved
0110: Reserved
0111: PH[x] pin
7.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
19
6
5
4
3
18
17
16
2
1
0
Reserved
EXTI7[3:0]
rw
rw
rw
7
EXTI6[3:0]
rw
rw
rw
EXTI5[3:0]
rw
rw
rw
rw
rw
EXTI4[3:0]
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx
external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: Reserved
0110: Reserved
0111: PH[x] pin
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RM0383
System configuration controller (SYSCFG)
7.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
6
5
4
3
18
17
16
2
1
0
Reserved
15
14
13
12
11
EXTI11[3:0]
rw
rw
rw
10
9
8
7
EXTI10[3:0]
rw
rw
rw
rw
EXTI9[3:0]
rw
rw
rw
rw
EXTI8[3:0]
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
These bits are written by software to select the source input for the EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: Reserved
0110: Reserved
0111: PH[x] pin
7.2.6
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
Reserved
15
14
13
12
11
rw
rw
EXTI15[3:0]
rw
rw
rw
10
9
8
7
rw
rw
EXTI14[3:0]
rw
rw
EXTI13[3:0]
rw
rw
EXTI12[3:0]
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: Reserved
0110: Reserved
0111: PH[x] pin
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141
System configuration controller (SYSCFG)
7.2.7
RM0383
Compensation cell control register (SYSCFG_CMPCR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Reserved
15
14
13
12
Reserved
11
10
9
8
7
READY
r
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 READY: Compensation cell ready flag
0: I/O compensation cell not ready
1: O compensation cell ready
Bits 7:2 Reserved, must be kept at reset value.
Bit 0 CMP_PD: Compensation cell power-down
0: I/O compensation cell power-down mode
1: I/O compensation cell enabled
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Reserved
CMP_PD
rw
RM0383
7.2.8
System configuration controller (SYSCFG)
SYSCFG register map
The following table gives the SYSCFG register map and the reset values.
0x00
SYSCFG_
MEMRMP
MEM_MODE
Register
Reserved
SYSCFG_PMC
Reserved
Reset value
0x08
0x0C
0x10
0x14
0x20
SYSCFG_EXTICR1
Reset value
SYSCFG_EXTICR2
Reset value
SYSCFG_EXTICR3
Reset value
SYSCFG_EXTICR4
Reset value
SYSCFG_CMPCR
x
Reserved
0
EXTI3[3:0]
Reserved
0
0
0
0
EXTI7[3:0]
Reserved
0
Reserved
Reserved
0
0
0
EXTI2[3:0]
0
0
0
0
EXTI6[3:0]
0
0
0
0
EXTI11[3:0]
EXTI10[3:0]
0
0
0
0
0
0
0
0
EXTI1[3:0]
0
0
0
0
EXTI5[3:0]
0
0
0
0
EXTI9[3:0]
0
0
0
0
EXTI0[3:0]
0
0
0
0
EXTI4[3:0]
0
0
0
0
EXTI8[3:0]
0
0
0
0
EXTI15[3:0]
EXTI14[3:0]
EXTI13[3:0]
EXTI12[3:0]
0
0
0
0
0
0
0
0
Reserved
Reset value
0
0
READY
0x04
x
ADC1DC2
Reset value
0
0
0
0
0
Reserved
0
0
CMP_PD
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 22. SYSCFG register map and reset values
0
Refer to Table 3 on page 41 for the register boundary addresses.
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General-purpose I/Os (GPIO)
8
RM0383
General-purpose I/Os (GPIO)
GPIO F/G/H/I/J/K (except GPIOH0 and GPIOH1) are not available in STM32F411xC/E.
8.1
GPIO introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking
register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH
and GPIOx_AFRL).
8.2
8.3
GPIO main features
•
Up to 16 I/Os under control
•
Output states: push-pull or open drain + pull-up/down
•
Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
•
Speed selection for each I/O
•
Input states: floating, pull-up/down, analog
•
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•
Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
•
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration
•
Analog function
•
Alternate function input/output selection registers (at most 16 AFs per I/O)
•
Fast toggle capable of changing every two clock cycles
•
Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions
GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
142/836
•
Input floating
•
Input pull-up
•
Input-pull-down
•
Analog
•
Output open-drain with pull-up or pull-down capability
•
Output push-pull with pull-up or pull-down capability
•
Alternate function push-pull with pull-up or pull-down capability
•
Alternate function open-drain with pull-up or pull-down capability
DocID026448 Rev 1
RM0383
General-purpose I/Os (GPIO)
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is
to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no
risk of an IRQ occurring between the read and the modify access.
show the basic structure of a 5 V tolerant I/O port bit. Table 26 gives the possible port bit
configurations.
Figure 16. Basic structure of a five-volt tolerant I/O port bit
!NALOG
4OONCHIP
PERIPHERAL
!LTERNATEFUNCTIONINPUT
2EADWRITE
&ROMONCHIP
PERIPHERAL
)NPUTDATAREGISTER
6$$
44,3CHMITT
TRIGGER
ONOFF
6$$?&4 0ROTECTION
DIODE
0ULL
UP
)NPUTDRIVER
/UTPUTDATAREGISTER
"ITSETRESETREGISTERS
2EAD
7RITE
ONOFF
)/PIN
/UTPUTDRIVER
6$$
ONOFF
0-/3
633
/UTPUT
CONTROL
0ROTECTION
DIODE
0ULL
DOWN
633
.-/3
633
!LTERNATEFUNCTIONOUTPUT
0USHPULL
OPENDRAINOR
DISABLED
!NALOG
AIB
1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
Table 23. Port bit configuration table(1)
MODER(i)
[1:0]
01
OTYPER(i)
OSPEEDR(i)
[B:A]
PUPDR(i)
[1:0]
I/O configuration
0
0
0
GP output
PP
0
0
1
GP output
PP + PU
0
1
0
GP output
PP + PD
1
1
Reserved
0
0
GP output
OD
1
0
1
GP output
OD + PU
1
1
0
GP output
OD + PD
1
1
1
Reserved (GP output OD)
0
1
SPEED
[B:A]
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General-purpose I/Os (GPIO)
RM0383
Table 23. Port bit configuration table(1) (continued)
MODER(i)
[1:0]
10
00
11
OTYPER(i)
OSPEEDR(i)
[B:A]
PUPDR(i)
[1:0]
I/O configuration
0
0
0
AF
PP
0
0
1
AF
PP + PU
0
1
0
AF
PP + PD
1
1
Reserved
0
0
AF
OD
1
0
1
AF
OD + PU
1
1
0
AF
OD + PD
1
1
1
Reserved
0
SPEED
[B:A]
1
x
x
x
0
0
Input
Floating
x
x
x
0
1
Input
PU
x
x
x
1
0
Input
PD
x
x
x
1
1
Reserved (input floating)
x
x
x
0
0
Input/output
x
x
x
0
1
x
x
x
1
0
x
x
x
1
1
Analog
Reserved
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.
8.3.1
General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and the I/O ports are
configured in input floating mode.
The debug pins are in AF pull-up/pull-down after reset:
•
PA15: JTDI in pull-up
•
PA14: JTCK/SWCLK in pull-down
•
PA13: JTMS/SWDAT in pull-up
•
PB4: NJTRST in pull-up
•
PB3: JTDO in floating state
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the N-MOS is activated when 0 is output).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.
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RM0383
8.3.2
General-purpose I/Os (GPIO)
I/O pin multiplexer and mapping
The microcontroller I/O pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin
at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.
Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can
be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15)
registers:
•
After reset all I/Os are connected to the system’s alternate function 0 (AF0)
•
The peripherals’ alternate functions are mapped from AF1 to AF13
•
Cortex®-M4 with FPU EVENTOUT is mapped on AF15
This structure is shown in Figure 17 below.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, proceed as follows:
•
System function
Connect the I/O to AF0 and configure it depending on the function used:
Note:
–
JTAG/SWD, after each device reset these pins are assigned as dedicated pins
immediately usable by the debugger host (not controlled by the GPIO controller)
–
RTC_REFIN: this pin should be configured in Input floating mode
–
MCO1 and MCO2: these pins have to be configured in alternate function mode.
You can disable some or all of the JTAG/SWD pins and so release the associated pins for
GPIO usage.
For more details please refer to Section 6.2.10: Clock-out capability.
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General-purpose I/Os (GPIO)
RM0383
Table 24. Flexible SWJ-DP pin assignment
SWJ I/O pin assigned
PA13 /
JTMS/
SWDIO
PA14 /
JTCK/
SWCLK
PA15 /
JTDI
PB3 /
JTDO
PB4/
NJTRST
Full SWJ (JTAG-DP + SW-DP) - Reset state
X
X
X
X
X
Full SWJ (JTAG-DP + SW-DP) but without
NJTRST
X
X
X
X
JTAG-DP Disabled and SW-DP Enabled
X
X
Available debug ports
JTAG-DP Disabled and SW-DP Disabled
•
Released
GPIO
Configure the desired I/O as output or input in the GPIOx_MODER register.
•
Peripheral alternate function
For the ADC, configure the desired I/O as analog in the GPIOx_MODER register.
For other peripherals:
•
–
Configure the desired I/O as an alternate function in the GPIOx_MODER register
–
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively
–
Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register
EVENTOUT
Configure the I/O pin used to output the Cortex®-M4 with FPU EVENTOUT signal by
connecting it to AF15
Note:
EVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0 and PH1.
Please refer to the “Alternate function mapping” table in the datasheets for the detailed
mapping of the system and peripherals’ alternate function I/O pins.
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General-purpose I/Os (GPIO)
Figure 17. Selecting an alternate function onSTM32F411xC/E
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1. Configured in FS.
8.3.3
I/O port control registers
Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed (the I/O speed pins are directly connected to the
corresponding GPIOx_OSPEEDR register bits whatever the I/O direction). The
GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.
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8.3.4
RM0383
I/O port data registers
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A..E and H) and
Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A..E and H) for the register
descriptions.
8.3.5
I/O data bitwise handling
The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BSRR(i) and
BSRR(i+SIZE). When written to 1, bit BSRR(i) sets the corresponding ODR(i) bit. When
written to 1, bit BSRR(i+SIZE) resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB1 write access.
8.3.6
GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next reset. Each GPIOx_LCKR bit freezes the
corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).
The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A..E and H)) can only be performed using a word (32-bit long) access
to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the
same time as the [15:0] bits.
For more details please refer to LCKR register description in Section 8.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A..E and H).
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8.3.7
General-purpose I/Os (GPIO)
I/O alternate function input/output
Two registers are provided to select one out of the sixteen alternate function inputs/outputs
available for each I/O. With these registers, you can connect an alternate function to some
other pin as required by your application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of one I/O.
To know which functions are multiplexed on each GPIO pin, refer to the datasheets.
Note:
The application is allowed to select one of the possible peripheral functions for each I/O at a
time.
8.3.8
External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode, refer to Section 10.2: External interrupt/event controller (EXTI)
and Section 10.2.3: Wakeup event management.
Input configuration
When the I/O port is programmed as Input:
•
the output buffer is disabled
•
the Schmitt trigger input is activated
•
the pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register provides the I/O State
Figure 18 shows the input configuration of the I/O port bit.
)NPUTDATAREGISTER
Figure 18. Input floating/pull up/pull down configurations
7RITE
2EADWRITE
/UTPUTDATAREGISTER
2EAD
"ITSETRESETREGISTERS
8.3.9
ON
44,3CHMITT
TRIGGER
6$$ 6$$
ONOFF
PULL
UP
INPUTDRIVER
PROTECTION
DIODE
)/PIN
ONOFF
OUTPUTDRIVER
PULL
DOWN
633
PROTECTION
DIODE
633
AIB
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8.3.10
RM0383
Output configuration
When the I/O port is programmed as output:
•
The output buffer is enabled:
–
Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
–
Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
•
The Schmitt trigger input is activated
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register gets the I/O state
•
A read access to the output data register gets the last written value
Figure 19 shows the output configuration of the I/O port bit.
)NPUTDATAREGISTER
Figure 19. Output configuration
2EADWRITE
/UTPUTDATAREGISTER
7RITE
"ITSETRESETREGISTERS
2EAD
ON
6$$
44,3CHMITT
TRIGGER
6$$
ONOFF
)NPUTDRIVER
PROTECTION
DIODE
PULL
UP
/UTPUTDRIVER
6$$
)/PIN
ONOFF
0-/3
/UTPUT
CONTROL
PULL
DOWN
633
.-/3
0USHPULLOR
633
/PENDRAIN
PROTECTION
DIODE
633
AIB
8.3.11
Alternate function configuration
When the I/O port is programmed as alternate function:
•
The output buffer can be configured as open-drain or push-pull
•
The output buffer is driven by the signal coming from the peripheral (transmitter enable
and data)
•
The Schmitt trigger input is activated
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register gets the I/O state
Figure 20 shows the Alternate function configuration of the I/O port bit.
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Figure 20. Alternate function configuration
!LTERNATEFUNCTIONINPUT
2EADWRITE
&ROMONCHIP
PERIPHERAL
6$$ 6$$
44,3CHMITT
TRIGGER
ONOFF
PROTECTION
DIODE
0ULL
UP
)NPUTDRIVER
/UTPUTDATAREGISTER
"ITSETRESETREGISTERS
2EAD
7RITE
ON
)NPUTDATAREGISTER
4OONCHIP
PERIPHERAL
)/PIN
/UTPUTDRIVER
ONOFF
6$$
0-/3
/UTPUT
CONTROL
PROTECTION
DIODE
0ULL
DOWN
633
633
.-/3
633
PUSHPULLOR
OPENDRAIN
!LTERNATEFUNCTIONOUTPUT
AIB
8.3.12
Analog configuration
When the I/O port is programmed as analog configuration:
The output buffer is disabled
•
The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
•
The weak pull-up and pull-down resistors are disabled
•
Read access to the input data register gets the value “0”
In the analog configuration, the I/O pins cannot be 5 Volt tolerant.
Figure 21 shows the high-impedance, analog-input configuration of the I/O port bit.
Figure 21. High impedance-analog configuration
)NPUTDATAREGISTER
!NALOG
4OONCHIP
PERIPHERAL
7RITE
2EADWRITE
&ROMONCHIP
PERIPHERAL
/UTPUTDATAREGISTER
2EAD
"ITSETRESETREGISTERS
Note:
•
OFF
6$$
44,3CHMITT
TRIGGER
PROTECTION
DIODE
)NPUTDRIVER
)/PIN
PROTECTION
DIODE
633
!NALOG
AI
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8.3.13
RM0383
Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15
port pins
The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose
PC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os
are only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE
oscillator is ON. This is done by setting the LSEON bit in the RCC_BDCR register. The LSE
has priority over the GPIO function.
Note:
The PC14/PC15 GPIO functionality is lost when the 1.2 V domain is powered off (by the
device entering the standby mode) or when the backup domain is supplied by VBAT (VDD no
more supplied). In this case the I/Os are set in analog input mode.
8.3.14
Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1
I/Os, respectively, when the HSE oscillator is OFF. (after reset, the HSE oscillator is off). The
PH0/PH1 I/Os are only configured as OSC_IN/OSC_OUT HSE oscillator pins when the
HSE oscillator is ON. This is done by setting the HSEON bit in the RCC_CR register. The
HSE has priority over the GPIO function.
8.3.15
Selection of RTC additional functions
The STM32F4xx feature one GPIO pins RTC_AF1 that can be used for the detection of a
tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs.
•
The RTC_AF1 (PC13) can be used for the following purposes:
RTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup
depending on the OSEL[1:0] bits in the RTC_CR register
•
RTC_CALIB output: this feature is enabled by setting the COE[23] in the RTC_CR
register
•
RTC_TAMP1: tamper event detection
•
RTC_TS: time stamp event detection
The selection of the corresponding pin is performed through the RTC_TAFCR register as
follows:
•
TAMP1INSEL is used to select which pin is used as the RTC_TAMP1 tamper input
•
TSINSEL is used to select which pin is used as the RTC_TS time stamp input
•
ALARMOUTTYPE is used to select whether the RTC_ALARM is output in push-pull or
open-drain mode
The output mechanism follows the priority order listed in Table 25
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Table 25. RTC additional functions(1)
Pin
configuration
and function
TSINSEL
Time TAMP1INSEL
TIMESTAMP ALARMOUTTYP
stamp
TAMPER1
pin
E configuration
enabled pin selection
selection
enabled
enabled
Tamper
enabled
Alarm out
output OD
1
Don’t care
Don’t
care
Don’t
care
Don’t care
Don’t care
0
Alarm out
output PP
1
Don’t care
Don’t
care
Don’t
care
Don’t care
Don’t care
1
Calibration
out output PP
0
1
Don’t
care
Don’t
care
Don’t care
Don’t care
Don’t care
TAMPER1
input floating
0
0
1
0
0
Don’t care
Don’t care
TIMESTAMP
and
TAMPER1
input floating
0
0
1
1
0
0
Don’t care
TIMESTAMP
input floating
0
0
0
1
Don’t care
0
Don’t care
Standard
GPIO
0
0
0
0
Don’t care
Don’t care
Don’t care
1. OD: open drain; PP: push-pull.
8.4
GPIO registers
This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 26.
The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits).
8.4.1
GPIO port mode register (GPIOx_MODER) (x = A..E and H)
Address offset: 0x00
Reset values:
31
30
MODER15[1:0]
•
0x0C00 0000 for port A
•
0x0000 0280 for port B
•
0x0000 0000 for other ports
29
28
MODER14[1:0]
27
26
MODER13[1:0]
25
24
MODER12[1:0]
23
22
MODER11[1:0]
21
20
MODER10[1:0]
19
18
MODER9[1:0]
17
16
MODER8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODER7[1:0]
rw
rw
MODER6[1:0]
rw
rw
MODER5[1:0]
rw
rw
MODER4[1:0]
rw
rw
MODER3[1:0]
rw
rw
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MODER2[1:0]
rw
rw
MODER1[1:0]
rw
rw
MODER0[1:0]
rw
rw
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Bits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O direction mode.
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode
8.4.2
GPIO port output type register (GPIOx_OTYPER)
(x = A..E and H)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OT15
OT14
OT13
OT12
OT11
OT10
OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reserved
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OTy: Port x configuration bits (y = 0..15)
These bits are written by software to configure the output type of the I/O port.
0: Output push-pull (reset state)
1: Output open-drain
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8.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..E and H)
Address offset: 0x08
Reset values:
31
30
OSPEEDR15
[1:0]
•
0x0C00 0000 for port A
•
0x0000 00C0 for port B
•
0x0000 0000 for other ports
29
28
OSPEEDR14
[1:0]
27
26
OSPEEDR13
[1:0]
25
24
OSPEEDR12
[1:0]
23
22
OSPEEDR11
[1:0]
21
20
OSPEEDR10
[1:0]
19
18
17
16
OSPEEDR9
[1:0]
OSPEEDR8
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSPEEDR7[1:0] OSPEEDR6[1:0] OSPEEDR5[1:0] OSPEEDR4[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
OSPEEDR3[1:0]
rw
rw
OSPEEDR2[1:0]
rw
rw
OSPEEDR1
[1:0]
OSPEEDR0
1:0]
rw
rw
rw
rw
Bits 2y:2y+1 OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: Fast speed
11: High speed
Note: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD
range and external load.
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8.4.4
RM0383
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..E and H)
Address offset: 0x0C
Reset values:
31
30
•
0x6400 0000 for port A
•
0x0000 0100 for port B
•
0x0000 0000 for other ports
29
PUPDR15[1:0]
28
PUPDR14[1:0]
27
26
PUPDR13[1:0]
25
24
23
PUPDR12[1:0]
22
PUPDR11[1:0]
21
20
PUPDR10[1:0]
19
18
PUPDR9[1:0]
17
16
PUPDR8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PUPDR7[1:0]
rw
rw
PUPDR6[1:0]
rw
rw
PUPDR5[1:0]
rw
rw
PUPDR4[1:0]
rw
rw
PUPDR3[1:0]
rw
rw
PUPDR2[1:0]
rw
rw
PUPDR1[1:0]
rw
rw
PUPDR0[1:0]
rw
rw
17
16
Bits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
8.4.5
GPIO port input data register (GPIOx_IDR) (x = A..E and H)
Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDR15
IDR14
IDR13
IDR12
IDR11
IDR10
IDR9
IDR8
IDR7
IDR6
IDR5
IDR4
IDR3
IDR2
IDR1
IDR0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Reserved
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data (y = 0..15)
These bits are read-only and can be accessed in word mode only. They contain the input
value of the corresponding I/O port.
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8.4.6
GPIO port output data register (GPIOx_ODR) (x = A..E and H)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw
rw
rw
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
ODR9
ODR8
ODR7
ODR6
ODR5
ODR4
ODR3
ODR2
ODR1
ODR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data (y = 0..15)
These bits can be read and written by software.
Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the
GPIOx_BSRR register (x = A..E and H).
8.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:16 BRy: Port x reset bit y (y = 0..15)
These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x set bit y (y= 0..15)
These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit
8.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A..E and H)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
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General-purpose I/Os (GPIO)
RM0383
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next reset.
Note:
A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this write sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
Access: 32-bit word only, read/write register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LCKK
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
LCK12
LCK11
LCK10
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK[16]: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset
occurs.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will
return ‘1’ until the next CPU reset.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked
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RM0383
General-purpose I/Os (GPIO)
8.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
AFRL7[3:0]
26
25
24
23
22
AFRL6[3:0]
21
20
19
AFRL5[3:0]
18
17
16
AFRL4[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
18
17
16
AFRL3[3:0]
rw
AFRL2[3:0]
rw
rw
AFRL1[3:0]
rw
AFRL0[3:0]
Bits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7)
These bits are written by software to configure alternate function I/Os
AFRLy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
8.4.10
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
GPIO alternate function high register (GPIOx_AFRH)
(x = A..E and H)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
AFRH15[3:0]
26
25
24
23
AFRH14[3:0]
22
21
20
19
AFRH13[3:0]
AFRH12[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AFRH11[3:0]
rw
rw
rw
AFRH10[3:0]
rw
rw
rw
rw
AFRH9[3:0]
rw
rw
rw
rw
AFRH8[3:0]
rw
rw
rw
rw
rw
Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFRHy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
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161
Reset value
0x08
0x08
160/836
GPIOA_
OSPEEDER
Reset value
GPIOB_
OSPEEDER
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reset value
DocID026448 Rev 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
OT1
OT0
0
0
0
0
0
0
0
0
0
0
0
0
OSPEEDR0[1:0]
0
OSPEEDR0[1:0]
0
MODER1[1:0]
0
MODER1[1:0]
0
OSPEEDR0[1:0]
OT2
0
OT3
0
OSPEEDR1[1:0]
0
OSPEEDR1[1:0]
0
MODER2[1:0]
0
MODER2[1:0]
0
OSPEEDR1[1:0]
OT4
0
OT5
0
OSPEEDR2[1:0]
1
OSPEEDR2[1:0]
0
MODER3[1:0]
0
MODER3[1:0]
0
OSPEEDR2[1:0]
OT6
0
OT7
0
OSPEEDR3[1:0]
1
OSPEEDR3[1:0]
0
MODER4[1:0]
0
MODER4[1:0]
0
OSPEEDR3[1:0]
OT8
0
OT9
0
OSPEEDR4[1:0]
0
OSPEEDR4[1:0]
0
MODER5[1:0]
0
MODER5[1:0]
0
OSPEEDR4[1:0]
OT11
0
OT10
0
OSPEEDR5[1:0]
0
OSPEEDR5[1:0]
0
MODER6[1:0]
0
MODER6[1:0]
0
OSPEEDR5[1:0]
0
OT12
0
OT13
0
OSPEEDR6[1:0]
0
OSPEEDR6[1:0]
0
OSPEEDR6[1:0]
MODER7[1:0]
0
MODER7[1:0]
0
OT14
0
OT15
0
OSPEEDR7[1:0]
0
OSPEEDR7[1:0]
0
0
OSPEEDR7[1:0]
0
MODER8[1:0]
0
MODER8[1:0]
0
OSPEEDR8[1:0]
0
OSPEEDR8[1:0]
0
0
OSPEEDR8[1:0]
0
MODER9[1:0]
0
MODER9[1:0]
0
OSPEEDR9[1:0]
0
OSPEEDR9[1:0]
0
0
OSPEEDR9[1:0]
0
MODER10[1:0]
0
MODER10[1:0]
0
OSPEEDR10[1:0]
GPIOx_
OTYPER
(where x = A..E
and H)
0
OSPEEDR10[1:0]
0
0
OSPEEDR10[1:0]
0
MODER11[1:0]
0
MODER11[1:0]
0
OSPEEDR11[1:0]
0
OSPEEDR11[1:0]
0
1
OSPEEDR11[1:0]
0
MODER12[1:0]
0
MODER12[1:0]
0
OSPEEDR12[1:0]
1
OSPEEDR12[1:0]
0
MODER13[1:0]
0
MODER13[1:0]
MODER14[1:0]
0
OSPEEDR13[1:0]
MODER14[1:0]
0
0
OSPEEDR12[1:0]
0x08
GPIOx_
OSPEEDER
(where x = C..E
andH)
0
0
OSPEEDR13[1:0]
Reset value
0
OSPEEDR13[1:0]
0x04
GPIOx_MODER
(where x = C..E
and H)
0
OSPEEDR14[1:0]
Reset value
0
OSPEEDR14[1:0]
0x00
GPIOB_
MODER
MODER15[1:0]
Reset value
OSPEEDR14[1:0]
0x00
0
0
0
0
0
0
0
MODER0[1:0]
0
MODER0[1:0]
MODER0[1:0]
MODER1[1:0]
MODER2[1:0]
MODER3[1:0]
MODER4[1:0]
MODER5[1:0]
MODER6[1:0]
MODER7[1:0]
MODER8[1:0]
MODER9[1:0]
MODER10[1:0]
MODER11[1:0]
MODER12[1:0]
MODER13[1:0]
MODER14[1:0]
MODER15[1:0]
GPIOA_
MODER
MODER15[1:0]
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
OSPEEDR15[1:0]
Offset
OSPEEDR15[1:0]
8.4.11
OSPEEDR15[1:0]
General-purpose I/Os (GPIO)
RM0383
GPIO register map
The following table gives the GPIO register map and the reset values.
Table 26. GPIO register map and reset values
0
0
0
0
0
RM0383
General-purpose I/Os (GPIO)
0x20
Reset value
0x24
GPIOx_AFRH
(where x = A..E
and H)
Reset value
0
PUPDR0[1:0]
0
0
0
0
0
IDR1
IDR0
x
x
x
x
0
0
0
0
BS5
BS4
BS3
BS2
BS1
BS0
0
0
0
0
0
0
0
0
0
0
LCK4
LCK3
LCK2
LCK1
LCK0
0
LCK5
0
BS6
0
BS7
0
LCK6
0
LCK7
0
BS8
0
BS9
0
LCK8
0
LCK9
0
LCK11
0
LCK10
0
LCK12
0
LCK13
0
LCK14
0
LCK15
BS11
0
BS10
0
BS12
0
BS13
0
BS14
0
BS15
0
BR0
0
BR1
0
BR2
0
BR3
0
BR4
0
BR5
0
BR6
ODR0
x
ODR1
IDR2
PUPDR1[1:0]
IDR3
x
ODR2
IDR4
x
ODR3
IDR5
x
ODR4
IDR6
x
ODR5
IDR7
x
ODR6
x
ODR7
IDR8
x
ODR8
x
ODR9
IDR9
PUPDR2[1:0]
0
IDR11
PUPDR3[1:0]
0
PUPDR0[1:0]
0
0
PUPDR0[1:0]
0
PUPDR1[1:0]
0
PUPDR1[1:0]
0
0
IDR10
PUPDR4[1:0]
0
PUPDR2[1:0]
0
PUPDR3[1:0]
0
PUPDR4[1:0]
0
PUPDR2[1:0]
PUPDR3[1:0]
PUPDR4[1:0]
PUPDR5[1:0]
PUPDR5[1:0]
0
0
IDR12
PUPDR6[1:0]
0
0
x
0
Reset value
1
0
x
0
Reserved
0
x
0
GPIOx_LCKR
(where x = A..E
and H)
GPIOx_AFRL
(where x = A..E
and H)
0
BR7
0
0
BR8
0
0
BR9
0
0
BR11
BR12
0
0
0
BR10
BR13
Reset value
0
0
0
LCKK
0x1C
BR14
0x18
GPIOx_BSRR
(where x = A..E
and H)
BR15
Reset value
0
0
ODR11
Reserved
0
0
ODR10
GPIOx_ODR
(where x = A..E
and H)
0
0
IDR13
PUPDR8[1:0]
Reserved
Reset value
0x14
0
0
PUPDR5[1:0]
0
0
PUPDR6[1:0]
0
PUPDR6[1:0]
PUPDR7[1:0]
0
0
ODR12
0
0
ODR13
0
0
PUPDR7[1:0]
0
0
PUPDR7[1:0]
0
0
0
PUPDR8[1:0]
0
PUPDR8[1:0]
PUPDR9[1:0]
PUPDR10[1:0]
0
0
0
IDR14
GPIOx_IDR
(where x = A..E
and H)
0
0
0
PUPDR9[1:0]
0
0
0
PUPDR9[1:0]
0
0
0
PUPDR10[1:0]
0
0
PUPDR10[1:0]
0
PUPDR11[1:0]
PUPDR12[1:0]
0
0
0
PUPDR11[1:0]
0
0
0
PUPDR12[1:0]
0
0
PUPDR13[1:0]
0
PUPDR13[1:0]
PUPDR14[1:0]
0
0
0
IDR15
0
0
0
ODR14
0x10
0
1
ODR15
Reset value
0
0
PUPDR11[1:0]
0x0C
GPIOx_PUPDR
(where x = C..E
and H)
0
0
PUPDR12[1:0]
Reset value
1
PUPDR13[1:0]
GPIOB_PUPDR
1
PUPDR14[1:0]
0x0C
0
PUPDR14[1:0]
Reset value
PUPDR15[1:0]
GPIOA_PUPDR
PUPDR15[1:0]
0x0C
Register
PUPDR15[1:0]
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 26. GPIO register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AFRL7[3:0]
AFRL6[3:0]
AFRL5[3:0]
AFRL4[3:0]
AFRL3[3:0]
AFRL2[3:0]
AFRL1[3:0]
AFRL0[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0]
AFRH9[3:0]
AFRH8[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Table 1 on page 37 for the register boundary addresses.
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DMA controller (DMA)
RM0383
9
DMA controller (DMA)
9.1
DMA introduction
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory and between memory and memory. Data can be quickly moved by
DMA without any CPU action. This keeps CPU resources free for other operations.
The DMA controller combines a powerful dual AHB master bus architecture with
independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix
architecture.
The two DMA controllers have 16 streams in total (8 for each controller), each dedicated to
managing memory access requests from one or more peripherals. Each stream can have
up to 8 channels (requests) in total. And each has an arbiter for handling the priority
between DMA requests.
9.2
DMA main features
The main DMA features are:
•
Dual AHB master bus architecture, one dedicated to memory accesses and one
dedicated to peripheral accesses
•
AHB slave programming interface supporting only 32-bit accesses
•
8 streams for each DMA controller, up to 8 channels (requests) per stream
•
Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be
used in FIFO mode or direct mode:
–
FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the
FIFO size
–
Direct mode
Each DMA request immediately initiates a transfer from/to the memory. When it is
configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads only one data from the memory to the internal
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DMA controller (DMA)
FIFO to ensure an immediate data transfer as soon as a DMA request is triggered
by a peripheral.
•
Each stream can be configured by hardware to be:
–
a regular channel that supports peripheral-to-memory, memory-to-peripheral and
memory-to-memory transfers
–
a double buffer channel that also supports double buffering on the memory side
•
Each of the 8 streams are connected to dedicated hardware DMA channels (requests)
•
Priorities between DMA stream requests are software-programmable (4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request 0
has priority over request 1, etc.)
•
Each stream also supports software trigger for memory-to-memory transfers (only
available for the DMA2 controller)
•
Each stream request can be selected among up to 8 possible channel requests. This
selection is software-configurable and allows several peripherals to initiate DMA
requests
•
The number of data items to be transferred can be managed either by the DMA
controller or by the peripheral:
–
DMA flow controller: the number of data items to be transferred is softwareprogrammable from 1 to 65535
–
Peripheral flow controller: the number of data items to be transferred is unknown
and controlled by the source or the destination peripheral that signals the end of
the transfer by hardware
•
Independent source and destination transfer width (byte, half-word, word): when the
data widths of the source and destination are not equal, the DMA automatically
packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only
available in FIFO mode
•
Incrementing or nonincrementing addressing for source and destination
•
Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
•
Each stream supports circular buffer management
•
5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA
FIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for
each stream
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DMA controller (DMA)
RM0383
9.3
DMA functional description
9.3.1
General description
Figure 22 shows the block diagram of a DMA.
Figure 22. DMA block diagram
STREAM 7
Peripheral port
FIFO
FIFO
Memory port
STREAM 7
STREAM 6
STREAM 5
FIFO
STREAM 5
STREAM 6
STREAM 4
FIFO
STREAM 3
FIFO
STREAM 3
STREAM 4
STREAM 1
STREAM 2
FIFO
FIFO
FIFO
STREAM 2
REQ_STR7_CH0
REQ_STR7_CH1
Arbiter
STREAM 1
REQ_STR1_CH7
REQ_STREAM0
REQ_STREAM1
REQ_STREAM2
REQ_STREAM3
REQ_STREAM4
REQ_STREAM5
REQ_STREAM6
REQ_STREAM7
STREAM 0
REQ_STR1_CH0
REQ_STR1_CH1
STREAM 0
REQ_STR0_CH7
AHB master
REQ_STR0_CH0
REQ_STR0_CH1
AHB master
DMA controller
REQ_STR7_CH7
Channel
selection
AHB slave
programming
interface
Programming port
ai15945
The DMA controller performs direct memory transfer: as an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
It can carry out the following transactions:
•
peripheral-to-memory
•
memory-to-peripheral
•
memory-to-memory
The DMA controller provides two AHB master ports: the AHB memory port, intended to be
connected to memories and the AHB peripheral port, intended to be connected to
peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must
also have access to the memories.
The AHB slave port is used to program the DMA controller (it supports only 32-bit
accesses).
See Figure 23 for the implementation of the system of two DMA controllers.
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RM0383
DMA controller (DMA)
Figure 23. System implementation of the two DMA controllers( STM32F411xC/E)
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1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus
only DMA2 streams are able to perform memory-to-memory transfers.
9.3.2
DMA transactions
A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable.
Each DMA transfer consists of three operations:
•
A loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
•
A storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
•
A post-decrement of the DMA_SxNDTR register, which contains the number of
transactions that still have to be performed
After an event, the peripheral sends a request signal to the DMA controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the
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DMA controller. The peripheral releases its request as soon as it gets the Acknowledge
signal from the DMA controller. Once the request has been deasserted by the peripheral,
the DMA controller releases the Acknowledge signal. If there are more requests, the
peripheral can initiate the next transaction.
9.3.3
Channel selection
Each stream is associated with a DMA request that can be selected out of 8 possible
channel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR
register.
Figure 24. Channel selection
REQ_STRx_CH7
REQ_STRx_CH6
REQ_STRx_CH5
REQ_STRx_CH4
REQ_STREAMx
REQ_STRx_CH3
REQ_STRx_CH2
REQ_STRx_CH1
REQ_STRx_CH0
31
29
27
0
CHSEL[2:0]
DMA_SxCR
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The 8 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently connected
to each channel and their connection depends on the product implementation.
Table 79 and Table 81 give examples of DMA request mappings.
Table 27. DMA1 request mapping (STM32F411xC/E)
Peripheral
Stream 0
requests
Stream 1
Stream 2
Stream 3
Stream 4
SPI3_RX
SPI2_RX
SPI2_TX
Channel 0
SPI3_RX
I2C1_TX
Channel 1
I2C1_RX
I2C3_RX
Channel 2
TIM4_CH1
Channel 3
I2S3_EXT_RX
TIM2_UP
TIM2_CH3
I2S3_EXT_RX
TIM4_CH2
I2C3_RX
I2S2_EXT_RX
TIM3_CH4
TIM3_UP
Channel 6
Channel 7
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TIM5_CH3
TIM5_UP
TIM5_CH4
TIM5_TRIG
TIM5_CH1
TIM5_CH4
TIM5_TRIG
I2C2_RX
I2C2_RX
SPI3_TX
I2C1_TX
TIM4_UP
TIM4_CH3
TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM2_UP
TIM2_CH4
USART2_RX
USART2_TX
TIM3_CH1
TIM3_TRIG
TIM3_CH2
TIM5_CH2
I2C3_TX
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Stream 7
I2C1_TX
I2S2_EXT_TX I2S3_EXT_TX
I2C3_TX
Stream 6
SPI3_TX
I2C1_RX
Channel 4
Channel 5
Stream 5
TIM3_CH3
TIM5_UP
USART2_RX
I2C2_TX
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DMA controller (DMA)
Table 28. DMA2 request mapping (STM32F411xC/E)
Peripheral
Stream 0
requests
Channel 0
Stream 1
Stream 2
Stream 3
Stream 4
ADC1
Stream 5
Stream 6
Stream 7
TIM1_CH1
TIM1_CH2
TIM1_CH3
ADC1
Channel 1
Channel 2
Channel 3
SPI1_RX
Channel 4
SPI4_RX
Channel 5
Channel 6
TIM1_TRIG
SPI1_TX
SPI5_RX
SPI1_RX
SPI1_TX
SPI4_TX
USART1_RX
SDIO
USART6_RX
USART6_RX
TIM1_CH1
TIM1_CH2
SPI5_TX
SPI1_TX
SPI4_RX
USART1_RX
SDIO
USART1_TX
SPI4_RX
SPI4_TX
SPI5_TX
USART6_TX
USART6_TX
TIM1_CH1
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM1_UP
TIM1_CH3
SPI5_RX
SPI5_TX
Channel 7
9.3.4
Arbiter
An arbiter manages the 8 DMA stream requests based on their priority for each of the two
AHB master ports (memory and peripheral ports) and launches the peripheral/memory
access sequences.
Priorities are managed in two stages:
•
•
9.3.5
Software: each stream priority can be configured in the DMA_SxCR register. There are
four levels:
–
Very high priority
–
High priority
–
Medium priority
–
Low priority
Hardware: If two requests have the same software priority level, the stream with the
lower number takes priority over the stream with the higher number. For example,
Stream 2 takes priority over Stream 4.
DMA streams
Each of the 8 DMA controller streams provides a unidirectional transfer link between a
source and a destination.
Each stream can be configured to perform:
•
Regular type transactions: memory-to-peripherals, peripherals-to-memory or memoryto-memory transfers
•
Double-buffer type transactions: double buffer transfers using two memory pointers for
the memory (while the DMA is reading/writing from/to a buffer, the application can
write/read to/from the other buffer).
The amount of data to be transferred (up to 65535) is programmable and related to the
source width of the peripheral that requests the DMA transfer connected to the peripheral
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AHB port. The register that contains the amount of data items to be transferred is
decremented after each transaction.
9.3.6
Source, destination and transfer modes
Both source and destination transfers can address peripherals and memories in the entire
4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers
three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory
transfers. Table 29 describes the corresponding source and destination addresses.
Table 29. Source and destination address
Bits DIR[1:0] of the
DMA_SxCR register
Direction
Source address
Destination address
00
Peripheral-to-memory
DMA_SxPAR
DMA_SxM0AR
01
Memory-to-peripheral
DMA_SxM0AR
DMA_SxPAR
10
Memory-to-memory
DMA_SxPAR
DMA_SxM0AR
11
reserved
-
-
When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register)
is a half-word or a word, respectively, the peripheral or memory address written into the
DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word
address boundary, respectively.
Peripheral-to-memory mode
Figure 25 describes this mode.
When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a
peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.
When the threshold level of the FIFO is reached, the contents of the FIFO are drained and
stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold
level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO,
the corresponding data are immediately drained and stored into the destination.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
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DMA controller (DMA)
Figure 25. Peripheral-to-memory mode
DMA_SxM0AR
DMA controller
DMA_SxM1AR(1)
AHB memory
port
Memory bus
Memory
destination
REQ_STREAMx
Arbiter
FIFO
level
FIFO
AHB peripheral
port
Peripheral bus
peripheral
source
DMA_SxPAR
Peripheral DMA request
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1. For double-buffer mode.
Memory-to-peripheral mode
Figure 26 describes this mode.
When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream
immediately initiates transfers from the source to entirely fill the FIFO.
Each time a peripheral request occurs, the contents of the FIFO are drained and stored into
the destination. When the level of the FIFO is lower than or equal to the predefined
threshold level, the FIFO is fully reloaded with data from the memory.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold
level of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to
transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA
transfers the preloaded value into the configured destination. It then reloads again the
empty internal FIFO with the next data to be transfer. The preloaded data size corresponds
to the value of the PSIZE bitfield in the DMA_SxCR register.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
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Figure 26. Memory-to-peripheral mode
DMA_SxM0AR
DMA controller
DMA_SxM1AR(1)
AHB memory
port
Memory bus
Memory
source
REQ_STREAMx
Arbiter
FIFO
level
FIFO
AHB peripheral
port
Peripheral bus
DMA_SxPAR
Peripheral
destination
Peripheral DMA request
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1. For double-buffer mode.
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This is the memory-to-memory mode, described in Figure 27.
When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the
stream immediately starts to fill the FIFO up to the threshold level. When the threshold level
is reached, the FIFO contents are drained and stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the
DMA_SxCR register is cleared by software.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
Note:
When memory-to-memory mode is used, the Circular and direct modes are not allowed.
Only the DMA2 controller is able to perform memory-to-memory transfers.
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Figure 27. Memory-to-memory mode
DMA_SxM0AR
DMA controller
DMA_SxM1AR(1)
AHB memory
port
Memory bus
Memory 2
destination
Arbiter
Stream enable
FIFO
level
FIFO
AHB peripheral
port
DMA_SxPAR
Peripheral bus
Memory 1
source
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1. For double-buffer mode.
9.3.7
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented or kept
constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR
register.
Disabling the Increment mode is useful when the peripheral source or destination data are
accessed through a single register.
If the Increment mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on
the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.
In order to optimize the packing operation, it is possible to fix the increment offset size for
the peripheral address whatever the size of the data transferred on the AHB peripheral port.
The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with
the data size on the peripheral AHB port, or on a 32-bit address (the address is then
incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.
If PINCOS bit is set, the address of the next transfer is the address of the previous one
incremented by 4 (automatically aligned on a 32-bit address) whatever the PSIZE value.
The AHB memory port, however, is not impacted by this operation.
9.3.8
Circular mode
The Circular mode is available to handle circular buffers and continuous data flows (e.g.
ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR
register.
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When the circular mode is activated, the number of data items to be transferred is
automatically reloaded with the initial value programmed during the stream configuration
phase, and the DMA requests continue to be served.
Note:
In the circular mode, it is mandatory to respect the following rule in case of a burst mode
configured for memory:
DMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:
–
(Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR
register)
–
((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and
PSIZE bits in the DMA_SxCR register. They are byte dependent)
–
DMA_SxNDTR = Number of data items to transfer on the AHB peripheral port
For example: Mburst beat = 8 (INCR8), MSIZE = ‘00’ (byte) and PSIZE = ‘01’ (half-word), in
this case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).
If this formula is not respected, the DMA behavior and data integrity are not guaranteed.
NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data
size, otherwise this could result in a bad DMA behavior.
9.3.9
Double buffer mode
This mode is available for all the DMA1 and DMA2 streams.
The Double buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.
A double-buffer stream works as a regular (single buffer) stream with the difference that it
has two memory pointers. When the Double buffer mode is enabled, the Circular mode is
automatically enabled (CIRC bit in DMA_SxCR is don’t care) and at each end of transaction,
the memory pointers are swapped.
In this mode, the DMA controller swaps from one memory target to another at each end of
transaction. This allows the software to process one memory area while the second memory
area is being filled/used by the DMA transfer. The double-buffer stream can work in both
directions (the memory can be either the source or the destination) as described in
Table 30: Source and destination address registers in Double buffer mode (DBM=1).
Note:
In Double buffer mode, it is possible to update the base address for the AHB memory port
on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the
following conditions:
•
When the CT bit is ‘0’ in the DMA_SxCR register, the DMA_SxM1AR register can be
written. Attempting to write to this register while CT = '1' sets an error flag (TEIF) and
the stream is automatically disabled.
•
When the CT bit is ‘1’ in the DMA_SxCR register, the DMA_SxM0AR register can be
written. Attempting to write to this register while CT = '0', sets an error flag (TEIF) and
the stream is automatically disabled.
To avoid any error condition, it is advised to change the base address as soon as the TCIF
flag is asserted because, at this point, the targeted memory must have changed from
memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in
accordance with one of the two above conditions.
For all the other modes (except the Double buffer mode), the memory address registers are
write-protected as soon as the stream is enabled.
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DMA controller (DMA)
Table 30. Source and destination address registers in Double buffer mode (DBM=1)
Bits DIR[1:0] of the
DMA_SxCR register
Direction
Source address
Destination address
00
Peripheral-to-memory
DMA_SxPAR
DMA_SxM0AR /
DMA_SxM1AR
01
Memory-to-peripheral
DMA_SxM0AR /
DMA_SxM1AR
DMA_SxPAR
10
Not allowed(1)
11
Reserved
-
-
1. When the Double buffer mode is enabled, the Circular mode is automatically enabled. Since the memoryto-memory mode is not compatible with the Circular mode, when the Double buffer mode is enabled, it is
not allowed to configure the memory-to-memory mode.
9.3.10
Programmable data width, packing/unpacking, endianess
The number of data items to be transferred has to be programmed into DMA_SxNDTR
(number of data items to transfer bit, NDT) before enabling the stream (except when the
flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).
When using the internal FIFO, the data widths of the source and destination data are
programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-,
16- or 32-bit).
When PSIZE and MSIZE are not equal:
•
The data width of the number of data items to transfer, configured in the DMA_SxNDTR
register is equal to the width of the peripheral bus (configured by the PSIZE bits in the
DMA_SxCR register). For instance, in case of peripheral-to-memory, memory-toperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for
half-word, the number of bytes to be transferred is equal to 2 × NDT.
•
The DMA controller only copes with little-endian addressing for both source and
destination. This is described in Table 31: Packing/unpacking & endian behavior (bit
PINC = MINC = 1).
This packing/unpacking procedure may present a risk of data corruption when the operation
is interrupted before the data are completely packed/unpacked. So, to ensure data
coherence, the stream may be configured to generate burst transfers: in this case, each
group of transfers belonging to a burst are indivisible (refer to Section 9.3.11: Single and
burst transfers).
In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is
not possible. In this case, it is not allowed to have different source and destination transfer
data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR MSIZE bits are
don’t care).
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Table 31. Packing/unpacking & endian behavior (bit PINC = MINC = 1)
Number
AHB
AHB
of data
Memory Memory port
memory
peripheral items to transfer address / byte
port
port width transfer number lane
width
(NDT)
Peripheral port address / byte lane
Peripher
al
transfer
PINCOS = 1
PINCOS = 0
number
8
8
4
1
2
3
4
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
0x0 / B1|B0[15:0]
2
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
0x0 / B1|B0[15:0]
16
1
2
3
4
1
8
2
0x4 / B3|B2[15:0]
0x2 / B3|B2[15:0]
1
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
0x0 / B3|B2|B1|B0[31:0] 0x0 / B3|B2|B1|B0[31:0]
32
1
2
3
4
1
8
1
0x0 / B1|B0[15:0]
16
8
4
2
0x2 / B3|B2[15:0]
1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
0x0 / B1|B0[15:0]
1
0x0 / B1|B0[15:0]
0x0 / B1|B0[15:0]
16
16
2
2
0x2 / B1|B0[15:0]
2
0x4 / B3|B2[15:0]
0x2 / B3|B2[15:0]
1
2
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
1
0x0 / B3|B2|B1|B0[31:0] 0x0 / B3|B2|B1|B0[31:0]
1
0x0 / B3|B2|B1|B0[31:0] 1
2
3
4
1
0x0 /B3|B2|B1|B0[31:0]
1
0x0 /B3|B2|B1|B0 [31:0] 1
16
32
1
32
8
4
32
16
2
32
32
1
Note:
1
2
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0]
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
0x0 /B3|B2|B1|B0 [31:0] 0x0 / B3|B2|B1|B0[31:0]
Peripheral port may be the source or the destination (it could also be the memory source in
the case of memory-to-memory transfer).
PSIZE, MSIZE and NDT[15:0] have to be configured so as to ensure that the last transfer
will not be incomplete. This can occur when the data width of the peripheral port (PSIZE
bits) is lower than the data width of the memory port (MSIZE bits). This constraint is
summarized in Table 32.
Table 32. Restriction on NDT versus PSIZE and MSIZE
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MSIZE[1:0] of DMA_SxCR
NDT[15:0] of DMA_SxNDTR
00 (8-bit)
01 (16-bit)
must be a multiple of 2
00 (8-bit)
10 (32-bit)
must be a multiple of 4
01 (16-bit)
10 (32-bit)
must be a multiple of 2
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9.3.11
DMA controller (DMA)
Single and burst transfers
The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16
beats.
The size of the burst is configured by software independently for the two AHB ports by using
the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
The burst size indicates the number of beats in the burst, not the number of bytes
transferred.
To ensure data coherence, each group of transfers that form a burst are indivisible: AHB
transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master
during the sequence of the burst transfer.
Depending on the single or burst configuration, each DMA request initiates a different
number of transfers on the AHB peripheral port:
•
When the AHB peripheral port is configured for single transfers, each DMA request
generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits
in the DMA_SxCR register
•
When the AHB peripheral port is configured for burst transfers, each DMA request
generates 4,8 or 16 beats of byte, half word or word transfers depending on the
PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.
The same as above has to be considered for the AHB memory port considering the
MBURST and MSIZE bits.
In direct mode, the stream can only generate single transfers and the MBURST[1:0] and
PBURST[1:0] bits are forced by hardware.
The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to
ensure that all transfers within a burst block are aligned on the address boundary equal to
the size of the transfer.
The burst configuration has to be selected in order to respect the AHB protocol, where
bursts must not cross the 1 KB address boundary because the minimum address space that
can be allocated to a single slave is 1 KB. This means that the 1 KB address boundary
should not be crossed by a burst block transfer, otherwise an AHB error would be
generated, that is not reported by the DMA registers.
9.3.12
FIFO
FIFO structure
The FIFO is used to temporarily store data coming from the source before transmitting them
to the destination.
Each stream has an independent 4-word FIFO and the threshold level is softwareconfigurable between 1/4, 1/2, 3/4 or full.
To enable the use of the FIFO threshold level, the direct mode must be disabled by setting
the DMDIS bit in the DMA_SxFCR register.
The structure of the FIFO differs depending on the source and destination data widths, and
is described in Figure 28: FIFO structure.
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Figure 28. FIFO structure
4 words
Empty
Source: byte
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
1/4
1/2
3/4
Full
byte lane 3
B15
B 11
B7
B3
byte lane 2
B14
B10
B6
B2
byte lane 1
B13
B9
B5
B1
byte lane 0 W3 B12
B8
B4
B0
W2
W1
W0
Destination: word
W3, W2, W1, W0
4 words
Empty
Source: byte
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
byte lane 3
1/4
1/2
3/4
B15
B 11
B7
byte lane 2 H7 B14
H5 B10
H3 B6
B13
B9
B5
byte lane 0 H6 B12
H4 B8
H2 B4
byte lane 1
Full
B3
H1
Destination: half-word
B2
H7, H6, H5, H4, H3, H2, H1, H0
B1
H0
B0
4 words
Empty
Source: half-word
1/4
1/2
3/4
Full
byte lane 3
H7
H5
H3
H1
H6
H4
H2
H0
Destination: word
byte lane 2
H7 H6 H5 H4 H3 H2 H1 H0
byte lane 1
W3, W2, W1, W0
byte lane 0 W3
W2
W1
W0
4-words
Empty
Source: half-word
H7 H6 H5 H4 H3 H2 H1 H0
byte lane 3
1/4
1/2
3/4
B15
B 11
B7
byte lane 2 H7 B14
H5 B10
H3 B6
B13
B9
B5
byte lane 0 H6 B12
H4 B8
H2 B4
byte lane 1
Full
B3
H1
B1
H0
Destination: byte
B2
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
B0
ai15951
FIFO threshold and burst configuration
Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR
register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The
content pointed by the FIFO threshold must exactly match to an integer number of memory
burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or
DMA_LISR register) will be generated when the stream is enabled, then the stream will be
automatically disabled. The allowed and forbidden configurations are described in the
Table 33: FIFO threshold configurations.
Table 33. FIFO threshold configurations
MSIZE
Byte
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FIFO level MBURST = INCR4
MBURST = INCR8
1/4
1 burst of 4 beats
forbidden
1/2
2 bursts of 4 beats
1 burst of 8 beats
3/4
3 bursts of 4 beats
forbidden
Full
4 bursts of 4 beats
2 bursts of 8 beats
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MBURST = INCR16
forbidden
1 burst of 16 beats
RM0383
DMA controller (DMA)
Table 33. FIFO threshold configurations (continued)
MSIZE
Half-word
FIFO level MBURST = INCR4
1/4
forbidden
1/2
1 burst of 4 beats
3/4
forbidden
Full
2 bursts of 4 beats
MBURST = INCR8
forbidden
1 burst of 8 beats
1/4
Word
1/2
forbidden
3/4
Full
MBURST = INCR16
forbidden
forbidden
1 burst of 4 beats
In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data
size can be: 1 (byte), 2 (half-word) or 4 (word)).
Incomplete Burst transfer at the end of a DMA transfer may happen if one of the following
conditions occurs:
•
For the AHB peripheral port configuration: the total number of data items (set in the
DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size
•
For the AHB memory port configuration: the number of remaining data items in the
FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the
data size
In such cases, the remaining data to be transferred will be managed in single mode by the
DMA, even if a burst transaction was requested during the DMA stream configuration.
Note:
When burst transfers are requested on the peripheral AHB port and the FIFO is used
(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to
avoid permanent underrun or overrun conditions, depending on the DMA stream direction:
If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with
PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.
This rule ensures that enough FIFO space at a time will be free to serve the request from
the peripheral.
FIFO flush
The FIFO can be flushed when the stream is disabled by resetting the EN bit in the
DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or
memory-to-memory transfers: If some data are still present in the FIFO when the stream is
disabled, the DMA controller continues transferring the remaining data to the destination
(even though stream is effectively disabled). When this flush is completed, the transfer
complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.
The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how
many data items are currently available in the destination memory.
Note that during the FIFO flush operation, if the number of remaining data items in the FIFO
to be transferred to memory (in bytes) is less than the memory data width (for example 2
bytes in FIFO while MSIZE is configured to word), data will be sent with the data width set in
the MSIZE bit in the DMA_SxCR register. This means that memory will be written with an
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DMA controller (DMA)
RM0383
undesired value. The software may read the DMA_SxNDTR register to determine the
memory area that contains the good data (start address and last address).
If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST
bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB
memory port), single transactions will be generated to complete the FIFO flush.
Direct mode
By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and
the FIFO threshold level is not used. This mode is useful when the system requires an
immediate and single transfer to or from the memory after each DMA request.
When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads one data from the memory to the internal FIFO to
ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.
To avoid saturating the FIFO, it is recommended to configure the corresponding stream with
a high priority.
This mode is restricted to transfers where:
•
The source and destination transfer widths are equal and both defined by the
PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are don’t care)
•
Burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR
are don’t care)
Direct mode must not be used when implementing memory-to-memory transfers.
9.3.13
DMA transfer completion
Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR
or DMA_HISR status register:
•
•
Note:
In DMA flow controller mode:
–
The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode
–
The stream is disabled before the end of transfer (by clearing the EN bit in the
DMA_SxCR register) and (when transfers are peripheral-to-memory or memoryto-memory) all the remaining data have been flushed from the FIFO into the
memory
In Peripheral flow controller mode:
–
The last external burst or single request has been generated from the peripheral
and (when the DMA is operating in peripheral-to-memory mode) the remaining
data have been transferred from the FIFO into the memory
–
The stream is disabled by software, and (when the DMA is operating in peripheralto-memory mode) the remaining data have been transferred from the FIFO into
the memory
The transfer completion is dependent on the remaining data in FIFO to be transferred into
memory only in the case of peripheral-to-memory mode. This condition is not applicable in
memory-to-peripheral mode.
If the stream is configured in noncircular mode, after the end of the transfer (that is when the
number of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR
register is cleared by Hardware) and no DMA request is served unless the software
reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).
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RM0383
9.3.14
DMA controller (DMA)
DMA transfer suspension
At any time, a DMA transfer can be suspended to be restarted later on or to be definitively
disabled before the end of the DMA transfer.
There are two cases:
•
The stream disables the transfer with no later-on restart from the point where it was
stopped. There is no particular action to do, except to clear the EN bit in the
DMA_SxCR register to disable the stream. The stream may take time to be disabled
(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the
DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The
value of the EN bit in DMA_SxCR is now ‘0’ to confirm the stream interruption. The
DMA_SxNDTR register contains the number of remaining data items at the moment
when the stream was stopped so that the software can determine how many data items
have been transferred before the stream was interrupted.
•
The stream suspends the transfer before the number of remaining data items to be
transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer
later by re-enabling the stream. In order to restart from the point where the transfer was
stopped, the software has to read the DMA_SxNDTR register after disabling the stream
by writing the EN bit in DMA_SxCR register (and then checking that it is at ‘0’) to know
the number of data items already collected. Then:
–
The peripheral and/or memory addresses have to be updated in order to adjust
the address pointers
–
The SxNDTR register has to be updated with the remaining number of data items
to be transferred (the value read when the stream was disabled)
–
The stream may then be re-enabled to restart the transfer from the point it was
stopped
Note:
Note that a Transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to
indicate the end of transfer due to the stream interruption.
9.3.15
Flow controller
The entity that controls the number of data to be transferred is known as the flow controller.
This flow controller is configured independently for each stream using the PFCTRL bit in the
DMA_SxCR register.
The flow controller can be:
•
The DMA controller: in this case, the number of data items to be transferred is
programmed by software into the DMA_SxNDTR register before the DMA stream is
enabled.
•
The peripheral source or destination: this is the case when the number of data items to
be transferred is unknown. The peripheral indicates by hardware to the DMA controller
when the last data are being transferred. This feature is only supported for peripherals
which are able to signal the end of the transfer, that is:
–
SDIO
When the peripheral flow controller is used for a given stream, the value written into the
DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it will
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be forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following
schemes:
•
Anticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the
software to stop the stream before the last data hardware signal (single or burst) is sent
by the peripheral. In such a case, the stream is switched off and the FIFO flush is
triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the
corresponding stream is set in the status register to indicate the DMA completion. To
know the number of data items transferred during the DMA transfer, read the
DMA_SxNDTR register and apply the following formula:
–
Note:
Number_of_data_transferred = 0xFFFF – DMA_SxNDTR
•
Normal stream interruption due to the reception of a last data hardware signal: the
stream is automatically interrupted when the peripheral requests the last transfer
(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding
stream is set in the status register to indicate the DMA transfer completion. To know the
number of data items transferred, read the DMA_SxNDTR register and apply the same
formula as above.
•
The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is
set in the status register to indicate the forced DMA transfer completion. The stream is
automatically switched off even though the last data hardware signal (single or burst)
has not been yet asserted. The already transferred data will not be lost. This means
that a maximum of 65535 data items can be managed by the DMA in a single
transaction, even in peripheral flow control mode.
When configured in memory-to-memory mode, the DMA is always the flow controller and
the PFCTRL bit is forced to 0 by hardware.
The Circular mode is forbidden in the peripheral flow controller mode.
9.3.16
Summary of the possible DMA configurations
Table 34 summarizes the different possible DMA configurations.
Table 34. Possible DMA configurations
DMA transfer
mode
Peripheral-tomemory
Memory-toperipheral
Memory-tomemory
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Source
Destination
Flow
controller
Circular
mode
DMA
possible
Peripheral
forbidden
DMA
possible
Peripheral
forbidden
DMA only
forbidden
AHB
AHB
peripheral port memory port
AHB
memory port
AHB
peripheral port
AHB
AHB
peripheral port memory port
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Transfer
type
Direct
mode
single
possible
burst
forbidden
single
possible
burst
forbidden
single
possible
burst
forbidden
single
possible
burst
forbidden
single
burst
forbidden
Double
buffer mode
possible
forbidden
possible
forbidden
forbidden
RM0383
9.3.17
DMA controller (DMA)
Stream configuration procedure
The following sequence should be followed to configure a DMA stream x (where x is the
stream number):
1.
If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register,
then read this bit in order to confirm that there is no ongoing stream operation. Writing
this bit to 0 is not immediately effective since it is actually written to 0 once all the
current transfers have finished. When the EN bit is read as 0, this means that the
stream is ready to be configured. It is therefore necessary to wait for the EN bit to be
cleared before starting any stream configuration. All the stream dedicated bits set in the
status register (DMA_LISR and DMA_HISR) from the previous data block DMA
transfer should be cleared before the stream can be re-enabled.
2.
Set the peripheral port register address in the DMA_SxPAR register. The data will be
moved from/ to this address to/ from the peripheral port after the peripheral event.
3.
Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R
register in the case of a double buffer mode). The data will be written to or read from
this memory after the peripheral event.
4.
Configure the total number of data items to be transferred in the DMA_SxNDTR
register. After each peripheral event or each beat of the burst, this value is
decremented.
5.
Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.
6.
If the peripheral is intended to be the flow controller and if it supports this feature, set
the PFCTRL bit in the DMA_SxCR register.
7.
Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.
8.
Configure the FIFO usage (enable or disable, threshold in transmission and reception)
9.
Configure the data transfer direction, peripheral and memory incremented/fixed mode,
single or burst transactions, peripheral and memory data widths, Circular mode,
Double buffer mode and interrupts after half and/or full transfer, and/or errors in the
DMA_SxCR register.
10. Activate the stream by setting the EN bit in the DMA_SxCR register.
As soon as the stream is enabled, it can serve any DMA request from the peripheral
connected to the stream.
Once half the data have been transferred on the AHB destination port, the half-transfer flag
(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is
set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is
generated if the transfer complete interrupt enable bit (TCIE) is set.
Warning:
To switch off a peripheral connected to a DMA stream
request, it is mandatory to, first, switch off the DMA stream to
which the peripheral is connected, then to wait for EN bit = 0.
Only then can the peripheral be safely disabled.
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9.3.18
RM0383
Error management
The DMA controller can detect the following errors:
•
•
•
Transfer error: the transfer error interrupt flag (TEIFx) is set when:
–
A bus error occurs during a DMA read or a write access
–
A write access is requested by software on a memory address register in Double
buffer mode whereas the stream is enabled and the current target memory is the
one impacted by the write into the memory address register (refer to Section 9.3.9:
Double buffer mode)
FIFO error: the FIFO error interrupt flag (FEIFx) is set if:
–
A FIFO underrun condition is detected
–
A FIFO overrun condition is detected (no detection in memory-to-memory mode
because requests and transfers are internally managed by the DMA)
–
The stream is enabled while the FIFO threshold level is not compatible with the
size of the memory burst (refer to Table 33: FIFO threshold configurations)
Direct mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the
peripheral-to-memory mode while operating in direct mode and when the MINC bit in
the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while
the previous data have not yet been fully transferred into the memory (because the
memory bus was not granted). In this case, the flag indicates that 2 data items were be
transferred successively to the same destination address, which could be an issue if
the destination is not able to manage this situation
In direct mode, the FIFO error flag can also be set under the following conditions:
•
In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory
bus is not granted for several peripheral requests
•
In the memory-to-peripheral mode, an underrun condition may occur if the memory bus
has not been granted before a peripheral request occurs
If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO
threshold level, the faulty stream is automatically disabled through a hardware clear of its
EN bit in the corresponding stream configuration register (DMA_SxCR).
If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty
stream is not automatically disabled and it is up to the software to disable or not the stream
by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss
when this kind of errors occur.
When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR
register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE,
FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.
Note:
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When a FIFO overrun or underrun condition occurs, the data are not lost because the
peripheral request is not acknowledged by the stream until the overrun or underrun
condition is cleared. If this acknowledge takes too much time, the peripheral itself may
detect an overrun or underrun condition of its internal buffer and data might be lost.
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RM0383
DMA controller (DMA)
9.4
DMA interrupts
For each DMA stream, an interrupt can be produced on the following events:
•
Half-transfer reached
•
Transfer complete
•
Transfer error
•
Fifo error (overrun, underrun or FIFO level error)
•
Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in Table 35.
Table 35. DMA interrupt requests
Interrupt event
Event flag
Enable control bit
Half-transfer
HTIF
HTIE
Transfer complete
TCIF
TCIE
Transfer error
TEIF
TEIE
FIFO overrun/underrun
FEIF
FEIE
DMEIF
DMEIE
Direct mode error
Note:
Before setting an Enable control bit to ‘1’, the corresponding event flag should be cleared,
otherwise an interrupt is immediately generated.
9.5
DMA registers
The DMA registers have to be accessed by words (32 bits).
9.5.1
DMA low interrupt status register (DMA_LISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
Reserved
27
26
25
TCIF3
HTIF3
TEIF3
r
r
r
r
r
r
r
15
14
13
12
11
10
9
TCIF1
HTIF1
TEIF1
r
r
r
Reserved
r
r
r
r
24
23
22
DMEIF3 Reserv FEIF3
ed
r
r
8
7
6
DMEIF1 Reserv FEIF1
ed
r
r
21
20
19
TCIF2
HTIF2
TEIF2
r
r
r
5
4
3
TCIF0
HTIF0
TEIF0
r
r
r
18
17
DMEIF2 Reserv
ed
r
2
1
DMEIF0 Reserv
ed
r
16
FEIF2
r
0
FEIF0
r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
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Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No Direct Mode Error on stream x
1: A Direct Mode Error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No FIFO Error event on stream x
1: A FIFO Error event occurred on stream x
9.5.2
DMA high interrupt status register (DMA_HISR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
Reserved
15
14
13
Reserved
12
27
26
25
TCIF7
HTIF7
TEIF7
r
r
r
11
10
9
TCIF5
HTIF5
TEIF5
r
r
r
24
23
22
DMEIF7 Reserv FEIF7
ed
r
r
8
7
6
DMEIF5 Reserv FEIF5
ed
r
r
21
20
19
TCIF6
HTIF6
TEIF6
r
r
r
5
4
3
TCIF4
HTIF4
TEIF4
r
r
r
18
17
DMEIF6 Reserv
ed
r
2
1
DMEIF4 Reserv
ed
r
16
FEIF6
r
0
FEIF4
r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
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DMA controller (DMA)
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No Direct mode error on stream x
1: A Direct mode error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x
9.5.3
DMA low interrupt flag clear register (DMA_LIFCR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
Reserved
15
14
13
Reserved
27
26
25
24
23
CTCIF3 CHTIF3 CTEIF3 CDMEIF3
12
w
w
w
w
11
10
9
8
w
w
w
21
20
CTCIF2
CHTIF2
w
w
w
7
CTCIF1 CHTIF1 CTEIF1 CDMEIF1
w
Reserved
22
CFEIF3
Reserved
6
5
4
CFEIF1
CTCIF0
CHTIF0
w
w
w
19
18
CTEIF2 CDMEIF2
w
w
3
2
CTEIF0 CDMEIF0
w
w
17
16
Reserved
1
CFEIF2
w
0
Reserved
CFEIF0
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register
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9.5.4
RM0383
DMA high interrupt flag clear register (DMA_HIFCR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
Reserved
15
14
13
Reserved
27
26
25
24
23
CTCIF7 CHTIF7 CTEIF7 CDMEIF7
12
w
w
w
w
11
10
9
8
w
w
w
21
20
CTCIF6
CHTIF6
w
w
w
w
w
6
5
4
3
2
CFEIF5
CTCIF4
CHTIF4
w
w
w
7
CTCIF5 CHTIF5 CTEIF5 CDMEIF5
w
Reserved
22
CFEIF7
Reserved
19
18
CTEIF6 CDMEIF6
CTEIF4 CDMEIF4
w
w
17
Reserved
1
Reserved
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register
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CFEIF6
w
0
CFEIF4
w
RM0383
DMA controller (DMA)
9.5.5
DMA stream x configuration register (DMA_SxCR) (x = 0..7)
This register is used to configure the concerned stream.
Address offset: 0x10 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
PINCOS
rw
14
13
12
24
23
MBURST [1:0]
22
21
PBURST[1:0]
20
19
18
Reserv
ed
CT
DBM or
reserved
17
16
PL[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw or r
rw
11
10
9
8
7
6
5
4
3
2
1
0
MINC
PINC
CIRC
PFCTRL
TCIE
HTIE
TEIE
DMEIE
EN
rw
rw
rw
rw
rw
rw
rw
rw
rw
MSIZE[1:0]
PSIZE[1:0]
rw
rw
rw
25
CHSEL[3:0]
Reserved
15
26
rw
DIR[1:0]
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:25 CHSEL[2:0]: Channel selection
These bits are set and cleared by software.
000: channel 0 selected
001: channel 1 selected
010: channel 2 selected
011: channel 3 selected
100: channel 4 selected
101: channel 5 selected
110: channel 6 selected
111: channel 7 selected
These bits are protected and can be written only if EN is ‘0’
Bits 24:23 MBURST: Memory burst transfer configuration
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is ‘0’
In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.
Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is ‘0’
In direct mode, these bits are forced to 0x0 by hardware.
Bit 20 Reserved, must be kept at reset value.
Bit 19 CT: Current target (only in double buffer mode)
This bits is set and cleared by hardware. It can also be written by software.
0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer)
1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer)
This bit can be written only if EN is ‘0’ to indicate the target memory area of the first transfer.
Once the stream is enabled, this bit operates as a status flag indicating which memory area
is the current target.
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DMA controller (DMA)
RM0383
Bit 18 DBM: Double buffer mode
This bits is set and cleared by software.
0: No buffer switching at the end of transfer
1: Memory target switched at the end of the DMA transfer
This bit is protected and can be written only if EN is ‘0’.
Bits 17:16 PL[1:0]: Priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
These bits are protected and can be written only if EN is ‘0’.
Bit 15 PINCOS: Peripheral increment offset size
This bit is set and cleared by software
0: The offset size for the peripheral address calculation is linked to the PSIZE
1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).
This bit has no meaning if bit PINC = '0'.
This bit is protected and can be written only if EN = '0'.
This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct
mode is selected or if PBURST are different from “00”.
Bits 14:13 MSIZE[1:0]: Memory data size
These bits are set and cleared by software.
00: byte (8-bit)
01: half-word (16-bit)
10: word (32-bit)
11: reserved
These bits are protected and can be written only if EN is ‘0’.
In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as bit EN
= '1'.
Bits 12:11 PSIZE[1:0]: Peripheral data size
These bits are set and cleared by software.
00: Byte (8-bit)
01: Half-word (16-bit)
10: Word (32-bit)
11: reserved
These bits are protected and can be written only if EN is ‘0’
Bit 10 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory address pointer is fixed
1: Memory address pointer is incremented after each data transfer (increment is done
according to MSIZE)
This bit is protected and can be written only if EN is ‘0’.
Bit 9 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral address pointer is fixed
1: Peripheral address pointer is incremented after each data transfer (increment is done
according to PSIZE)
This bit is protected and can be written only if EN is ‘0’.
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RM0383
DMA controller (DMA)
Bit 8 CIRC: Circular mode
This bit is set and cleared by software and can be cleared by hardware.
0: Circular mode disabled
1: Circular mode enabled
When the peripheral is the flow controller (bit PFCTRL=1) and the stream is enabled (bit
EN=1), then this bit is automatically forced by hardware to 0.
It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is
enabled (bit EN ='1').
Bits 7:6 DIR[1:0]: Data transfer direction
These bits are set and cleared by software.
00: Peripheral-to-memory
01: Memory-to-peripheral
10: Memory-to-memory
11: reserved
These bits are protected and can be written only if EN is ‘0’.
Bit 5 PFCTRL: Peripheral flow controller
This bit is set and cleared by software.
0: The DMA is the flow controller
1: The peripheral is the flow controller
This bit is protected and can be written only if EN is ‘0’.
When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is
automatically forced to 0 by hardware.
Bit 4 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 3 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 2 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 1 DMEIE: Direct mode error interrupt enable
This bit is set and cleared by software.
0: DME interrupt disabled
1: DME interrupt enabled
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DMA controller (DMA)
RM0383
Bit 0 EN: Stream enable / flag stream ready when read low
This bit is set and cleared by software.
0: Stream disabled
1: Stream enabled
This bit may be cleared by hardware:
–
on a DMA end of transfer (stream ready to be configured)
–
if a transfer error occurs on the AHB master buses
–
when the FIFO threshold on memory AHB port is not compatible with the size of the
burst
When this bit is read as 0, the software is allowed to program the Configuration and FIFO
bits registers. It is forbidden to write these registers when the EN bit is read as 1.
Note: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the
stream in DMA_LISR or DMA_HISR register must be cleared.
9.5.6
DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)
Address offset: 0x14 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
NDT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data items to transfer
Number of data items to be transferred (0 up to 65535). This register can be written only
when the stream is disabled. When the stream is enabled, this register is read-only,
indicating the remaining data items to be transmitted. This register decrements after each
DMA transfer.
Once the transfer has completed, this register can either stay at zero (when the stream is in
normal mode) or be reloaded automatically with the previously programmed value in the
following cases:
–
when the stream is configured in Circular mode.
–
when the stream is enabled again by setting EN bit to '1'
If the value of this register is zero, no transaction can be served even if the stream is
enabled.
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RM0383
DMA controller (DMA)
9.5.7
DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)
Address offset: 0x18 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PAR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
PAR[15:0]
rw
Bits 31:0 PAR[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
9.5.8
DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)
Address offset: 0x1C + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
M0A[31:16]
M0A[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 M0A[31:0]: Memory 0 address
Base address of Memory area 0 from/to which the data will be read/written.
These bits are write-protected. They can be written only if:
–
the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
–
the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '1' in the
DMA_SxCR register (in Double buffer mode).
9.5.9
DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)
Address offset: 0x20 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
M1A[31:16]
M1A[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
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DMA controller (DMA)
RM0383
Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode)
Base address of Memory area 1 from/to which the data will be read/written.
This register is used only for the Double buffer mode.
These bits are write-protected. They can be written only if:
–
the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
–
the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '0' in the
DMA_SxCR register.
9.5.10
DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)
Address offset: 0x24 + 0x24 × stream number
Reset value: 0x0000 0021
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
FEIE
Reser
ved
r
Reserved
15
14
13
12
11
Reserved
10
9
8
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 FEIE: FIFO error interrupt enable
This bit is set and cleared by software.
0: FE interrupt disabled
1: FE interrupt enabled
Bit 6 Reserved, must be kept at reset value.
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FS[2:0]
r
DMDIS
r
rw
FTH[1:0]
rw
rw
RM0383
DMA controller (DMA)
Bits 5:3 FS[2:0]: FIFO status
These bits are read-only.
000: 0 < fifo_level < 1/4
001: 1/4 ≤ fifo_level < 1/2
010: 1/2 ≤ fifo_level < 3/4
011: 3/4 ≤ fifo_level < full
100: FIFO is empty
101: FIFO is full
others: no meaning
These bits are not relevant in the direct mode (DMDIS bit is zero).
Bit 2 DMDIS: Direct mode disable
This bit is set and cleared by software. It can be set by hardware.
0: Direct mode enabled
1: Direct mode disabled
This bit is protected and can be written only if EN is ‘0’.
This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in
DMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’ because the direct
mode is not allowed in the memory-to-memory configuration.
Bits 1:0 FTH[1:0]: FIFO threshold selection
These bits are set and cleared by software.
00: 1/4 full FIFO
01: 1/2 full FIFO
10: 3/4 full FIFO
11: full FIFO
These bits are not used in the direct mode when the DMIS value is zero.
These bits are protected and can be written only if EN is ‘1’.
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DMA controller (DMA)
9.5.11
RM0383
DMA register map
Table 36 summarizes the DMA registers.
0
Reserved
0x0030
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
194/836
0
Reserved
FEIF0
Reserved
FEIF4
Reserved
CFEIF0
0
CFEIF4
0
Reserved
TEIF0
DMEIF4
CDMEIF0
CDMEIF4
DMEIF0
TEIF4
HTIF0
HTIF4
CTEIF0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M0A[31:0]
DMA_S0M0AR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S0FCR
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
CIRC
PSIZE[1:0]
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
NDT[15:.]
Reserved
Reset value
0
MSIZE[1:0]
0
PINCOS
0
PL[1:0]
0
PINC
0
MINC
0
DBM
0
DMA_S1NDTR
CT
Reserved
ACK
MBURST[1:]
CHSEL
[2:0]
DMA_S1CR
PBURST[1:0]
0
FS[2:0]
FTH
[1:0]
EN
0
DMEIE
0
DMDIS
0
TEIE
0
HTIE
0
TCIE
0
PFCTRL
0
FEIE
0
Reserved
M1A[31:0]
DMA_S0M1AR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
DMA_S1PAR
Reset value
0
PA[31:0]
Reset value
0x002C
0
0
NDT[15:.]
Reset value
0x0028
CHTIF0
0
0
0
CTEIF4
0
0
0
EN
0
0
DMEIE
0
0
0
TEIE
0
PSIZE[1:0]
MSIZE[1:0]
PINCOS
0
0
CHTIF4
PINC
0
0
HTIE
0
0
TCIE
0
FEIF1
CDMEIF5
0
TCIF0
CTEIF5
0
0
CIRC
CHTIF5
Reserved
TCIF4
0
0
CTCIF0
CDMEIF1
0
0
CTCIF4
CTEIF1
0
0
0
PFCTRL
CHTIF1
0
0
Reserved
CTCIF1
Reserved
FEIF5
0
Reserved
DMEIF5
0
CFEIF1
TEIF5
0
0
Reserved
HTIF5
0
0
0
0
CFEIF5
TCIF5
Reserved
0
0
Reserved
TEIF1
DMEIF1
0
DIR[1:0]
HTIF1
FEIF2
FEIF6
CFEIF2
TCIF1
Reserved
Reserved
Reserved
0
CFEIF6
0
0
Reserved
0
0
CTCIF5
0
0
0
MINC
0
0
0
0
PL[1:0]
TEIF2
DMEIF2
DMEIF6
CDMEIF2
0
CDMEIF6
0
DBM
TEIF6
CTEIF2
0
CTCIF6
HTIF2
HTIF6
CHTIF2
0
CTEIF6
0
CHTIF6
FEIF3
TCIF2
TCIF6
CTCIF2
0
CT
Reserved
FEIF7
0
Reserved
TEIF3
DMEIF3
DMEIF7
HTIF3
0
0
0
DMA_S0PAR
Reset value
0x0024
0
Reset value
Reset value
0x0020
0
DMA_S0NDTR
Reset value
0x001C
0
0
Reserved
DIR[1:0]
0x0018
TCIF3
Reserved
Reset value
0x0014
0
0
Reserved
DMA_S0CR
0
0
PBURST[1:0]
0x0010
0
CHSEL[2:0]
Reset value
0
0
CFEIF3
Reserved
0
0
Reserved
DMA_HIFCR
0
0
CFEIF7
0x000C
0
0
0
Reserved
Reset value
0
0
0
MBURST[1:0]
Reserved
0
CDMEIF3
DMA_LIFCR
0
CDMEIF7
0x0008
TEIF7
Reset value
0
TEIF3
Reserved
0
CTEIF7
DMA_HISR
0
HTIF7
0x0004
0
TCIF7
Reset value
CHTIF3
Reserved
CTCIF3
DMA_LISR
CHTIF7
0x0000
Register
CTCIF7
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 36. DMA register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DocID026448 Rev 1
0
RM0383
DMA controller (DMA)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S1FCR
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
CIRC
PSIZE[1:0]
0
PINC
0
MSIZE[1:0]
0
PINCOS
0
PL[1:0]
0
MINC
0
CT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x006C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
CIRC
PSIZE[1:0]
0
0
0
FTH
[1:0]
1
0
0
0
0
1
0
0
0
0
0
0
0
NDT[15:.]
Reserved
Reset value
MSIZE[1:0]
0
PINCOS
0
PL[1:0]
0
PINC
0
MINC
0
DBM
0
CT
0
ACK
Reserved
PBURST[1:0]
CHSEL[2:0]
MBURST[1:0]
0
FS[2:0]
EN
0
DMEIE
0
DMDIS
0
TEIE
0
DMA_S3NDTR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
DMA_S3PAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M0A[31:0]
DMA_S3M0AR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M1A[31:0]
DMA_S3M1AR
DMA_S3FCR
0
HTIE
0
DMA_S3CR
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reset value
0
0
0
DocID026448 Rev 1
FS[2:0]
1
0
0
DMDIS
0x0068
0
M1A[31:0]
DMA_S2FCR
Reset value
0
FEIE
0x0064
1
M0A[31:0]
DMA_S2M1AR
Reset value
0
Reserved
0x0060
0
PA[31:0]
Reset value
0x005C
0
0
Reset value
0x0058
0
0
NDT[15:.]
DMA_S2M0AR
Reset value
0x0054
0
DMA_S2PAR
Reset value
0x0050
0
Reserved
Reset value
Reset value
0x004C
0
1
FEIE
0x0048
0
FTH
[1:0]
Reserved
0x0044
0
DBM
Reset value
DMA_S2NDTR
ACK
Reserved
PBURST[1:0]
DMA_S2CR
CHSEL
[2:0]
0x0040
0
MBURST[1:0]
Reset value
FS[2:0]
EN
0
TEIE
0
DMEIE
0
HTIE
0
TCIE
0
PFCTRL
0
DMDIS
M1A[31:0]
DMA_S1M1AR
Reset value
0x003C
0
TCIE
0x0038
0
PFCTRL
Reset value
FEIE
M0A[31:0]
Reserved
DMA_S1M0AR
DIR
[1:0]
0x0034
Register
DIR[1:0]
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 36. DMA register map and reset values (continued)
0
FTH
[1:0]
0
1
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DMA controller (DMA)
RM0383
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CIRC
PSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
CIRC
PSIZE[1:0]
0
0
0
FTH
[1:0]
1
0
0
0
0
1
0
0
0
0
0
0
0
NDT[15:.]
Reserved
Reset value
MSIZE[1:0]
0
PINCOS
0
PL[1:0]
0
PINC
0
MINC
0
DBM
0
CT
0
DMA_S6NDTR
ACK
Reserved
PBURST[1:0]
CHSEL[2:0]
DMA_S6CR
MBURST[1:0]
0
FS[2:0]
EN
0
DMEIE
0
DMDIS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
DMA_S6PAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M0A[31:0]
DMA_S6M0AR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M1A[31:0]
DMA_S6M1AR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reset value
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0
TEIE
0
DMA_S5FCR
DMA_S6FCR
0
M1A[31:0]
DMA_S5M1AR
Reset value
1
0
0
0
DocID026448 Rev 1
FS[2:0]
1
0
0
DMDIS
0x00B0
0
M0A[31:0]
DMA_S5M0AR
Reset value
0
FEIE
0x00AC
0
PA[31:0]
DMA_S5PAR
Reset value
0
Reserved
0x00A8
0
1
NDT[15:.]
Reserved
Reset value
MSIZE[1:0]
0
PINCOS
0
PL[1:0]
0
PINC
0
MINC
0
DBM
0
CT
0
ACK
Reserved
PBURST[1:0]
CHSEL[2:0]
MBURST[1:0]
0
FS[2:0]
FTH
[1:0]
EN
0
DMEIE
0
DMDIS
0
TEIE
0
HTIE
0
Reset value
0x00A4
EN
0
Reset value
0x00A0
TEIE
0
HTIE
0x009C
0
TCIE
0
DMA_S5NDTR
Reset value
0
TCIE
0x0098
0
0
Reserved
DMA_S5CR
Reset value
0
FEIE
0x0094
0
PFCTRL
0
DMA_S4FCR
Reset value
0
Reserved
0x0090
0
M1A[31:0]
DMA_S4M1AR
Reset value
0x008C
0
0
Reset value
0x0088
DMEIE
0
HTIE
0
DIR
[1:0]
0
TCIE
0
PFCTRL
0
CIRC
PSIZE[1:0]
0
M0A[31:0]
DMA_S4M0AR
Reset value
0
PA[31:0]
DMA_S4PAR
Reset value
0
NDT[15:.]
Reserved
Reset value
Reset value
0
PINC
0
MSIZE[1:0]
0
PINCOS
0
PL[1:0]
0
MINC
0
CT
0
PFCTRL
0x0084
0
FEIE
0x0080
0
Reserved
0x007C
0
DIR[1:0]
0x0078
0
DIR[1:0]
0x0074
0
DBM
Reset value
DMA_S4NDTR
ACK
Reserved
PBURST[1:0]
DMA_S4CR
MBURST[1:0]
0x0070
Register
CHSEL[2:0]
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 36. DMA register map and reset values (continued)
0
FTH
[1:0]
0
1
RM0383
DMA controller (DMA)
0x00C8
0x00CC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEIE
DMEIE
EN
0
HTIE
0
0
0
0
0
0
0
0
DIR[1:0]
0
CIRC
PSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M1A[31:0]
DMA_S7M1AR
DMA_S7FCR
0
M0A[31:0]
DMA_S7M0AR
Reset value
0
PA[31:0]
DMA_S7PAR
Reset value
0
NDT[15:.]
Reserved
Reset value
Reset value
0
TCIE
0
MSIZE[1:0]
0
PINCOS
0
PL[1:0]
0
PFCTRL
0
PINC
0
MINC
0
CT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reset value
0
FS[2:0]
1
0
0
DMDIS
0x00C4
0
FEIE
0x00C0
0
Reserved
0x00BC
0
DBM
Reset value
DMA_S7NDTR
ACK
Reserved
PBURST[1:0]
DMA_S7CR
MBURST[1:0]
0x00B8
Register
CHSEL[2:0]
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 36. DMA register map and reset values (continued)
0
FTH
[1:0]
0
1
Refer to Table 3 on page 41 for the register boundary addresses.
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10
Interrupts and events
10.1
Nested vectored interrupt controller (NVIC)
10.1.1
NVIC features
The nested vector interrupt controller NVIC includes the following features:
•
52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with
FPU)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
low-latency exception and interrupt handling
•
power management control
•
implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to programming manual PM0214.
10.1.2
SysTick calibration value register
The SysTick calibration value is fixed to 10500, which gives a reference time base of 1 ms
with the SysTick clock set to 10.5 MHz (HCLK/8, with HCLK set to 84 MHz).
10.1.3
Interrupt and exception vectors
See Table 37, for the vector table for the STM32F411xC/E devices.
10.2
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 23 edge detectors for generating
event/interrupt requests. Each input line can be independently configured to select the type
(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line
can also masked independently. A pending register maintains the status line of the interrupt
requests.
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Position
Table 37. Vector table for STM32F411xC/E
Type of
priority
Acronym
Description
Address
-
-
-
Reserved
0x0000 0000
-3
fixed
Reset
Reset
0x0000 0004
DocID026448 Rev 1
RM0383
Interrupts and events
Priority
Position
Table 37. Vector table for STM32F411xC/E (continued)
Type of
priority
Acronym
Description
Address
-2
fixed
NMI
Non maskable interrupt, Clock Security
System
0x0000 0008
-1
fixed
HardFault
All class of fault
0x0000 000C
0
settable
MemManage
Memory management
0x0000 0010
1
settable
BusFault
Pre-fetch fault, memory access fault
0x0000 0014
2
settable
UsageFault
Undefined instruction or illegal state
0x0000 0018
-
-
-
Reserved
0x0000 001C 0x0000 002B
3
settable
SVCall
System Service call via SWI instruction
0x0000 002C
4
settable
Debug Monitor
Debug Monitor
0x0000 0030
-
-
Reserved
0x0000 0034
5
settable
PendSV
Pendable request for system service
0x0000 0038
6
settable
Systick
System tick timer
0x0000 003C
0
7
settable
WWDG
Window Watchdog interrupt
0x0000 0040
1
8
settable
EXTI16 / PVD
EXTI Line 16 interrupt / PVD through EXTI
line detection interrupt
0x0000 0044
2
9
settable
EXTI21 / TAMP_STAMP
EXTI Line 21 interrupt /
Tamper and TimeStamp interrupts through
the EXTI line
0x0000 0048
3
10
settable
EXTI22 / RTC_WKUP
EXTI Line 22 interrupt /
RTC Wakeup interrupt through the EXTI
line
0x0000 004C
4
11
settable
FLASH
Flash global interrupt
0x0000 0050
5
12
settable
RCC
RCC global interrupt
0x0000 0054
6
13
settable
EXTI0
EXTI Line0 interrupt
0x0000 0058
7
14
settable
EXTI1
EXTI Line1 interrupt
0x0000 005C
8
15
settable
EXTI2
EXTI Line2 interrupt
0x0000 0060
9
16
settable
EXTI3
EXTI Line3 interrupt
0x0000 0064
10
17
settable
EXTI4
EXTI Line4 interrupt
0x0000 0068
11
18
settable
DMA1_Stream0
DMA1 Stream0 global interrupt
0x0000 006C
12
19
settable
DMA1_Stream1
DMA1 Stream1 global interrupt
0x0000 0070
13
20
settable
DMA1_Stream2
DMA1 Stream2 global interrupt
0x0000 0074
14
21
settable
DMA1_Stream3
DMA1 Stream3 global interrupt
0x0000 0078
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Position
Priority
Table 37. Vector table for STM32F411xC/E (continued)
Type of
priority
15
22
settable
DMA1_Stream4
DMA1 Stream4 global interrupt
0x0000 007C
16
23
settable
DMA1_Stream5
DMA1 Stream5 global interrupt
0x0000 0080
17
24
settable
DMA1_Stream6
DMA1 Stream6 global interrupt
0x0000 0084
18
25
settable
ADC
ADC1 global interrupts
0x0000 0088
23
30
settable
EXTI9_5
EXTI Line[9:5] interrupts
0x0000 009C
24
31
settable
TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9 global
interrupt
0x0000 00A0
25
32
settable
TIM1_UP_TIM10
TIM1 Update interrupt and TIM10 global
interrupt
0x0000 00A4
26
33
settable
TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation interrupts
and TIM11 global interrupt
0x0000 00A8
27
34
settable
TIM1_CC
TIM1 Capture Compare interrupt
0x0000 00AC
28
35
settable
TIM2
TIM2 global interrupt
0x0000 00B0
29
36
settable
TIM3
TIM3 global interrupt
0x0000 00B4
30
37
settable
TIM4
TIM4 global interrupt
0x0000 00B8
31
38
settable
Acronym
Description
Address
I2C1_EV
2C1
event interrupt
0x0000 00BC
2C1
I
32
39
settable
I2C1_ER
I
error interrupt
0x0000 00C0
33
40
settable
I2C2_EV
I2C2 event interrupt
0x0000 00C4
I2C2
0x0000 00C8
34
41
settable
I2C2_ER
35
42
settable
SPI1
SPI1 global interrupt
0x0000 00CC
36
43
settable
SPI2
SPI2 global interrupt
0x0000 00D0
37
44
settable
USART1
USART1 global interrupt
0x0000 00D4
38
45
settable
USART2
USART2 global interrupt
0x0000 00D8
40
47
settable
EXTI15_10
EXTI Line[15:10] interrupts
0x0000 00E0
41
48
settable
EXTI17 / RTC_Alarm
EXTI Line 17 interrupt / RTC Alarms (A and
B) through EXTI line interrupt
0x0000 00E4
42
49
settable
EXTI18 / OTG_FS
WKUP
EXTI Line 18 interrupt / USB On-The-Go
FS Wakeup through EXTI line interrupt
0x0000 00E8
47
54
settable
DMA1_Stream7
DMA1 Stream7 global interrupt
0x0000 00FC
49
56
settable
SDIO
SDIO global interrupt
0x0000 0104
50
57
settable
TIM5
TIM5 global interrupt
0x0000 0108
51
58
settable
SPI3
SPI3 global interrupt
0x0000 010C
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error interrupt
RM0383
Interrupts and events
Position
Priority
Table 37. Vector table for STM32F411xC/E (continued)
Type of
priority
56
63
settable
DMA2_Stream0
DMA2 Stream0 global interrupt
0x0000 0120
57
64
settable
DMA2_Stream1
DMA2 Stream1 global interrupt
0x0000 0124
58
65
settable
DMA2_Stream2
DMA2 Stream2 global interrupt
0x0000 0128
59
66
settable
DMA2_Stream3
DMA2 Stream3 global interrupt
0x0000 012C
60
67
settable
DMA2_Stream4
DMA2 Stream4 global interrupt
0x0000 0130
67
74
settable
OTG_FS
USB On The Go FS global interrupt
0x0000 014C
68
75
settable
DMA2_Stream5
DMA2 Stream5 global interrupt
0x0000 0150
69
76
settable
DMA2_Stream6
DMA2 Stream6 global interrupt
0x0000 0154
70
77
settable
DMA2_Stream7
DMA2 Stream7 global interrupt
0x0000 0158
71
78
settable
USART6
USART6 global interrupt
0x0000 015C
Acronym
Description
Address
2C3
72
79
settable
I2C3_EV
I
event interrupt
0x0000 0160
73
80
settable
I2C3_ER
I2C3 error interrupt
0x0000 0164
81
88
Settable
FPU
FPU global interrupt
0x0000 0184
84
91
settable
SPI4
SPI 4 global interrupt
0x0000 0190
85
92
settable
SPI5
SPI 5 global interrupt
0x0000 0194
10.2.1
EXTI main features
The main features of the EXTI controller are the following:
•
independent trigger and mask on each interrupt/event line
•
dedicated status bit for each interrupt line
•
generation of up to 23 software event/interrupt requests
•
detection of external signals with a pulse width lower than the APB2 clock period. Refer
to the electrical characteristics section of the STM32F4xx datasheets for details on this
parameter.
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10.2.2
RM0383
EXTI block diagram
Figure 29 shows the block diagram.
Figure 29. External interrupt/event controller block diagram
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10.2.3
Wakeup event management
The STM32F4xx are able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
•
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex®-M4 with FPU System Control register. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
•
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
To use an external line as a wakeup event, refer to Section 10.2.4: Functional description.
10.2.4
Functional description
To generate the interrupt, the interrupt line should be configured and enabled. This is done
by programming the two trigger registers with the desired edge detection and by enabling
the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is
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Interrupts and events
generated. The pending bit corresponding to the interrupt line is also set. This request is
reset by writing a ‘1’ in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
An interrupt/event request can also be generated by software by writing a ‘1’ in the software
interrupt/event register.
Hardware interrupt selection
To configure the 23 lines as interrupt sources, use the following procedure:
•
Configure the mask bits of the 23 interrupt lines (EXTI_IMR)
•
Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
•
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
external interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines
can be correctly acknowledged.
Hardware event selection
To configure the 23 lines as event sources, use the following procedure:
•
Configure the mask bits of the 23 event lines (EXTI_EMR)
•
Configure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)
Software interrupt/event selection
The 23 lines can be configured as software interrupt/event lines. The following is the
procedure to generate a software interrupt.
•
Configure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)
•
Set the required bit in the software interrupt register (EXTI_SWIER)
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10.2.5
RM0383
External interrupt/event line mapping
Up to 81 GPIOs (STM32F411xC/E) are connected to the 16 external interrupt/event lines in
the following manner:
Figure 30. External interrupt/event GPIO mapping
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The five other EXTI lines are connected as follows:
204/836
•
EXTI line 16 is connected to the PVD output
•
EXTI line 17 is connected to the RTC Alarm event
•
EXTI line 18 is connected to the USB OTG FS Wakeup event
•
EXTI line 21 is connected to the RTC Tamper and TimeStamp events
•
EXTI line 22 is connected to the RTC Wakeup event
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RM0383
Interrupts and events
10.3
EXTI registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
10.3.1
Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
Reserved
22
21
MR22
MR21
rw
rw
20
19
Reserved
18
17
16
MR18
MR17
MR16
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
20
19
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
10.3.2
Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
Reserved
22
21
MR22
MR21
rw
rw
Reserved
18
17
16
MR18
MR17
MR16
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
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10.3.3
RM0383
Rising trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
Reserved
22
21
TR22
TR21
rw
rw
20
19
Reserved
18
17
16
TR18
TR17
TR16
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TR15
TR14
TR13
TR12
TR11
TR10
TR9
TR8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Note:
The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register,
the pending bit is be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
10.3.4
Falling trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
Reserved
22
21
TR22
TR21
rw
rw
20
19
Reserved
18
17
16
TR18
TR17
TR16
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TR15
TR14
TR13
TR12
TR11
TR10
TR9
TR8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Note:
The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register,
the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
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Interrupts and events
10.3.5
Software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
Reserved
15
14
13
12
11
10
9
8
SWIER SWIER SWIER SWIER SWIER SWIER SWIER
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
22
21
SWIER SWIER
22
21
rw
rw
rw
rw
6
5
7
20
19
Reserved
4
3
18
17
16
SWIER SWIER SWIER
18
17
16
rw
rw
rw
2
1
0
SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 SWIERx: Software Interrupt on line x
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is
set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
10.3.6
Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined
31
30
29
28
27
26
25
24
23
Reserved
22
21
PR22
PR21
rc_w1
rc_w1
20
19
Reserved
18
17
16
PR18
PR17
PR16
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PR15
PR14
PR13
PR12
PR11
PR10
PR9
PR8
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to ‘1’.
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10.3.7
RM0383
EXTI register map
Table 38 gives the EXTI register map and the reset values.
Offset
0x00
Register
EXTI_IMR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 38. External interrupt/event controller register map and reset values
Reserved
Reset value
0x04
EXTI_EMR
Reserved
Reset value
0x08
EXTI_RTSR
Reserved
Reset value
0x0C
EXTI_FTSR
Reserved
Reset value
0x10
EXTI_SWIER
Reserved
Reset value
0x14
EXTI_PR
Reset value
Reserved
MR
[22:21] Reser
ved
0 0
0
MR
[22:21] Reser
ved
0 0
0
TR
[22:21] Reser
ved
0 0
0
TR
[22:21] Reser
ved
0 0
0
SWIER
[22:21] Reser
ved
0 0
0
PR
[22:21] Reser
ved
0 0
0
MR[18:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MR[18:0]
0
0
0
0
0
0
0
0
0
0
TR[18:0]
0
0
0
0
0
0
0
0
0
0
TR[18:0]
0
0
0
0
0
0
0
0
0
0
SWIER[18:0]
0
0
0
0
0
0
0
0
0
0
PR[18:0]
0
0
0
0
0
0
0
0
Refer to Table 3 on page 41 for the register boundary addresses.
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0
RM0383
11
Analog-to-digital converter (ADC)
Analog-to-digital converter (ADC)
ADC2 and ADC3 are not available in STM32F411xC/E.
11.1
ADC introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19
multiplexed channels allowing it to measure signals from 16 external sources, two internal
sources, and the VBAT channel. The A/D conversion of the channels can be performed in
single, continuous, scan or discontinuous mode. The result of the ADC is stored into a leftor right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
beyond the user-defined, higher or lower thresholds.
11.2
ADC main features
•
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
•
Interrupt generation at the end of conversion, end of injected conversion, and in case of
analog watchdog or overrun events
•
Single and continuous conversion modes
•
Scan mode for automatic conversion of channel 0 to channel ‘n’
•
Data alignment with in-built data coherency
•
Channel-wise programmable sampling time
•
External trigger option with configurable polarity for both regular and injected
conversions
•
Discontinuous mode
•
ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower
speed
•
ADC input range: VREF– ≤VIN ≤VREF+
•
DMA request generation during regular channel conversion
Figure 31 shows the block diagram of the ADC.
Note:
VREF–, if available (depending on package), must be tied to VSSA.
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Analog-to-digital converter (ADC)
11.3
RM0383
ADC functional description
Figure 31 shows a single ADC block diagram and Table 39 gives the ADC pin description.
Figure 31. Single ADC block diagram
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-36
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Analog-to-digital converter (ADC)
Table 39. ADC pins
Name
11.3.1
Signal type
Remarks
VREF+
Input, analog reference
positive
The higher/positive reference voltage for the ADC,
1.8 V ≤VREF+ ≤VDDA
VDDA
Input, analog supply
Analog power supply equal to VDD and
2.4 V ≤VDDA ≤VDD (3.6 V) for full speed
1.8 V ≤VDDA ≤VDD (3.6 V) for reduced speed
VREF–
Input, analog reference
negative
The lower/negative reference voltage for the ADC,
VREF– = VSSA
VSSA
Input, analog supply
ground
Ground for analog power supply equal to VSS
ADCx_IN[15:0]
Analog input signals
16 analog input channels
ADC on-off control
The ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON
bit is set for the first time, it wakes up the ADC from the Power-down mode.
Conversion starts when either the SWSTART or the JSWSTART bit is set.
You can stop conversion and put the ADC in power down mode by clearing the ADON bit. In
this mode the ADC consumes almost no power (only a few µA).
11.3.2
ADC clock
The ADC features two clock schemes:
•
Clock for the analog circuitry: ADCCLK
This clock is generated from the APB2 clock divided by a programmable prescaler that
allows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the
maximum value of ADCCLK.
•
Clock for the digital interface (used for registers read/write access)
This clock is equal to the APB2 clock. The digital interface clock can be
enabled/disabled individually for each ADC through the RCC APB2 peripheral clock
enable register (RCC_APB2ENR).
11.3.3
Channel selection
There are 16 multiplexed channels. It is possible to organize the conversions in two groups:
regular and injected. A group consists of a sequence of conversions that can be done on
any channel and in any order. For instance, it is possible to implement the conversion
sequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0,
ADC_IN2, ADC_IN2, ADC_IN15.
•
A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADC_SQRx registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADC_SQR1 register.
•
An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
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RM0383
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current
conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen
group.
Temperature sensor, VREFINT and VBAT internal channels
•
The temperature sensor is internally connected to ADC1_IN18 channel which is shared
with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a
time. When the temperature sensor and VBAT conversion are set simultaneously, only
the VBAT conversion is performed.
The internal reference voltage VREFINT is connected to ADC1_IN17.
The VBAT channel is connected to channel ADC1_IN18. It can also be converted as an
injected or regular channel.
Note:
The temperature sensor, VREFINT and the VBAT channel are available only on the master
ADC1 peripheral.
11.3.4
Single conversion mode
In Single conversion mode the ADC does one conversion. This mode is started with the
CONT bit at 0 by either:
•
setting the SWSTART bit in the ADC_CR2 register (for a regular channel only)
•
setting the JSWSTART bit (for an injected channel)
•
external trigger (for a regular or injected channel)
Once the conversion of the selected channel is complete:
•
•
If a regular channel was converted:
–
The converted data are stored into the 16-bit ADC_DR register
–
The EOC (end of conversion) flag is set
–
An interrupt is generated if the EOCIE bit is set
If an injected channel was converted:
–
The converted data are stored into the 16-bit ADC_JDR1 register
–
The JEOC (end of conversion injected) flag is set
–
An interrupt is generated if the JEOCIE bit is set
Then the ADC stops.
11.3.5
Continuous conversion mode
In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one.
This mode is started with the CONT bit at 1 either by external trigger or by setting the
SWSTRT bit in the ADC_CR2 register (for regular channels only).
After each conversion:
•
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If a regular group of channels was converted:
–
The last converted data are stored into the 16-bit ADC_DR register
–
The EOC (end of conversion) flag is set
–
An interrupt is generated if the EOCIE bit is set
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RM0383
Analog-to-digital converter (ADC)
Note:
Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection section).
11.3.6
Timing diagram
As shown in Figure 32, the ADC needs a stabilization time of tSTAB before it starts
converting accurately. After the start of the ADC conversion and after 15 clock cycles, the
EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
Figure 32. Timing diagram
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11.3.7
Analog watchdog
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 40 shows how the ADC_CR1 register should be configured to enable the analog
watchdog on one or more channels.
Figure 33. Analog watchdog’s guarded area
!NALOGVOLTAGE
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AI
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RM0383
Table 40. Analog watchdog channel selection
Channels guarded by the analog
watchdog
ADC_CR1 register control bits (x = don’t care)
AWDSGL bit
AWDEN bit
JAWDEN bit
None
x
0
0
All injected channels
0
0
1
All regular channels
0
1
0
All regular and injected channels
0
1
1
(1)
injected channel
1
0
1
(1)
regular channel
1
1
0
1
1
1
Single
Single
Single (1) regular or injected channel
1. Selected by the AWDCH[4:0] bits
11.3.8
Scan mode
This mode is used to scan a group of analog channels.
The Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
has been set, the ADC scans all the channels selected in the ADC_SQRx registers (for
regular channels) or in the ADC_JSQR register (for injected channels). A single conversion
is performed for each channel of the group. After each end of conversion, the next channel
in the group is converted automatically. If the CONT bit is set, regular channel conversion
does not stop at the last selected channel in the group but continues again from the first
selected channel.
If the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data
converted from the regular group of channels (stored in the ADC_DR register) to SRAM
after each regular channel conversion.
The EOC bit is set in the ADC_SR register:
•
At the end of each regular group sequence if the EOCS bit is cleared to 0
•
At the end of each regular channel conversion if the EOCS bit is set to 1
The data converted from an injected channel are always stored into the ADC_JDRx
registers.
11.3.9
Injected channel management
Triggered injection
To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.
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1.
Start the conversion of a group of regular channels either by external trigger or by
setting the SWSTART bit in the ADC_CR2 register.
2.
If an external injected trigger occurs or if the JSWSTART bit is set during the
conversion of a regular group of channels, the current conversion is reset and the
injected channel sequence switches to Scan-once mode.
3.
Then, the regular conversion of the regular group of channels is resumed from the last
interrupted regular conversion.
If a regular event occurs during an injected conversion, the injected conversion is not
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RM0383
Analog-to-digital converter (ADC)
interrupted but the regular sequence is executed at the end of the injected sequence.
Figure 34 shows the corresponding timing diagram.
Note:
When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 30 ADC clock
cycles (that is two conversions with a sampling time of 3 clock periods), the minimum
interval between triggers must be 31 ADC clock cycles.
Auto-injection
If the JAUTO bit is set, then the channels in the injected group are automatically converted
after the regular group of channels. This can be used to convert a sequence of up to 20
conversions programmed in the ADC_SQRx and ADC_JSQR registers.
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
Note:
It is not possible to use both the auto-injected and discontinuous modes simultaneously.
Figure 34. Injected conversion latency
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1. The maximum latency value can be found in the electrical characteristics of the STM32F411xC/E
datasheets.
11.3.10
Discontinuous mode
Regular group
This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to
convert a short sequence of n conversions (n ≤8) that is part of the sequence of conversions
selected in the ADC_SQRx registers. The value of n is specified by writing to the
DISCNUM[2:0] bits in the ADC_CR1 register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.
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Example:
Note:
•
n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10
•
1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each
conversion.
•
2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each
conversion
•
3rd trigger: sequence converted 9, 10.An EOC event is generated at each conversion
•
4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion
When a regular group is converted in discontinuous mode, no rollover occurs.
When all subgroups are converted, the next trigger starts the conversion of the first
subgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the
1st subgroup.
Injected group
This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to
convert the sequence selected in the ADC_JSQR register, channel by channel, after an
external trigger event.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
n = 1, channels to be converted = 1, 2, 3
1st trigger: channel 1 converted
2nd trigger: channel 2 converted
3rd trigger: channel 3 converted and JEOC event generated
4th trigger: channel 1
Note:
When all injected channels are converted, the next trigger starts the conversion of the first
injected channel. In the example above, the 4th trigger reconverts the 1st injected channel
1.
It is not possible to use both the auto-injected and discontinuous modes simultaneously.
Discontinuous mode must not be set for regular and injected groups at the same time.
Discontinuous mode must be enabled only for the conversion of one group.
11.4
Data alignment
The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 35 and Figure 36.
The converted data value from the injected group of channels is decreased by the userdefined offset written in the ADC_JOFRx registers so the result can be a negative value.
The SEXT bit represents the extended sign value.
For channels in a regular group, no offset is subtracted so only twelve bits are significant.
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Analog-to-digital converter (ADC)
Figure 35. Right alignment of 12-bit data
)NJECTEDGROUP
3%84 3%84 3%84 3%84
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
2EGULARGROUP
AI
Figure 36. Left alignment of 12-bit data
)NJECTEDGROUP
3%84 $
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
2EGULARGROUP
$
$
$
$
AI
Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in
Figure 37.
Figure 37. Left alignment of 6-bit data
)NJECTEDGROUP
3%84 3%84 3%84
3%84 3%84 3%84 3%84 3%84 3%84
$
$
$
$
$
$
$
$
$
2EGULARGROUP
$
$
$
AI
11.5
Channel-wise programmable sampling time
The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12 cycles
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
Tconv = 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz
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11.6
RM0383
Conversion on external trigger and trigger polarity
Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the
EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected
conversion) are different from “0b00”, then external events are able to trigger a conversion
with the selected polarity. Table 41 provides the correspondence between the EXTEN[1:0]
and JEXTEN[1:0] values and the trigger polarity.
Table 41. Configuring the trigger polarity
Source
Note:
EXTEN[1:0] / JEXTEN[1:0]
Trigger detection disabled
00
Detection on the rising edge
01
Detection on the falling edge
10
Detection on both the rising and falling edges
11
The polarity of the external trigger can be changed on the fly.
The EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible
events can trigger conversion for the regular and injected groups.
Table 42 gives the possible external trigger for regular conversion.
Table 42. External trigger for regular channels
Source
Type
EXTSEL[3:0]
TIM1_CH1 event
0000
TIM1_CH2 event
0001
TIM1_CH3 event
0010
TIM2_CH2 event
0011
TIM2_CH3 event
0100
TIM2_CH4 event
0101
TIM2_TRGO event
TIM3_CH1 event
0110
Internal signal from on-chip
timers
0111
TIM3_TRGO event
1000
TIM4_CH4 event
1001
TIM5_CH1 event
1010
TIM5_CH2 event
1011
TIM5_CH3 event
1100
Reserved
1101
Reserved
1110
EXTI line11
External pin
1111
Table 43 gives the possible external trigger for injected conversion.
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Table 43. External trigger for injected channels
Source
Connection type
JEXTSEL[3:0]
TIM1_CH4 event
0000
TIM1_TRGO event
0001
TIM2_CH1 event
0010
TIM2_TRGO event
0011
TIM3_CH2 event
0100
TIM3_CH4 event
0101
TIM4_CH1 event
TIM4_CH2 event
0110
Internal signal from on-chip
timers
0111
TIM4_CH3 event
1000
TIM4_TRGO event
1001
TIM5_CH4 event
1010
TIM5_TRGO event
1011
Reserved
1100
Reserved
1101
Reserved
1110
EXTI line15
External pin
1111
Software source trigger events can be generated by setting SWSTART (for regular
conversion) or JSWSTART (for injected conversion) in ADC_CR2.
A regular group conversion can be interrupted by an injected trigger.
Note:
The trigger selection can be changed on the fly. However, when the selection changes,
there is a time frame of 1 APB clock cycle during which the trigger detection is disabled.
This is to avoid spurious detection during transitions.
11.7
Fast conversion mode
It is possible to perform faster conversion by reducing the ADC resolution. The RES bits are
used to select the number of bits available in the data register. The minimum conversion
time for each resolution is then as follows:
•
12 bits: 3 + 12 = 15 ADCCLK cycles
•
10 bits: 3 + 10 = 13 ADCCLK cycles
•
8 bits: 3 + 8 = 11 ADCCLK cycles
•
6 bits: 3 + 6 = 9 ADCCLK cycles
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11.8
Data management
11.8.1
Using the DMA
RM0383
Since converted regular channel values are stored into a unique data register, it is useful to
use DMA for conversion of more than one regular channel. This avoids the loss of the data
already stored in the ADC_DR register.
When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each
conversion of a regular channel, a DMA request is generated. This allows the transfer of the
converted data from the ADC_DR register to the destination location selected by the
software.
Despite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an
interrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and
DMA requests are no longer accepted. In this case, if a DMA request is made, the regular
conversion in progress is aborted and further regular triggers are ignored. It is then
necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to reinitialize both the DMA and the ADC to have the wanted converted channel data transferred
to the right memory location. Only then can the conversion be resumed and the data
transfer, enabled again. Injected channel conversions are not impacted by overrun errors.
When OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have
been transferred, which means that all the data transferred to the RAM can be considered
as valid.
At the end of the last DMA transfer (number of transfers configured in the DMA controller’s
DMA_SxNTR register):
•
No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the
ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is
not cleared by hardware. It must be written to 0, then to 1 to start a new transfer.
•
Requests can continue to be generated if the DDS bit is set to 1. This allows
configuring the DMA in double-buffer circular mode.
To recover the ADC from OVR state when the DMA is used, follow the steps below:
11.8.2
1.
Reinitialize the DMA (adjust destination address and NDTR counter)
2.
Clear the ADC OVR bit in ADC_SR register
3.
Trigger the ADC to start the conversion.
Managing a sequence of conversions without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by the
software. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status
bit to be set at the end of each conversion, and not only at the end of the sequence. When
EOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is
complete, EOC is set and the ADC_DR register can be read. The overrun management is
the same as when the DMA is used.
To recover the ADC from OVR state when the EOCS is set, follow the steps below:
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1.
Clear the ADC OVR bit in ADC_SR register
2.
Trigger the ADC to start the conversion.
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11.8.3
Analog-to-digital converter (ADC)
Conversions without DMA and without overrun detection
It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). For that, the DMA must be disabled
(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this
configuration, overrun detection is disabled.
11.9
Temperature sensor
The temperature sensor can be used to measure the ambient temperature (TA) of the
device.
Figure 38 shows the block diagram of the temperature sensor.
When not in use, the sensor can be put in power down mode.
The TSVREFE bit must be set to enable the conversion of both internal channels: the
ADC1_IN16 or ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT).
Main features
•
Supported temperature range: –40 to 125 °C
•
Precision: ±1.5 °C
Figure 38. Temperature sensor and VREFINT channel block diagram
4362%&%CONTROLBIT
4EMPERATURE
SENSOR
6 3%.3%
!$#?).
!$#?).
CONVERTEDDATA
!$# )NTERNAL
POWERBLOCK
62%&).4
!DDRESSDATABUS
Note:
!$#?).
-36
1. VSENSE is input to ADC1_IN18
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RM0383
Reading the temperature
To use the sensor:
3.
Select ADC1_IN16 or ADC1_IN18 input channel.
4.
Select a sampling time greater than the minimum sampling time specified in the
datasheet.
5.
Set the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor
from power down mode
6.
Start the ADC conversion by setting the SWSTART bit (or by external trigger)
7.
Read the resulting VSENSE data in the ADC data register
8.
Calculate the temperature using the following formula:
Temperature (in °C) = {(VSENSE – V25) / Avg_Slope} + 25
Where:
–
V25 = VSENSE value for 25° C
–
Avg_Slope = average slope of the temperature vs. VSENSE curve (given in mV/°C
or µV/°C)
Refer to the datasheet’s electrical characteristics section for the actual values of V25
and Avg_Slope.
Note:
The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADON and TSVREFE bits should be set at the same time.
The temperature sensor output voltage changes linearly with temperature. The offset of this
linear function depends on each chip due to process variation (up to 45 °C from one chip to
another).
The internal temperature sensor is more suited for applications that detect temperature
variations instead of absolute temperatures. If accurate temperature reading is required, an
external temperature sensor should be used.
11.10
Battery charge monitoring
The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the
VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the
VBAT pin is internally connected to a bridge divider.
When the VBATE is set, the bridge is automatically enabled to connect:
•
VBAT/4 to the ADC1_IN18 input channel
Note:
The VBAT and temperature sensor are connected to the same ADC internal channel
(ADC1_IN18). Only one conversion, either temperature sensor or VBAT, must be selected
at a time. When both conversion are enabled simultaneously, only the VBAT conversion is
performed.
11.11
ADC interrupts
An interrupt can be produced on the end of conversion for regular and injected groups,
when the analog watchdog status bit is set and when the overrun status bit is set. Separate
interrupt enable bits are available for flexibility.
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Analog-to-digital converter (ADC)
Two other flags are present in the ADC_SR register, but there is no interrupt associated with
them:
•
JSTRT (Start of conversion for channels of an injected group)
•
STRT (Start of conversion for channels of a regular group)
Table 44. ADC interrupts
Interrupt event
Event flag
Enable control bit
End of conversion of a regular group
EOC
EOCIE
End of conversion of an injected group
JEOC
JEOCIE
Analog watchdog status bit is set
AWD
AWDIE
Overrun
OVR
OVRIE
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11.12
RM0383
ADC registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers must be written at word level (32 bits). Read accesses can be done
by bytes (8 bits), half-words (16 bits) or words (32 bits).
11.12.1
ADC status register (ADC_SR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
Reserved
5
4
3
2
1
0
OVR
STRT
JSTRT
JEOC
EOC
AWD
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 OVR: Overrun
This bit is set by hardware when data are lost . It is cleared by software. Overrun detection is
enabled only when DMA = 1 or EOCS = 1.
0: No overrun occurred
1: Overrun has occurred
Bit 4 STRT: Regular channel start flag
This bit is set by hardware when regular channel conversion starts. It is cleared by software.
0: No regular channel conversion started
1: Regular channel conversion has started
Bit 3 JSTRT: Injected channel start flag
This bit is set by hardware when injected group conversion starts. It is cleared by software.
0: No injected group conversion started
1: Injected group conversion has started
Bit 2 JEOC: Injected channel end of conversion
This bit is set by hardware at the end of the conversion of all injected channels in the group.
It is cleared by software.
0: Conversion is not complete
1: Conversion complete
Bit 1 EOC: Regular channel end of conversion
This bit is set by hardware at the end of the conversion of a regular group of channels. It is
cleared by software or by reading the ADC_DR register.
0: Conversion not complete (EOCS=0), or sequence of conversions not complete (EOCS=1)
1: Conversion complete (EOCS=0), or sequence of conversions complete (EOCS=1)
Bit 0 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in
the ADC_LTR and ADC_HTR registers. It is cleared by software.
0: No analog watchdog event occurred
1: Analog watchdog event occurred
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11.12.2
ADC control register 1 (ADC_CR1)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
Reserved
15
14
13
DISCNUM[2:0]
rw
rw
rw
26
25
OVRIE
24
RES
23
22
21
20
AWDEN JAWDEN
rw
rw
rw
rw
rw
19
18
17
16
1
0
rw
rw
Reserved
12
11
10
9
8
7
6
5
JDISCE
N
DISC
EN
JAUTO
AWDSG
L
SCAN
JEOCIE
AWDIE
EOCIE
rw
rw
rw
rw
rw
rw
rw
rw
4
3
2
AWDCH[4:0]
rw
rw
rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the Overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Bits 25:24 RES[1:0]: Resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit (15 ADCCLK cycles)
01: 10-bit (13 ADCCLK cycles)
10: 8-bit (11 ADCCLK cycles)
11: 6-bit (9 ADCCLK cycles)
Bit 23 AWDEN: Analog watchdog enable on regular channels
This bit is set and cleared by software.
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
This bit is set and cleared by software.
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
Bits 21:16 Reserved, must be kept at reset value.
Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted
in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Bit 12 JDISCEN: Discontinuous mode on injected channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected
channels of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
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RM0383
Bit 11 DISCEN: Discontinuous mode on regular channels
This bit is set and cleared by software to enable/disable Discontinuous mode on regular
channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
Bit 10 JAUTO: Automatic injected group conversion
This bit is set and cleared by software to enable/disable automatic injected group conversion
after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
This bit is set and cleared by software to enable/disable the analog watchdog on the channel
identified by the AWDCH[4:0] bits.
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Bit 8 SCAN: Scan mode
This bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the
inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
0: Scan mode disabled
1: Scan mode enabled
Note: An EOC interrupt is generated if the EOCIE bit is set:
–
At the end of each regular group sequence if the EOCS bit is cleared to 0
–
At the end of each regular channel conversion if the EOCS bit is set to 1
Note: A JEOC interrupt is generated only on the end of conversion of the last channel if the
JEOCIE bit is set.
Bit 7 JEOCIE: Interrupt enable for injected channels
This bit is set and cleared by software to enable/disable the end of conversion interrupt for
injected channels.
0: JEOC interrupt disabled
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Bit 6 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Bit 5 EOCIE: Interrupt enable for EOC
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
Note: 00000: ADC analog input Channel0
00001: ADC analog input Channel1
...
01111: ADC analog input Channel15
10000: ADC analog input Channel16
Other values reserved
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11.12.3
ADC control register 2 (ADC_CR2)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
SWST
reserved ART
15
28
27
EXTEN
26
25
24
22
JSWST
ART
reserved
EXTSEL[3:0]
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
ALIGN
EOCS
DDS
DMA
rw
rw
rw
rw
reserved
23
7
21
20
19
JEXTEN
18
17
16
JEXTSEL[3:0]
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
CONT
ADON
rw
rw
Reserved
Bit 31 Reserved, must be kept at reset value.
Bit 30 SWSTART: Start conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon as the
conversion starts.
0: Reset state
1: Starts conversion of regular channels
Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
Bits 29:28 EXTEN: External trigger enable for regular channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of a regular group.
00: Trigger detection disabled
01: Trigger detection on the rising edge
10: Trigger detection on the falling edge
11: Trigger detection on both the rising and falling edges
Bits 27:24 EXTSEL[3:0]: External event select for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
0000: Timer 1 CC1 event
0001: Timer 1 CC2 event
0010: Timer 1 CC3 event
0011: Timer 2 CC2 event
0100: Timer 2 CC3 event
0101: Timer 2 CC4 event
0110: Timer 2 TRGO event
0111: Timer 3 CC1 event
1000: Timer 3 TRGO event
1001: Timer 4 CC4 event
1010: Timer 5 CC1 event
1011: Timer 5 CC2 event
1100: Timer 5 CC3 event
1101: Reserved
1110: Reserved
1111: EXTI line11
Bit 23 Reserved, must be kept at reset value.
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RM0383
Bit 22 JSWSTART: Start conversion of injected channels
This bit is set by software and cleared by hardware as soon as the conversion starts.
0: Reset state
1: Starts conversion of injected channels
Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
Bits 21:20 JEXTEN: External trigger enable for injected channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of an injected group.
00: Trigger detection disabled
01: Trigger detection on the rising edge
10: Trigger detection on the falling edge
11: Trigger detection on both the rising and falling edges
Bits 19:16 JEXTSEL[3:0]: External event select for injected group
These bits select the external event used to trigger the start of conversion of an injected
group.
0000: Timer 1 CC4 event
0001: Timer 1 TRGO event
0010: Timer 2 CC1 event
0011: Timer 2 TRGO event
0100: Timer 3 CC2 event
0101: Timer 3 CC4 event
0110: Timer 4 CC1 event
0111: Timer 4 CC2 event
1000: Timer 4 CC3 event
1001: Timer 4 TRGO event
1010: Timer 5 CC4 event
1011: Timer 5 TRGO event
1100: Reserved
1101: Reserved
1110: Reserved
1111: EXTI line15
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 ALIGN: Data alignment
This bit is set and cleared by software. Refer to Figure 35 and Figure 36.
0: Right alignment
1: Left alignment
Bit 10 EOCS: End of conversion selection
This bit is set and cleared by software.
0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
is enabled only if DMA=1.
1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
Bit 9 DDS: DMA disable selection (for single ADC mode)
This bit is set and cleared by software.
0: No new DMA request is issued after the last transfer (as configured in the DMA controller)
1: DMA requests are issued as long as data are converted and DMA=1
Bit 8 DMA: Direct memory access mode (for single ADC mode)
This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
0: DMA mode disabled
1: DMA mode enabled
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Bits 7:2 Reserved, must be kept at reset value.
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D Converter ON / OFF
This bit is set and cleared by software.
Note: 0: Disable ADC conversion and go to power down mode
1: Enable ADC
11.12.4
ADC sample time register 1 (ADC_SMPR1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
14
SMP15_0
13
12
11
SMP14[2:0]
rw
rw
rw
24
23
SMP18[2:0]
Reserved
15
25
rw
21
20
SMP17[2:0]
19
18
SMP16[2:0]
17
16
SMP15[2:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
10
9
8
7
6
5
4
3
2
1
0
SMP13[2:0]
rw
22
rw
SMP12[2:0]
rw
rw
rw
SMP11[2:0]
rw
rw
rw
SMP10[2:0]
rw
rw
rw
rw
Bits 31: 27 Reserved, must be kept at reset value.
Bits 26:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
11.12.5
ADC sample time register 2 (ADC_SMPR2)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
Reserved
15
14
SMP
5_0
rw
29
28
27
25
24
23
SMP8[2:0]
22
21
20
SMP7[2:0]
19
18
SMP6[2:0]
17
16
SMP5[2:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SMP4[2:0]
rw
26
SMP9[2:0]
rw
SMP3[2:0]
rw
rw
rw
SMP2[2:0]
rw
rw
rw
SMP1[2:0]
rw
DocID026448 Rev 1
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rw
SMP0[2:0]
rw
rw
rw
rw
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Analog-to-digital converter (ADC)
RM0383
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
11.12.6
ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
Address offset: 0x14-0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
JOFFSETx[11:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
11.12.7
ADC watchdog higher threshold register (ADC_HTR)
Address offset: 0x24
Reset value: 0x0000 0FFF
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
Reserved
Reserved
7
HT[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
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RM0383
Analog-to-digital converter (ADC)
11.12.8
ADC watchdog lower threshold register (ADC_LTR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
LT[11:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
11.12.9
ADC regular sequence register 1 (ADC_SQR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
14
13
SQ16_0
rw
12
11
10
9
rw
rw
rw
7
8
SQ15[4:0]
rw
22
21
20
19
18
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
L[3:0]
Reserved
15
23
rw
rw
rw
16
SQ16[4:1]
SQ14[4:0]
rw
17
SQ13[4:0]
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 16th in
the conversion sequence.
Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
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Analog-to-digital converter (ADC)
RM0383
11.12.10 ADC regular sequence register 2 (ADC_SQR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
Reserved
15
29
27
26
25
24
23
SQ12[4:0]
22
21
20
19
SQ11[4:0]
18
17
16
SQ10[4:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
SQ10_0
rw
28
SQ9[4:0]
rw
SQ8[4:0]
rw
SQ7[4:0]
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 12th in
the sequence to be converted.
Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
11.12.11 ADC regular sequence register 3 (ADC_SQR3)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
Reserved
15
29
27
26
25
24
23
SQ6[4:0]
22
21
20
19
SQ5[4:0]
18
17
16
SQ4[4:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
SQ4_0
rw
28
SQ3[4:0]
rw
SQ2[4:0]
rw
SQ1[4:0]
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 6th in the
sequence to be converted.
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
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RM0383
Analog-to-digital converter (ADC)
11.12.12 ADC injected sequence register (ADC_JSQR)
Address offset: 0x38
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
14
13
rw
rw
JSQ4[0]
rw
12
11
10
9
8
7
rw
rw
rw
rw
JSQ3[4:0]
rw
20
19
JL[1:0]
Reserved
15
21
17
16
JSQ4[4:1]
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
JSQ2[4:0]
rw
18
JSQ1[4:0]
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 JL[1:0]: Injected sequence length
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below)
These bits are written by software with the channel number (0..18) assigned as the 4th in the
sequence to be converted.
Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below)
Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below)
Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below)
Note:
When JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels
in the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the
following order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in
starting from JSQ3[4:0], and then JSQ4[4:0].
When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0]
channel.
11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
r
r
r
r
r
r
r
Reserved
15
14
13
12
11
10
9
8
7
JDATA[15:0]
r
r
r
r
r
r
r
r
r
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Analog-to-digital converter (ADC)
RM0383
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data
These bits are read-only. They contain the conversion result from injected channel x. The
data are left -or right-aligned as shown in Figure 35 and Figure 36.
11.12.14 ADC regular data register (ADC_DR)
Address offset: 0x4C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
r
r
r
r
r
r
r
Reserved
15
14
13
12
11
10
9
8
7
DATA[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data
These bits are read-only. They contain the conversion result from the regular
channels. The data are left- or right-aligned as shown in Figure 35 and
Figure 36.
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RM0383
Analog-to-digital converter (ADC)
11.12.15 ADC common control register (ADC_CCR)
Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Reserved
15
14
13
12
11
23
22
21
TSVREFE VBATE
10
9
8
rw
rw
7
6
20
19
18
4
3
16
ADCPRE
Reserved
5
17
2
rw
rw
1
0
Reserved
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and VREFINT enable
This bit is set and cleared by software to enable/disable the temperature sensor and the
VREFINT channel.
0: Temperature sensor and VREFINT channel disabled
1: Temperature sensor and VREFINT channel enabled
Note: VBATE must be disabled when TSVREFE is set. If both bits are set, only the VBAT
conversion is performed.
Bit 22 VBATE: VBAT enable
This bit is set and cleared by software to enable/disable the VBAT channel.
0: VBAT channel disabled
1: VBAT channel enabled
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. .
Note: 00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
Bits 15:0 Reserved, must be kept at reset value.
11.12.16 ADC register map
The following table summarizes the ADC registers.
Table 45. ADC global register map
Offset
Register
0x000 - 0x04C
ADC1
0x050 - 0x0FC
Reserved
0x100 - 0x14C
Reserved
0x118 - 0x1FC
Reserved
0x200 - 0x24C
Reserved
0x250 - 0x2FC
Reserved
0x300 - 0x308
Common registers
DocID026448 Rev 1
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Analog-to-digital converter (ADC)
RM0383
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
Reset value
0x38
0x3C
0x40
0x44
0x48
0x4C
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0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC_JOFR4
ADC_HTR
0
0
0
ADC_LTR
ADC_SQR1
Reset value
ADC_JDR4
Reset value
ADC_DR
Reset value
0
0
0
0
0
0
0
0
0
0
EOC
AWD
EOCIE
JEOC
AWDIE
DMA
SCAN
JAUTO
AWD SGL
DDS
0
JEOCIE
DISCEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AWDCH[4:0]
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
JOFFSET1[11:0]
0
0
0
0
0
0
0
0
0
0
0
JOFFSET2[11:0]
0
0
0
0
0
0
0
0
JOFFSET3[11:0]
0
0
0
0
0
0
0
0
JOFFSET4[11:0]
0
0
0
0
0
0
0
HT[11:0]
1
1
1
1
1
1
1
LT[11:0]
0
L[3:0]
Reserved
Reset value
ADC_JDR3
0
Reserved
Reset value
Reset value
0
Reserved
Reset value
ADC_JDR2
0
Reserved
Reset value
Reset value
Reserved
Reserved
Reset value
ADC_JDR1
0
Reserved
ADC_JOFR3
Reset value
0
Reserved
Reset value
ADC_JSQR
0
0
Sample time bits SMPx_x
ADC_JOFR2
Reset value
0
0
0
0
Sample time bits SMPx_x
Reset value
Reset value
0
JDISCEN
JEXTEN[1:0]
AWDEN
0
JEXTSEL
[3:0]
0
0
ADON
0
ADC_JOFR1
ADC_SQR3
0x34
0
Re
se
rv
ed
0
ADC_SMPR2
ADC_SQR2
0x30
0
0
EOCS
0x10
0
EXTSEL [3:0]
0
ADC_SMPR1
Reserved Reserved
0x0C
0
0
DISC
NUM [2:0]
Reserved
ALIGN
Reset value
0
JAWDEN
Re
se
rv
ed
EXTEN[1:0]
0x08
ADC_CR2
0
SWSTART
Reset value
JSWSTART
Reserved
RES[1:0]
ADC_CR1
OVRIE
0x04
0
CONT
Reserved
Reset value
JSTRT
ADC_SR
OVR
0x00
Register
STRT
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 46. ADC register map and reset values for each ADC
0
0
0
0
0
0
Regular channel sequence SQx_x bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Regular channel sequence SQx_x bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Regular channel sequence SQx_x bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
JL[1:0]
Reserved
0
0
0
0
0
0
0
Injected channel sequence JSQx_x bits
Reserved
Reserved
Reserved
Reserved
Reserved
DocID026448 Rev 1
0
0
0
0
0
0
0
0
0
JDATA[15:0]
0
0
0
0
0
0
0
0
0
0
JDATA[15:0]
0
0
0
0
0
0
0
0
0
0
JDATA[15:0]
0
0
0
0
0
0
0
0
0
0
JDATA[15:0]
0
0
0
0
0
0
0
0
0
0
Regular DATA[15:0]
0
0
0
0
0
0
0
0
0
0
0
RM0383
Analog-to-digital converter (ADC)
Reset value
Reserved
0
0
Reserved
ADCPRE[1:0]
ADC_CCR
VBATE
0x04
Register
TSVREFE
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 47. ADC register map and reset values (common ADC registers)
0
Reserved
0
Refer to Table 3 on page 41 for the register boundary addresses.
DocID026448 Rev 1
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237
Advanced-control timer (TIM1)
12
RM0383
Advanced-control timer (TIM1)
TIM8 is not available in STM32F411xC/E.
12.1
TIM1 introduction
The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1) and general-purpose (TIMx) timers are completely
independent, and do not share any resources. They can be synchronized together as
described in Section 12.3.20.
12.2
TIM1 main features
TIM1 timer features include:
238/836
•
16-bit up, down, up/down auto-reload counter.
•
16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65536.
•
Up to 4 independent channels for:
–
Input Capture
–
Output Compare
–
PWM generation (Edge and Center-aligned Mode)
–
One-pulse mode output
•
Complementary outputs with programmable dead-time
•
Synchronization circuit to control the timer with external signals and to interconnect
several timers together.
•
Repetition counter to update the timer registers only after a given number of cycles of
the counter.
•
Break input to put the timer’s output signals in reset state or in a known state.
DocID026448 Rev 1
RM0383
Advanced-control timer (TIM1)
•
Interrupt/DMA generation on the following events:
–
Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
–
Trigger event (counter start, stop, initialization or count by internal/external trigger)
–
Input capture
–
Output compare
–
Break input
•
Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
•
Trigger input for external clock or cycle-by-cycle current management
Figure 39. Advanced-control timer block diagram
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DocID026448 Rev 1
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Advanced-control timer (TIM1)
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12.3
TIM1 functional description
12.3.1
Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
•
Counter register (TIMx_CNT)
•
Prescaler register (TIMx_PSC)
•
Auto-reload register (TIMx_ARR)
•
Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 40 and Figure 41 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:
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Advanced-control timer (TIM1)
Figure 40. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC
00
01
02
03
Update event (UEV)
Prescaler control register
0
1
Write a new value in TIMx_PSC
Prescaler buffer
0
Prescaler counter
0
1
0
1
0
1
0
1
0
1
Figure 41. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC
00
01
Update event (UEV)
Prescaler control register
0
3
Write a new value in TIMx_PSC
12.3.2
Prescaler buffer
0
Prescaler counter
0
3
0
1
2
3
0
1
2
3
Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
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preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register,
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 42. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 43. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0034
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
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0000
0001
0002
0003
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Advanced-control timer (TIM1)
Figure 44. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0035
0000
0036
0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 45. Counter timing diagram, internal clock divided by N
CK_PSC
Timer clock = CK_CNT
Counter register
1F
00
20
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 46. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
FF
36
Write a new value in TIMx_ARR
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Figure 47. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F0
F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
F5
36
Auto-reload shadow register
F5
36
Write a new value in TIMx_ARR
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register plus one
(TIMx_RCR+1). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
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•
The repetition counter is reloaded with the content of TIMx_RCR register
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one
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Advanced-control timer (TIM1)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 48. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
04 03 02 01 00 36 35 34 33 32 31 30 2F
05
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
Figure 49. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0002
0001 0000
0036
0035
0034
0033
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 50. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0001
0000
0036
0035
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
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Figure 51. Counter timing diagram, internal clock divided by N
CK_PSC
Timer clock = CK_CNT
Counter register
20
1F
00
36
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 52. Counter timing diagram, update event when repetition counter
is not used
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
05
04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
FF
36
Write a new value in TIMx_ARR
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
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The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 53. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
04
03 02 01 00 01 02 03 04 05 06 05 04 03
Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
1. Here, center-aligned mode 1 is used (for more details refer to Section 12.4: TIM1 registers on page 278).
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Figure 54. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0003
0002 0001
0000
0001
0002
0003
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 55. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0034
0035
0036
0035
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
1.
Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 56. Counter timing diagram, internal clock divided by N
CK_PSC
Timer clock = CK_CNT
Counter register
20
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
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01
00
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Advanced-control timer (TIM1)
Figure 57. Counter timing diagram, update event with ARPE=1 (counter underflow)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
06
05 04 03 02 01 00 01 02 03 04 05 06 07
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FD
36
Write a new value in TIMx_ARR
Auto-reload active register
FD
36
Figure 58. Counter timing diagram, Update event with ARPE=1 (counter overflow)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FD
36
Write a new value in TIMx_ARR
Auto-reload active register
12.3.3
FD
36
Repetition counter
Section 12.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
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The repetition counter is decremented:
•
At each counter overflow in upcounting mode,
•
At each counter underflow in downcounting mode,
•
At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xTck, due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 59). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.
In center-aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was started. If the RCR was written before starting the counter, the UEV occurs
on the overflow. If the RCR was written after starting the counter, the UEV occurs on the
underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or
underflow event depending on when RCR was written.
Figure 59. Update rate examples depending on mode and TIMx_RCR register settings
Center-aligned mode
Edge-aligned mode
Upcounting
Downcounting
Counter
TIMx_CNT
TIMx_RCR = 0 UEV
TIMx_RCR = 1 UEV
TIMx_RCR = 2 UEV
TIMx_RCR = 3 UEV
TIMx_RCR = 3
and
re-synchronization
UEV
(by SW)
UEV
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(by SW)
Update Event: Preload registers transferred to active registers and update interrupt generated
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12.3.4
Advanced-control timer (TIM1)
Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin
•
External clock mode2: external trigger input ETR
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Using
one timer as prescaler for another for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 60 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 60. Control circuit in normal mode, internal clock divided by 1
Internal clock
CEN=CNT_EN
UG
CNT_INIT
Counter clock = CK_CNT = CK_PSC
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
Figure 61. TI2 external clock connection example
TIMx_SMCR
TS[2:0]
or
ITRx
TI2
TI2F_Rising
Filter
ICF[3:0]
TIMx_CCMR1
Edge
Detector TI2F_Falling
0
1
0xx
TI2F
TI1F
or
or
encoder
mode
TI1_ED 100
TI1FP1 101
TRGI
external clock
mode 1
CK_PSC
TI2FP2 110
ETRF 111
ETRF
external clock
mode 2
CC2P
TIMx_CCER
CK_INT
internal clock
mode
(internal clock)
ECE SMS[2:0]
TIMx_SMCR
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For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
Note:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
2.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
3.
Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.
4.
Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5.
Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 62. Control circuit in external clock mode 1
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
TIF
Write TIF=0
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Advanced-control timer (TIM1)
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 63 gives an overview of the external trigger input block.
Figure 63. External trigger input block
or
ETR pin
ETR
0
1
ETP
TIMx_SMCR
divider
/1, /2, /4, /8
ETRP
filter
downcounter
fDTS
ETPS[1:0]
ETF[3:0]
TIMx_SMCR
TI2F
TI1F
or
or
encoder
mode
TRGI
external clock
mode 1
CK_PSC
ETRF
external clock
mode 2
CK_INT
internal clock
mode
(internal clock)
TIMx_SMCR
ECE SMS[2:0]
TIMx_SMCR
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3.
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 64. Control circuit in external clock mode 2
fCK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock = CK_CNT = CK_PSC
Counter register
34
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12.3.5
RM0383
Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 65 to Figure 68 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 65. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
to the slave mode controller
TI1
fDTS
filter
downcounter
TI1F
TI1F_Rising
Edge
Detector
TI1F_Falling
ICF[3:0]
CC1P/CC1NP
TIMx_CCMR1
TIMx_CCER
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
0
TI1FP1
1
01
TI2FP1
10
IC1
divider
/1, /2, /4, /8
IC1PS
TRC
11
(from slave mode
controller)
0
CC1S[1:0] ICPS[1:0]
1
TIMx_CCMR1
CC1E
TIMx_CCER
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 66. Capture/compare channel 1 main circuit
APB Bus
read CCR1L
read_in_progress
CC1S[0]
IC1PS
Capture/compare preload register
input
mode
output
mode
Capture/compare shadow register
comparator
capture
CNT>CCR1
Counter
CC1G
TIM1_EGR
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R
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CC1E
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write_in_progress
R
capture_transfer
CC1S[1]
8
low
read CCR1H S
high
8
(if 16-bit)
MCU-peripheral interface
CNT=CCR1
write CCR1L
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
TIM1_CCMR1
(from time
base unit)
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Advanced-control timer (TIM1)
Figure 67. Output stage of capture/compare channel (channel 1 to 3)
ETR
To the master mode
controller
‘0’
OC1_DT
CNT>CCR1
Output mode OC1REF
CNT=CCR1
controller
Dead-time
generator
0
x0
01
1
11
CC1P
Output
enable
circuit
OC1
Output
enable
circuit
OC1N
TIM1_CCER
OC1N_DT
11
0
10
‘0’
0x
1
CC1NE CC1E TIM1_CCER
OC1CE OC1M[2:0]
TIM1_CCMR1
DTG[7:0]
CC1NE CC1E
TIM1_BDTR
TIM1_CCER
CC1NP MOE OSSI OSSR TIM1_BDTR
TIM1_CCER
Figure 68. Output stage of capture/compare channel (channel 4)
ETR
To the master mode
controller
0
1
Output
enable
circuit
OC4
CC4P
CNT > CCR4
Output mode OC4 REF
CNT = CCR4 controller
TIM1_CCER
CC4E TIM1_CCER
OC2M[2:0]
MOE OSSI TIM1_BDTR
TIM1_CCMR2
OIS4 TIM1_CR2
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
12.3.6
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
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The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
•
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
•
Program the input filter duration you need with respect to the signal you connect to the
timer (by programming ICxF bits in the TIMx_CCMRx register if the input is a TIx input).
Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal
clock cycles. We must program a filter duration longer than these 5 clock cycles. We
can validate a transition on TI1 when 8 consecutive samples with the new level have
been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
•
Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP
bits to 0 in the TIMx_CCER register (rising edge in this case).
•
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
•
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
•
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
•
The TIMx_CCR1 register gets the value of the counter on the active transition.
•
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
•
An interrupt is generated depending on the CC1IE bit.
•
A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:
IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.
12.3.7
PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
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•
Two ICx signals are mapped on the same TIx input.
•
These 2 ICx signals are active on edges with opposite polarity.
•
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
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For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
•
Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
•
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).
•
Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
•
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
and CC2NP bits to ‘1’ (active on falling edge).
•
Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
•
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
•
Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
Figure 69. PWM input mode timing
TI1
TIMx_CNT
0004
0000
0001
0002
TIMx_CCR1
0004
TIMx_CCR2
0002
IC1 capture
IC2 capture
reset counter
0003
0004
IC2 capture
pulse width
measurement
0000
IC1 capture
period
measurement
ai15413
12.3.8
Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
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Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.
12.3.9
Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
•
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
•
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
•
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
•
Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse mode).
Procedure:
1.
Select the counter clock (internal, external, prescaler).
2.
Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3.
Set the CCxIE bit if an interrupt request is to be generated.
4.
Select the output mode. For example:
5.
–
Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
–
Write OCxPE = 0 to disable preload register
–
Write CCxP = 0 to select active high polarity
–
Write CCxE = 1 to enable the output
Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 70.
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Figure 70. Output compare mode, toggle on OC1.
Write B201h in the CC1R register
TIM1_CNT
TIM1_CCR1
0039
003A
003B
003A
B200
B201
B201
oc1ref=OC1
Match detected on CCR1
Interrupt generated if enabled
12.3.10
PWM mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤TIMx_CNT or TIMx_CNT ≤TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
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PWM edge-aligned mode
•
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
Section : Upcounting mode on page 241.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 71 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
Figure 71. Edge-aligned PWM waveforms (ARR=8)
0
Counter register
CCRx=4
1
2
3
4
5
6
7
8
0
1
OCXREF
CCxIF
CCRx=8
CCRx>8
CCRx=0
•
OCXREF
CCxIF
OCXREF
‘1’
CCxIF
OCXREF
‘0’
CCxIF
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section :
Downcounting mode on page 244
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Section : Center-aligned mode (up/down counting) on page 246.
Figure 72 shows some center-aligned PWM waveforms in an example where:
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•
TIMx_ARR=8,
•
PWM mode is the PWM mode 1,
•
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
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Figure 72. Center-aligned PWM waveforms (ARR=8)
#OUNTERREGISTER
/#X2%&
##2X
#-3
#-3
#-3
##X)&
/#X2%&
##2X
#-3OR
##X)&
/#X2%&
##2X
gg
#-3
#-3
#-3
##X)&
/#X2%&
##2X
gg
#-3
#-3
#-3
##X)&
/#X2%&
##2X
##X)&
gg
#-3
#-3
#-3
AIB
Hints on using center-aligned mode:
•
When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
•
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
•
–
The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.
–
The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.
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Complementary outputs and dead-time insertion
The advanced-control timers (TIM1) can output two complementary signals and manage the
switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the
devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...)
You can select the polarity of the outputs (main output OCx or complementary OCxN)
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 50: Output control bits for complementary OCx and OCxN channels with break
feature on page 296 for more details. In particular, the dead-time is activated when
switching to the IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the
dead-time generation for all channels. From a reference waveform OCxREF, it generates 2
outputs OCx and OCxN. If OCx and OCxN are active high:
•
The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
•
The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)
Figure 73. Complementary output with dead-time insertion.
OCxREF
OCx
delay
OCxN
delay
Figure 74. Dead-time waveforms with delay greater than the negative pulse.
OCxREF
OCx
delay
OCxN
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Figure 75. Dead-time waveforms with delay greater than the positive pulse.
OCxREF
OCx
OCxN
delay
The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 12.4.18: TIM1 break and dead-time
register (TIMx_BDTR) on page 300 for delay calculation.
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows you to send a specific waveform (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note:
When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.
12.3.12
Using the break function
When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 50: Output control bits for
complementary OCx and OCxN channels with break feature on page 296 for more details.
The break source can be either the break input pin or a clock failure event, generated by the
Clock Security System (CSS), from the Reset Clock Controller. For further information on
the Clock Security System, refer to Section 6.2.7: Clock security system (CSS).
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable
the break function by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
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must insert a delay (dummy instruction) before reading it correctly. This is because you write
the asynchronous signal and read the synchronous signal.
When a break occurs (selected level on the break input):
Note:
•
The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
•
Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
•
When complementary outputs are used:
–
The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
–
If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
–
If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
•
The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if
the BDE bit in the TIMx_DIER register is set.
•
If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for
security and you can connect the break input to an alarm from power drivers, thermal
sensors or any security components.
The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
There are two solutions to generate a break:
•
By using the BRK input which has a programmable polarity and an enable bit BKE in
the TIMx_BDTR register
•
By software through the BG bit of the TIMx_EGR register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows you to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). You can choose from 3
levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to
Section 12.4.18: TIM1 break and dead-time register (TIMx_BDTR) on page 300. The LOCK
bits can be written only once after an MCU reset.
Figure 76 shows an example of behavior of the outputs in response to a break.
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Figure 76. Output behavior in response to a break.
BREAK (MOE
)
OCxREF
OCx
(OCxN not implemented, CCxP=0, OISx=1)
OCx
(OCxN not implemented, CCxP=0, OISx=0)
OCx
(OCxN not implemented, CCxP=1, OISx=1)
OCx
(OCxN not implemented, CCxP=1, OISx=0)
OCx
delay
delay
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)
delay
OCx
delay
delay
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)
delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)
delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)
delay
OCx
OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)
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RM0383
Clearing the OCxREF signal on an external event
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for
current handling. In this case, the ETR must be configured as follow:
1.
The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.
2.
The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3.
The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 77 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.
Figure 77. Clearing TIMx OCxREF
(CCRx)
counter (CNT)
ETRF
OCxREF
(OCxCE=’0’)
OCxREF
(OCxCE=’1’)
ETRF
becomes high
Note:
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ETRF
still high
In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.
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12.3.14
Advanced-control timer (TIM1)
6-step PWM generation
When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus you can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request
(if the COMDE bit is set in the TIMx_DIER register).
Figure 78 describes the behavior of the OCx and OCxN outputs when a COM event occurs,
in 3 different examples of programmed configurations.
Figure 78. 6-step generation, COM example (OSSR=1)
counter (CNT)
(CCRx)
OCxREF
Write COM to 1
COM event
Example 1
CCxE=1
write OCxM to 100
CCxNE=0
OCxM=100 (forced inactive)
CCxE=1
CCxNE=0
OCxM=100
Write CCxNE to 1
and OCxM to 101
CCxE=1
CCxNE=0
OCxM=100 (forced inactive)
CCxE=0
CCxNE=1
OCxM=101
OCx
OCxN
OCx
Example 2
OCxN
write CCxNE to 0
CCxE=1
and OCxM to 100
CCxNE=0
OCxM=100 (forced inactive)
Example 3
CCxE=1
CCxNE=0
OCxM=100
OCx
OCxN
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One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
•
In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
•
In downcounting: CNT > CCRx
Figure 79. Example of one pulse mode.
TI2
OC1REF
Counter
OC1
TIM1_ARR
TIM1_CCR1
0
tDELAY
tPULSE
t
For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
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•
Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
•
TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
•
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
•
TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
•
The tDELAY is defined by the value written in the TIMx_CCR1 register.
•
The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
•
Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
12.3.16
Encoder interface mode
To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the
counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, you can program the input filter as well. CC1NP and CC2NP must
be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 48. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
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configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler,
repetition counter, trigger output features continue to work as normal. Encoder mode and
External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.
Table 48. Counting direction versus encoder signals
Active edge
Level on
opposite
signal (TI1FP1
for TI2,
TI2FP2 for
TI1)
TI1FP1 signal
TI2FP2 signal
Rising
Falling
Rising
Falling
Counting on
TI1 only
High
Down
Up
No Count
No Count
Low
Up
Down
No Count
No Count
Counting on
TI2 only
High
No Count
No Count
Up
Down
Low
No Count
No Count
Down
Up
Counting on
TI1 and TI2
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 80 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
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•
CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
•
CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).
•
CC1P=’0’, CC1NP=’0’, and IC1F = ‘0000’ (TIMx_CCER register, TI1FP1 non-inverted,
TI1FP1=TI1).
•
CC2P=’0’, CC2NP=’0’, and IC2F = ‘0000’ (TIMx_CCER register, TI1FP2 non-inverted,
TI1FP2= TI2).
•
SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges).
•
CEN=’1’ (TIMx_CR1 register, Counter enabled).
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Figure 80. Example of counter operation in encoder interface mode.
forward
jitter
backward
jitter
forward
TI1
TI2
Counter
down
up
up
Figure 81 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=’1’).
Figure 81. Example of encoder interface mode with TI1FP1 polarity inverted.
forward
jitter
backward
jitter
forward
TI1
TI2
Counter
down
up
down
The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a real-time clock.
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12.3.17
RM0383
Timer input XOR function
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture. An example of this feature used to interface Hall sensors is given in
Section 12.3.18 below.
12.3.18
Interfacing with Hall sensors
This is done using the advanced-control timers (TIM1) to generate PWM signals to drive the
motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as “interfacing timer”
in Figure 82. The “interfacing timer” captures the 3 timer input pins (TIMx_CH1, TIMx_CH2,
and TIMx_CH3) connected through a XOR to the TI1 input channel (selected by setting the
TI1S bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,
each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a
time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode,
capture signal is TRC (see Figure 65: Capture/compare channel (example: channel 1 input
stage) on page 254). The captured value, which corresponds to the time elapsed between 2
changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the
configuration of the channels of the advanced-control timer (TIM1) (by triggering a COM
event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the
interfacing timer channel must be programmed so that a positive pulse is generated after a
programmed delay (in output compare or PWM mode). This pulse is sent to the advancedcontrol timer (TIM1) through the TRGO output.
Example: you want to change the PWM configuration of your advanced-control timer TIM1
after a programmed delay each time a change occurs on the Hall inputs connected to one of
the TIMx timers.
•
Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the
TIMx_CR2 register to ‘1’,
•
Program the time base: write the TIMx_ARR to the max value (the counter must be
cleared by the TI1 change. Set the prescaler to get a maximum counter period longer
than the time between 2 changes on the sensors,
•
Program channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to ‘11’. You can also program the digital filter if needed,
•
Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’
and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,
•
Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to ‘101’,
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the
timer is programmed to generate PWM signals, the capture/compare control signals are
preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the
trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are
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Advanced-control timer (TIM1)
written after a COM event for the next step (this can be done in an interrupt subroutine
generated by the rising edge of OC2REF).
Figure 82 describes this example.
Figure 82. Example of hall sensor interface
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12.3.19
RM0383
TIMx and external trigger synchronization
The TIMx timer can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
•
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
rising edges only).
•
Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 83. Control circuit in reset mode
TI1
UG
Counter clock = ck_cnt = ck_psc
Counter register
30 31 32 33 34 35 36 00 01 02 03 00 01 02 03
TIF
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Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
•
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
low level only).
•
Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 84. Control circuit in gated mode
TI1
CNT_EN
Counter clock = ck_cnt = ck_psc
Counter register
30 31 32 33
34
35 36 37 38
TIF
Write TIF=0
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Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
•
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register.
Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and
detect low level only).
•
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 85. Control circuit in trigger mode
TI2
CNT_EN
Counter clock = ck_cnt = ck_psc
Counter register
34
35 36 37 38
TIF
Slave mode: external clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input (in reset mode, gated mode or
trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1.
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Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–
ETF = 0000: no filter
–
ETPS = 00: prescaler disabled
–
ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
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Advanced-control timer (TIM1)
2.
3.
Configure the channel 1 as follows, to detect rising edges on TI:
–
IC1F=0000: no filter.
–
The capture prescaler is not used for triggering and does not need to be
configured.
–
CC1S=01 in TIMx_CCMR1 register to select only the input capture source
–
CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and
detect rising edge only).
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 86. Control circuit in external clock mode 2 + trigger mode
TI1
CEN/CNT_EN
ETR
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
36
TIF
12.3.20
Timer synchronization
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 13.3.15: Timer synchronization on page 336 for details.
12.3.21
Debug mode
When the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBG module. For more details, refer to Section 23.16.2: Debug support
for timers, watchdog and I2C.
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TIM1 registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).
12.4.1
TIM1 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
11
Reserved
10
9
8
CKD[1:0]
rw
7
6
ARPE
rw
rw
5
CMS[1:0]
rw
rw
4
3
2
1
0
DIR
OPM
URS
UDIS
CEN
rw
rw
rw
rw
rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(ETR, TIx),
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
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Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
12.4.2
TIM1 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
15
Res.
14
13
12
11
10
9
8
7
OIS4
OIS3N
OIS3
OIS2N
OIS2
OIS1N
OIS1
TI1S
rw
rw
rw
rw
rw
rw
rw
rw
6
5
4
MMS[2:0]
rw
rw
rw
3
2
CCDS
CCUS
rw
rw
1
Res.
0
CCPC
rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 OIS4: Output Idle state 4 (OC4 output)
refer to OIS1 bit
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
refer to OIS1N bit
Bit 12 OIS3: Output Idle state 3 (OC3 output)
refer to OIS1 bit
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Bit 11 OIS2N: Output Idle state 2 (OC2N output)
refer to OIS1N bit
Bit 10 OIS2: Output Idle state 2 (OC2 output)
refer to OIS1 bit
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enable. The Counter Enable signal is generated by a logic OR between CEN control bit and
the trigger input when configured in gated mode. When the Counter Enable signal is
controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is
selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
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Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when a commutation event (COM) occurs (COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.
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12.4.3
RM0383
TIM1 slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
15
14
ETP
ECE
rw
rw
13
12
11
ETPS[1:0]
rw
rw
10
9
8
ETF[3:0]
rw
rw
7
6
MSM
rw
rw
rw
5
4
TS[2:0]
rw
rw
3
2
Res.
rw
Res.
1
0
SMS[2:0]
rw
rw
rw
Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time,
the external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
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Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS[2:0]: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 49: TIMx Internal trigger connection on page 284 for more details on ITRx meaning
for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
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Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Table 49. TIMx Internal trigger connection
12.4.4
Slave TIM
ITR0 (TS = 000)
ITR1 (TS = 001)
ITR2 (TS = 010)
ITR3 (TS = 011)
TIM1
TIM5
TIM2
TIM3
TIM4
TIM1 DMA/interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
Res.
14
TDE
rw
13
12
11
10
9
COMDE CC4DE CC3DE CC2DE CC1DE
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
UDE
BIE
TIE
COMIE
CC4IE
CC3IE
CC2IE
CC1IE
UIE
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
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Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
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12.4.5
RM0383
TIM1 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
Reserved
13
12
11
10
9
CC4OF CC3OF CC2OF CC1OF
rc_w0
rc_w0
rc_w0
rc_w0
8
7
6
5
4
3
2
1
0
Res.
BIF
TIF
COMIF
CC4IF
CC3IF
CC2IF
CC1IF
UIF
Res.
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected.It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
refer to CC1IF description
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Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow or underflow regarding the repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by a trigger event (refer to Section 12.4.3: TIM1 slave mode
control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
12.4.6
TIM1 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
Reserved
9
8
7
6
5
4
3
2
1
0
BG
TG
COMG
CC4G
CC3G
CC2G
CC1G
UG
w
w
w
w
w
w
w
w
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
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Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G: Capture/Compare 4 generation
refer to CC1G description
Bit 3 CC3G: Capture/Compare 3 generation
refer to CC1G description
Bit 2 CC2G: Capture/Compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
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12.4.7
TIM1 capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15
14
OC2
CE
13
12
OC2M[2:0]
IC2F[3:0]
rw
rw
rw
11
10
OC2
PE
OC2
FE
9
8
CC2S[1:0]
7
6
OC1
CE
rw
rw
4
OC1M[2:0]
IC2PSC[1:0]
rw
5
IC1F[3:0]
rw
rw
rw
rw
rw
3
2
OC1
PE
OC1
FE
1
0
CC1S[1:0]
IC1PSC[1:0]
rw
rw
rw
rw
rw
Output compare mode:
Bit 15 OC2CE: Output Compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
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Bits 6:4 OC1M: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
3: On channels having a complementary output, this bit field is preloaded. If the CCPC
bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from
the preloaded bits only when a COM event is generated.
Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
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Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied
to TI1. The digital filter is made of an event counter in which N events are needed to validate a
transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
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Bits 1:0 CC1S: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
12.4.8
TIM1 capture/compare mode register 2 (TIMx_CCMR2)
Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.
15
14
OC4
CE
13
12
OC4M[2:0]
IC4F[3:0]
rw
rw
rw
11
10
OC4
PE
OC4
FE
9
8
CC4S[1:0]
7
6
OC3
CE.
rw
rw
4
OC3M[2:0]
IC4PSC[1:0]
rw
5
IC3F[3:0]
rw
rw
rw
rw
rw
3
2
OC3
PE
OC3
FE
1
0
CC3S[1:0]
IC3PSC[1:0]
rw
rw
rw
rw
rw
Output compare mode
Bit 15 OC4CE: Output compare 4 clear enable
Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).
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Input capture mode
Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).
12.4.9
TIM1 capture/compare enable register (TIMx_CCER)
Address offset: 0x20
Reset value: 0x0000
15
14
Reserved
13
12
CC4P
CC4E
rw
rw
11
10
CC3NP CC3NE
rw
rw
9
8
CC3P
CC3E
rw
rw
7
6
CC2NP CC2NE
rw
rw
5
4
CC2P
CC2E
rw
rw
3
2
CC1NP CC1NE
rw
rw
1
0
CC1P
CC1E
rw
rw
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output polarity
refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable
refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 complementary output polarity
refer to CC1NP description
Bit 10 CC3NE: Capture/Compare 3 complementary output enable
refer to CC1NE description
Bit 9 CC3P: Capture/Compare 3 output polarity
refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable
refer to CC1E description
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RM0383
Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
refer to CC1NP description
Bit 6 CC2NE: Capture/Compare 2 complementary output enable
refer to CC1NE description
Bit 5 CC2P: Capture/Compare 2 output polarity
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
CC1 channel configured as output:
0: OC1N active high.
1: OC1N active low.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
to CC1P description.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
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RM0383
Advanced-control timer (TIM1)
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture
operations.
00: non-inverted/rising edge
The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
01: inverted/falling edge
The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external
clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder
mode).
10: reserved, do not use this configuration.
11: non-inverted/both edges
The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations
in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 0 CC1E: Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1E active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
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RM0383
Table 50. Output control bits for complementary OCx and OCxN channels with
break feature
Output states(1)
Control bits
MOE
bit
1
OSSI
bit
OSSR
bit
CCxE
bit
0
0
0
Output Disabled (not driven by Output Disabled (not driven by the
the timer)
timer)
OCx=0, OCx_EN=0
OCxN=0, OCxN_EN=0
0
0
1
Output Disabled (not driven by
OCxREF + Polarity OCxN=OCxREF
the timer)
xor CCxNP, OCxN_EN=1
OCx=0, OCx_EN=0
0
1
0
OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1
0
1
1
Complementary to OCREF (not
OCREF + Polarity + dead-time
OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1
1
0
0
Output Disabled (not driven by Output Disabled (not driven by the
timer)
the timer)
OCxN=CCxNP, OCxN_EN=0
OCx=CCxP, OCx_EN=0
1
0
1
Off-State (output enabled with
inactive state)
OCx=CCxP, OCx_EN=1
OCxREF + Polarity
OCxN=OCxREF xor CCxNP,
OCxN_EN=1
1
1
0
OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1
Off-State (output enabled with
inactive state)
OCxN=CCxNP, OCxN_EN=1
1
1
1
Complementary to OCREF (not
OCREF + Polarity + dead-time
OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1
0
0
0
Output Disabled (not driven by Output Disabled (not driven by the
the timer)
timer)
OCx=CCxP, OCx_EN=0
OCxN=CCxNP, OCxN_EN=0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
X
0
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CCxNE
OCx output state
bit
X
OCxN output state
Output Disabled (not driven by the
timer)
OCxN=0, OCxN_EN=0
Output Disabled (not driven by the timer)
Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
dead-time, assuming that OISx and OISxN do not correspond to OCX
and OCxN both in active state.
Output Disabled (not driven by Output Disabled (not driven by the
the timer)
timer)
OCx=CCxP, OCx_EN=0
OCxN=CCxNP, OCxN_EN=0
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
dead-time, assuming that OISx and OISxN do not correspond to OCX
and OCxN both in active state
DocID026448 Rev 1
RM0383
Advanced-control timer (TIM1)
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept
cleared.
Note:
The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO registers.
12.4.10
TIM1 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15
14
13
12
11
10
9
8
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CNT[15:0]
Bits 15:0 CNT[15:0]: Counter value
12.4.11
TIM1 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
12
11
10
9
PSC[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
12.4.12
TIM1 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ARR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 12.3.1: Time-base unit on page 240 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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12.4.13
RM0383
TIM1 repetition counter register (TIMx_RCR)
Address offset: 0x30
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
REP[7:0]
Reserved
rw
rw
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
–
the number of PWM periods in edge-aligned mode
–
the number of half PWM period in center-aligned mode.
12.4.14
TIM1 capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
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Advanced-control timer (TIM1)
12.4.15
TIM1 capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
12.4.16
TIM1 capture/compare register 3 (TIMx_CCR3)
Address offset: 0x3C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR3[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR3[15:0]: Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3 is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
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12.4.17
RM0383
TIM1 capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR4[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR4[15:0]: Capture/Compare value
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register
(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
12.4.18
TIM1 break and dead-time register (TIMx_BDTR)
Address offset: 0x44
Reset value: 0x0000
15
14
13
12
11
10
MOE
AOE
BKP
BKE
OSSR
OSSI
rw
rw
rw
rw
rw
rw
Note:
9
8
7
6
5
LOCK[1:0]
rw
rw
4
3
2
1
0
rw
rw
rw
DTG[7:0]
rw
rw
rw
rw
rw
As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register).
See OC/OCN enable description for more details (Section 12.4.9: TIM1 capture/compare
enable register (TIMx_CCER) on page 293).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
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Advanced-control timer (TIM1)
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CSS clock failure event) disabled
1; Break inputs (BRK and CSS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details (Section 12.4.9: TIM1 capture/compare
enable register (TIMx_CCER) on page 293).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 12.4.9: TIM1 capture/compare
enable register (TIMx_CCER) on page 293).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.
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Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
12.4.19
TIM1 DMA control register (TIMx_DCR)
Address offset: 0x48
Reset value: 0x0000
15
14
13
Reserved
12
11
10
9
8
DBL[4:0]
rw
rw
rw
rw
rw
7
6
Reserved
5
4
3
2
1
0
rw
rw
DBA[4:0]
rw
rw
rw
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer detects a burst transfer
when a read or a write access to the TIMx_DMAR register address is performed).
the TIMx_DMAR address)
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In
this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
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Advanced-control timer (TIM1)
12.4.20
TIM1 DMA address for full transfer (TIMx_DMAR)
Address offset: 0x4C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DMAB[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Example of how to use the DMA burst feature
In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1.
Note:
Configure the corresponding DMA channel as follows:
–
DMA channel peripheral address is the DMAR register address
–
DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
–
Number of data to transfer = 3 (See note below).
–
Circular mode disabled.
2.
Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3.
Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4.
Enable TIMx
5.
Enable the DMA channel
This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
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12.4.21
RM0383
TIM1 register map
TIM1 registers are mapped as 16-bit addressable registers as described in the table below:
TIMx_CNT
TIMx_PSC
TIMx_ARR
TIMx_RCR
DIR
OPM
URS
UDIS
CEN
CCDS
CCUS
Reserved
CCPC
ARPE
TIE
COMIE
CC4IE
CC3IE Reserved
CC2IE
CC1IE
UIE
TI1S
BIE
MSM
UDE
0
OC4M
[2:0]
0
0
0
IC4F[3:0]
0
Reserved
0
0
0
CC4S
[1:0]
CC2IF
CC1IF
UIF
CC1G
UG
0
CC2G
0
0
0
0
OC1FE
CC3IF
0
CC3G
CC4IF
0
OC1PE
COMIF
COMG
0
CC4G
TIF
0
OC1M
[2:0]
OC3M
[2:0]
0 0 0 0 0 0 0 0
IC4
CC4S
PSC
IC3F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0
CC3P
0
0
0 0 0 0 0 0 0 0
IC2
CC2S
PSC
IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0
CC3NE
Reserved
0
0
0
0
0
CC1S
[1:0]
0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0
CC3S
[1:0]
0 0 0 0
IC3
CC3S
PSC
[1:0]
[1:0]
0 0 0 0
CC1E
0
0
OC3FE
0
0
CC1P
0
0
CC1NE
0
0
CC1NP
0
CC2S
[1:0]
0
CC2E
OC2M
[2:0]
0
TG
0
0
BIF
Reserved
0
0
BG
0
OC3PE
OIS2
OIS1N
CC1DE
CC1OF
CC2DE
CC2OF
0
OC2FE
CC3DE
0
SMS[2:0]
CC2P
0
0
0
0
0
0
0
0
0
0
CNT[15:0]
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PSC[15:0]
Reserved
0
0
0
0
0
0
0
0
0
0
ARR[15:0]
Reserved
0
0
0
0
0
0
0
0
0
0
REP[7:0]
Reserved
Reset value
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0
0
TS[2:0]
CC2NE
0
Reset value
0x30
0
0
IC2F[3:0]
Reserved
Reset value
0x2C
0
0
OC4FE
OC2CE
0
Reset value
0x28
0
0
Reset value
0x24
0
0
CC4E
TIMx_CCER
0
0
CC3NP
0x20
0
0
CC4P
0x1C
0
0
0
0
0
0
Reserved
Reserved
0
0
Reserved
Reserved
0
0
0
O24CE
0x18
Reset value
TIMx_CCMR1
Output Compare
mode
Reset value
TIMx_CCMR1
Input Capture
mode
Reset value
TIMx_CCMR2
Output Compare
mode
Reset value
TIMx_CCMR2
Input Capture
mode
Reset value
0
0
0
Reserved
TIMx_EGR
MMS[2:0]
0
Reset value
0x14
0
0
CC4DE
TIMx_SR
0
0
Reset value
0x10
0
0
ETF[3:0]
CC3OF
TIMx_DIER
0
OC4PE
0x0C
0
CC4OF
Reset value
0
0
OC2PE
Reserved
0
0
0
0
ETP
TIMx_SMCR
0
ETPS
[1:0]
0
0
ECE
0x08
0
CMS
[1:0]
TDE
Reset value
0
OIS3
Reserved
0
OIS2N
OIS4
TIMx_CR2
0
COMDE
0x04
OIS3N
Reset value
OIS1
CKD
[1:0]
Reserved
OC1CE
TIMx_CR1
OC3CE
0x00
CC3E
Register
CC2NP
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 51. TIM1 register map and reset values
0
DocID026448 Rev 1
0
0
0
0
RM0383
Advanced-control timer (TIM1)
Reset value
TIMx_CCR3
TIMx_CCR4
TIMx_BDTR
TIMx_DCR
0
0
0
0
TIMx_DMAR
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LOCK
[1:0]
0
0
DBL[4:0]
Reserved
0
DT[7:0]
0
0
0
0
DBA[4:0]
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
DMAB[15:0]
Reserved
Reset value
0
CCR4[15:0]
Reserved
Reset value
0x4C
0
CCR3[15:0]
0
Reset value
0x48
0
Reserved
Reset value
0x44
0
CCR2[15:0]
0
Reset value
0x40
0
Reserved
Reset value
0x3C
0
OSSI
TIMx_CCR2
0
BKE
0x38
CCR1[15:0]
Reserved
OSSR
TIMx_CCR1
BKP
0x34
AOE
Register
MOE
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 51. TIM1 register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
Refer to Table 3 on page 41 for the register boundary addresses.
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General-purpose timers (TIM2 to TIM5)
RM0383
13
General-purpose timers (TIM2 to TIM5)
13.1
TIM2 to TIM5 introduction
The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together as described in Section 13.3.15.
13.2
TIM2 to TIM5 main features
General-purpose TIMx timer features include:
306/836
•
16-bit (TIM3 and TIM4) or 32-bit (TIM2 and TIM5) up, down, up/down auto-reload
counter.
•
16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65536.
•
Up to 4 independent channels for:
–
Input capture
–
Output compare
–
PWM generation (Edge- and Center-aligned modes)
–
One-pulse mode output
•
Synchronization circuit to control the timer with external signals and to interconnect
several timers.
•
Interrupt/DMA generation on the following events:
–
Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
–
Trigger event (counter start, stop, initialization or count by internal/external trigger)
–
Input capture
–
Output compare
•
Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
•
Trigger input for external clock or cycle-by-cycle current management
DocID026448 Rev 1
RM0383
General-purpose timers (TIM2 to TIM5)
Figure 87. General-purpose timer block diagram
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13.3
TIM2 to TIM5 functional description
13.3.1
Time-base unit
The main block of the programmable timer is a 16-bit/32-bit counter with its related autoreload register. The counter can count up. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
•
Counter Register (TIMx_CNT)
•
Prescaler Register (TIMx_PSC):
•
Auto-Reload Register (TIMx_ARR)
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General-purpose timers (TIM2 to TIM5)
RM0383
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC
register). It can be changed on the fly as this control register is buffered. The new prescaler
ratio is taken into account at the next update event.
Figure 88 and Figure 89 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:
Figure 88. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC
00
01
02
03
Update event (UEV)
Prescaler control register
0
1
Write a new value in TIMx_PSC
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Prescaler buffer
0
Prescaler counter
0
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1
0
1
0
1
0
1
0
1
RM0383
General-purpose timers (TIM2 to TIM5)
Figure 89. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC
00
01
Update event (UEV)
Prescaler control register
0
3
Write a new value in TIMx_PSC
13.3.2
Prescaler buffer
0
Prescaler counter
0
3
0
1
2
3
0
1
2
3
Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
does not change). In addition, if the URS bit (update request selection) in TIMx_CR1
register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
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General-purpose timers (TIM2 to TIM5)
RM0383
Figure 90. Counter timing diagram, internal clock divided by 1
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
32 33 34 35 36 00 01 02 03 04 05 06 07
31
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 91. Counter timing diagram, internal clock divided by 2
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
0034
0035 0036
0000
0001
0002
0003
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 92. Counter timing diagram, internal clock divided by 4
CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
0035
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
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0036
0000
0001
RM0383
General-purpose timers (TIM2 to TIM5)
Figure 93. Counter timing diagram, internal clock divided by N
CK_INT
Timer clock = CK_CNT
Counter register
1F
00
20
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 94. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
FF
36
Write a new value in TIMx_ARR
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General-purpose timers (TIM2 to TIM5)
RM0383
Figure 95. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR
preloaded)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
F0
F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
F5
36
Auto-reload shadow register
F5
36
Write a new value in TIMx_ARR
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
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RM0383
General-purpose timers (TIM2 to TIM5)
Figure 96. Counter timing diagram, internal clock divided by 1
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
04 03 02 01 00 36 35 34 33 32 31 30 2F
05
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
Figure 97. Counter timing diagram, internal clock divided by 2
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
0002
0001 0000
0036
0035
0034
0033
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 98. Counter timing diagram, internal clock divided by 4
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
0001
0000
0036
0035
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
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General-purpose timers (TIM2 to TIM5)
RM0383
Figure 99. Counter timing diagram, internal clock divided by N
CK_INT
Timer clock = CK_CNT
Counter register
20
1F
00
36
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 100. Counter timing diagram, Update event
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
05
04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
FF
36
Write a new value in TIMx_ARR
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
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RM0383
General-purpose timers (TIM2 to TIM5)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 101. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
04
03 02 01 00 01 02 03 04 05 06 05 04 03
Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
1. Here, center-aligned mode 1 is used (for more details refer to Section 13.4.1: TIMx control register 1 (TIMx_CR1)
on page 342).
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General-purpose timers (TIM2 to TIM5)
RM0383
Figure 102. Counter timing diagram, internal clock divided by 2
CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
0003
0002 0001
0000
0001
0002
0003
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
0034
0035
0036
0035
Counter overflow (cnt_ovf)
Update event (UEV)
Update interrupt flag (UIF)
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 104. Counter timing diagram, internal clock divided by N
CK_INT
Timer clock = CK_CNT
Counter register
20
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
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01
00
RM0383
General-purpose timers (TIM2 to TIM5)
Figure 105. Counter timing diagram, Update event with ARPE=1 (counter underflow)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
06
05 04 03 02 01 00 01 02 03 04 05 06 07
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FD
36
Write a new value in TIMx_ARR
Auto-reload active register
FD
36
Figure 106. Counter timing diagram, Update event with ARPE=1 (counter overflow)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FD
36
Write a new value in TIMx_ARR
Auto-reload active register
13.3.3
FD
36
Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin (TIx)
•
External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4
only.
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer to act as a prescaler for Timer 2. Refer to : Using
one timer as prescaler for another on page 336 for more details.
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General-purpose timers (TIM2 to TIM5)
RM0383
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 107 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 107. Control circuit in normal mode, internal clock divided by 1
CK_INT
CEN=CNT_EN
UG
CNT_INIT
Counter clock = CK_CNT = CK_PSC
COUNTER REGISTER
31
32 33 34 35 36 00 01 02 03 04 05 06 07
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
Figure 108. TI2 external clock connection example
TIMx_SMCR
TS[2:0]
or
ITRx
001
TI1F_ED 100
TI2
Filter
ICF[3:0]
TIMx_CCMR1
Edge
Detector
TI2F_Rising
0
TI2F_Falling
1
TI1FP1 101
TI2FP2 110
ETRF
111
CC2P
TIMx_CCER
TI2F
TI1F
or
or
encoder
mode
TRGI
external clock
mode 1
ETRF
external clock
mode 2
CK_INT
(internal clock)
CK_PSC
internal clock
mode
ECE SMS[2:0]
TIMx_SMCR
For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
318/836
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the
TIMx_CCMR1 register.
2.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
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RM0383
Note:
General-purpose timers (TIM2 to TIM5)
The capture prescaler is not used for triggering, so you don’t need to configure it.
3.
Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.
4.
Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5.
Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 109. Control circuit in external clock mode 1
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
36
TIF
Write TIF=0
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 110 gives an overview of the external trigger input block.
Figure 110. External trigger input block
or
ETR pin
ETR
0
1
ETP
TIMx_SMCR
divider
/1, /2, /4, /8
ETRP
CK_INT
ETPS[1:0]
TIMx_SMCR
filter
downcounter
ETF[3:0]
TIMx_SMCR
TI2F
TI1F
or
or
encoder
mode
TRGI
external clock
mode 1
ETRF
external clock
mode 2
CK_INT
internal clock
mode
(internal clock)
CK_PSC
ECE SMS[2:0]
TIMx_SMCR
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
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RM0383
1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3.
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 111. Control circuit in external clock mode 2
CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock = CK_CNT = CK_PSC
Counter register
13.3.4
34
35
36
Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 112. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
to the slave mode controller
TI1
fDTS
filter
downcounter
TI1F
TI1F_Rising
Edge
Detector
TI1FP1
TI1F_Falling
TI2FP1
ICF[3:0]
CC1P/CC1NP
TIMx_CCMR1
TIMx_CCER
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
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01
10
IC1
divider
/1, /2, /4, /8
IC1PS
TRC
11
(from slave mode
controller)
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
CC1E
TIMx_CCER
RM0383
General-purpose timers (TIM2 to TIM5)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 113. Capture/compare channel 1 main circuit
APB Bus
read CCR1L
read_in_progress
8
low
read CCR1H S
high
8
(if 16-bit)
MCU-peripheral interface
write_in_progress
Capture/Compare Preload Register
R
R
compare_transfer
capture_transfer
input
mode
CC1S[1]
output
mode
IC1PS
comparator
capture
CC1E
write CCR1L
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
TIMx_CCMR1
(from time
base unit)
Capture/Compare Shadow Register
CC1S[0]
S write CCR1H
CNT>CCR1
Counter
CC1G
CNT=CCR1
TIMx_EGR
Figure 114. Output stage of capture/compare channel (channel 1)
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The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
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13.3.5
RM0383
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
•
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
•
Program the input filter duration you need with respect to the signal you connect to the
timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of
the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at
must 5 internal clock cycles. We must program a filter duration longer than these 5
clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the
new level have been detected (sampled at fDTS frequency). Then write IC1F bits to
0011 in the TIMx_CCMR1 register.
•
Select the edge of the active transition on the TI1 channel by writing the CC1P and
CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
•
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
•
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
•
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
•
The TIMx_CCR1 register gets the value of the counter on the active transition.
•
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
•
An interrupt is generated depending on the CC1IE bit.
•
A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:
322/836
IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.
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13.3.6
General-purpose timers (TIM2 to TIM5)
PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
•
Two ICx signals are mapped on the same TIx input.
•
These 2 ICx signals are active on edges with opposite polarity.
•
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
•
Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
•
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).
•
Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
•
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).
•
Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
•
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
•
Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.
Figure 115. PWM input mode timing
TI1
TIMx_CNT
0004
0000
0001
0002
TIMx_CCR1
0004
TIMx_CCR2
0002
IC1 capture
IC2 capture
reset counter
0003
0004
IC2 capture
pulse width
measurement
0000
IC1 capture
period
measurement
ai15413
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13.3.7
RM0383
Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101
in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high
(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section.
13.3.8
Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
•
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
•
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
•
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
•
Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on ocxref and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
324/836
1.
Select the counter clock (internal, external, prescaler).
2.
Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3.
Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be
generated.
4.
Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0
and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not
used, OCx is enabled and active high.
5.
Enable the counter by setting the CEN bit in the TIMx_CR1 register.
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General-purpose timers (TIM2 to TIM5)
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 116.
Figure 116. Output compare mode, toggle on OC1
Write B201h in the CC1R register
TIMx_CNT
TIMx_CCR1
0039
003A
003B
003A
B200
B201
B201
OC1REF=OC1
Match detected on CCR1
Interrupt generated if enabled
13.3.9
PWM mode
Pulse width modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register by
setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx≤TIMx_CNT or TIMx_CNT≤TIMx_CCRx (depending on the direction of
the counter). However, to comply with the ETRF (OCREF can be cleared by an external
event through the ETR signal until the next PWM period), the OCREF signal is asserted
only:
•
When the result of the comparison changes, or
•
When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes
(OCxM=‘110 or ‘111).
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RM0383
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section :
Upcounting mode on page 309.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.
If the compare value is 0 then OCxREF is held at ‘0. Figure 117 shows some edge-aligned
PWM waveforms in an example where TIMx_ARR=8.
Figure 117. Edge-aligned PWM waveforms (ARR=8)
0
Counter register
CCRx=4
1
2
3
4
5
6
7
8
0
1
OCxREF
CCxIF
CCRx=8
CCRx>8
CCRx=0
OCxREF
CCxIF
OCxREF
‘1
CCxIF
OCxREF
‘0
CCxIF
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section :
Downcounting mode on page 312.
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Section : Center-aligned mode (up/down counting) on page 314.
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General-purpose timers (TIM2 to TIM5)
Figure 118 shows some center-aligned PWM waveforms in an example where:
•
TIMx_ARR=8,
•
PWM mode is the PWM mode 1,
•
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
Figure 118. Center-aligned PWM waveforms (ARR=8)
#OUNTERREGISTER
/#X2%&
##2X
#-3
#-3
#-3
##X)&
/#X2%&
##2X
#-3OR
##X)&
/#X2%&
##2X
gg
#-3
#-3
#-3
##X)&
/#X2%&
##2X
gg
#-3
#-3
#-3
##X)&
/#X2%&
##2X
##X)&
gg
#-3
#-3
#-3
AIB
Hints on using center-aligned mode:
•
When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
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RM0383
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
•
•
13.3.10
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
–
The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.
–
The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.
One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
•
In upcounting: CNT<CCRx≤ARR (in particular, 0<CCRx),
•
In downcounting: CNT>CCRx.
Figure 119. Example of one-pulse mode
TI2
OC1REF
Counter
OC1
TIM1_ARR
TIM1_CCR1
0
tDELAY
tPULSE
t
For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
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General-purpose timers (TIM2 to TIM5)
Let’s use TI2FP2 as trigger 1:
•
Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.
•
TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER
register.
•
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in
the TIMx_SMCR register.
•
TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
•
The tDELAY is defined by the value written in the TIMx_CCR1 register.
•
The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR + 1).
•
Let’s say you want to build a waveform with a transition from ‘0 to ‘1 when a compare
match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=1 in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
13.3.11
Clearing the OCxREF signal on an external event
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for
current handling. In this case, ETR must be configured as follows:
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RM0383
1.
The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR
register are cleared to 00.
2.
The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is
cleared to 0.
3.
The external trigger polarity (ETP) and the external trigger filter (ETF) can be
configured according to the application’s needs.
Figure 120 shows the behavior of the OCxREF signal when the ETRF input becomes high,
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.
Figure 120. Clearing TIMx OCxREF
(CCRx)
counter (CNT)
ETRF
OCxREF
(OCxCE=0)
OCxREF
(OCxCE=1)
ETRF
becomes high
ETRF
still high
1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter
overflow.
13.3.12
Encoder interface mode
To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, you can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 52. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler,
trigger output features continue to work as normal.
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General-purpose timers (TIM2 to TIM5)
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.
Table 52. Counting direction versus encoder signals
Level on opposite
signal (TI1FP1 for
TI2, TI2FP2 for TI1)
Rising
Falling
Rising
Falling
Counting on
TI1 only
High
Down
Up
No Count
No Count
Low
Up
Down
No Count
No Count
Counting on
TI2 only
High
No Count
No Count
Up
Down
Low
No Count
No Count
Down
Up
Counting on
TI1 and TI2
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
Active edge
TI1FP1 signal
TI2FP2 signal
An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 121 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
•
CC1S= ‘01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
•
CC2S= ‘01’ (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
•
CC1P= ‘0’, CC1NP = ‘0’, IC1F =’0000’ (TIMx_CCER register, TI1FP1 noninverted,
TI1FP1=TI1)
•
CC2P= ‘0’, CC2NP = ‘0’, IC2F =’0000’ (TIMx_CCER register, TI2FP2 noninverted,
TI2FP2=TI2)
•
SMS= ‘011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges)
•
CEN = 1 (TIMx_CR1 register, Counter is enabled)
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Figure 121. Example of counter operation in encoder interface mode
forward
jitter
backward
jitter
forward
TI1
TI2
Counter
down
up
up
Figure 122 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).
Figure 122. Example of encoder interface mode with TI1FP1 polarity inverted
forward
jitter
backward
jitter
forward
TI1
TI2
Counter
down
up
down
The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.
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13.3.13
General-purpose timers (TIM2 to TIM5)
Timer input XOR function
The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.
13.3.14
Timers and external trigger synchronization
The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
•
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edges only).
•
Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 123. Control circuit in reset mode
TI1
UG
Counter clock = CK_CNT = CK_PSC
Counter register
30 31 32 33 34 35 36 00 01 02 03 00 01 02 03
TIF
Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
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In the following example, the upcounter counts only when TI1 input is low:
•
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
•
Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 124. Control circuit in gated mode
TI1
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
30 31 32 33
34
35 36 37 38
TIF
Write TIF=0
1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect
in gated mode because gated mode acts on a level and not on an edge.
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
•
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are
selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write
CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
•
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
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Figure 125. Control circuit in trigger mode
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
34
35 36 37 38
TIF
Slave mode: External Clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS
bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1.
2.
3.
Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–
ETF = 0000: no filter
–
ETPS = 00: prescaler disabled
–
ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
Configure the channel 1 as follows, to detect rising edges on TI:
–
IC1F = 0000: no filter.
–
The capture prescaler is not used for triggering and does not need to be
configured.
–
CC1S = 01 in TIMx_CCMR1 register to select only the input capture source
–
CC1P = 0 in TIMx_CCER register to validate the polarity (and detect rising edge
only).
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
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Figure 126. Control circuit in external clock mode 2 + trigger mode
TI1
CEN/CNT_EN
ETR
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
36
TIF
13.3.15
Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 127: Master/Slave timer example presents an overview of the trigger selection and
the master mode selection blocks.
Using one timer as prescaler for another
Figure 127. Master/Slave timer example
TIM1
TIM2
MMS
Clock
UEV
Master
mode
Prescaler
Counter
TS
TRGO1 ITR0
control
SMS
Slave
CK_PSC
mode
control
Prescaler
Counter
Input
trigger
selection
For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Figure 127. To do this:
Note:
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•
Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
•
To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in
slave mode using ITR0 as internal trigger. You select this through the TS bits in the
TIM2_SMCR register (writing TS=000).
•
Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the
periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).
•
Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer 2.
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General-purpose timers (TIM2 to TIM5)
Using one timer to enable another timer
In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.
Refer to Figure 127 for connections. Timer 2 counts on the divided internal clock only when
OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
Note:
•
Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
•
Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
•
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
•
Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
•
Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
•
Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2
counter enable signal.
Figure 128. Gating timer 2 with OC1REF of timer 1
CK_INT
TIMER1-OC1REF
TIMER1-CNT
TIMER2-CNT
FC
FD
3045
FE
3046
FF
3047
00
01
3048
TIMER 2-TIF
Write TIF=0
In the example in Figure 162, the Timer 2 counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer 1. You can then write any value
you want in the timer counters. The timers can easily be reset by software using the UG bit
in the TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts
from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both
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timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1
register:
•
Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
•
Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
•
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
•
Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
•
Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).
•
Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).
•
Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).
•
Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
•
Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
•
Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).
Figure 129. Gating timer 2 with Enable of timer 1
CK_INT
TIMER1-CEN=CNT_EN
TIMER1-CNT_INIT
TIMER1-CNT
TIMER2-CNT
75
00
AB
00
E7
01
02
E8
E9
TIMER2-CNT_INIT
TIMER2
write CNT
TIMER 2-TIF
Write TIF=0
Using one timer to start another timer
In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to
Figure 127 for connections. Timer 2 starts counting from its current value (which can be
nonzero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
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•
Configure Timer 1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register).
•
Configure the Timer 1 period (TIM1_ARR registers).
•
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
•
Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).
•
Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
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General-purpose timers (TIM2 to TIM5)
Figure 130. Triggering timer 2 with update of timer 1
CK_INT
TIMER1-UEV
TIMER1-CNT
FD
FE
TIMER2-CNT
00
FF
45
02
01
47
46
48
TIMER2-CEN=CNT_EN
TIMER 2-TIF
Write TIF=0
As in the previous example, you can initialize both counters before starting counting.
Figure 131 shows the behavior with the same configuration as in Figure 162 but in trigger
mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
Figure 131. Triggering timer 2 with Enable of timer 1
CK_INT
TIMER1-CEN=CNT_EN
TIMER1-CNT_INIT
TIMER1-CNT
TIMER2-CNT
75
00
CD
00
01
E7
E8
02
E9
EA
TIMER2-CNT_INIT
TIMER2
write CNT
TIMER 2-TIF
Write TIF=0
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Using one timer as prescaler for another timer
For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Figure 127 for connections. To do this:
•
Configure Timer 1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register). then it outputs a periodic signal on each counter
overflow.
•
Configure the Timer 1 period (TIM1_ARR registers).
•
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
•
Configure Timer 2 in external clock mode 1 (SMS=111 in TIM2_SMCR register).
•
Start Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
•
Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of
Timer 2 with the enable of Timer 1. Refer to Figure 127 for connections. To ensure the
counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer 2):
•
Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the
TIM1_CR2 register).
•
Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM1_SMCR register).
•
Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).
•
Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).
•
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
•
Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note:
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In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.
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Figure 132. Triggering timer 1 and 2 with timer 1 TI1 input
CK_INT
TIMER 1-TI1
TIMER1-CEN=CNT_EN
TIMER 1-CK_PSC
TIMER1-CNT
00
01 02 03 04 05 06 07 08 09
00
01 02 03 04 05 06 07 08 09
TIMER1-TIF
TIMER2-CEN=CNT_EN
TIMER 2-CK_PSC
TIMER2-CNT
TIMER2-TIF
13.3.16
Debug mode
When the microcontroller enters debug mode (Cortex®-M4 with FPU core - halted), the
TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBGMCU module. For more details, refer to Section 23.16.2: Debug
support for timers, watchdog and I2C.
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13.4
RM0383
TIM2 to TIM5 registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral
registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be
done by bytes (8 bits), half-words (16 bits) or words (32 bits).
13.4.1
TIMx control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
Reserved
11
10
9
8
CKD[1:0]
rw
7
6
ARPE
rw
rw
5
CMS
rw
rw
4
3
2
1
0
DIR
OPM
URS
UDIS
CEN
rw
rw
rw
rw
rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
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Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.
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13.4.2
RM0383
TIMx control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
15
14
13
12
11
Reserved
10
9
8
7
6
TI1S
rw
5
4
MMS[2:0]
rw
rw
3
CCDS
rw
rw
2
1
0
Reserved
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, must be kept at reset value.
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General-purpose timers (TIM2 to TIM5)
13.4.3
TIMx slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
15
14
ETP
ECE
rw
rw
13
12
11
ETPS[1:0]
rw
rw
10
9
8
ETF[3:0]
rw
rw
7
6
MSM
rw
rw
rw
5
4
TS[2:0]
rw
rw
rw
3
Res.
2
1
0
SMS[2:0]
rw
rw
rw
Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is noninverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
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General-purpose timers (TIM2 to TIM5)
RM0383
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0).
001: Internal Trigger 1 (ITR1).
010: Internal Trigger 2 (ITR2).
011: Internal Trigger 3 (ITR3).
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 53: TIMx internal trigger connection on page 347 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
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General-purpose timers (TIM2 to TIM5)
Table 53. TIMx internal trigger connection
Slave TIM
ITR0 (TS = 000)
ITR1 (TS = 001)
ITR2 (TS = 010)
ITR3 (TS = 011)
TIM2
TIM1
Reserved
TIM3
TIM4
TIM3
TIM1
TIM2
TIM5
TIM4
TIM4
TIM1
TIM2
TIM3
Reserved
TIM5
TIM2
TIM3
TIM4
Reserved
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13.4.4
RM0383
TIMx DMA/Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
Res.
14
TDE
rw
13
Res
Bit 15
12
11
10
9
8
CC4DE CC3DE CC2DE CC1DE
rw
rw
rw
rw
UDE
rw
7
Res.
6
TIE
rw
Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13
Reserved, always read as 0
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7
Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5
Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
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5
Res
4
3
2
1
0
CC4IE
CC3IE
CC2IE
CC1IE
UIE
rw
rw
rw
rw
rw
RM0383
General-purpose timers (TIM2 to TIM5)
13.4.5
TIMx status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
12
11
10
9
8
CC4OF CC3OF CC2OF CC1OF
Reserved
rc_w0
Bits 15:13
rc_w0
rc_w0
rc_w0
7
Reserved
6
TIF
rc_w0
5
Res
4
3
2
1
0
CC4IF
CC3IF
CC2IF
CC1IF
UIF
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7
Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5
Reserved, must be kept at reset value.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
refer to CC1IF description
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RM0383
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow
(in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected
on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
″
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
″
At overflow or underflow (for TIM2 to TIM5) and if UDIS=0 in the TIMx_CR1 register.
″
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description),
if URS=0 and UDIS=0 in the TIMx_CR1 register.
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General-purpose timers (TIM2 to TIM5)
13.4.6
TIMx event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
TG
Reserved
w
5
Res.
4
3
2
1
0
CC4G
CC3G
CC2G
CC1G
UG
w
w
w
w
w
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G: Capture/compare 4 generation
refer to CC1G description
Bit 3 CC3G: Capture/compare 3 generation
refer to CC1G description
Bit 2 CC2G: Capture/compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
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13.4.7
RM0383
TIMx capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15
14
OC2CE
13
12
OC2M[2:0]
IC2F[3:0]
rw
rw
rw
11
10
OC2PE OC2FE
IC2PSC[1:0]
rw
rw
rw
9
8
CC2S[1:0]
rw
7
6
OC1CE
rw
5
4
OC1M[2:0]
IC1F[3:0]
rw
rw
rw
3
2
OC1PE OC1FE
IC1PSC[1:0]
rw
rw
rw
1
0
CC1S[1:0]
rw
rw
Output compare mode
Bit 15 OC2CE: Output compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
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General-purpose timers (TIM2 to TIM5)
Bits 6:4 OC1M: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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RM0383
Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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General-purpose timers (TIM2 to TIM5)
13.4.8
TIMx capture/compare mode register 2 (TIMx_CCMR2)
Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.
15
14
OC4CE
13
12
OC4M[2:0]
IC4F[3:0]
rw
rw
rw
11
10
OC4PE OC4FE
IC4PSC[1:0]
rw
rw
rw
9
8
CC4S[1:0]
rw
7
6
OC3CE
rw
5
4
OC3M[2:0]
IC3F[3:0]
rw
rw
rw
3
2
OC3PE OC3FE
IC3PSC[1:0]
rw
rw
rw
1
0
CC3S[1:0]
rw
rw
Output compare mode
Bit 15 OC4CE: Output compare 4 clear enable
Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
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RM0383
Input capture mode
Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
13.4.9
TIMx capture/compare enable register (TIMx_CCER)
Address offset: 0x20
Reset value: 0x0000
15
CC4NP
rw
14
Res.
13
12
11
CC4P
CC4E
CC3NP
rw
rw
rw
10
Res.
9
8
7
CC3P
CC3E
CC2NP
rw
rw
rw
6
Res.
Bit 15 CC4NP: Capture/Compare 4 output Polarity.
Refer to CC1NP description
Bit 14
Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output Polarity.
refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable.
refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 output Polarity.
refer to CC1NP description
Bit 10
Reserved, must be kept at reset value.
Bit 9 CC3P: Capture/Compare 3 output Polarity.
refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable.
refer to CC1E description
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4
3
CC2P
CC2E
CC1NP
rw
rw
rw
2
Res.
1
0
CC1P
CC1E
rw
rw
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General-purpose timers (TIM2 to TIM5)
Bit 7 CC2NP: Capture/Compare 2 output Polarity.
refer to CC1NP description
Bit 6
Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable.
refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
CC1NP must be kept cleared in this case.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P
description.
Bit 2
Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled
Table 54. Output control bit for standard OCx channels
CCxE bit
OCx output state
0
Output Disabled (OCx=0, OCx_EN=0)
1
OCx=OCxREF + Polarity, OCx_EN=1
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RM0383
Note:
The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
13.4.10
TIMx counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CNT[15:0]: Counter value
13.4.11
TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
12
11
10
9
PSC[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.
13.4.12
TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ARR[15:0]
rw
rw
rw
Bits 15:0
13.4.13
rw
rw
rw
rw
rw
rw
ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 13.3.1: Time-base unit on page 307 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
TIMx capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
CCR1[31:16] (depending on timers)
rw
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General-purpose timers (TIM2 to TIM5)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5).
Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
13.4.14
TIMx capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000 0000
31
30
29
28
27
26
25
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
24
23
22
21
20
19
18
17
16
CCR2[31:16] (depending on timers)
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5).
Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
13.4.15
TIMx capture/compare register 3 (TIMx_CCR3)
Address offset: 0x3C
Reset value: 0x0000 0000
31
30
29
28
27
26
rw
rw
rw
rw
rw
rw
25
24
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
CCR3[31:16] (depending on timers)
rw
rw
rw
rw
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14
13
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10
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9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR3[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5).
Bits 15:0 CCR3[15:0]: Low Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit
OC3PE). Else the preload value is copied in the active capture/compare 3 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC3 output.
If channel CC3 is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
13.4.16
TIMx capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CCR4[31:16] (depending on timers)
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
CCR4[15:0]
rw
rw
Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5).
Bits 15:0 CCR4[15:0]: Low Capture/Compare value
1.
if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register
(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
2.
if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
13.4.17
TIMx DMA control register (TIMx_DCR)
Address offset: 0x48
Reset value: 0x0000
15
14
Reserved
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12
11
10
9
8
DBL[4:0]
rw
rw
rw
rw
rw
7
6
Reserved
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4
3
2
1
0
rw
rw
DBA[4:0]
rw
rw
rw
RM0383
General-purpose timers (TIM2 to TIM5)
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this
case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
13.4.18
TIMx DMA address for full transfer (TIMx_DMAR)
Address offset: 0x4C
Reset value: 0x0000
15
14
13
12
11
10
9
8
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DMAB[15:0]
rw
rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Example of how to use the DMA burst feature
In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
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General-purpose timers (TIM2 to TIM5)
1.
Note:
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Configure the corresponding DMA channel as follows:
–
DMA channel peripheral address is the DMAR register address
–
DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
–
Number of data to transfer = 3 (See note below).
–
Circular mode disabled.
2.
Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3.
Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4.
Enable TIMx
5.
Enable the DMA channel
This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
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General-purpose timers (TIM2 to TIM5)
13.4.19
TIM2 option register (TIM2_OR)
Address offset: 0x50
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
ITR1_RMP
Reserved
rw
5
4
3
2
1
0
3
2
1
0
Reserved
rw
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:10 ITR1_RMP: Internal trigger 1 remap
Set and cleared by software.
00: Reserved
01: PTP trigger output is connected to TIM2_ITR1
10: OTG FS SOF is connected to the TIM2_ITR1 input
11: OTG HS SOF is connected to the TIM2_ITR1 input
Bits 9:0 Reserved, must be kept at reset value.
13.4.20
TIM5 option register (TIM5_OR)
Address offset: 0x50
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
TI4_RMP
Reserved
rw
rw
5
4
Reserved
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:6 TI4_RMP: Timer Input 4 remap
Set and cleared by software.
00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table
in the datasheets.
01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes
10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes
11: the RTC wakeup interrupt is connected to TIM5_CH4 input for calibration purposes.
Wakeup interrupt should be enabled.
Bits 5:0 Reserved, must be kept at reset value.
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13.4.21
RM0383
TIMx register map
TIMx registers are mapped as described in the table below:
0
0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CC4S
[1:0]
0
0
0
0
0
0
UIE
0
0
CC1S
[1:0]
0
0
0
0
0
IC1F[3:0]
0
0
0
0
OC3M
[2:0]
0
0
0
IC1
PSC
[1:0]
CC1S
[1:0]
0
0
0
CC3S
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CC3E
CC2NP
Reserved
Reserved
CC3S
[1:0]
CC3P
IC3
PSC
[1:0]
Reserved
IC3F[3:0]
0
CC3NP
CC4S
[1:0]
0
CC4E
IC4
PSC
[1:0]
UIF
OC1CE
OC2FE
CC2S
[1:0]
0
OC1M
[2:0]
0
IC2
PSC
[1:0]
0
0
0
0
0
0
CNT[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0
0
0
0
0
TIMx_CNT
0
0
CC4P
Reserved
Reset value
Reset value
0
0
0
CC4NP
Reset value
0x24
OC4M
[2:0]
IC4F[3:0]
Reserved
TIMx_CCER
0
0
0
0
0
0
0
0
0
0
CC1E
Reset value
0
0
0
0
CC1P
Reserved
TIMx_CCMR2
Input Capture
mode
0x20
0
O24CE
Reset value
0x1C
0
IC2F[3:0]
Reserved
TIMx_CCMR2
Output Compare
mode
0
OC3CE
TIMx_CCMR1
Input Capture
mode
0
OC4FE
0
CC2S
[1:0]
OC4PE
Reset value
OC2M
[2:0]
0
SMS[2:0]
Reserved
0x18
Reserved
OC2PE
0
OC2CE
Reset value
TIMx_CCMR1
Output Compare
mode
0
UG
0
Reserved
0
CC1NP
TIMx_EGR
0
TG
0x14
CC1IE
0
CC2IE
0
0
CC1IF
0
Reset value
0
CC2IF
CC1OF
0
Reserved
0
CC1G
0
CC2G
UDE
0
OC1FE
CC1DE
0
TS[2:0]
OC3FE
CC2DE
0
Reserved
CC3DE
0
CC2OF
TIMx_SR
CC4DE
0x10
0
CC3OF
Reset value
Reserved
Reserved
TIE
0
Reserved
0
CC3IE
0
CC4IE
0
CC3IF
0
CC3G
0
OC1PE
0
Reserved
0
CC4IF
0
Reserved
0
CC4G
0
Reserved
0
MSM
0
COMDE
TIMx_DIER
0
0
CC4OF
0x0C
0
ETP
Reset value
CEN
Reserved
0
ETPS
[1:0]
ETF[3:0]
URS
MMS[2:0]
ECE
Reserved
UDIS
0
0
TDE
TIMx_SMCR
0
0
Reset value
0x08
0
DIR
Reserved
0
OPM
0
CC2E
TIMx_CR2
0
0
CC2P
0x04
0
CMS
[1:0]
CCDS
Reset value
CKD
[1:0]
OC3PE
Reserved
ARPE
TIMx_CR1
TI1S
0x00
Register
TIF
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 55. TIM2 to TIM5 register map and reset values
0
0
0
0
CNT[15:0]
0
0
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0
0
0
0
0
0
0
0
0
RM0383
General-purpose timers (TIM2 to TIM5)
Offset
0x28
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 55. TIM2 to TIM5 register map and reset values (continued)
TIMx_PSC
PSC[15:0]
Reserved
Reset value
0x2C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CCR2[15:0]
0
0
0
0
0
0
0
0
0
0
0
CCR3[15:0]
0
0
0
0
0
0
0
0
0
0
0
CCR4[15:0]
0
0
0
0
0
0
0
0
0
0
0
Reserved
TIMx_DCR
DBL[4:0]
Reserved
TIMx_DMAR
0
TIM2_OR
0
0
DBA[4:0]
Reserved
0
0
0
0
0
0
0
0
0
0
0
DMAB[15:0]
0
Reserved
Reset value
TIM5_OR
0
Reserved
Reset value
0x50
0
CCR1[15:0]
Reset value
0x50
0
ARR[15:0]
CCR4[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0x44
0x4C
0
CCR3[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
TIMx_CCR4
Reset value
0x48
0
CCR2[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
TIMx_CCR3
Reset value
0x40
0
TIMx_CCR2
Reset value
0x3C
0
CCR1[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
TIMx_CCR1
Reset value
0x38
0
Reserved
0x30
0x34
0
ARR[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
TIMx_ARR
Reset value
0
0
0
0
Reserved
0
0
0
0
0
ITR1_
RMP
0
Reserved
0
0
Reserved
0
Reserved
Reset value
IT4_
RMP
0
Reserved
0
Refer to Table 3 on page 41 for the register boundary addresses.
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General-purpose timers (TIM9 to TIM11)
TIM8 is not available in STM32F411xC/E.
14.1
TIM9/10/11 introduction
The TIM9/10/11 general-purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM9/10/11 timers are completely independent, and do not share any resources. They
can be synchronized together as described in Section 14.3.12.
14.2
TIM9/10/11 main features
14.2.1
TIM9 main features
The features of the TIM9 general-purpose timer include:
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•
16-bit auto-reload upcounter
•
16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65536 (can be changed “on the fly”)
•
Up to 2 independent channels for:
–
Input capture
–
Output compare
–
PWM generation (edge-aligned mode)
–
One-pulse mode output
•
Synchronization circuit to control the timer with external signals and to interconnect
several timers together
•
Interrupt generation on the following events:
–
Update: counter overflow, counter initialization (by software or internal trigger)
–
Trigger event (counter start, stop, initialization or count by internal trigger)
–
Input capture
–
Output compare
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General-purpose timers (TIM9 to TIM11)
Figure 133. General-purpose timer block diagram (TIM9)
Internal clock (CK_INT)
ITR0
ITR1
TGI
ITR
ITR2
TRC
Trigger
controller
TRGI
ITR3
TI1F_ED
Slave
mode
controller
Reset, Enable, Count
TI1FP1
TI2FP2
U
Auto-reload register
Stop, Clear
CK_PSC
PSC
CK_CNT
Prescaler
+/-
Input filter &
Edge detector
TIMx_CH1
TI1FP1
TI1FP2
IC1
Prescaler
CC1I
TIMx_CH2
Input filter &
Edge detector
Capture/Compare 1 register
OC1REF
output
OC1
control
TRC
TI2
IC1PS U
U
CNT
COUNTER
CC1I
TI1
UI
TI2FP1
TI2FP2
CC2I
IC2
CC2I
IC2PS U
Prescaler
TIMx_CH1
Capture/Compare 2 register
OC2REF
output
OC2
TIMx_CH2
control
TRC
Notes:
Reg
Preload registers transferred
to active registers on U event
according to control bit
event
interrupt
ai17190
14.2.2
TIM10/TIM11 main features
The features of general-purpose timers TIM10/TIM11 include:
•
16-bit auto-reload upcounter
•
16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65536 (can be changed “on the fly”)
•
independent channel for:
•
–
Input capture
–
Output compare
–
PWM generation (edge-aligned mode)
–
One-pulse mode output
Interrupt generation on the following events:
–
Update: counter overflow, counter initialization (by software)
–
Input capture
–
Output compare
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RM0383
Figure 134. General-purpose timer block diagram (TIM10/11)
)NTERNALCLOCK#+?).4
4RIGGER
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5
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COUNTER
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#+?03#
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5
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4)-X?#(
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0RESCALER
)#03
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0RELOADREGISTERSTRANSFERRED
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AIC
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General-purpose timers (TIM9 to TIM11)
14.3
TIM9 to TIM11 functional description
14.3.1
Time-base unit
The main block of the timer is a 16-bit counter with its related auto-reload register.
The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
•
Counter register (TIMx_CNT)
•
Prescaler register (TIMx_PSC)
•
Auto-reload register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be
generated by software. The generation of the update event is described in details for each
configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 135 and Figure 136 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.
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Figure 135. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC
00
01
02
03
Update event (UEV)
Prescaler control register
0
1
Write a new value in TIMx_PSC
Prescaler buffer
0
Prescaler counter
0
1
0
1
0
1
0
1
0
1
Figure 136. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB FC
00
01
Update event (UEV)
Prescaler control register
0
3
Write a new value in TIMx_PSC
14.3.2
Prescaler buffer
0
Prescaler counter
0
3
0
1
2
3
0
1
2
3
Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software ) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
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General-purpose timers (TIM9 to TIM11)
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 137. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 138. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0034
0035 0036
0000
0001
0002
0003
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
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RM0383
Figure 139. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0035
0000
0036
0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 140. Counter timing diagram, internal clock divided by N
CK_PSC
Timer clock = CK_CNT
Counter register
1F
00
20
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 141. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
FF
Write a new value in TIMx_ARR
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General-purpose timers (TIM9 to TIM11)
Figure 142. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F0
F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
F5
36
Auto-reload shadow register
F5
36
Write a new value in TIMx_ARR
14.3.3
Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1 (for TIM9): external input pin (TIx)
•
Internal trigger inputs (ITRx) (for TIM9): connecting the trigger output from another
timer. Refer to Section : Using one timer as prescaler for another for more details.
Internal clock source (CK_INT)
The internal clock source is the default clock source for TIM10/TIM11.
For TIM9, the internal clock source is selected when the slave mode controller is disabled
(SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR
register are then used as control bits and can be changed only by software (except for UG
which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is
clocked by the internal clock CK_INT.
Figure 143 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
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Figure 143. Control circuit in normal mode, internal clock divided by 1
Internal clock
CEN=CNT_EN
UG
CNT_INIT
Counter clock = CK_CNT = CK_PSC
Counter register
32 33 34 35 36 00 01 02 03 04 05 06 07
31
External clock source mode 1(TIM9)
This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.
Figure 144. TI2 external clock connection example
TIMx_SMCR
TS[2:0]
or
ITRx
TI1_ED
TI2
Filter
ICF[3:0]
TIMx_CCMR1
TI2F_Rising 0
Edge
Detector TI2F_Falling
1
0xx
100
TI1FP1 101
TI2FP2 110
CC2P
TI2F
TI1F
TRGI
or
or
external clock
mode 1
CK_PSC
CK_INT
internal clock
mode
(internal clock)
TIMx_CCER
SMS[2:0]
TIMx_SMCR
For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
Note:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
2.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=’0000’).
3.
Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
4.
Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR
register.
5.
Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register.
6.
Enable the counter by writing CEN=’1’ in the TIMx_CR1 register.
The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
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Figure 145. Control circuit in external clock mode 1
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
36
TIF
Write TIF=0
14.3.4
Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 146 to Figure 148 give an overview of one capture/compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 146. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
to the slave mode controller
TI1
fDTS
filter
downcounter
ICF[3:0]
TIMx_CCMR1
TI1F
TI1F_Rising
Edge
Detector
TI1F_Falling
0
1
CC1P/CC1NP
(from channel 2)
TI2FP1
01
10
IC1
divider
/1, /2, /4, /8
IC1PS
TRC
11
(from slave mode
controller)
TIMx_CCER
TI2F_rising
(from channel 2)
TI2F_falling
TI1FP1
0
CC1S[1:0] ICPS[1:0]
1
TIMx_CCMR1
CC1E
TIMx_CCER
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
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Figure 147. Capture/compare channel 1 main circuit
APB Bus
read CCR1L
read_in_progress
8
low
read CCR1H S
high
8
(if 16-bit)
MCU-peripheral interface
write_in_progress
Capture/compare preload register
R
R
compare_transfer
capture_transfer
input
mode
CC1S[1]
CC1S[0]
output
mode
Capture/compare shadow register
IC1PS
comparator
capture
CC1E
S write CCR1H
write CCR1L
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
TIM1_CCMR1
(from time
base unit)
CNT>CCR1
Counter
CC1G
CNT=CCR1
TIM1_EGR
Figure 148. Output stage of capture/compare channel (channel 1)
4OTHEMASTERMODE
CONTROLLER
/UTPUT
ENABLE
CIRCUIT
/#
##0
#.4##2
/UTPUTMODE /#?2%&
#.4##2 CONTROLLER
4)-X?##%2
##% 4)-X?##%2
/#-;=
4)-X?##-2
AI
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
14.3.5
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
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cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1.
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’,
the channel is configured in input mode and the TIMx_CCR1 register becomes readonly.
2.
Program the input filter duration you need with respect to the signal you connect to the
timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of
the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at
must 5 internal clock cycles. We must program a filter duration longer than these 5
clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the
new level have been detected (sampled at fDTS frequency). Then write IC1F bits to
‘0011’ in the TIMx_CCMR1 register.
3.
Select the edge of the active transition on the TI1 channel by programming CC1P and
CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).
4.
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
5.
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
6.
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register.
When an input capture occurs:
•
The TIMx_CCR1 register gets the value of the counter on the active transition.
•
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
•
An interrupt is generated depending on the CC1IE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:
IC interrupt requests can be generated by software by setting the corresponding CCxG bit in
the TIMx_EGR register.
14.3.6
PWM input mode (only for TIM9)
This mode is a particular case of input capture mode. The procedure is the same except:
•
Two ICx signals are mapped on the same TIx input.
•
These 2 ICx signals are active on edges with opposite polarity.
•
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
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1.
Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1
register (TI1 selected).
2.
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge).
3.
Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1
register (TI1 selected).
4.
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the
CC2P and CC2NP bits to ‘11’ (active on falling edge).
5.
Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register
(TI1FP1 selected).
6.
Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the
TIMx_SMCR register.
7.
Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
Figure 149. PWM input mode timing
TI1
TIMx_CNT
0004
0000
0001
0002
TIMx_CCR1
0004
TIMx_CCR2
0002
IC1 capture
IC2 capture
reset counter
0003
0004
IC2 capture
pulse width
measurement
0000
IC1 capture
period
measurement
ai15413
1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.
14.3.7
Forced output mode
In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the
TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is
described in the output compare mode section below.
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14.3.8
General-purpose timers (TIM9 to TIM11)
Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
1.
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set
active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on
match.
2.
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
3.
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1.
Select the counter clock (internal, external, prescaler).
2.
Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3.
Set the CCxIE bit if an interrupt request is to be generated.
4.
Select the output mode. For example:
5.
–
Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx
–
Write OCxPE = ‘0’ to disable preload register
–
Write CCxP = ‘0’ to select active high polarity
–
Write CCxE = ‘1’ to enable the output
Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 150.
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Figure 150. Output compare mode, toggle on OC1.
Write B201h in the CC1R register
TIM1_CNT
0039
003A
TIM1_CCR1
003B
003A
B200
B201
B201
oc1ref=OC1
Match detected on CCR1
Interrupt generated if enabled
14.3.9
PWM mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
It can be programmed as active high or active low. The OCx output is enabled by the CCxE
bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more
details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CNT ≤TIMx_CCRx.
The timer is able to generate PWM in edge-aligned mode only since the counter is
upcounting.
PWM edge-aligned mode
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 151 shows some edgealigned PWM waveforms in an example where TIMx_ARR=8.
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Figure 151. Edge-aligned PWM waveforms (ARR=8)
Counter register
CCRx=4
0
1
2
3
4
5
6
7
8
0
1
OCXREF
CCxIF
CCRx=8
CCRx>8
CCRx=0
CCxIF
OCXREF
CCxIF
OCXREF
CCxIF
One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be as follows:
CNT < CCRx≤ ARR (in particular, 0 < CCRx)
Figure 152. Example of one pulse mode.
TI2
OC1REF
OC1
Counter
14.3.10
OCXREF
TIM1_ARR
TIM1_CCR1
0
tDELAY
tPULSE
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For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Use TI2FP2 as trigger 1:
1.
Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
2.
TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER
register.
3.
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
4.
TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
•
The tDELAY is defined by the value written in the TIMx_CCR1 register.
•
The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
•
Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=’111’ in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.
Particular case: OCx fast enable
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
14.3.11
TIM9 external trigger synchronization
The TIM9 timer can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.
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Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
1.
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register.
Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and
detect rising edges only).
2.
Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select
TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.
3.
Start the counter by writing CEN=’1’ in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if
enabled (depending on the TIE bit in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 153. Control circuit in reset mode
TI1
UG
Counter clock = ck_cnt = ck_psc
Counter register
30 31 32 33 34 35 36 00 01 02 03 00 01 02 03
TIF
Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
1.
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program
CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect
low level only).
2.
Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register.
Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.
3.
Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=’0’, whatever is the trigger input level).
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The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 154. Control circuit in gated mode
TI1
cnt_en
Counter clock = ck_cnt = ck_psc
Counter register
30 31 32 33
34
35 36 37 38
TIF
Write TIF=0
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1.
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register.
Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and
detect low level only).
2.
Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register.
Select TI2 as the input source by writing TS=’110’ in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 155. Control circuit in trigger mode
TI2
cnt_en
Counter clock = ck_cnt = ck_psc
Counter register
34
TIF
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14.3.12
Timer synchronization (TIM9)
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 13.3.15: Timer synchronization on page 336 for details.
14.3.13
Debug mode
When the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBG module. For more details, refer to Section 23.16.2: Debug support
for timers, watchdog and I2C.
14.4
TIM9 registers
Refer to Section 1.1 for a list of abbreviations used in register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
14.4.1
TIM9 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
Reserved
11
10
9
8
CKD[1:0]
rw
7
ARPE
rw
rw
6
5
Reserved
4
3
2
1
0
OPM
URS
UDIS
CEN
rw
rw
rw
rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).
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Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt if enabled:
–
Counter overflow
–
Setting the UG bit
1: Only counter overflow generates an update interrupt if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update event (UEV) generation.
0: UEV enabled. An UEV is generated by one of the following events:
–
Counter overflow
–
Setting the UG bit
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
CEN is cleared automatically in one-pulse mode, when an update event occurs.
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14.4.2
TIM9 slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
15
14
13
12
11
Reserved
10
9
8
7
6
MSM
rw
5
4
TS[2:0]
rw
rw
rw
3
Res.
2
1
0
SMS[2:0]
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful in
order to synchronize several timers on a single external event.
Bits 6:4 TS: Trigger selection
This bitfield selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: Reserved.
See Table 56: TIMx internal trigger connection on page 388 for more details on the meaning
of ITRx for each timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input control register and Control register
descriptions.
000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
clock
001: Reserved
010: Reserved
011: Reserved
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops
are both controlled
110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter
Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
Gated mode checks the level of the trigger signal.
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Table 56. TIMx internal trigger connection
14.4.3
Slave TIM
ITR0 (TS =’ 000’)
ITR1 (TS = ‘001’)
ITR2 (TS = ‘010’)
ITR3 (TS = ’011’)
TIM2
TIM1
Reserved
TIM3
TIM4
TIM3
TIM1
TIM2
TIM5
TIM4
TIM4
TIM1
TIM2
TIM3
Reserved
TIM5
TIM2
TIM3
TIM4
Reserved
TIM9
TIM2
TIM3
TIM10
TIM11
TIM9 Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
TIE
Reserved
Bits 15:7
6
rw
Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5:3
Reserved, must be kept at reset value.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.
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14.4.4
TIM9 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
Reserved
Bits 15:11
12
11
10
9
8
CC2OF CC1OF
rc_w0
rc_w0
7
Reserved
6
TIF
rc_w0
5
4
Reserved
3
2
1
0
CC2IF
CC1IF
UIF
rc_w0
rc_w0
rc_w0
Reserved, must be kept at reset value.
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7
Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bits 5:3
Reserved, must be kept at reset value.
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Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow and if UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and
UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to the synchro control register
description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.
14.4.5
TIM9 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
TG
Reserved
w
5
4
Reserved
3
2
1
0
CC2G
CC1G
UG
w
w
w
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled
Bits 5:3 Reserved, must be kept at reset value.
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Bit 2 CC2G: Capture/compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
the CC1IF flag is set, the corresponding interrupt is sent if enabled.
If channel CC1 is configured as input:
The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. The prescaler counter
is also cleared and the prescaler ratio is not affected. The counter is cleared.
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TIM9 capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits in this register have different functions in input and output modes. For a given bit, OCxx
describes its function when the channel is configured in output mode, ICxx describes its
function when the channel is configured in input mode. So you must take care that the same
bit can have different meanings for the input stage and the output stage.
15
14
Res.
13
12
OC2M[2:0]
IC2F[3:0]
rw
rw
rw
11
10
OC2PE OC2FE
IC2PSC[1:0]
rw
rw
rw
9
8
CC2S[1:0]
rw
rw
7
6
Res.
5
4
OC1M[2:0]
IC1F[3:0]
rw
rw
rw
3
2
OC1PE OC1FE
IC1PSC[1:0]
rw
rw
rw
1
0
CC1S[1:0]
rw
rw
Output compare mode
Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register
Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 6:4 OC1M: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N
depend on the CC1P and CC1NP bits, respectively.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. The OC1REF signal is forced high when the
TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the
TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
100: Force inactive level - OC1REF is forced low
101: Force active level - OC1REF is forced high
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else it is inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1, else it is active (OC1REF=’1’)
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else it is active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1
else it is inactive.
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
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Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken into account immediately
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded into the active register at each update event
Note: The PWM mode can be used without validating the preload register only in one-pulse
mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on the counter and CCR1 values even when the
trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the
trigger input is 5 clock cycles
1: An active edge on the trigger input acts like a compare match on the CC1 output. Then,
OC is set to the compare level independently of the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE
acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bitfield defines the frequency used to sample the TI1 input and the length of the digital
filter applied to TI1. The digital filter is made of an event counter in which N events are
needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6
0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8
0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5
0011: fSAMPLING=fCK_INT, N=8 1011: fSAMPLING=fDTS/16, N=6
0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8
0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5
0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6
0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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14.4.7
TIM9 capture/compare enable register (TIMx_CCER)
Address offset: 0x20
Reset value: 0x0000
15
14
13
12
11
Reserved
10
9
8
7
CC2NP
rw
6
Res.
5
4
3
CC2P
CC2E
CC1NP
rw
rw
rw
2
Res.
1
0
CC1P
CC1E
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 CC2NP: Capture/Compare 2 output Polarity
refer to CC1NP description
Bits 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity
CC1 channel configured as output: CC1NP must be kept cleared
CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define
TI1FP1/TI2FP1 polarity (refer to CC1P description).
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high.
1: OC1 active low.
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
Note: 11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset,
external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This
configuration must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
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Table 57. Output control bit for standard OCx channels
CCxE bit
OCx output state
0
Output disabled (OCx=’0’, OCx_EN=’0’)
1
OCx=OCxREF + Polarity, OCx_EN=’1’
Note:
The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.
14.4.8
TIM9 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CNT[15:0]: Counter value
14.4.9
TIM9 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
12
11
10
9
PSC[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.
14.4.10
TIM9 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ARR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to the Section 14.3.1: Time-base unit on page 369 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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14.4.11
TIM9 capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signaled on the OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
14.4.12
TIM9 capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signalled on the OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
14.4.13
TIM9 register map
TIM9 registers are mapped as 16-bit addressable registers as described below:
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Reset value
0
0
0
0
0
IC2
PSC
[1:0]
CC2S
[1:0]
0
0
0
0
URS
UDIS
CEN
UIE
CC1
S
[1:0]
0
0
0
0
IC1
PSC
[1:0]
CC1
S
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CC1E
0
CC1P
TIMx_ARR
0
Reserved
TIMx_PSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT[15:0]
Reserved
0
0
0
0
0
0
0
0
0
0
PSC[15:0]
Reserved
0
0
0
0
0
0
0
0
0
0
ARR[15:0]
Reserved
0
0
0
0
0
0
0
0
0
0
Reserved
0x30
TIMx_CCR1
CCR1[15:0]
Reserved
Reset value
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0
CC2E
TIMx_CNT
0
Reset value
0x34
0
0
0
CC1NP
Reserved
Reset value
0x2C
0
IC1F[3:0]
CC2NP
TIMx_CCER
Reset value
0x28
0
0
Reserved
Reset value
0x24
0
0
UG
0
0
CC1G
0
0
CC2G
0
0
IC2F[3:0]
Reserved
0x1C
0x20
0
OC1M
[2:0]
0
OC1FE
0
Reserved
Reset value
TIMx_CCMR1
Input Capture
mode
OC2FE
Reserved
CC2S
[1:0]
0
0
Reserved
0
OC2M
[2:0]
0
OC1PE
Reserved
OC2PE
0x18
Reserved
0
Reset value
TIMx_CCMR1
Output Compare
mode
Reserved
0
UIF
TIF
0
Reserved
0
TG
TIMx_EGR
CC1OF
Reserved
Reset value
0x14
SMS[2:0]
0
CC2OF
TIMx_SR
0
0
CC1IE
Reserved
Reset value
0x10
0
0
0
CC1IF
TIMx_DIER
0
TIE
0
TS[2:0]
0
OPM
Reserved
Reset value
0x0C
Reserved
Reserved
TIMx_SMCR
0
0
CC2P
0x08
0
MSM
Reset value
CKD
[1:0]
CC2IE
Reserved
CC2IF
TIMx_CR1
ARPE
0x00
Register
Reserved
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 58. TIM9 register map and reset values
0
DocID026448 Rev 1
0
0
0
0
0
0
0
0
0
RM0383
General-purpose timers (TIM9 to TIM11)
Offset
0x38
Register
TIMx_CCR2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 58. TIM9 register map and reset values (continued)
CCR2[15:0]
Reserved
Reset value
0x3C to
0x4C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Refer to Table 3 on page 41 for the register boundary addresses.
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14.5
RM0383
TIM10/11 registers
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
14.5.1
TIM10/11 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
11
10
Reserved
9
8
CKD[1:0]
rw
7
ARPE
rw
rw
6
5
4
Reserved
3
2
1
0
URS
UDIS
CEN
rw
rw
rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 URS: Update request source
This bit is set and cleared by software to select the update interrupt (UEV) sources.
0: Any of the following events generate an UEV if enabled:
–
Counter overflow
–
Setting the UG bit
1: Only counter overflow generates an UEV if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update interrupt (UEV) event
generation.
0: UEV enabled. An UEV is generated by one of the following events:
–
Counter overflow
–
Setting the UG bit.
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
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14.5.2
TIM status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
12
11
10
Reserved
Bits 15:10
9
8
7
6
CC1OF
5
4
3
2
Reserved
rc_w0
1
0
CC1IF
UIF
rc_w0
rc_w0
Reserved, must be kept at reset value.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:2
Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–
At overflow and if UDIS=’0’ in the TIMx_CR1 register.
–
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.
14.5.3
TIM event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
Reserved
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5
4
3
2
1
0
CC1G
UG
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Bits 15:2 Reserved, must be kept at reset value.
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.
14.5.4
TIM10/11 capture/compare mode register 1
(TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15
14
13
12
11
10
9
8
7
6
Reserved
Reserved
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5
4
OC1M[2:0]
rw
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rw
2
OC1PE OC1FE
IC1F[3:0]
rw
3
IC1PSC[1:0]
rw
rw
rw
1
0
CC1S[1:0]
rw
rw
RM0383
General-purpose timers (TIM9 to TIM11)
Output compare mode
Bits 15:7
Reserved, must be kept at reset value.
Bits 6:4 OC1M: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 is
derived. OC1REF is active high whereas OC1 active level depends on CC1P bit.
000: Frozen. The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.
111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.
Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison
changes or when the output compare mode switches from frozen to PWM mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then
set to the compare level independently of the result of the comparison. Delay to sample the
trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the
channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10:
11:
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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Input capture mode
Bits 15:8
Reserved, must be kept at reset value.
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6
0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8
0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5
0011: fSAMPLING=fCK_INT, N=81011: fSAMPLING=fDTS/16, N=6
0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8
0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5
0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6
0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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General-purpose timers (TIM9 to TIM11)
14.5.5
TIM10/11 capture/compare enable register
(TIMx_CCER)
Address offset: 0x20
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
CC1NP
Reserved
rw
2
Res.
1
0
CC1P
CC1E
rw
rw
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
CC1 channel configured as output: CC1NP must be kept cleared.
CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define
TI1FP1 polarity (refer to CC1P description).
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted.
01: inverted/falling edge
Circuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted.
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not
inverted.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled
Table 59. Output control bit for standard OCx channels
CCxE bit
Note:
OCx output state
0
Output Disabled (OCx=’0’, OCx_EN=’0’)
1
OCx=OCxREF + Polarity, OCx_EN=’1’
The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
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14.5.6
RM0383
TIM10/11 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CNT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CNT[15:0]: Counter value
14.5.7
TIM10/11 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
12
11
10
9
8
rw
rw
rw
rw
rw
rw
rw
rw
PSC[15:0]
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.
14.5.8
TIM10/11 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ARR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 14.3.1: Time-base unit on page 369 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.
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General-purpose timers (TIM9 to TIM11)
14.5.9
TIM10/11 capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
14.5.10
TIM11 option register 1 (TIM11_OR)
Address offset: 0x50
Reset value: 0x0x0000
15
14
13
12
11
10
9
8
7
Reserved
6
5
4
3
2
1
0
TI1_RMP[1:0]
rw
Bits 15:2 Reserved, must be kept at reset value.
Bits 1:0 TI1_RMP[1:0]: TIM11 Input 1 remapping capability
Set and cleared by software.
00,01,11: TIM11 Channel1 is connected to the GPIO (refer to the Alternate function mapping
table in the datasheets).
10: HSE_RTC clock (HSE divided by programmable prescaler) is connected to the
TIM11_CH1 input for measurement purposes.
14.5.11
TIM10/11 register map
TIMx registers are mapped as 16-bit addressable registers as described in the tables below:
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General-purpose timers (TIM9 to TIM11)
RM0383
Reset value
0x08
TIMx_SMCR
CKD
[1:0]
0
0
0
Reserved
CEN
Reserved
URS
TIMx_CR1
UDIS
0x00
Register
ARPE
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 60. TIM10/11 register map and reset values
0
0
0
Reserved
Reserved
Reset value
0x14
Reserved
0
TIMx_EGR
Reserved
Reset value
0
TIMx_CCMR1
Input capture
mode
0
IC1F[3:0]
Reserved
Reset value
0
0
0
0
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UIE
0
0
IC1
PSC
[1:0]
CC1S
[1:0]
0
0
0
0
CC1P
CC1E
TIMx_CNT
0
0
0
0
0
0
0
CNT[15:0]
Reserved
TIMx_PSC
0
0
0
0
0
0
0
0
0
0
PSC[15:0]
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
TIMx_CCR1
CCR1[15:0]
Reserved
Reset value
0x38 to
0x4C
0
0
0x30
0x34
0
0
Reserved
Reset value
0x28
CC1S
[1:0]
CC1NP
TIMx_CCER
Reset value
0x24
0
Reserved
0x1C
0x20
0
0
Reserved
0x18
OC1M
[2:0]
Reserved
0
OC1FE
TIMx_CCMR1
Output compare
mode
0
OC1PE
Reset value
0
UIF
TIMx_SR
CC1OF
0x10
0
UG
Reserved
Reset value
CC1IF
TIMx_DIER
CC1G
0x0C
CC1IE
Reset value
0
Reserved
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0
0
0
0
0
0
0
0
0
RM0383
General-purpose timers (TIM9 to TIM11)
0x50
Register
TIMx_OR
TI1_RMP
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 60. TIM10/11 register map and reset values (continued)
Reserved
Reset value
0
0
Refer to Table 3 on page 41 for the register boundary addresses.
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Independent watchdog (IWDG)
RM0383
15
Independent watchdog (IWDG)
15.1
IWDG introduction
The STM32F411xC/E device has two embedded watchdog peripherals which offer a
combination of high safety level, timing accuracy and flexibility of use. Both watchdog
peripherals (Independent and Window) serve to detect and resolve malfunctions due to
software failure, and to trigger system reset or an interrupt (window watchdog only) when
the counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails. The window watchdog (WWDG) clock is
prescaled from the APB1 clock and has a configurable time-window that can be
programmed to detect abnormally late or early application behavior.
The IWDG is best suited to applications which require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. The WWDG is best suited to applications which require the watchdog to react
within an accurate timing window. For further information on the window watchdog, refer to
Section 16 on page 416.
15.2
15.3
IWDG main features
•
Free-running downcounter
•
clocked from an independent RC oscillator (can operate in Standby and Stop modes)
•
Reset (if watchdog activated) when the downcounter value of 0x000 is reached
IWDG functional description
Figure 156 shows the functional blocks of the independent watchdog module.
When the independent watchdog is started by writing the value 0xCCCC in the Key register
(IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it
reaches the end of count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value
is reloaded in the counter and the watchdog reset is prevented.
15.3.1
Hardware watchdog
If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and will generate a reset unless the Key register is
written by the software before the counter reaches end of count.
15.3.2
Register access protection
Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you
must first write the code 0x5555 in the IWDG_KR register. A write access to this register
with a different value will break the sequence and register access will be protected again.
This implies that it is the case of the reload operation (writing 0xAAAA).
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Independent watchdog (IWDG)
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
15.3.3
Debug mode
When the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the IWDG
counter either continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module. For more details, refer to Section 23.16.2: Debug support
for timers, watchdog and I2C.
Figure 156. Independent watchdog block diagram
#/2%
0RESCALERREGISTER
)7$'?02
3TATUSREGISTER
)7$'?32
2ELOADREGISTER
)7$'?2,2
+EYREGISTER
)7$'?+2
BITRELOADVALUE
BIT
,3)
K(Z PRESCALER
BITDOWNCOUNTER
)7$'RESET
6$$VOLTAGEDOMAIN
-36
Note:
The watchdog function is implemented in the VDD voltage domain that is still functional in
Stop and Standby modes.
Table 61. Min/max IWDG timeout period at 32 kHz (LSI)(1)
Prescaler divider
PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4
0
0.125
512
/8
1
0.25
1024
/16
2
0.5
2048
/32
3
1
4096
/64
4
2
8192
/128
5
4
16384
/256
6
32768
1. These timings are given for a 32 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
15.4
IWDG registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
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Independent watchdog (IWDG)
15.4.1
RM0383
Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
31 30 29 28 27 26 25
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 KEY[15:0]: Key value (write only, read 0000h)
These bits must be written by software at regular intervals with the key value AAAAh,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers
(see Section 15.3.2)
Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is
selected)
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15.4.2
Independent watchdog (IWDG)
Prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PR[2:0]
Reserved
rw
rw
rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected seeSection 15.3.2. They are written by software to
select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in
order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG_SR
register is reset.
15.4.3
Reload register (IWDG_RLR)
Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29 28 27 26 25
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
RL[11:0]
Reserved
rw rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 RL[11:0]: Watchdog counter reload value
These bits are write access protected see Section 15.3.2. They are written by software to
define the value to be loaded in the watchdog counter each time the value AAAAh is written
in the IWDG_KR register. The watchdog counter counts down from this value. The timeout
period is a function of this value and the clock prescaler. Refer to Table 61.
The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be up to date/valid if a write operation to this register is ongoing on this
register. For this reason the value read from this register is valid only when the RVU bit
in the IWDG_SR register is reset.
15.4.4
Status register (IWDG_SR)
Address offset: 0x0C
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Independent watchdog (IWDG)
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Reset value: 0x0000 0000 (not reset by Standby mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
RVU PVU
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the VDD voltage domain
(takes up to 5 RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
Bit 0 PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the VDD voltage
domain (takes up to 5 RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.
Note:
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If several reload values or prescaler values are used by application, it is mandatory to wait
until RVU bit is reset before changing the reload value and to wait until PVU bit is reset
before changing the prescaler value. However, after updating the prescaler and/or the
reload value it is not necessary to wait until RVU or PVU is reset before continuing code
execution (even in case of low-power mode entry, the write operation is taken into account
and will complete)
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15.4.5
Independent watchdog (IWDG)
IWDG register map
The following table gives the IWDG register map and reset values.
0x04
0x08
0x0C
IWDG_KR
Reset value
IWDG_PR
Reset value
IWDG_SR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR[2:0]
Reserved
Reset value
IWDG_RLR
KEY[15:0]
Reserved
0
0
0
1
1
1
PVU
0x00
Register
RVU
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 62. IWDG register map and reset values
0
0
RL[11:0]
Reserved
1
1
Reserved
Reset value
1
1
1
1
1
1
1
Refer to Table 3 on page 41 for the register boundary addresses.
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Window watchdog (WWDG)
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16
Window watchdog (WWDG)
16.1
WWDG introduction
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the
application program to abandon its normal sequence. The watchdog circuit generates an
MCU reset on expiry of a programmed time period, unless the program refreshes the
contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also
generated if the 7-bit downcounter value (in the control register) is refreshed before the
downcounter has reached the window register value. This implies that the counter must be
refreshed in a limited window.
16.2
WWDG main features
•
Programmable free-running downcounter
•
Conditional reset
•
16.3
–
Reset (if watchdog activated) when the downcounter value becomes less than
0x40
–
Reset (if watchdog activated) if the downcounter is reloaded outside the window
(see Figure 158)
Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when
the downcounter is equal to 0x40.
WWDG functional description
If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the
7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates
a reset. If the software reloads the counter while the counter is greater than the value stored
in the window register, then a reset is generated.
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Window watchdog (WWDG)
Figure 157. Watchdog block diagram
Watchdog configuration register (WWDG_CFR)
RESET
-
comparator
= 1 when
T6:0 > W6:0
W6
W5
W4
W3
W2
W1
W0
CMP
Write WWDG_CR
Watchdog control register (WWDG_CR)
WDGA T6
T5
T4
T3
T2
T1
T0
6-bit downcounter (CNT)
PCLK1
(from RCC clock controller)
WDG prescaler
(WDGTB)
The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value. The value to be stored in the WWDG_CR
register must be between 0xFF and 0xC0:
Enabling the watchdog
The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.
Controlling the downcounter
This downcounter is free-running: It counts down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 158).The Configuration register (WWDG_CFR) contains the high limit of the window:
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x3F. Figure 158 describes the window watchdog
process.
Note:
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
Advanced watchdog interrupt feature
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the actual reset is generated. The EWI interrupt is enabled by
setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value
0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR)
can be used to trigger specific actions (such as communications or data logging), before
resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
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Window watchdog (WWDG)
RM0383
case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note:
When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.
16.4
How to program the watchdog timeout
You can use the formula in Figure 158 to calculate the WWDG timeout.
Warning:
When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 158. Window watchdog timing diagram
4;=#.4DOWNCOUNTER
7;=
X&
2EFRESHNOTALLOWED
2EFRESHALLOWED
4IME
4BIT
2%3%4
AIB
The formula to calculate the timeout value is given by:
WDGTB
t WWDG = tPCLK1 × 4096 × 2
× ( t [ 5:0 ] + 1 )
( ms )
where:
tWWDG: WWDG timeout
tPCLK1: APB1 clock period measured in ms
Refer to the table below for the minimum and maximum values of the TWWDG.
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16.5
Window watchdog (WWDG)
Debug mode
When the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the
WWDG counter either continues to work normally or stops, depending on
DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to
Section 23.16.2: Debug support for timers, watchdog and I2C.
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Window watchdog (WWDG)
16.6
RM0383
WWDG registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
16.6.1
Control register (WWDG_CR)
Address offset: 0x00
Reset value: 0x0000 007F
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
6
5
4
19
18
17
16
3
2
1
0
Reserved
Reserved
7
WDGA
T[6:0]
rs
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every (4096 x
2WDGTB) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6
becomes cleared).
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Window watchdog (WWDG)
16.6.2
Configuration register (WWDG_CFR)
Address offset: 0x04
Reset value: 0x0000 007F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Reserved
15
14
13
12
11
10
9
EWI
Reserved
8
7
WDGTB[1:0]
rs
W[6:0]
rw
rw
Bit 31:10 Reserved, must be kept at reset value.
Bit 9 EWI: Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
Bits 8:7 WDGTB[1:0]: Timer base
The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK1 div 4096) div 1
01: CK Counter Clock (PCLK1 div 4096) div 2
10: CK Counter Clock (PCLK1 div 4096) div 4
11: CK Counter Clock (PCLK1 div 4096) div 8
Bits 6:0 W[6:0]: 7-bit window value
These bits contain the window value to be compared to the downcounter.
16.6.3
Status register (WWDG_SR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6
5
4
3
2
1
16
Reserved
15
14
13
12
11
10
9
8
7
Reserved
0
EWIF
rc_w0
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wakeup interrupt flag
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing ‘0. A write of ‘1 has no effect. This bit is also set if the interrupt is not
enabled.
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Window watchdog (WWDG)
16.6.4
RM0383
WWDG register map
The following table gives the WWDG register map and reset values.
WWDG_CR
Reserved
Reserved
Reset value
0x08
WWDG_SR
Reserved
Reset value
0
0
0
1
1
1
1
1
1
1
1
1
W[6:0]
1
1
1
1
1
0
Refer to Table 3 on page 41 for the register boundary addresses.
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WDGTB0
WWDG_CFR
EWI
0x04
0
WDGTB1
Reset value
T[6:0]
EWIF
0x00
Register
WDGA
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 63. WWDG register map and reset values
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Real-time clock (RTC)
17
Real-time clock (RTC)
17.1
Introduction
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC also includes an automatic wakeup unit to
manage low power modes.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day
of week), date (day of month), month, and year, expressed in binary coded decimal format
(BCD). The sub-seconds value is also available in binary format
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator
accuracy.
After backup domain reset, all RTC registers are protected against possible parasitic write
accesses.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low power mode or under reset).
17.2
RTC main features
The RTC unit main features are the following (see Figure 159: RTC block diagram):
•
Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year.
•
Daylight saving compensation programmable by software.
•
Two programmable alarms with interrupt function. The alarms can be triggered by any
combination of the calendar fields.
•
Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup
interrupt.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Accurate synchronization with an external clock using the subsecond shift feature.
•
Maskable interrupts/events:
•
–
Alarm A
–
Alarm B
–
Wakeup interrupt
–
Timestamp
–
Tamper detection
Digital calibration circuit (periodic counter correction)
–
5 ppm accuracy
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–
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0.95 ppm accuracy, obtained in a calibration window of several seconds
•
Timestamp function for event saving (1 event)
•
Tamper detection:
–
Tamper event with configurable filter and internal pull-up.
•
20 backup registers (80 bytes). The backup registers are reset when a tamper
detection event occurs.
•
Alternate function output (RTC_OUT) which selects one of the following two outputs:
–
RTC_CALIB: 512 Hz or 1 Hz clock output (with an LSE frequency of 32.768 kHz).
This output is enabled by setting the COE bit in the RTC_CR register. It is routed
to the device RTC_AF1 function.
–
RTC_ALARM (Alarm A, Alarm B or wakeup).
This output is selected by configuring the OSEL[1:0] bits in the RTC_CR register.
It is routed to the device RTC_AF1 function.
•
RTC additional function inputs:
–
RTC_TS: timestamp event detection. It is routed to the device RTC_AF1 function.
–
RTC_TAMP1: TAMPER1 event detection. It is routed to the device RTC_AF1
function.
–
RTC_REFIN: reference clock input (usually the mains, 50 or 60 Hz).
Refer to Section 8.3.15: Selection of RTC additional functions and the STM32F411xx
datasheet pin definition table.
Figure 159. RTC block diagram
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1. The RTC_AF1 additional function is connected to PC13.
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Real-time clock (RTC)
17.3
RTC functional description
17.3.1
Clock and prescalers
The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to Section 6: Reset and clock control (RCC) for
STM32F411xC/ESTM32F411xC/E.
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 159: RTC block diagram):
Note:
•
A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
•
A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 222.
This corresponds to a maximum input frequency of around 4 MHz.
fck_apre is given by the following formula:
f RTCCLK
f CK_APRE = --------------------------------------PREDIV_A + 1
The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
fck_spre is given by the following formula:
f RTCCLK
f CK_SPRE = ----------------------------------------------------------------------------------------------( PREDIV_S + 1 ) × ( PREDIV_A + 1 )
The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see Section 17.3.4: Periodic auto-wakeup for details).
17.3.2
Real-time clock and calendar
The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK1 (APB1 clock).
•
RTC_SSR for the subseconds
•
RTC_TR for the time
•
RTC_DR for the date
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Every two RTCCLK periods, the current calendar value is copied into the shadow registers,
and the RSF bit of RTC_ISR register is set (see Section 17.6.4). The copy is not performed
in Stop and Standby mode. When exiting these modes, the shadow registers are updated
after up to 2 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow
registers. It is possible to make a direct access to the calendar registers by setting the
BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user
accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the
frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock
(fRTCCLK).
The shadow registers are reset by system reset.
17.3.3
Programmable alarms
The RTC unit provides two programmable alarms, Alarm A and Alarm B.
The programmable alarm functions are enabled through the ALRAIE and ALRBIE bits in the
RTC_CR register. The ALRAF and ALRBF flags are set to 1 if the calendar subseconds,
seconds, minutes, hours, date or day match the values programmed in the alarm registers
RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR, respectively.
Each calendar field can be independently selected through the MSKx bits of the
RTC_ALRMAR and RTC_ALRMBR registers, and through the MASKSSx bits of the
RTC_ALRMASSR and RTC_ALRMBSSR registers. The alarm interrupts are enabled
through the ALRAIE and ALRBIE bits in the RTC_CR register.
Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the
RTC_ALARM output. RTC_ALARM polarity can be configured through bit POL in the
RTC_CR register.
Caution:
If the seconds field is selected (MSK0 bit reset in RTC_ALRMAR or RTC_ALRMBR), the
synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to
ensure correct behavior.
17.3.4
Periodic auto-wakeup
The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR register.
The wakeup timer clock input can be:
•
RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period
from 122 µs to 32 s, with a resolution down to 61µs.
•
ck_spre (usually 1 Hz internal clock)
When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to
around 36 hours with one-second resolution. This large programmable time range is
divided in 2 parts:
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–
from 1s to 18 hours when WUCKSEL [2:1] = 10
–
and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is
added to the 16-bit counter current value.When the initialization sequence is
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Real-time clock (RTC)
complete (see Programming the wakeup timer on page 428), the timer starts
counting down.When the wakeup function is enabled, the down-counting remains
active in low power modes. In addition, when it reaches 0, the WUTF flag is set in
the RTC_ISR register, and the wakeup counter is automatically reloaded with its
reload value (RTC_WUTR register value).
The WUTF flag must then be cleared by software.
When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2
register, it can exit the device from low power modes.
The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been
enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARMpolarity can be
configured through the POL bit in the RTC_CR register.
System reset, as well as low power modes (Sleep, Stop and Standby) have no influence on
the wakeup timer.
17.3.5
RTC initialization and configuration
RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC
register accesses except on read accesses to calendar shadow registers when
BYPSHAD=0.
RTC register write protection
After system reset, the RTC registers are protected against parasitic write access with the
DBP bit of the PWR power control register (PWR_CR). The DBP bit must be set to enable
RTC registers write access.
After backup domain reset, all the RTC registers are write-protected. Writing to the RTC
registers is enabled by writing a key into the Write Protection register, RTC_WPR.
The following steps are required to unlock the write protection on all the RTC registers
except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR.
1.
Write ‘0xCA’ into the RTC_WPR register.
2.
Write ‘0x53’ into the RTC_WPR register.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.
Calendar initialization and configuration
To program the initial time and date calendar values, including the time format and the
prescaler configuration, the following sequence is required:
1.
Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the
calendar counter is stopped and its value can be updated.
2.
Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when
INITF is set to 1. It takes from 1 to 2 RTCCLK clock cycles (due to clock
synchronization).
3.
To generate a 1 Hz clock for the calendar counter, program first the synchronous
prescaler factor in RTC_PRER register, and then program the asynchronous prescaler
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factor. Even if only one of the two fields needs to be changed, 2 separate write
accesses must be performed to the RTC_PRER register.
4.
Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR),
and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR
register.
5.
Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is
then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
When the initialization sequence is complete, the calendar starts counting.
Note:
After a system reset, the application can read the INITS flag in the RTC_ISR register to
check if the calendar has been initialized or not. If this flag equals 0, the calendar has not
been initialized since the year field is set at its backup domain reset default value (0x00).
To read the calendar after initialization, the software must first check that the RSF flag is set
in the RTC_ISR register.
Daylight saving time
The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP
of the RTC_CR register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one
single operation without going through the initialization procedure.
In addition, the software can use the BKP bit to memorize this operation.
Programming the alarm
A similar procedure must be followed to program or update the programmable alarm (Alarm
A or Alarm B):
Note:
1.
Clear ALRAE or ALRBIE in RTC_CR to disable Alarm A or Alarm B.
2.
Poll ALRAWF or ALRBWF in RTC_ISR until it is set to make sure the access to alarm
registers is allowed. This takes 1 to 2 RTCCLK clock cycles (due to clock
synchronization).
3.
Program the Alarm A or Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR or
RTC_ALRMBSSR/RTC_ALRMBR).
4.
Set ALRAE or ALRBIE in the RTC_CR register to enable Alarm A or Alarm B again.
Each change of the RTC_CR register is taken into account after 1 to 2 RTCCLK clock cycles
due to clock synchronization.
Programming the wakeup timer
The following sequence is required to configure or change the wakeup timer auto-reload
value (WUT[15:0] in RTC_WUTR):
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1.
Clear WUTE in RTC_CR to disable the wakeup timer.
2.
Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload
counter and to WUCKSEL[2:0] bits is allowed. It takes 1 to 2 RTCCLK clock cycles
(due to clock synchronization).
3.
Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection
(WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the timer again.
The wakeup timer restarts down-counting.
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17.3.6
Real-time clock (RTC)
Reading the calendar
To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1
clock frequency (fPCLK1) must be equal to or greater than seven times the fRTCCLK RTC
clock frequency. This ensures a secure behavior of the synchronization mechanism.
If the APB1 clock frequency is less than seven times the RTC clock frequency, the software
must read the calendar time and date registers twice. If the second read of the RTC_TR
gives the same result as the first read, this ensures that the data is correct. Otherwise a third
read access must be done. In any case the APB1 clock frequency must never be lower than
the RTC clock frequency.
The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the
RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two
RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or
RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is
read. In case the software makes read accesses to the calendar in a time interval smaller
than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and
then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR
and RTC_DR registers.
After waking up from low power mode (Stop or Standby), RSF must be cleared by software.
The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and
RTC_DR registers.
The RSF bit must be cleared after wakeup and not before entering low power mode.
Note:
After a system reset, the software must wait until RSF is set before reading the RTC_SSR,
RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to
their default values.
After an initialization (refer to Calendar initialization and configuration on page 427): the
software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR
registers.
After synchronization (refer to Section 17.3.8: RTC synchronization): the software must wait
until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow
registers)
Reading the calendar registers gives the values from the calendar counters directly, thus
eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting
from low power modes (STOP or Standby), since the shadow registers are not updated
during these modes.
When the BYPSHAD bit is set to 1, the results of the different registers might not be
coherent with each other if an RTCCLK edge occurs between two read accesses to the
registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge
occurs during the read operation. The software must read all the registers twice, and then
compare the results to confirm that the data is coherent and correct. Alternatively, the
software can just compare the two results of the least-significant calendar register.
Note:
While BYPSHAD=1, instructions which read the calendar registers require one extra APB
cycle to complete.
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Resetting the RTC
The calendar shadow registers (RTC_SSR,RTC_TR and RTC_DR) and some bits of the
RTC status register (RTC_ISR) are reset to their default values by all available system reset
sources.
On the contrary, the following registers are resetted to their default values by a backup
domain reset and are not affected by a system reset: the RTC current calendar registers,
the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC
calibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR),
the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper
and alternate function configuration register (RTC_TAFCR), the RTC backup registers
(RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers
(RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR).
In addition, the RTC keeps on running under system reset if the reset source is different
from a backup domain reset. When a backup domain reset occurs, the RTC is stopped and
all the RTC registers are set to their reset values.
17.3.8
RTC synchronization
The RTC can be synchronized to a remote clock with a high degree of precision. After
reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the
precise offset between the times being maintained by the remote clock and the RTC. The
RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a
second using RTC_SHIFTR.
RTC_SSR contains the value of the synchronous prescaler’s counter. This allows one to
calculate the exact time being maintained by the RTC down to a resolution of
1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by
increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution
allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing PREDIV_S means that PREDIV_A must be decreased in order to
maintain the synchronous prescaler’s output at 1 Hz. In this way, the frequency of the
asynchronous prescaler’s output increases, which may increase the RTC dynamic
consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing
to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a
resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the
SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock.
If at the same time the ADD1S bit is set, this results in adding one second and at the same
time subtracting a fraction of second, so this will advance the clock.
Caution:
Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that
no overflow will occur.
As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF
flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by
hardware as soon as the shift operation has completed.
Caution:
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This synchronization feature is not compatible with the reference clock detection feature:
firmware must not write to RTC_SHIFTR when REFCKON=1.
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17.3.9
Real-time clock (RTC)
RTC reference clock detection
The RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually
the mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision
than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit
of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to
compensate for the imprecision of the calendar update frequency (1 Hz).
Each 1 Hz clock edge is compared to the nearest reference clock edge (if one is found
within a given time window). In most cases, the two clock edges are properly aligned. When
the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts
the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism,
the calendar becomes as precise as the reference clock.
The RTC detects if the reference clock source is present by using the 256 Hz clock
(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time
window around each of the calendar updates (every 1 s). The window equals 7 ck_apre
periods when detecting the first reference clock edge. A smaller window of 3 ck_apre
periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the asynchronous prescaler which
outputs the ck_apre clock is forced to reload. This has no effect when the reference clock
and the 1 Hz clock are aligned because the prescaler is being reloaded at the same
moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little
for them to be aligned with the reference clock.
If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window),
the calendar is updated continuously based solely on the LSE clock. The RTC then waits for
the reference clock using a large 7 ck_apre period detection window centered on the
ck_spre edge.
When the reference clock detection is enabled, PREDIV_A and PREDIV_S must be set to
their default values:
•
PREDIV_A = 0x007F
•
PREDIV_S = 0x00FF
Note:
The reference clock detection is not available in Standby mode.
Caution:
The reference clock detection feature cannot be used in conjunction with the coarse digital
calibration: RTC_CALIBR must be kept at 0x0000 0000 when REFCKON=1.
17.3.10
RTC coarse digital calibration
Two digital calibration methods are available: coarse and smooth calibration. To perform
coarse calibration refer to Section 17.6.7: RTC calibration register (RTC_CALIBR).
The two calibration methods are not intended to be used together, the application must
select one of the two methods. Coarse calibration is provided for compatibly reasons. To
perform smooth calibration refer to Section 17.3.11: RTC smooth digital calibration and the
Section 17.6.16: RTC calibration register (RTC_CALR)
The coarse digital calibration can be used to compensate crystal inaccuracy by adding
(positive calibration) or masking (negative calibration) clock cycles at the output of the
asynchronous prescaler (ck_apre).
Positive and negative calibration are selected by setting the DCS bit in RTC_CALIBR
register to ‘0’ and ‘1’, respectively.
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When positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute
(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated
sooner, thereby adjusting the effective RTC frequency to be a bit higher.
When negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute
(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated
later, thereby adjusting the effective RTC frequency to be a bit lower.
DC is configured through bits DC[4:0] of RTC_CALIBR register. This number ranges from 0
to 31 corresponding to a time interval (2xDC) ranging from 0 to 62.
The coarse digital calibration can be configured only in initialization mode, and starts when
the INIT bit is cleared. The full calibration cycle lasts 64 minutes. The first 2xDC minutes of
the 64 -minute cycle are modified as just described.
Negative calibration can be performed with a resolution of about 2 ppm while positive
calibration can be performed with a resolution of about 4 ppm. The maximum calibration
ranges from −63 ppm to 126 ppm.
The calibration can be performed either on the LSE or on the HSE clock.
Caution:
Digital calibration may not work correctly if PREDIV_A < 6.
Case of RTCCLK=32.768 kHz and PREDIV_A+1=128
The following description assumes that ck_apre frequency is 256 Hz obtained with an LSE
clock nominal frequency of 32.768 kHz, and PREDIV_A set to 127 (default value).
The ck_spre clock frequency is only modified during the first 2xDC minutes of the 64-minute
cycle. For example, when DC equals 1, only the first 2 minutes are modified. This means
that the first 2xDC minutes of each 64-minute cycle have, once per minute, one second
either shortened by 256 or lengthened by 128 RTCCLK cycles, given that each ck_apre
cycle represents 128 RTCCLK cycles (with PREDIV_A+1=128).
Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125829120 RTCCLK cycles (64min x 60 s/min x 32768 cycles/s). This is
equivalent to +4.069 ppm or-2.035 ppm per calibration step. As a result, the calibration
resolution is +10.5 or −5.27 seconds per month, and the total calibration ranges from +5.45
to −2.72 minutes per month.
In order to measure the clock deviation, a 512 Hz clock is output for calibration.Refer to
Section 17.3.14: Calibration clock output.
17.3.11
RTC smooth digital calibration
RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range
from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series
of small adjustments (adding and/or subtracting individual RTCCLK pulses). These
adjustments are fairly well distributed so that the RTC is well calibrated even when observed
over short durations of time.
The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or
32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit
counter, cal_cnt[19:0], clocked by RTCCLK.
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Real-time clock (RTC)
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles
to be masked during the 32-second cycle:
Note:
•
Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32second cycle.
•
Setting CALM[1] to 1 causes two additional cycles to be masked
•
Setting CALM[2] to 1 causes four additional cycles to be masked
•
and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.
CALM[8:0] (RTC_CALRx) specifies the number of RTCCLK pulses to be masked during the
32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked
during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1
causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1
causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000);
and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine
resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP
to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means
that 512 clocks are added during every 32-second cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can
be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm
to +488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (FCAL) given the input frequency
(FRTCCLK) is as follows:
FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]
Calibration when PREDIV_A<3
The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are
set to a value less than 3, CALP is ignored and the calibration operates as if CALP was
equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value
(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock
cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result,
between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to
244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor
of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other
interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather
than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the
calibrated input clock is as follows:
FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct
setting if RTCCLK is exactly 32768.00 Hz.
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Verifying the RTC calibration
RTC precision is performed by measuring the precise frequency of RTCCLK and calculating
the correct CALM value and CALP values. An optional 1 Hz output is provided to allow
applications to measure and verify the RTC precision.Measuring the precise frequency of
the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock
cycles over the measurement period, depending on how the digital calibration cycle is
aligned with the measurement period.
However, this measurement error can be eliminated if the measurement period is the same
length as the calibration cycle period. In this case, the only error observed is the error due to
the resolution of the digital calibration.
•
By default, the calibration cycle period is 32 seconds.
Using this mode and measuring the accuracy of the 1 Hz output over exactly 32
seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32
seconds, due to the limitation of the calibration resolution).
•
CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration
cycle period.
In this case, the RTC precision can be measured during 16 seconds with a maximum
error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the
calibration resolution is reduced, the long term RTC precision is also reduced to 0.954
ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.
•
CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration
cycle period.
In this case, the RTC precision can be measured during 8 seconds with a maximum
error of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also
reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.
Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by
using the follow process:
17.3.12
1.
Poll the RTC_ISR/RECALPF (re-calibration pending flag).
2.
If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then
automatically set to 1
3.
Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration
settings take effect.
Timestamp function
Timestamp is enabled by setting the TSE bit of RTC_CR register to 1.
The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a timestamp event is detected on the pin to which the TIMESTAMP additional function
is mapped. When a timestamp event occurs, the timestamp flag bit (TSF) in RTC_ISR
register is set.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp
event occurs.
If a new timestamp event is detected while the timestamp flag (TSF) is already set, the
timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and
RTC_TSDR) maintain the results of the previous event.
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Note:
Real-time clock (RTC)
TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization
process.
There is no delay in the setting of TSOVF. This means that if two timestamp events are
close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is
recommended to poll TSOVF only after TSF has been set.
Caution:
If a timestamp event occurs immediately after the TSF bit is supposed to be cleared, then
both TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the
same moment, the application must not write ‘0’ into TSF bit unless it has already read it to
‘1’.
Optionally, a tamper event can cause a timestamp to be recorded. See the description of the
TAMPTS control bit in Section 17.6.17: RTC tamper and alternate function configuration
register (RTC_TAFCR). If the timestamp event is on the same pin as a tamper event
configured in filtered mode (TAMPFLT set to a non-zero value), the timestamp on tamper
detection event mode must be selected by setting TAMPTS='1' in RTC_TAFCR register.
TIMESTAMP additional function
The TIMESTAMP additional function is mapped to RTC_AF1.
17.3.13
Tamper detection
One tamper detection input is available. It can be configured either for edge detection, or for
level detection with filtering.
RTC backup registers
The backup registers (RTC_BKPxR) are twenty 32-bit registers for storing 80 bytes of user
application data. They are implemented in the backup domain that remains powered-on by
VBAT when the VDD power is switched off. They are not reset by system reset or when the
device wakes up from Standby mode. They are reset by a backup domain reset
The backup registers are reset when a tamper detection event occurs (see Section 17.6.20:
RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 435.
Tamper detection initialization
The tamper detection input is associated with the TAMP1F flag in the RTC_ISR register. The
input can be enabled by setting the TAMP1E bit to 1 in the RTC_TAFCR register.
A tamper detection event resets all backup registers (RTC_BKPxR).
By setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a
tamper detection event occurs.
Timestamp on tamper event
With TAMPTS set to ‘1 , any tamper event causes a timestamp to occur. In this case, either
the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal
timestamp event occurs. The tamper flag register (TAMP1F) is set at the same time that
TSF or TSOVF is set.
Edge detection on tamper inputs
If the TAMPFLT bits are “00”, the TAMPER pin generates tamper detection events
(RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed
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depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the
TAMPER input are deactivated when edge detection is selected.
Caution:
To avoid losing tamper detection events, the signal used for edge detection is logically
ANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the
TAMPERx pin is enabled.
•
When TAMPxTRG = 0: if the TAMPERx additional function is already high before
tamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon
as TAMPERx is enabled, even if there was no rising edge on TAMPERx after TAMPxE
was set.
•
When TAMPxTRG = 1: if the TAMPERx additional function is already low before
tamper detection is enabled, a tamper event is detected as soon as TAMPERx is
enabled (even if there was no falling edge on TAMPERx after TAMPxE was set.
After a tamper event has been detected and cleared, the TAMPERx additional function
should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the
backup registers (RTC_BKPxR). This prevents the application from writing to the backup
registers while the TAMPERx value still indicates a tamper detection. This is equivalent to a
level detection on the TAMPERx additional function.
Note:
Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting
of the backup registers, the pin to which the TAMPER additional function is mapped should
be externally tied to the correct level.
Level detection with filtering on tamper input
Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits (TAMP1TRG).
The TAMPER input is pre-charged through the I/O internal pull-up resistance before its state
is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is
determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper inputs.
The trade-off between tamper detection latency and power consumption through the pull-up
can be optimized by using TAMPFREQ to determine the frequency of the sampling for level
detection.
Note:
Refer to the datasheets for the electrical characteristics of the pull-up resistors.
TAMPER additional function detection
The TAMPER1 addtional function is mapped to the RTC_AF1 pin.
17.3.14
Calibration clock output
When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the
RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and
PREDIV_A = 0x7F, the RTC_CALIB frequency is fRTCCLK/64. This corresponds to a
calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz.
The RTC_CALIB output is not impacted by the calibration value programmed in
RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling
edges. It is therefore recommended to use rising edges.
If COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] =
0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a
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calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S =
0xFF), with an RTCCLK frequency at 32.768 kHz.
Calibration alternate function output
When the COE bit in the RTC_CR register is set to 1, the calibration alternate function
(RTC_CALIB) is enabled on RTC_OUT.
Note:
When RTC_CALIB or RTC_ALARM is selected, RTC_OUT is automatically configured in
output alternate function.
17.3.15
Alarm output
Three functions can be selected on Alarm output: ALRAF. These functions reflect the
contents of the corresponding flags in the RTC_ISR register.
The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate
function output (RTC_ALARM) in RTC_AF1, and to select the function which is output on
RTC_ALARM.
The polarity of the output is determined by the POL control bit in RTC_CR so that the
opposite of the selected flag bit is output when POL is set to 1.
Alarm alternate function output
RTC_ALARM can be configured in output open drain or output push-pull using the control
bit ALARMOUTTYPE in the RTC_TAFCR register.
Note:
Once RTC_ALARM is enabled, it has priority over RTC_CALIB (COE bit is don't care on
RTC_AF1).
When RTC_CALIB or RTC_ALARM is selected, RTC_OUT is automatically configured in
output alternate function.
17.4
RTC and low power modes
Table 64. Effect of low power modes on RTC
Mode
Description
Sleep
No effect
RTC interrupts cause the device to exit the Sleep mode.
Stop
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
tamper event, RTC time stamp event, and RTC Wakeup cause the device to exit the Stop
mode.
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
Standby tamper event, RTC time stamp event, and RTC Wakeup cause the device to exit the
Standby mode.
17.5
RTC interrupts
All RTC interrupts are connected to the EXTI controller.
To enable the RTC Alarm interrupt, the following sequence is required:
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1.
Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge
sensitivity.
2.
Configure and enable the RTC_Alarm IRQ channel in the NVIC.
3.
Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
To enable the RTC Wakeup interrupt, the following sequence is required:
1.
Configure and enable the EXTI Line 22 in interrupt mode and select the rising edge
sensitivity.
2.
Configure and enable the RTC_WKUP IRQ channel in the NVIC.
3.
Configure the RTC to generate the RTC wakeup timer event.
To enable the RTC Tamper interrupt, the following sequence is required:
1.
Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge
sensitivity.
2.
Configure and Enable the TAMP_STAMP IRQ channel in the NVIC.
3.
Configure the RTC to detect the RTC tamper event.
To enable the RTC TimeStamp interrupt, the following sequence is required:
1.
Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge
sensitivity.
2.
Configure and Enable the TAMP_STAMP IRQ channel in the NVIC.
3.
Configure the RTC to detect the RTC timestamp event.
Table 65. Interrupt control bits
Event flag
Enable
control
bit
Exit the
Sleep
mode
Exit the
Stop
mode
Exit the
Standby
mode
Alarm A
ALRAF
ALRAIE
yes
yes(1)
yes(1)
Alarm B
ALRBF
ALRBIE
yes
yes(1)
yes(1)
Wakeup
WUTF
WUTIE
yes
yes(1)
yes(1)
TSF
TSIE
yes
yes(1)
yes(1)
TAMP1F
TAMPIE
yes
yes(1)
yes(1)
Interrupt event
TimeStamp
Tamper1 detection
1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.
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17.6
RTC registers
Refer to Section 1.1 of the reference manual for a list of abbreviations used in register
descriptions.
The peripheral registers have to be accessed by words (32 bits).
17.6.1
RTC time register (RTC_TR)
The RTC_TR is the calendar time shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 427 and
Reading the calendar on page 429.
Address offset: 0x00
Backup domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31
30
29
28
27
26
25
24
23
Res.
14
13
12
11
MNT[2:0]
rw
rw
10
9
8
MNU[3:0]
rw
rw
21
PM
Reserved
15
22
rw
rw
rw
19
18
HT[1:0]
17
16
HU[3:0]
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
7
Res.
20
ST[2:0]
rw
rw
SU[3:0]
rw
rw
rw
Bits 31-24 Reserved
Bit 23 Reserved, must be kept at reset value.
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bit 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format
Note:
This register is write protected. The write access procedure is described in RTC register
write protection on page 427.
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17.6.2
RM0383
RTC date register (RTC_DR)
The RTC_DR is the calendar date shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 427 and
Reading the calendar on page 429.
Address offset: 0x04
Backup domain reset value: 0x0000_2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31
30
29
28
27
26
25
24
14
13
WDU[2:0]
rw
rw
12
11
10
rw
rw
MT
rw
rw
22
21
20
19
18
YT[3:0]
Reserved
15
23
9
8
rw
rw
MU[3:0]
17
16
YU[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
Reserved
DT[1:0]
rw
DU[3:0]
Bits 31-24 Reserved
Bits 23:20 YT[3:0]: Year tens in BCD format
Bits 19:16 YU[3:0]: Year units in BCD format
Bits 15:13 WDU[2:0]: Week day units
000: forbidden
001: Monday
...
111: Sunday
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format
Note:
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write protection on page 427.
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17.6.3
RTC control register (RTC_CR)
Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
26
25
24
Reserved
15
TSIE
rw
14
13
12
WUTIE ALRBIE ALRAIE
rw
rw
rw
11
23
COE
10
TSE
WUTE
rw
rw
9
8
ALRBE ALRAE
rw
22
20
19
POL
18
17
BKP
16
SUB1H ADD1H
rw
rw
rw
rw
rw
rw
w
w
7
6
5
4
3
2
1
0
DCE
FMT
rw
rw
rw
21
OSEL[1:0]
BYPS
REFCKON TSEDGE
HAD
rw
rw
rw
WUCKSEL[2:0]
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 COE: Calibration output enable
This bit enables the RTC_CALIB output
0: Calibration output disabled
1: Calibration output enabled
Bits 22:21 OSEL[1:0]: Output selection
These bits are used to select the flag to be routed to RTC_ALARM output
00: Output disabled
01: Alarm A output enabled
10:Alarm B output enabled
11: Wakeup output enabled
Bit 20 POL: Output polarity
This bit is used to configure the polarity of RTC_ALARM output
0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).
Bit 19 COSEL: Calibration output selection
When COE=1, this bit selects which signal is output on RTC_CALIB.
0: Calibration output is 512 Hz
1: Calibration output is 1 Hz
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default
values (PREDIV_A=127 and PREDIV_S=255). Refer to Section 17.3.14: Calibration clock
output
Bit 18 BKP: Backup
This bit can be written by the user to memorize whether the daylight saving time change has
been performed or not.
Bit 17 SUB1H: Subtract 1 hour (winter time change)
When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the
current hour is not 0. This bit is always read as 0.
Setting this bit has no effect when current hour is 0.
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time change.
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Bit 16 ADD1H: Add 1 hour (summer time change)
When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit
is always read as 0.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change
Bit 15 TSIE: Timestamp interrupt enable
0: Timestamp Interrupt disable
1: Timestamp Interrupt enable
Bit 14 WUTIE: Wakeup timer interrupt enable
0: Wakeup timer interrupt disabled
1: Wakeup timer interrupt enabled
Bit 13 ALRBIE: Alarm B interrupt enable
0: Alarm B Interrupt disable
1: Alarm B Interrupt enable
Bit 12 ALRAIE: Alarm A interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
Bit 11 TSE: Time stamp enable
0: Time stamp disable
1: Time stamp enable
Bit 10 WUTE: Wakeup timer enable
0: Wakeup timer disabled
1: Wakeup timer enabled
Bit 9 ALRBE: Alarm B enable
0: Alarm B disabled
1: Alarm B enabled
Bit 8 ALRAE: Alarm A enable
0: Alarm A disabled
1: Alarm A enabled
Bit 7 DCE: Coarse digital calibration enable
0: Digital calibration disabled
1: Digital calibration enabled
PREDIV_A must be 6 or greater
Bit 6 FMT: Hour format
0: 24 hour/day format
1: AM/PM hour format
Bit 5 BYPSHAD: Bypass the shadow registers
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,
BYPSHAD must be set to ‘1’.
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Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz)
0: Reference clock detection disabled
1: Reference clock detection enabled
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Timestamp event active edge
0: TIMESTAMP rising edge generates a timestamp event
1: TIMESTAMP falling edge generates a timestamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value
(see note below)
Note:
WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in RTC register
write protection on page 427.
17.6.4
RTC initialization and status register (RTC_ISR)
Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset value: Not affected except INIT, INITF and RSF which are cleared to 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RECAL
PF
Reserved
15
14
13
12
11
10
9
8
Res.
Res.
TAMP
1F
TSOVF
TSF
WUTF
ALRBF ALRAF
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
r
7
6
5
4
3
2
1
0
INIT
INITF
RSF
INITS
SHPF
WUT
WF
ALRB
WF
ALRA
WF
rw
r
rc_w0
r
r
r
r
r
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Bits 31:17 Reserved
Bit 16 RECALPF: Recalibration pending Flag
The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR
register, indicating that the RTC_CALR register is blocked. When the new calibration
settings are taken into account, this bit returns to ‘0’. Refer to Section : Re-calibration on-thefly.
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 TAMP1F: Tamper detection flag
This flag is set by hardware when a tamper detection event is detected.
It is cleared by software writing 0.
Bit 12 TSOVF: Timestamp overflow flag
This flag is set by hardware when a timestamp event occurs while TSF is already set.
This flag is cleared by software by writing 0. It is recommended to check and then clear
TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a
timestamp event occurs immediately before the TSF bit is cleared.
Bit 11 TSF: Timestamp flag
This flag is set by hardware when a timestamp event occurs.
This flag is cleared by software by writing 0.
Bit 10 WUTF: Wakeup timer flag
This flag is set by hardware when the wakeup auto-reload counter reaches 0.
This flag is cleared by software by writing 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
Bit 9 ALRBF: Alarm B flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
Alarm B register (RTC_ALRMBR).
This flag is cleared by software by writing 0.
Bit 8 ALRAF: Alarm A flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
Alarm A register (RTC_ALRMAR).
This flag is cleared by software by writing 0.
Bit 7 INIT: Initialization mode
0: Free running mode
1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and
prescaler register (RTC_PRER). Counters are stopped and start counting from the new
value when INIT is reset.
Bit 6 INITF: Initialization flag
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler
registers can be updated.
0: Calendar registers update is not allowed
1: Calendar registers update is allowed.
Bit 5 RSF: Registers synchronization flag
This bit is set by hardware each time the calendar registers are copied into the shadow
registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in
initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow
register mode (BYPSHAD=1). This bit can also be cleared by software.
0: Calendar shadow registers not yet synchronized
1: Calendar shadow registers synchronized
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Real-time clock (RTC)
Bit 4 INITS: Initialization status flag
This bit is set by hardware when the calendar year field is different from 0 (backup domain
reset value state).
0: Calendar has not been initialized
1: Calendar has been initialized
Bit 3 SHPF: Shift operation pending
0: No shift operation is pending
1: A shift operation is pending
This flag is set by hardware as soon as a shift operation is initiated by a write to the
RTC_SHIFTR. It is cleared by hardware when the corresponding shift operation has been
executed. Writing to SHPF has no effect.
Bit 2 WUTWF: Wakeup timer write flag
This bit is set by hardware when the wakeup timer values can be changed, after the WUTE
bit has been set to 0 in RTC_CR.
0: Wakeup timer configuration update not allowed
1: Wakeup timer configuration update allowed
Bit 1 ALRBWF: Alarm B write flag
This bit is set by hardware when Alarm B values can be changed, after the ALRBIE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm B update not allowed
1: Alarm B update allowed.
Bit 0 ALRAWF: Alarm A write flag
This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm A update not allowed
1: Alarm A update allowed
Note:
The ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming
them to 0.
This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure
is described in RTC register write protection on page 427.
17.6.5
RTC prescaler register (RTC_PRER)
Address offset: 0x10
Backup domain reset value: 0x007F 00FF
System reset: not affected
31
30
29
28
27
26
25
24
23
Res.
14
13
12
11
21
20
19
18
17
16
PREDIV_A[6:0]
Reserved
15
22
10
9
8
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
7
PREDIV_S[14:0]
rw
rw
rw
rw
rw
rw
rw
rw
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Real-time clock (RTC)
RM0383
Bits 31:24 Reserved
Bit 23 Reserved, must be kept at reset value.
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
Note:
This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to Calendar initialization and configuration on
page 427
This register is write protected. The write access procedure is described in RTC register
write protection on page 427.
17.6.6
RTC wakeup timer register (RTC_WUTR)
Address offset: 0x14
Backup domain reset value: 0x0000 FFFF
System reset: not affected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
WUT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved
Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]
+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the
RTC_CR register
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
Note: The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting
WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.
Note:
This register can be written only when WUTWF is set to 1 in RTC_ISR.
This register is write protected. The write access procedure is described in RTC register
write protection on page 427.
17.6.7
RTC calibration register (RTC_CALIBR)
Address offset: 0x18
Backup domain reset value: 0x0000 0000
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RM0383
Real-time clock (RTC)
System reset: not affected
31
30
29
28
27
26
25
24
23
22
21
20
6
5
4
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
DCS
Reserved
2
1
0
rw
rw
DC[4:0]
Reserved
rw
3
rw
rw
rw
Bits 31:8 Reserved
Bit 7 DCS: Digital calibration sign
0: Positive calibration: calendar update frequency is increased
1: Negative calibration: calendar update frequency is decreased
Bits 6:5 Reserved, must be kept at reset value.
Bits 4:0 DC[4:0]: Digital calibration
DCS = 0 (positive calibration)
00000: + 0 ppm
00001: + 4 ppm (rounded value)
00010: + 8 ppm (rounded value)
..
11111: + 126 ppm (rounded value)
DCS = 1 (negative calibration)
00000: − 0 ppm
00001: − 2 ppm (rounded value)
00010: − 4 ppm (rounded value)
..
11111: − 63 ppm (rounded value)
Refer to Case of RTCCLK=32.768 kHz and PREDIV_A+1=128 on page 432 for the exact
step value.
Note:
This register can be written in initialization mode only (RTC_ISR/INITF = ‘1’).
This register is write protected. The write access procedure is described in RTC register
write protection on page 427.
17.6.8
RTC alarm A register (RTC_ALRMAR)
Address offset: 0x1C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
MSK4
WDSEL
rw
rw
15
14
MSK2
rw
29
28
27
DT[1:0]
25
24
DU[3:0]
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
MNT[2:0]
rw
26
rw
MNU[3:0]
rw
rw
rw
23
22
MSK3
PM
rw
rw
7
6
MSK1
rw
rw
rw
21
20
19
DocID026448 Rev 1
17
16
HU[3:0]
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
rw
rw
ST[2:0]
rw
18
HT[1:0]
rw
SU[3:0]
rw
rw
rw
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Real-time clock (RTC)
RM0383
Bit 31 MSK4: Alarm A date mask
0: Alarm A set if the date/day match
1: Date/day don’t care in Alarm A comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format.
Bits 27:24 DU[3:0]: Date units or day in BCD format.
Bit 23 MSK3: Alarm A hours mask
0: Alarm A set if the hours match
1: Hours don’t care in Alarm A comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 MSK2: Alarm A minutes mask
0: Alarm A set if the minutes match
1: Minutes don’t care in Alarm A comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 MSK1: Alarm A seconds mask
0: Alarm A set if the seconds match
1: Seconds don’t care in Alarm A comparison
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.
Note:
This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 427.
17.6.9
RTC alarm B register (RTC_ALRMBR)
Address offset: 0x20
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
MSK4
WDSEL
rw
rw
448/836
29
28
27
DT[1:0]
rw
rw
26
25
24
DU[3:0]
rw
rw
rw
rw
23
22
MSK3
PM
rw
rw
DocID026448 Rev 1
21
20
19
HT[1:0]
rw
rw
18
17
16
HU[3:0]
rw
rw
rw
rw
RM0383
Real-time clock (RTC)
15
14
MSK2
13
12
11
MNT[2:0]
rw
rw
rw
10
9
8
MNU[3:0]
rw
rw
rw
7
6
MSK1
rw
rw
rw
5
4
3
2
1
ST[2:0]
rw
rw
0
SU[3:0]
rw
rw
rw
rw
rw
Bit 31 MSK4: Alarm B date mask
0: Alarm B set if the date and day match
1: Date and day don’t care in Alarm B comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format
Bits 27:24 DU[3:0]: Date units or day in BCD format
Bit 23 MSK3: Alarm B hours mask
0: Alarm B set if the hours match
1: Hours don’t care in Alarm B comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 MSK2: Alarm B minutes mask
0: Alarm B set if the minutes match
1: Minutes don’t care in Alarm B comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 MSK1: Alarm B seconds mask
0: Alarm B set if the seconds match
1: Seconds don’t care in Alarm B comparison
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format
Note:
This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 427.
17.6.10
RTC write protection register (RTC_WPR)
Address offset: 0x24
Backup domain reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
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Real-time clock (RTC)
15
14
13
12
RM0383
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
KEY
Reserved
w
w
w
w
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY: Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to RTC register write protection for a description of how to unlock RTC register write
protection.
17.6.11
RTC sub second register (RTC_SSR)
Address offset: 0x28
Backup domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31
30
29
28
27
26
25
24
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
Reserved
SS[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved
Bits 15:0 SS: Sub second value
SS[15:0] is the value in the synchronous prescaler’s counter. The fraction of a second is
given by the formula below:
Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 )
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.
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Real-time clock (RTC)
17.6.12
RTC shift control register (RTC_SHIFTR)
Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
26
25
24
ADD1S
23
22
21
20
19
18
17
16
r
r
r
r
Reserved
w
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Res.
SUBFS[14:0]
r
w
Bit 31 ADD1S: Add one second
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to
effectively add a fraction of a second to the clock in an atomic operation.
Bits 30:15 Reserved
Bits 14:0 SUBFS: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler’s counter. Since
this counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / ( PREDIV_S + 1 )
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
sure that the shadow registers have been updated with the shifted time.
Refer to Section 17.3.8: RTC synchronization.
Note:
This register is write protected. The write access procedure is described in RTC register
write protection on page 427
17.6.13
RTC time stamp time register (RTC_TSTR)
Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
Reserved
26
25
24
23
22
21
PM
r
DocID026448 Rev 1
20
19
18
HT[1:0]
r
17
16
HU[3:0]
r
r
r
r
r
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Real-time clock (RTC)
15
14
13
12
RM0383
11
MNT[2:0]
Res.
r
r
10
9
8
MNU[3:0]
r
r
r
r
r
7
6
5
4
3
2
ST[2:0]
Res.
r
r
1
0
SU[3:0]
r
r
r
r
r
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15
Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.
Note:
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
17.6.14
RTC time stamp date register (RTC_TSDR)
Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
r
r
r
r
r
Reserved
15
14
13
WDU[1:0]
r
r
12
11
10
r
r
MT
r
r
9
8
r
r
MU[3:0]
7
Reserved
DT[1:0]
r
DU[3:0]
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 WDU[1:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bit 3:0 DU[3:0]: Date units in BCD format
Note:
452/836
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
DocID026448 Rev 1
RM0383
Real-time clock (RTC)
17.6.15
RTC timestamp sub second register (RTC_TSSSR)
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
r
r
r
r
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
SS[15:0]
r
Bits 31:16 Reserved
Bits 15:0 SS: Sub second value
SS[15:0] is the value of the synchronous prescaler’s counter when the timestamp event
occurred.
Note:
The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
17.6.16
RTC calibration register (RTC_CALR)
Address offset: 0x3C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
26
25
24
r
r
r
r
r
r
r
r
14
13
10
9
8
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
7
6
5
Reserved
15
CALP
rw
12
CALW8 CALW16
rw
rw
11
Reserved
r
r
r
4
3
2
1
0
rw
rw
rw
rw
CALM[8:0]
r
rw
rw
rw
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rw
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RM0383
Bits 31:16 Reserved
Bit 15 CALP: Increase frequency of RTC by 488.5 ppm
0: No RTCCLK pulses are added.
1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by
488.5 ppm).
This feature is intended to be used in conjunction with CALM, which lowers the frequency of
the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of
RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) CALM.
Refer to Section 17.3.11: RTC smooth digital calibration.
Bit 14 CALW8: Use an 8-second calibration cycle period
When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.
CALM[1:0] are stuck at “00” when CALW8=’1’.
Refer to Section 17.3.11: RTC smooth digital calibration.
Bit 13 CALW16: Use a 16-second calibration cycle period
When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected. This bit must
not be set to ‘1’ if CALW8=1.
Note: CALM[0] is stuck at ‘0’ when CALW16=’1’.
Refer to Section 17.3.11: RTC smooth digital calibration.
Bits 12:9 Reserved
Bits 8:0 CALM[8:0]: Calibration minus
The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32
seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar
with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with
CALP.
See Section 17.3.11: RTC smooth digital calibration on page 432.
Note:
454/836
This register is write protected. The write access procedure is described in RTC register
write protection on page 427
DocID026448 Rev 1
RM0383
Real-time clock (RTC)
17.6.17
RTC tamper and alternate function configuration register
(RTC_TAFCR)
Address offset: 0x40
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
26
25
24
23
22
21
20
19
Reserved
15
TAMPPUDIS
rw
14
13
TAMPPRCH[1:0]
rw
rw
12
11
TAMPFLT[1:0]
rw
rw
10
9
8
TAMPFREQ[2:0]
rw
rw
7
6
TAMPT
S
rw
rw
5
4
Reserved
3
18
17
16
ALARMOUT
TYPE
TSIN
SEL
TAMP1
INSEL
rw
rw
rw
2
1
0
TAMPIE
rw
TAMP1 TAMP1
TRG
E
rw
rw
Bits 31:19 Reserved. Always read as 0.
Bit 18 ALARMOUTTYPE: RTC_ALARM output type
0: RTC_ALARM is an open-drain output
1: RTC_ALARM is a push-pull output
Bit 17 TSINSEL: TIMESTAMP mapping
0: RTC_AF1 used as TIMESTAMP
1: Reserved
Bit 16 TAMP1INSEL: TAMPER1 mapping
0: RTC_AF1 used as TAMPER1
1: Reserved
Bit 15 TAMPPUDIS: TAMPER pull-up disable
This bit determines if each of the tamper pins are pre-charged before each sample.
0: Precharge tamper pins before sampling (enable internal pull-up)
1: Disable precharge of tamper pins
Note:
Bits 14:13 TAMPPRCH[1:0]: Tamper precharge duration
These bit determines the duration of time during which the pull-up/is activated before each
sample. TAMPPRCH is valid for each of the tamper inputs.
0x0: 1 RTCCLK cycle
0x1: 2 RTCCLK cycles
0x2: 4 RTCCLK cycles
0x3: 8 RTCCLK cycles
Bits 12:11 TAMPFLT[1:0]: Tamper filter count
These bits determines the number of consecutive samples at the specified level
(TAMP*TRG) necessary to activate a Tamper event. TAMPFLT is valid for each of the tamper
inputs.
0x0: Tamper is activated on edge of tamper input transitions to the active level (no internal
pull-up on tamper input).
0x1: Tamper is activated after 2 consecutive samples at the active level.
0x2: Tamper is activated after 4 consecutive samples at the active level.
0x3: Tamper is activated after 8 consecutive samples at the active level.
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Bits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency
Determines the frequency at which each of the tamper inputs are sampled.
0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
Bit 7 TAMPTS: Activate timestamp on tamper detection event
0: Tamper detection event does not cause a timestamp to be saved
1: Save timestamp on tamper detection event
TAMPTS is valid even if TSE=0 in the RTC_CR register.
Bits 6:3 Reserved. Always read as 0.
Bit 2 TAMPIE: Tamper interrupt enable
0: Tamper interrupt disabled
1: Tamper interrupt enabled
Bit 1 TAMP1TRG: Active level for tamper 1
if TAMPFLT != 00 (Cat.2, Cat.3, Cat.4 and Cat.5 device only)
0: TAMPER1 staying low triggers a tamper detection event.
1: TAMPER1 staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: TAMPER1 rising edge triggers a tamper detection event.
1: TAMPER1 falling edge triggers a tamper detection event.
Caution: When TAMPFLT = 0, TAMP1E must be reset when TAMP1TRG is changed to avoid
spuriously setting TAMP1F.
Bit 0 TAMP1E: Tamper 1 detection enable
0: Tamper 1 detection disabled
1: Tamper 1 detection enabled
17.6.18
RTC alarm A sub second register (RTC_ALRMASSR)
Address offset: 0x44
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
Reserved
r
r
15
14
26
25
24
456/836
22
21
r
r
13
12
rw
11
rw
10
20
19
18
17
16
r
r
r
Reserved
rw
rw
9
8
Reserved
r
23
MASKSS[3:0]
r
r
r
r
r
7
6
5
4
3
2
1
0
rw
rw
rw
rw
w
rw
rw
SS[14:0]
rw
rw
rw
rw
rw
rw
rw
rw
DocID026448 Rev 1
RM0383
Real-time clock (RTC)
Bits 31:28 Reserved
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.
2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared.
3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared.
...
12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.
13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.
14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.
15: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits 23:15 Reserved
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler’s counter to
determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
Note:
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 427
17.6.19
RTC alarm B sub second register (RTC_ALRMBSSR)
Address offset: 0x48
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
r
r
29
28
27
r
r
rw
13
12
Reserved
15
14
26
25
24
23
22
21
20
rw
rw
r
r
r
r
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
w
rw
rw
MASKSS[3:0]
11
rw
10
18
17
16
r
r
r
Reserved
Reserved
r
19
r
SS[14:0]
rw
rw
rw
rw
rw
rw
rw
rw
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Bits 31:28 Reserved
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared.
0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared.
0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared.
...
0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared.
0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared.
0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared.
0xF: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits 23:15 Reserved
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler’s counter to
determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
Note:
This register can be written only when ALRBIE is reset in RTC_CR register, or in
initialization mode.
This register is write protected.The write access procedure is described in Section : RTC
register write protection
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Real-time clock (RTC)
17.6.20
RTC backup registers (RTC_BKPxR)
Address offset: 0x50 to 0x9C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BKP[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
w
rw
rw
BKP[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 BKP[31:0]
The application can write or read data to and from these registers.
They are powered-on by VBAT when VDD is switched off, so that they are not reset by
System reset, and their contents remain valid when the device operates in low-power mode.
This register is reset on a tamper detection event, as long as TAMPxF=1
17.6.21
RTC register map
RTC_WUTR
1
1
1
1
1
1
Reserved
0
1
TSEDGE
0
BYPSHAD
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
PREDIV_S[14:0]
0 0
0
0
0
0
0
1
1
WUT[15:0]
1
DocID026448 Rev 1
0
WCKSEL
[2:0]
Reserved
Reset value
0
ALRAWF
0x14
1
DU[3:0]
ALRBWF
Reset value
0
SHPF
Reserved
0
WUTWF
PREDIV_A[6:0]
RTC_PRER
0x10
Reserved
Reset value
1
DT
[1:0]
0
REFCKON
Reserved
0
0
RSF
0
0
0
INITS
0
0
0
FMT
0
MU[3:0]
0
DCE
0
0
INITF
0
0
ALRAE
TSIE
0
WUTIE
0
0
ADD1H
0
1
0
INIT
RTC_ISR
0
0
0
ALRAF
0x0C
0
0
BKP
Reset value
OSEL
[1:0]
0
WDU[2:0]
SUB1H
Reserved
POL
RTC_CR
COSEL
0x08
COE
Reset value
0
WUTE
YU[3:0]
0
ALRBE
0
WUTF
0
SU[3:0]
ALRBF
YT[3:0]
Reserved
0
MT
0
ST[2:0]
TSE
0
MNU[3:0]
ALRAIE
RTC_DR
0
MNT[2:0]
TSF
0x04
0
HU[3:0]
ALRBIE
Reset value
HT
[1:0]
TSOVF
Reserved
TAMP1F
RTC_TR
Reserved
0x00
Register
PM
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 66. RTC register map and reset values
1
1
1
1
1
1
1
1
1
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Reserved
0
0
DU[3:0]
0
0
0
0
0
0
0
HT
[1:0]
0
0
0
RTC_WPR
0
0
0
0
0
0
HU[3:0]
0
0
0
0
0
0
MNT[2:0]
0
0
0
0
0
0
0
0
0
0
MNU[3:0]
0
0
0
0
0
RTC_TSSSR
0
0
0
0
0
0
RTC_
ALRMBSSR
Reset value
460/836
0
0
Reserved
MASKSS[3:0]
0
Reserved
0
0
0
0
0
0
0
0
0
MNU[3:0]
0
0
0
0
0
0
0
0
0
0
0
SU[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ST[2:0]
SU[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SS[14:0]
Reserved
0
DocID026448 Rev 1
0
SS[14:0]
Reserved
0
0
CALM[8:0]
TAMPFLT[1:0]
0
0
TAMPFREQ[2:0]
0
0
Reserved
CALW16
0
TAMPPRCH[1:0]
CALP
CALW8
0
TAMPPUDIS
0
TSINSEL
0
0
0
MASKSS[3:0]
0
0
0
TAMP1INSEL
Reserved
ALARMOUTTYPE
RTC_TAFCR
0
0
SS[15:0]
Reserved
Reset value
0x48
0
Reserved
RTC_ CALR
RTC_
ALRMASSR
0
MNT[2:0]
HU[3:0]
Reserved
Reserved
HT[1:0]
RTC_TSTR
PM
0
Reset value
0x44
0
0
SU[3:0]
SS[15:0]
Reserved
Reset value
0x40
0
TAMPTS
RTC_SSR
Reset value
0x3C
0
0
Reset value
0x38
ST[2:0]
0
0
KEY[7:0]
Reset value
0x30
0
Reserved
Reset value
0x28
0
0
TAMP1E
0
0
ST[2:0]
0
TAMPIE
0
0
MNU[3:0]
0
TAMP1ETRG
Reset value
0
MNT[2:0]
0
MSK1
DT
[1:0]
0
MSK2
RTC_ALRMBR
0
HU[3:0]
MSK2
0
PM
0
MSK3
0
HT
[1:0]
PM
Reset value
DU[3:0]
MSK3
MSK4
DT
[1:0]
DC[4:0]
Reserved
0x24
WDSEL
0x20
RTC_ALRMAR
MSK4
0x1C
0
WDSEL
Reset value
Reserved
DCS
RTC_CALIBR
MSK2
0x18
Register
Reserved
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 66. RTC register map and reset values (continued)
0
0
0
0
0
0
0
0
RM0383
Real-time clock (RTC)
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 66. RTC register map and reset values (continued)
RTC_BKP0R
BKP[31:0]
Offset
0x50
to 0x9C
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
to
RTC_BKP19R
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BKP[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Table 3 on page 41 for the register boundary addresses.
Caution:
In Table 66, the reset value is the value after a backup domain reset. The majority of the
registers are not affected by a system reset. For more information, please refer to
Section 17.3.7: Resetting the RTC.
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Inter-integrated circuit (I2C) interface
RM0383
18
Inter-integrated circuit (I2C) interface
18.1
I2C introduction
I2C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller
and the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific
sequencing, protocol, arbitration and timing. It supports the standard mode (Sm, up to 100
kHz) and Fm mode (Fm, up to 400 kHz). The I2C bus frequency can be increased up to 1
MHz. For more details about the complete solution, please contact your local ST sales
representative.
It may be used for a variety of purposes, including CRC generation and verification, SMBus
(system management bus) and PMBus (power management bus).
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18.2
I2C main features
•
Parallel-bus/I2C protocol converter
•
Multimaster capability: the same interface can act as Master or Slave
•
I2C Master features:
•
–
Clock generation
–
Start and Stop generation
I2C
Slave features:
–
Programmable I2C Address detection
–
Dual Addressing Capability to acknowledge 2 slave addresses
–
Stop bit detection
•
Generation and detection of 7-bit/10-bit addressing and General Call
•
Supports different communication speeds:
–
Standard Speed (up to 100 kHz)
–
Fast Speed (up to 400 kHz)
–
The I2C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, please contact your local ST sales representative
•
Analog noise filter
•
Programmable digital noise filter
•
Status flags:
•
•
–
Transmitter/Receiver mode flag
–
End-of-Byte transmission flag
–
I2C busy flag
Error flags:
–
Arbitration lost condition for master mode
–
Acknowledgment failure after address/ data transmission
–
Detection of misplaced start or stop condition
–
Overrun/Underrun if clock stretching is disabled
2 Interrupt vectors:
–
1 Interrupt for successful address/ data communication
–
1 Interrupt for error condition
•
Optional clock stretching
•
1-byte buffer with DMA capability
•
Configurable PEC (packet error checking) generation or verification:
•
•
–
PEC value can be transmitted as last byte in Tx mode
–
PEC error checking for last received byte
SMBus 2.0 Compatibility:
–
25 ms clock low timeout delay
–
10 ms master cumulative clock low extend time
–
25 ms slave cumulative clock low extend time
–
Hardware PEC generation/verification with ACK control
–
Address Resolution Protocol (ARP) supported
PMBus Compatibility
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Note:
Some of the above features may not be available in certain products. The user should refer
to the product data sheet, to identify the specific features supported by the I2C interface
implementation.
18.3
I2C functional description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz) or fast (up to 400 kHz) I2C bus.
18.3.1
Mode selection
The interface can operate in one of the four following modes:
•
Slave transmitter
•
Slave receiver
•
Master transmitter
•
Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master, after it generates a START condition and from master to slave, if an arbitration loss
or a Stop generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a start condition and ends with a stop condition. Both
start and stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection may be enabled or disabled
by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 160.
Figure 160. I2C bus protocol
SDA
ACK
MSB
SCL
1
2
8
9
Stop
condition
Start
condition
Acknowledge may be enabled or disabled by software. The I2C interface addresses (dual
addressing 7-bit/ 10-bit and/or general call address) can be selected by software.
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The block diagram of the I2C interface is shown in Figure 161.
Figure 161. I2C block diagram
$ATAREGISTER
3$!
.OISE
FILTER
$ATA
CONTROL
$ATASHIFTREGISTER
0%#CALCULATION
#OMPARATOR
/WNADDRESSREGISTER
$UALADDRESSREGISTER
3#,
.OISE
FILTER
#LOCK
CONTROL
0%#REGISTER
#LOCKCONTROL
2EGISTER##2
#ONTROLREGISTERS
#2#2
#ONTROL
LOGIC
3TATUSREGISTERS
3232
3-"!
)NTERRUPTS
$-!REQUESTS!#+
-36
1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.
18.3.2
I2C slave mode
By default the I2C interface operates in Slave mode. To switch from default Slave mode to
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
•
2 MHz in Sm mode
•
4 MHz in Fm mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
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Note:
RM0383
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
Header or address not matched: the interface ignores it and waits for another Start
condition.
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set and waits for the 8-bit slave address.
Address matched: the interface generates in sequence:
•
An acknowledge pulse if the ACK bit is set
•
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is
set.
•
If ENDUAL=1, the software has to read the DUALF bit to check which slave address
has been acknowledged.
In 10-bit mode, after receiving the address sequence the slave is always in Receiver mode.
It will enter Transmitter mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
The TRA bit indicates whether the slave is in Receiver or Transmitter mode.
Slave transmitter
Following the address reception and after clearing ADDR, the slave sends bytes from the
DR register to the SDA line via the internal shift register.
The slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent
(see Figure 162 Transfer sequencing EV1 EV3).
When the acknowledge pulse is received:
•
The TxE bit is set by hardware with an interrupt if the ITEVFEN and the ITBUFEN bits
are set.
If TxE is set and some data were not written in the I2C_DR register before the end of the
next data transmission, the BTF bit is set and the interface waits until BTF is cleared by a
read to I2C_SR1 followed by a write to the I2C_DR register, stretching SCL low.
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Figure 162. Transfer sequence diagram for slave transmitter
7-bit slave transmitter
S Address
A
Data1
EV1 EV3-1 EV3
A
Data2
A
EV3
EV3
.....
DataN
NA
P
EV3-2
10-bit slave transmitter
S Header
A
Address
A
EV1
Sr Header A
Data1
EV1 EV3_1
EV3
A
.... DataN
NA P
EV3
EV3-2
Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,
EVx= Event (with interrupt if ITEVFEN=1)
EV1: ADDR=1, cleared by reading SR1 followed by reading SR2
EV3-1: TxE=1, shift register empty, data register empty, write Data1 in DR.
EV3: TxE=1, shift register not empty, data register empty, cleared by writing DR
EV3-2: AF=1; AF is cleared by writing ‘0’ in AF bit of SR1 register.
ai18209
1. The EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence.
2. The EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte
transmission
Slave receiver
Following the address reception and after clearing ADDR, the slave receives bytes from the
SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
•
An acknowledge pulse if the ACK bit is set
•
The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bit is set.
If RxNE is set and the data in the DR register is not read before the end of the next data
reception, the BTF bit is set and the interface waits until BTF is cleared by a read from the
I2C_DR register, stretching SCL low (see Figure 163 Transfer sequencing).
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Figure 163. Transfer sequence diagram for slave receiver
7-bit slave receiver
S Address
A
Data1
A
EV1
Data2
A
EV2
EV2
.....
DataN
A
P
EV2
EV4
10-bit slav e receiver
S Header
A
Address
A
Data1
EV1
A
EV2
.....
DataN
A
P
EV2
EV4
Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge,
EVx= Event (with interrupt if ITEVFEN=1)
EV1: ADDR=1, cleared by reading SR1 followed by reading SR2
EV2: RxNE=1 cleared by reading DR register.
EV4: STOPF=1, cleared by reading SR1 register followed by writing to the CR1 register
ai18208
1. The EV1 event stretches SCL low until the end of the corresponding software sequence.
2. The EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte
reception.
3. After checking the SR1 register content, the user should perform the complete clearing sequence for each
flag found set.
Thus, for ADDR and STOPF flags, the following sequence is required inside the I2C interrupt routine:
READ SR1
if (ADDR == 1) {READ SR1; READ SR2}
if (STOPF == 1) {READ SR1; WRITE CR1}
The purpose is to make sure that both ADDR and STOPF flags are cleared if both are found set.
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
•
The STOPF bit and generates an interrupt if the ITEVFEN bit is set.
The STOPF bit is cleared by a read of the SR1 register followed by a write to the CR1
register (see Figure 163: Transfer sequence diagram for slave receiver EV4).
18.3.3
I2C master mode
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a Start condition and ends with a Stop condition.
Master mode is selected as soon as the Start condition is generated on the bus with a
START bit.
The following is the required sequence in master mode.
•
Program the peripheral input clock in I2C_CR2 Register in order to generate correct
timings
•
Configure the clock control registers
•
Configure the rise time register
•
Program the I2C_CR1 register to enable the peripheral
•
Set the START bit in the I2C_CR1 register to generate a Start condition
The peripheral input clock frequency must be at least:
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•
2 MHz in Sm mode
•
4 MHz in Fm mode
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SCL master clock generation
The CCR bits are used to generate the high and low level of the SCL clock, starting from the
generation of the rising and falling edge (respectively). As a slave may stretch the SCL line,
the peripheral checks the SCL input from the bus at the end of the time programmed in
TRISE bits after rising edge generation.
•
If the SCL line is low, it means that a slave is stretching the bus, and the high level
counter stops until the SCL line is detected high. This allows to guarantee the minimum
HIGH period of the SCL clock parameter.
•
If the SCL line is high, the high level counter keeps on counting.
Indeed, the feedback loop from the SCL rising edge generation by the peripheral to the SCL
rising edge detection by the peripheral takes time even if no slave stretches the clock. This
loopback duration is linked to the SCL rising time (impacting SCL VIH input detection), plus
delay due to the noise filter present on the SCL input path, plus delay due to internal SCL
input synchronization with APB clock. The maximum time used by the feedback loop is
programmed in the TRISE bits, so that the SCL frequency remains stable whatever the SCL
rising time.
Start condition
Setting the START bit causes the interface to generate a Start condition and to switch to
Master mode (MSL bit set) when the BUSY bit is cleared.
Note:
In master mode, setting the START bit causes the interface to generate a ReStart condition
at the end of the current byte transfer.
Once the Start condition is sent:
•
The SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address (see Figure 164 and Figure 165 Transfer sequencing EV5).
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
•
In 10-bit addressing mode, sending the header sequence causes the following event:
–
The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Then the master waits for a read of the SR1 register followed by a write in the DR
register with the second address byte (see Figure 164 and Figure 165 Transfer
sequencing).
–
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see Figure 164 and Figure 165 Transfer sequencing).
•
In 7-bit addressing mode, one address byte is sent.
As soon as the address byte is sent,
–
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see Figure 164 and Figure 165 Transfer sequencing).
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The master can decide to enter Transmitter or Receiver mode depending on the LSB of the
slave address sent.
•
•
In 7-bit addressing mode,
–
To enter Transmitter mode, a master sends the slave address with LSB reset.
–
To enter Receiver mode, a master sends the slave address with LSB set.
In 10-bit addressing mode,
–
To enter Transmitter mode, a master sends the header (11110xx0) and then the
slave address, (where xx denotes the two most significant bits of the address).
–
To enter Receiver mode, a master sends the header (11110xx0) and then the
slave address. Then it should send a repeated Start condition followed by the
header (11110xx1), (where xx denotes the two most significant bits of the
address).
The TRA bit indicates whether the master is in Receiver or Transmitter mode.
Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from
the DR register to the SDA line via the internal shift register.
The master waits until the first data byte is written into I2C_DR (see Figure 164 Transfer
sequencing EV8_1).
When the acknowledge pulse is received, the TxE bit is set by hardware and an interrupt is
generated if the ITEVFEN and ITBUFEN bits are set.
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared by a write to I2C_DR,
stretching SCL low.
Closing the communication
After the last byte is written to the DR register, the STOP bit is set by software to generate a
Stop condition (see Figure 164 Transfer sequencing EV8_2). The interface automatically
goes back to slave mode (MSL bit cleared).
Note:
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Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.
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Figure 164. Transfer sequence diagram for master transmitter
7-bit master transmitter
S
Address
A
EV5
Data1
EV6 EV8_1
EV8
A
Data2
A
EV8
EV8
.....
DataN
A
P
EV8_2
10-bit master transmitter
S
Header
EV5
A
Address
EV9
A
Data1
EV6
EV8_1
EV8
A
EV8
.....
DataN
A
P
EV8_2
Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge,
EVx= Event (with interrupt if ITEVFEN = 1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.
EV8_1: TxE=1, shift register empty, data register empty, write Data1 in DR.
EV8: TxE=1, shift register not empty,.data register empty, cleared by writing DR register
EV8_2: TxE=1, BTF = 1, Program Stop request. TxE and BTF are cleared by hardware by the Stop condition
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.
ai18210
1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence.
2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission.
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Master receiver
Following the address transmission and after clearing ADDR, the I2C interface enters
Master Receiver mode. In this mode the interface receives bytes from the SDA line into the
DR register via the internal shift register. After each byte the interface generates in
sequence:
1.
An acknowledge pulse if the ACK bit is set
2.
The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are
set (see Figure 165 Transfer sequencing EV7).
If the RxNE bit is set and the data in the DR register is not read before the end of the last
data reception, the BTF bit is set by hardware and the interface waits until BTF is cleared by
a read in the DR register, stretching SCL low.
Closing the communication
The master sends a NACK for the last byte received from the slave. After receiving this
NACK, the slave releases the control of the SCL and SDA lines. Then the master can send
a Stop/Restart condition.
1.
To generate the nonacknowledge pulse after the last received data byte, the ACK bit
must be cleared just after reading the second last data byte (after second last RxNE
event).
2.
In order to generate the Stop/Restart condition, software must set the STOP/START bit
after reading the second last data byte (after the second last RxNE event).
3.
In case a single byte has to be received, the Acknowledge disable is made during EV6
(before ADDR flag is cleared) and the STOP condition generation is made after EV6.
After the Stop condition generation, the interface goes automatically back to slave mode
(MSL bit cleared).
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Figure 165. Transfer sequence diagram for master receiver
BITMASTERRECEIVER
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BITMASTERRECEIVER
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,EGEND33TART3R2EPEATED3TART03TOP!!CKNOWLEDGE.!.ONACKNOWLEDGE
%6X%VENTWITHINTERRUPTIF)4%6&%.
%63"CLEAREDBYREADING32REGISTERFOLLOWEDBYWRITING$2REGISTER
%6!$$2CLEAREDBYREADING32REGISTERFOLLOWEDBYREADING32)NBITMASTERRECEIVERMODETHISSE
QUENCESHOULDBEFOLLOWEDBYWRITING#2WITH34!24 )NCASEOFTHERECEPTIONOFBYTETHE!CKNOWLEDGEDISABLEMUSTBEPERFORMEDDURING%6EVENTIEBEFORECLEARING!$$2FLAG
%62X.%CLEAREDBYREADING$2REGISTER
%6?2X.%CLEAREDBYREADING$2REGISTERPROGRAM!# +AND34/0REQUEST
%6!$$CLEAREDBYREADING32REGISTERFOLLOWEDBYWRITING$2REGISTER
AID
1. If a single byte is received, it is NA.
2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
3. The EV7 event stretches SCL low if the software sequence is not completed before the end of the next byte reception.
4. The EV7_1 software sequence must be completed before the ACK pulse of the current byte transfer.
The procedures described below are recommended if the EV7-1 software sequence is not
completed before the ACK pulse of the current byte transfer.
These procedures must be followed to make sure:
•
The ACK bit is set low on time before the end of the last data reception
•
The STOP bit is set high after the last data reception without reception of
supplementary data.
For 2-byte reception:
•
Wait until ADDR = 1 (SCL stretched low until the ADDR flag is cleared)
•
Set ACK low, set POS high
•
Clear ADDR flag
•
Wait until BTF = 1 (Data 1 in DR, Data2 in shift register, SCL stretched low until a data
1 is read)
•
Set STOP high
•
Read data 1 and 2
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For N >2 -byte reception, from N-2 data reception
18.3.4
•
Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until
data N-2 is read)
•
Set ACK low
•
Read data N-2
•
Wait until BTF = 1 (data N-1 in DR, data N in shift register, SCL stretched low until a
data N-1 is read)
•
Set STOP high
•
Read data N-1 and N
Error conditions
The following are the error conditions which may cause communication to fail.
Bus error (BERR)
This error occurs when the I2C interface detects an external Stop or Start condition during
an address or a data transfer. In this case:
•
the BERR bit is set and an interrupt is generated if the ITERREN bit is set
•
in Slave mode: data are discarded and the lines are released by hardware:
•
–
in case of a misplaced Start, the slave considers it is a restart and waits for an
address, or a Stop condition
–
in case of a misplaced Stop, the slave behaves like for a Stop condition and the
lines are released by hardware
In Master mode: the lines are not released and the state of the current transmission is
not affected. It is up to the software to abort or not the current transmission
Acknowledge failure (AF)
This error occurs when the interface detects a nonacknowledge bit. In this case:
•
the AF bit is set and an interrupt is generated if the ITERREN bit is set
•
a transmitter which receives a NACK must reset the communication:
–
If Slave: lines are released by hardware
–
If Master: a Stop or repeated Start condition must be generated by software
Arbitration lost (ARLO)
This error occurs when the I2C interface detects an arbitration lost condition. In this case,
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•
the ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is
set)
•
the I2C Interface goes automatically back to slave mode (the MSL bit is cleared). When
the I2C loses the arbitration, it is not able to acknowledge its slave address in the same
transfer, but it can acknowledge it after a repeated Start from the winning master.
•
lines are released by hardware
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Overrun/underrun error (OVR)
An overrun error can occur in slave mode when clock stretching is disabled and the I2C
interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR
has not been read, before the next byte is received by the interface. In this case,
•
The last received byte is lost.
•
In case of Overrun error, software should clear the RxNE bit and the transmitter should
re-transmit the last received byte.
Underrun error can occur in slave mode when clock stretching is disabled and the I2C
interface is transmitting data. The interface has not updated the DR with the next byte
(TxE=1), before the clock comes for the next byte. In this case,
•
The same byte in the DR register will be sent again
•
The user should make sure that data received on the receiver side during an underrun
error are discarded and that the next bytes are written within the clock low time
specified in the I2C bus standard.
For the first byte to be transmitted, the DR must be written after ADDR is cleared and before
the first SCL rising edge. If not possible, the receiver must discard the first data.
18.3.5
Programmable noise filter
In Fm mode, the I2C standard requires that spikes are suppressed to a length of 50 ns on
SDA and SCL lines.
An analog noise filter is implemented in the SDA and SCL I/Os. This filter is enabled by
default and can be disabled by setting the ANOFF bit in the I2C_FLTR register.
A digital noise filter can be enabled by configuring the DNF[3:0] bits to a non-zero value.
This suppresses the spikes on SDA and SCL inputs with a length of up to DNF[3:0] *
TPCLK1.
Enabling the digital noise filter increases the SDA hold time by (DNF[3:0] +1)* TPCLK.
To be compliant with the maximum hold time of the I2C-bus specification version 2.1
(Thd:dat), the DNF bits must be programmed using the constraints shown in Table 67, and
assuming that the analog filter is disabled.
Note:
DNF[3:0] must only be configured when the I2C is disabled (PE = 0). If the analog filter is
also enabled, the digital filter is added to the analog filter.
Table 67. Maximum DNF[3:0] value to be compliant with Thd:dat(max)
Maximum DNF value
PCLK1 frequency
Sm mode
Fm mode
2 <= FPCLK1 <= 5
2
0
5 < FPCLK1 <= 10
12
0
10 < FPCLK1 <= 20
15
1
20 < FPCLK1 <= 30
15
7
30 < FPCLK1 <= 40
15
13
40 < FPCLK1 <= 50
15
15
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Note:
For each frequency range, the constraint is given based on the worst case which is the
minimum frequency of the range. Greater DNF values can be used if the system can
support maximum hold time violation.
18.3.6
SDA/SCL line control
•
•
18.3.7
If clock stretching is enabled:
–
Transmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low
before transmission to wait for the microcontroller to write the byte in the Data
Register (both buffer and shift register are empty).
–
Receiver mode: If RxNE=1 and BTF=1: the interface holds the clock line low after
reception to wait for the microcontroller to read the byte in the Data Register (both
buffer and shift register are full).
If clock stretching is disabled in Slave mode:
–
Overrun Error in case of RxNE=1 and no read of DR has been done before the
next byte is received. The last received byte is lost.
–
Underrun Error in case TxE=1 and no write into DR has been done before the next
byte must be transmitted. The same byte will be sent again.
–
Write Collision not managed.
SMBus
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I2C
principles of operation. SMBus provides a control bus for system and power management
related tasks. A system may use SMBus to pass messages to and from devices instead of
toggling individual control lines.
The System Management Bus Specification refers to three types of devices. A slave is a
device that is receiving or responding to a command. A master is a device that issues
commands, generates the clocks, and terminates the transfer. A host is a specialized
master that provides the main interface to the system's CPU. A host must be a master-slave
and must support the SMBus host notify protocol. Only one host is allowed in a system.
Similarities between SMBus and I2C
•
2 wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional
•
Master-slave communication, Master provides clock
•
Multi master capability
•
SMBus data format similar to I2C 7-bit addressing format (Figure 160).
Differences between SMBus and I2C
The following table describes the differences between SMBus and I2C.
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Table 68. SMBus vs. I2C
I2C
SMBus
Max. speed 100 kHz
Max. speed 400 kHz
Min. clock speed 10 kHz
No minimum clock speed
35 ms clock low timeout
No timeout
Logic levels are fixed
Logic levels are VDD dependent
Different address types (reserved, dynamic etc.)
7-bit, 10-bit and general call slave address types
Different bus protocols (quick command, process
No bus protocols
call etc.)
SMBus application usage
With System Management Bus, a device can provide manufacturer information, tell the
system what its model/part number is, save its state for a suspend event, report different
types of errors, accept control parameters, and return its status. SMBus provides a control
bus for system and power management related tasks.
Device identification
Any device that exists on the System Management Bus as a slave has a unique address
called the Slave Address. For the list of reserved slave addresses, refer to the SMBus
specification version. 2.0 (http://smbus.org/).
Bus protocols
The SMBus specification supports up to 9 bus protocols. For more details of these protocols
and SMBus address types, refer to SMBus specification version. 2.0 (http://smbus.org/).
These protocols should be implemented by the user software.
Address resolution protocol (ARP)
SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. The Address Resolution Protocol (ARP) has the following
attributes:
•
Address assignment uses the standard SMBus physical layer arbitration mechanism
•
Assigned addresses remain constant while device power is applied; address retention
through device power loss is also allowed
•
No additional SMBus packet overhead is incurred after address assignment. (i.e.
subsequent accesses to assigned slave addresses have the same overhead as
accesses to fixed address devices.)
•
Any SMBus master can enumerate the bus
Unique device identifier (UDID)
In order to provide a mechanism to isolate each device for the purpose of address
assignment, each device must implement a unique device identifier (UDID).
For the details on 128 bit UDID and more information on ARP, refer to SMBus specification
version 2.0 (http://smbus.org/).
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SMBus alert mode
SMBus Alert is an optional signal with an interrupt line for devices that want to trade their
ability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are.
SMBA is used in conjunction with the SMBus General Call Address. Messages invoked with
the SMBus are 2 bytes long.
A slave-only device can signal the host through SMBA that it wants to talk by setting ALERT
bit in I2C_CR1 register. The host processes the interrupt and simultaneously accesses all
SMBA devices through the Alert Response Address (known as ARA having a value 0001
100X). Only the device(s) which pulled SMBA low will acknowledge the Alert Response
Address. This status is identified using SMBALERT Status flag in I2C_SR1 register. The
host performs a modified Receive Byte operation. The 7 bit device address provided by the
slave transmit device is placed in the 7 most significant bits of the byte. The eighth bit can
be a zero or one.
If more than one device pulls SMBA low, the highest priority (lowest address) device will win
communication rights via standard arbitration during the slave address transfer. After
acknowledging the slave address the device must disengage its SMBA pull-down. If the
host still sees SMBA low when the message transfer is complete, it knows to read the ARA
again.
A host which does not implement the SMBA signal may periodically access the ARA.
For more details on SMBus Alert mode, refer to SMBus specification version 2.0
(http://smbus.org/).
Timeout error
There are differences in the timing specifications between I2C and SMBus.
SMBus defines a clock low timeout, TIMEOUT of 35 ms. Also SMBus specifies TLOW:
SEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW:
MEXT as the cumulative clock low extend time for a master device. For more details on
these timeouts, refer to SMBus specification version 2.0 (http://smbus.org/).
The status flag Timeout or Tlow Error in I2C_SR1 shows the status of this feature.
How to use the interface in SMBus mode
To switch from I2C mode to SMBus mode, the following sequence should be performed.
•
Set the SMBus bit in the I2C_CR1 register
•
Configure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the
application
If you want to configure the device as a master, follow the Start condition generation
procedure in Section 18.3.3: I2C master mode. Otherwise, follow the sequence in
Section 18.3.2: I2C slave mode.
The application has to control the various SMBus protocols by software.
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•
SMB Device Default Address acknowledged if ENARP=1 and SMBTYPE=0
•
SMB Host Header acknowledged if ENARP=1 and SMBTYPE=1
•
SMB Alert Response Address acknowledged if SMBALERT=1
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18.3.8
DMA requests
DMA requests (when enabled) are generated only for data transfer. DMA requests are
generated by Data Register becoming empty in transmission and Data Register becoming
full in reception. The DMA must be initialized and enabled before the I2C data transfer. The
DMAEN bit must be set in the I2C_CR2 register before the ADDR event. In master mode or
in slave mode when clock stretching is enabled, the DMAEN bit can also be set during the
ADDR event, before clearing the ADDR flag. The DMA request must be served before the
end of the current byte transfer. When the number of data transfers which has been
programmed for the corresponding DMA stream is reached, the DMA controller sends an
End of Transfer EOT signal to the I2C interface and generates a Transfer Complete interrupt
if enabled:
•
Master transmitter: In the interrupt routine after the EOT interrupt, disable DMA
requests then wait for a BTF event before programming the Stop condition.
•
Master receiver
–
When the number of bytes to be received is equal to or greater than two, the DMA
controller sends a hardware signal, EOT_1, corresponding to the last but one data
byte (number_of_bytes – 1). If, in the I2C_CR2 register, the LAST bit is set, I2C
automatically sends a NACK after the next byte following EOT_1. The user can
generate a Stop condition in the DMA Transfer Complete interrupt routine if
enabled.
–
When a single byte must be received: the NACK must be programmed during EV6
event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag. Then the
user can program the STOP condition either after clearing ADDR flag, or in the
DMA Transfer Complete interrupt routine.
Transmission using DMA
DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
register. Data will be loaded from a Memory area configured using the DMA peripheral (refer
to the DMA specification) to the I2C_DR register whenever the TxE bit is set. To map a DMA
stream x for I2C transmission (where x is the stream number), perform the following
sequence:
1.
Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved
to this address from the memory after each TxE event.
2.
Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register
in the case of a bouble buffer mode). The data will be loaded into I2C_DR from this
memory after each TxE event.
3.
Configure the total number of bytes to be transferred in the DMA_SxNDTR register.
After each TxE event, this value will be decremented.
4.
Configure the DMA stream priority using the PL[0:1] bits in the DMA_SxCR register
5.
Set the DIR bit in the DMA_SxCR register and configure interrupts after half transfer or
full transfer depending on application requirements.
6.
Activate the stream by setting the EN bit in the DMA_SxCR register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I2C interface and the DMA generates an interrupt, if enabled, on the DMA stream interrupt
vector.
Note:
Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.
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Reception using DMA
DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
Data will be loaded from the I2C_DR register to a Memory area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
stream x for I2C reception (where x is the stream number), perform the following sequence:
1.
Set the I2C_DR register address in DMA_SxPAR register. The data will be moved from
this address to the memory after each RxNE event.
2.
Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register
in the case of a bouble buffer mode). The data will be loaded from the I2C_DR register
to this memory area after each RxNE event.
3.
Configure the total number of bytes to be transferred in the DMA_SxNDTR register.
After each RxNE event, this value will be decremented.
4.
Configure the stream priority using the PL[0:1] bits in the DMA_SxCR register
5.
Reset the DIR bit and configure interrupts in the DMA_SxCR register after half transfer
or full transfer depending on application requirements.
6.
Activate the stream by setting the EN bit in the DMA_SxCR register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I2C interface and DMA generates an interrupt, if enabled, on the DMA stream interrupt
vector.
Note:
Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
18.3.9
Packet error checking
A PEC calculator has been implemented to improve the reliability of communication. The
PEC is calculated by using the C(x) = x8 + x2 + x + 1 CRC-8 polynomial serially on each bit.
•
480/836
PEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a
CRC-8 calculated on all message bytes including addresses and R/W bits.
–
In transmission: set the PEC transfer bit in the I2C_CR1 register after the TxE
event corresponding to the last byte. The PEC will be transferred after the last
transmitted byte.
–
In reception: set the PEC bit in the I2C_CR1 register after the RxNE event
corresponding to the last byte so that the receiver sends a NACK if the next
received byte is not equal to the internally calculated PEC. In case of MasterReceiver, a NACK must follow the PEC whatever the check result. The PEC must
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Inter-integrated circuit (I2C) interface
RM0383
be set before the ACK of the CRC reception in slave mode. It must be set when
the ACK is set low in master mode.
18.4
•
A PECERR error flag/interrupt is also available in the I2C_SR1 register.
•
If DMA and PEC calculation are both enabled:–
In transmission: when the I2C interface receives an EOT signal from the DMA
controller, it automatically sends a PEC after the last byte.
–
In reception: when the I2C interface receives an EOT_1 signal from the DMA
controller, it will automatically consider the next byte as a PEC and will check it. A
DMA request is generated after PEC reception.
•
To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register
(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA
request for a master receiver, a NACK is automatically sent after the last received byte.
•
PEC calculation is corrupted by an arbitration loss.
I2C interrupts
The table below gives the list of I2C interrupt requests.
Table 69. I2C Interrupt requests
Interrupt event
Start bit sent (Master)
Enable control bit
SB
Address sent (Master) or Address matched (Slave)
ADDR
10-bit header sent (Master)
ADD10
Stop received (Slave)
STOPF
Data byte transfer finished
BTF
Receive buffer not empty
RxNE
Transmit buffer empty
TxE
Bus error
BERR
Arbitration loss (Master)
ARLO
Acknowledge failure
ITEVFEN
ITEVFEN and ITBUFEN
AF
Overrun/Underrun
OVR
PEC error
PECERR
Timeout/Tlow error
TIMEOUT
SMBus Alert
Note:
Event flag
ITERREN
SMBALERT
SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt
channel.
BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the
same interrupt channel.
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Figure 166. I2C interrupt mapping diagram
SB
ITEVFEN
ADDR
ADD10
STOPF
it_event
BTF
TxE
ITBUFEN
RxNE
ITERREN
BERR
ARLO
it_error
AF
OVR
PECERR
TIMEOUT
SMBALERT
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I2C debug mode
18.5
When the microcontroller enters the debug mode (Cortex®-M4 with FPU core halted), the
SMBUS timeout either continues to work normally or stops, depending on the
DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details,
refer to Section 23.16.2: Debug support for timers, watchdog and I2C on page 818.
I2C registers
18.6
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
I2C Control register 1 (I2C_CR1)
18.6.1
Address offset: 0x00
Reset value: 0x0000
15
SWRST
rw
14
Res.
13
12
11
10
ALERT
PEC
POS
ACK
rw
rw
rw
rw
9
8
STOP START
rw
rw
7
NO
STRETCH
rw
6
5
4
ENGC ENPEC ENARP
rw
rw
rw
3
2
1
0
SMB
TYPE
Res.
SMBU
S
PE
rw
rw
rw
Bit 15 SWRST: Software reset
When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are
released and the bus is free.
0: I2C Peripheral not under reset
1: I2C Peripheral under reset state
Note: This bit can be used to reinitialize the peripheral after an error or a locked state. As an
example, if the BUSY bit is set and remains locked due to a glitch on the bus, the
SWRST bit can be used to exit from this state.
Bit 14 Reserved, must be kept at reset value
Bit 13 ALERT: SMBus alert
This bit is set and cleared by software, and cleared by hardware when PE=0.
0: Releases SMBA pin high. Alert Response Address Header followed by NACK.
1: Drives SMBA pin low. Alert Response Address Header followed by ACK.
Bit 12 PEC: Packet error checking
This bit is set and cleared by software, and cleared by hardware when PEC is transferred or
by a START or Stop condition or when PE=0.
0: No PEC transfer
1: PEC transfer (in Tx or Rx mode)
Note: PEC calculation is corrupted by an arbitration loss.
Bit 11 POS: Acknowledge/PEC Position (for data reception)
This bit is set and cleared by software and cleared by hardware when PE=0.
0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The
PEC bit indicates that current byte in shift register is a PEC.
1: ACK bit controls the (N)ACK of the next byte which will be received in the shift register.
The PEC bit indicates that the next byte in the shift register is a PEC
Note: The POS bit must be used only in 2-byte reception configuration in master mode. It
must be configured before data reception starts, as described in the 2-byte reception
procedure recommended in Section : Master receiver on page 472.
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Bit 10 ACK: Acknowledge enable
This bit is set and cleared by software and cleared by hardware when PE=0.
0: No acknowledge returned
1: Acknowledge returned after a byte is received (matched address or data)
Bit 9 STOP: Stop generation
The bit is set and cleared by software, cleared by hardware when a Stop condition is
detected, set by hardware when a timeout error is detected.
In Master Mode:
0: No Stop generation.
1: Stop generation after the current byte transfer or after the current Start condition is sent.
In Slave mode:
0: No Stop generation.
1: Release the SCL and SDA lines after the current byte transfer.
Bit 8 START: Start generation
This bit is set and cleared by software and cleared by hardware when start is sent or PE=0.
In Master Mode:
0: No Start generation
1: Repeated start generation
In Slave mode:
0: No Start generation
1: Start generation when the bus is free
Bit 7 NOSTRETCH: Clock stretching disable (Slave mode)
This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until
it is reset by software.
0: Clock stretching enabled
1: Clock stretching disabled
Bit 6 ENGC: General call enable
0: General call disabled. Address 00h is NACKed.
1: General call enabled. Address 00h is ACKed.
Bit 5 ENPEC: PEC enable
0: PEC calculation disabled
1: PEC calculation enabled
Bit 4 ENARP: ARP enable
0: ARP disable
1: ARP enable
SMBus Device default address recognized if SMBTYPE=0
SMBus Host address recognized if SMBTYPE=1
Bit 3 SMBTYPE: SMBus type
0: SMBus Device
1: SMBus Host
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Bit 2 Reserved, must be kept at reset value
Bit 1 SMBUS: SMBus mode
0: I2C mode
1: SMBus mode
Bit 0 PE: Peripheral enable
0: Peripheral disable
1: Peripheral enable
Note: If this bit is reset while a communication is on going, the peripheral is disabled at the
end of the current communication, when back to IDLE state.
All bit resets due to PE=0 occur at the end of the communication.
In master mode, this bit must not be reset before the end of the communication.
Note:
When the STOP, START or PEC bit is set, the software must not perform any write access
to I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of setting a
second STOP, START or PEC request.
18.6.2
I2C Control register 2 (I2C_CR2)
Address offset: 0x04
Reset value: 0x0000
15
14
13
Reserved
12
11
LAST
DMA
EN
rw
rw
10
9
8
ITBUF ITEVTE ITERR
EN
N
EN
rw
rw
7
6
5
4
2
1
0
rw
rw
FREQ[5:0]
Reserved
rw
3
rw
rw
rw
rw
Bits 15:13 Reserved, must be kept at reset value
Bit 12 LAST: DMA last transfer
0: Next DMA EOT is not the last transfer
1: Next DMA EOT is the last transfer
Note: This bit is used in master receiver mode to permit the generation of a NACK on the last
received data.
Bit 11 DMAEN: DMA requests enable
0: DMA requests disabled
1: DMA request enabled when TxE=1 or RxNE =1
Bit 10 ITBUFEN: Buffer interrupt enable
0: TxE = 1 or RxNE = 1 does not generate any interrupt.
1: TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)
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Bit 9 ITEVTEN: Event interrupt enable
0: Event interrupt disabled
1: Event interrupt enabled
This interrupt is generated when:
–
SB = 1 (Master)
–
ADDR = 1 (Master/Slave)
–
ADD10= 1 (Master)
–
STOPF = 1 (Slave)
–
BTF = 1 with no TxE or RxNE event
–
TxE event to 1 if ITBUFEN = 1
–
RxNE event to 1if ITBUFEN = 1
ITERREN: Error interrupt enable
0: Error interrupt disabled
1: Error interrupt enabled
This interrupt is generated when:
–
BERR = 1
–
ARLO = 1
–
AF = 1
–
OVR = 1
–
PECERR = 1
–
TIMEOUT = 1
–
SMBALERT = 1
Bits 7:6 Reserved, must be kept at reset value
Bits 5:0 FREQ[5:0]: Peripheral clock frequency
The FREQ bits must be configured with the APB clock frequency value (I2C peripheral
connected to APB). The FREQ field is used by the peripheral to generate data setup and
hold times compliant with the I2C specifications. The minimum allowed frequency is 2 MHz,
the maximum frequency is limited by the maximum APB frequency (42 MHz) and an intrinsic
limitation of 46 MHz.
0b000000: Not allowed
0b000001: Not allowed
0b000010: 2 MHz
...
0b101010: 42MHz
Higher than 0b101010: Not allowed
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I2C Own address register 1 (I2C_OAR1)
18.6.3
Address offset: 0x08
Reset value: 0x0000
15
14
13
ADD
MODE
12
11
10
9
8
7
6
5
ADD[9:8]
Reserved
rw
rw
rw
4
3
2
1
ADD[7:1]
rw
rw
rw
rw
0
ADD0
rw
rw
rw
rw
Bit 15 ADDMODE Addressing mode (slave mode)
0: 7-bit slave address (10-bit address not acknowledged)
1: 10-bit slave address (7-bit address not acknowledged)
Bit 14
Bits 13:10
Should always be kept at 1 by software.
Reserved, must be kept at reset value
Bits 9:8 ADD[9:8]: Interface address
7-bit addressing mode: don’t care
10-bit addressing mode: bits9:8 of address
Bits 7:1 ADD[7:1]: Interface address
bits 7:1 of address
Bit 0 ADD0: Interface address
7-bit addressing mode: don’t care
10-bit addressing mode: bit 0 of address
I2C Own address register 2 (I2C_OAR2)
18.6.4
Address offset: 0x0C
Reset value: 0x0000
15
14
13
12
11
Reserved
10
9
8
7
6
5
rw
rw
rw
4
3
2
1
rw
rw
rw
ADD2[7:1]
rw
0
ENDUAL
rw
Bits 15:8 Reserved, must be kept at reset value
Bits 7:1 ADD2[7:1]: Interface address
bits 7:1 of address in dual addressing mode
Bit 0 ENDUAL: Dual addressing mode enable
0: Only OAR1 is recognized in 7-bit addressing mode
1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode
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I2C Data register (I2C_DR)
18.6.5
Address offset: 0x10
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
DR[7:0]
Reserved
rw
rw
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value
Bits 7:0 DR[7:0] 8-bit data register
Byte received or to be transmitted to the bus.
– Transmitter mode: Byte transmission starts automatically when a byte is written in the DR
register. A continuous transmit stream can be maintained if the next data to be transmitted is
put in DR once the transmission is started (TxE=1)
– Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream
can be maintained if DR is read before the next data byte is received (RxNE=1).
Note: In slave mode, the address is not copied into DR.
Write collision is not managed (DR can be written if TxE=0).
If an ARLO event occurs on ACK pulse, the received byte is not copied into DR
and so cannot be read.
I2C Status register 1 (I2C_SR1)
18.6.6
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
SMB
ALERT
TIME
OUT
Res.
PEC
ERR
OVR
AF
ARLO
BERR
TxE
RxNE
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
r
r
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5
Res.
4
3
STOPF ADD10
r
r
2
1
0
BTF
ADDR
SB
r
r
r
Inter-integrated circuit (I2C) interface
RM0383
Bit 15 SMBALERT: SMBus alert
In SMBus host mode:
0: no SMBALERT
1: SMBALERT event occurred on pin
In SMBus slave mode:
0: no SMBALERT response address header
1: SMBALERT response address header to SMBALERT LOW received
– Cleared by software writing 0, or by hardware when PE=0.
Bit 14 TIMEOUT: Timeout or Tlow error
0: No timeout error
1: SCL remained LOW for 25 ms (Timeout)
or
Master cumulative clock low extend time more than 10 ms (Tlow:mext)
or
Slave cumulative clock low extend time more than 25 ms (Tlow:sext)
– When set in slave mode: slave resets the communication and lines are released by
hardware
– When set in master mode: Stop condition sent by hardware
– Cleared by software writing 0, or by hardware when PE=0.
Note: This functionality is available only in SMBus mode.
Bit 13 Reserved, must be kept at reset value
Bit 12 PECERR: PEC Error in reception
0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: PEC error: receiver returns NACK after PEC reception (whatever ACK)
– Cleared by software writing 0, or by hardware when PE=0.
– Note: When the received CRC is wrong, PECERR is not set in slave mode if the PEC control
bit is not set before the end of the CRC reception. Nevertheless, reading the PEC value
determines whether the received CRC is right or wrong.
Bit 11 OVR: Overrun/Underrun
0: No overrun/underrun
1: Overrun or underrun
– Set by hardware in slave mode when NOSTRETCH=1 and:
– In reception when a new byte is received (including ACK pulse) and the DR register has not
been read yet. New received byte is lost.
– In transmission when a new byte should be sent and the DR register has not been written
yet. The same byte is sent twice.
– Cleared by software writing 0, or by hardware when PE=0.
Note: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a
hold timing error occurs
Bit 10 AF: Acknowledge failure
0: No acknowledge failure
1: Acknowledge failure
– Set by hardware when no acknowledge is returned.
– Cleared by software writing 0, or by hardware when PE=0.
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Bit 9 ARLO: Arbitration lost (master mode)
0: No Arbitration Lost detected
1: Arbitration Lost detected
Set by hardware when the interface loses the arbitration of the bus to another master
– Cleared by software writing 0, or by hardware when PE=0.
After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Note: In SMBUS, the arbitration on the data in slave mode occurs only during the data phase,
or the acknowledge transmission (not on the address acknowledge).
Bit 8 BERR: Bus error
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
– Set by hardware when the interface detects an SDA rising or falling edge while SCL is high,
occurring in a non-valid position during a byte transfer.
– Cleared by software writing 0, or by hardware when PE=0.
Bit 7 TxE: Data register empty (transmitters)
0: Data register not empty
1: Data register empty
– Set when DR is empty in transmission. TxE is not set during address phase.
– Cleared by software writing to the DR register or by hardware after a start or a stop condition
or when PE=0.
TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)
Note: TxE is not cleared by writing the first data being transmitted, or by writing data when
BTF is set, as in both cases the data register is still empty.
Bit 6 RxNE: Data register not empty (receivers)
0: Data register empty
1: Data register not empty
– Set when data register is not empty in receiver mode. RxNE is not set during address phase.
– Cleared by software reading or writing the DR register or by hardware when PE=0.
RxNE is not set in case of ARLO event.
Note: RxNE is not cleared by reading data when BTF is set, as the data register is still full.
Bit 5 Reserved, must be kept at reset value
Bit 4 STOPF: Stop detection (slave mode)
0: No Stop condition detected
1: Stop condition detected
– Set by hardware when a Stop condition is detected on the bus by the slave after an
acknowledge (if ACK=1).
– Cleared by software reading the SR1 register followed by a write in the CR1 register, or by
hardware when PE=0
Note: The STOPF bit is not set after a NACK reception.
It is recommended to perform the complete clearing sequence (READ SR1 then
WRITE CR1) after the STOPF is set. Refer to Figure 163: Transfer sequence diagram
for slave receiver on page 468.
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Bit 3 ADD10: 10-bit header sent (Master mode)
0: No ADD10 event occurred.
1: Master has sent first address byte (header).
– Set by hardware when the master has sent the first byte in 10-bit address mode.
– Cleared by software reading the SR1 register followed by a write in the DR register of the
second address byte, or by hardware when PE=0.
Note: ADD10 bit is not set after a NACK reception
Bit 2 BTF: Byte transfer finished
0: Data byte transfer not done
1: Data byte transfer succeeded
– Set by hardware when NOSTRETCH=0 and:
– In reception when a new byte is received (including ACK pulse) and DR has not been read
yet (RxNE=1).
– In transmission when a new byte should be sent and DR has not been written yet (TxE=1).
– Cleared by software by either a read or write in the DR register or by hardware after a start or
a stop condition in transmission or when PE=0.
Note: The BTF bit is not set after a NACK reception
The BTF bit is not set if next byte to be transmitted is the PEC (TRA=1 in I2C_SR2
register and PEC=1 in I2C_CR1 register)
Bit 1 ADDR: Address sent (master mode)/matched (slave mode)
This bit is cleared by software reading SR1 register followed reading SR2, or by hardware
when PE=0.
Address matched (Slave)
0: Address mismatched or not received.
1: Received address matched.
– Set by hardware as soon as the received slave address matched with the OAR registers
content or a general call or a SMBus Device Default Address or SMBus Host or SMBus Alert
is recognized. (when enabled depending on configuration).
Note: In slave mode, it is recommended to perform the complete clearing sequence (READ
SR1 then READ SR2) after ADDR is set. Refer to Figure 163: Transfer sequence
diagram for slave receiver on page 468.
Address sent (Master)
0: No end of address transmission
1: End of address transmission
– For 10-bit addressing, the bit is set after the ACK of the 2nd byte.
– For 7-bit addressing, the bit is set after the ACK of the byte.
Note: ADDR is not set after a NACK reception
Bit 0 SB: Start bit (Master mode)
0: No Start condition
1: Start condition generated.
– Set when a Start condition generated.
– Cleared by software by reading the SR1 register followed by writing the DR register, or by
hardware when PE=0
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I2C Status register 2 (I2C_SR2)
18.6.7
Address offset: 0x18
Reset value: 0x0000
Note:
15
Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was
set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found
set in I2C_SR1 or when the STOPF bit is cleared.
14
13
12
11
10
9
8
PEC[7:0]
r
r
r
r
r
r
r
r
7
6
5
4
3
DUALF
SMB
HOST
SMBDE
FAULT
GEN
CALL
Res.
r
r
r
r
2
1
0
TRA
BUSY
MSL
r
r
r
Bits 15:8 PEC[7:0] Packet error checking register
This register contains the internal PEC when ENPEC=1.
Bit 7 DUALF: Dual flag (Slave mode)
0: Received address matched with OAR1
1: Received address matched with OAR2
– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
Bit 6 SMBHOST: SMBus host header (Slave mode)
0: No SMBus Host address
1: SMBus Host address received when SMBTYPE=1 and ENARP=1.
– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
Bit 5 SMBDEFAULT: SMBus device default address (Slave mode)
0: No SMBus Device Default address
1: SMBus Device Default address received when ENARP=1
– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
Bit 4 GENCALL: General call address (Slave mode)
0: No General Call
1: General Call Address received when ENGC=1
– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
Bit 3 Reserved, must be kept at reset value
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Bit 2 TRA: Transmitter/receiver
0: Data bytes received
1: Data bytes transmitted
This bit is set depending on the R/W bit of the address byte, at the end of total address
phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start
condition, loss of bus arbitration (ARLO=1), or when PE=0.
Bit 1 BUSY: Bus busy
0: No communication on the bus
1: Communication ongoing on the bus
– Set by hardware on detection of SDA or SCL low
– cleared by hardware on detection of a Stop condition.
It indicates a communication in progress on the bus. This information is still updated when
the interface is disabled (PE=0).
Bit 0 MSL: Master/slave
0: Slave Mode
1: Master Mode
– Set by hardware as soon as the interface is in Master mode (SB=1).
– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
(ARLO=1), or by hardware when PE=0.
Note:
Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was
set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found
set in I2C_SR1 or when the STOPF bit is cleared.
18.6.8
I2C Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note:
fPCLK1 must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4
MHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the
400 kHz maximum I²C Fm mode clock.
The CCR register must be configured only when the I2C is disabled (PE = 0).
15
14
F/S
DUTY
rw
rw
13
12
Reserved
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
CCR[11:0]
rw
rw
rw
rw
rw
rw
rw
Bit 15 F/S: I2C master mode selection
0: Sm mode I2C
1: Fm mode I2C
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Bit 14 DUTY: Fm mode duty cycle
0: Fm mode tlow/thigh = 2
1: Fm mode tlow/thigh = 16/9 (see CCR)
Bits 13:12 Reserved, must be kept at reset value
Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)
Controls the SCL clock in master mode.
Sm mode or SMBus:
Thigh = CCR * TPCLK1
Tlow = CCR * TPCLK1
Fm mode:
If DUTY = 0:
Thigh = CCR * TPCLK1
Tlow = 2 * CCR * TPCLK1
If DUTY = 1: (to reach 400 kHz)
Thigh = 9 * CCR * TPCLK1
Tlow = 16 * CCR * TPCLK1
For instance: in Sm mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, TPCLK1 = 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40d x 125 ns = 5000 ns.)
Note: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum
allowed value is 0x01
thigh = tr(SCL) + tw(SCLH). See device datasheet for the definitions of parameters.
tlow = tf(SCL) + tw(SCLL). See device datasheet for the definitions of parameters.
I2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to
the analog noise filter input delay.
The CCR register must be configured only when the I2C is disabled (PE = 0).
I2C TRISE register (I2C_TRISE)
18.6.9
Address offset: 0x20
Reset value: 0x0002
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
TRISE[5:0]
Reserved
rw
rw
rw
rw
Bits 15:6 Reserved, must be kept at reset value
Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)
These bits should provide the maximum duration of the SCL feedback loop in master mode.
The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
These bits must be programmed with the maximum SCL rise time given in the I2C bus
specification, incremented by 1.
For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and TPCLK1 = 125 ns
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the tHIGH parameter.
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
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Inter-integrated circuit (I2C) interface
RM0383
18.6.10
I2C FLTR register (I2C_FLTR)
Address offset: 0x24
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
rw
rw
rw
0
DNF[3:0]
ANOFF
Reserved
1
rw
rw
Bits 15:5 Reserved, must be kept at reset value
Bit 4 ANOFF: Analog noise filter OFF
0: Analog noise filter enable
1: Analog noise filter disable
Note: ANOFF must be configured only when the I2C is disabled (PE = 0).
Bits 3:0 DNF[3:0]: Digital noise filter
These bits are used to configure the digital noise filter on SDA and SCL inputs. The digital filter
will suppress the spikes with a length of up to DNF[3:0] * TPCLK1.
0000: Digital noise filter disable
0001: Digital noise filter enabled and filtering capability up to 1* TPCLK1.
...
1111: Digital noise filter enabled and filtering capability up to 15* TPCLK1.
Note: DNF[3:0] must be configured only when the I2C is disabled (PE = 0). If the analog filter
is also enabled, the digital filter is added to the analog filter.
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Inter-integrated circuit (I2C) interface
18.6.11
RM0383
I2C register map
The table below provides the I2C register map and reset values.
ENGC
ENPEC
ENARP
SMBTYPE
0
0
0
0
0
0
0
0
ITBUFEN
ITEVTEN
ITERREN
0
0
0
0
0
0
I2C_TRISE
0
0
0
0
ADD0
0
0
0
0
0
0
BTF
ADDR
SB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CCR[11:0]
0
0
0
0
0
0
0
0
0
TRISE[5:0]
Reserved
0
DocID026448 Rev 1
0
GENCALL
0
0
SMBDEFAULT
AF
ARLO
0
0
TxE
0
0
0
RxNE
0
0
0
DUALF
0
0
SMBHOST
OVR
0
0
BERR
PECERR
Reserved
TIMEOUT
0
0
MSL
Reserved
0
Reset value
496/836
0
PEC[7:0]
Reset value
0x20
0
Reserved
I2C_CCR
0
Reserved
Reset value
0x1C
0
F/S
I2C_SR2
0
0
DR[7:0]
SMBALERT
Reserved
Reset value
0x18
0
Reserved
DUTY
I2C_SR1
0
ADD2[7:1]
Reset value
0x14
0
0
I2C_DR
0
ADD[7:1]
Reserved
Reset value
0x10
0
TRA
I2C_OAR2
0
0
BUSY
0x0C
0
0
ADD10
Reset value
ADD[9:8]
Reserved
0
Reserved
Reserved
0
STOPF
I2C_OAR1
0
FREQ[5:0]
Reserved
0x08
ADDMODE
Reset value
0
ENDUAL
Reserved
PE
NOSTRETCH
0
SMBUS
START
0
Reserved
7
6
5
4
3
2
1
0
ACK
STOP
0
Reserved
8
PEC
I2C_CR2
POS
0x04
0
DMAEN
Reset value
ALERT
Reserved
LAST
I2C_CR1
SWRST
0x00
Register
Reserved
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Table 70. I2C register map and reset values
0
0
0
1
0
Inter-integrated circuit (I2C) interface
RM0383
I2C_FLTR
Reserved
Reset value
7
6
5
4
3
2
1
0
ANOFF
0x24
Register
8
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Table 70. I2C register map and reset values (continued)
0
DNF[3:0]
0
0
0
0
Refer to Table 3 on page 41 for the register boundary addresses table.
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Universal synchronous asynchronous receiver transmitter (USART)
19
Universal synchronous asynchronous receiver
transmitter (USART)
19.1
USART introduction
RM0383
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format. The USART offers a very wide range of baud rates
using a fractional baud rate generator.
It supports synchronous one-way communication and half-duplex single wire
communication. It also supports the LIN (local interconnection network), Smartcard Protocol
and IrDA (infrared data association) SIR ENDEC specifications, and modem operations
(CTS/RTS). It allows multiprocessor communication.
High speed data communication is possible by using the DMA for multibuffer configuration.
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RM0383
19.2
Universal synchronous asynchronous receiver transmitter (USART)
USART main features
•
Full duplex, asynchronous communications
•
NRZ standard format (Mark/Space)
•
Configurable oversampling method by 16 or by 8 to give flexibility between speed and
clock tolerance
•
Fractional baud rate generator systems
–
Common programmable transmit and receive baud rate (refer to the datasheets
for the value of the baud rate at the maximum APB frequency.
•
Programmable data word length (8 or 9 bits)
•
Configurable stop bits - support for 1 or 2 stop bits
•
LIN Master Synchronous Break send capability and LIN slave break detection
capability
–
13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
•
Transmitter clock output for synchronous transmission
•
IrDA SIR encoder decoder
–
•
Support for 3/16 bit duration for normal mode
Smartcard emulation capability
–
The Smartcard interface supports the asynchronous protocol Smartcards as
defined in the ISO 7816-3 standards
–
0.5, 1.5 stop bits for Smartcard operation
•
Single-wire half-duplex communication
•
Configurable multibuffer communication using DMA (direct memory access)
–
Buffering of received/transmitted bytes in reserved SRAM using centralized DMA
•
Separate enable bits for transmitter and receiver
•
Transfer detection flags:
•
•
•
–
Receive buffer full
–
Transmit buffer empty
–
End of transmission flags
Parity control:
–
Transmits parity bit
–
Checks parity of received data byte
Four error detection flags:
–
Overrun error
–
Noise detection
–
Frame error
–
Parity error
Ten interrupt sources with flags:
–
CTS changes
–
LIN break detection
–
Transmit data register empty
–
Transmission complete
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Universal synchronous asynchronous receiver transmitter (USART)
19.3
–
Receive data register full
–
Idle line received
–
Overrun error
–
Framing error
–
Noise error
–
Parity error
RM0383
•
Multiprocessor communication - enter into mute mode if address match does not occur
•
Wake up from mute mode (by idle line detection or address mark detection)
•
Two receiver wakeup modes: Address bit (MSB, 9th bit), Idle line
USART functional description
The interface is externally connected to another device by three pins (see Figure 167). Any
USART bidirectional communication requires a minimum of two pins: Receive Data In (RX)
and Transmit Data Out (TX):
RX: Receive Data Input is the serial data input. Oversampling techniques are used for data
recovery by discriminating between valid incoming data and noise.
TX: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is enabled and nothing is to be transmitted, the TX
pin is at high level. In single-wire and smartcard modes, this I/O is used to transmit and
receive the data (at USART level, data are then received on SW_RX).
Through these pins, serial data is transmitted and received in normal USART mode as
frames comprising:
•
An Idle Line prior to transmission or reception
•
A start bit
•
A data word (8 or 9 bits) least significant bit first
•
0.5,1, 1.5, 2 Stop bits indicating that the frame is complete
•
This interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit
fraction
•
A status register (USART_SR)
•
Data Register (USART_DR)
•
A baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.
•
A Guardtime Register (USART_GTPR) in case of Smartcard mode.
Refer to Section 19.6: USART registers on page 538 for the definitions of each bit.
The following pin is required to interface in synchronous mode:
•
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SCLK: Transmitter clock output. This pin outputs the transmitter data clock for
synchronous transmission corresponding to SPI master mode (no clock pulses on start
bit and stop bit, and a software option to send a clock pulse on the last data bit). In
parallel data can be received synchronously on RX. This can be used to control
peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity
are software programmable. In smartcard mode, SCLK can provide the clock to the
smartcard.
DocID026448 Rev 1
RM0383
Universal synchronous asynchronous receiver transmitter (USART)
The following pins are required in Hardware flow control mode:
•
nCTS: Clear To Send blocks the data transmission at the end of the current transfer
when high
•
nRTS: Request to send indicates that the USART is ready to receive a data (when
low).
Figure 167. USART block diagram
PWDATA
PRDATA
Write
Read
(Data register) DR
(CPU or DMA)
(CPU or DMA)
Transmit data register (TDR)
Receive data register (RDR)
Transmit Shift Register
Receive Shift Register
TX
RX
SW_RX
IrDA
SIR
ENDEC
block
GTPR
GT
PSC
CR3
SCLK control
DMAT DMAR SCEN NACK HD IRLP IREN
LINE
STOP[1:0] CKEN CPOL CPHA LBCL
CR2
CR1
UE
USART Address
nRTS
nCTS
SCLK
CR2
M
WAKE PCE
PS
PEIE
Hardware
flow
controller
Wakeup
unit
Transmit
control
Receiver
clock
Receiver
control
SR
CR1
IDLE TE
TXEIE TCIE RXNE
IE
IE
CTS LBD
RE RWU SBK
TXE TC RXNE IDLE ORE NF FE PE
USART
interrupt
control
USART_BRR
CR1
OVER8
Transmitter
clock
/ [8 x (2 - OVER8)]
Transmitter rate
control
TE
/USARTDIV
SAMPLING
DIVIDER
DIV_Mantissa
15
fPCLKx(x=1,2)
DIV_Fraction
4
0
Receiver rate
control
RE
Conventional baud rate generator
USARTDIV = DIV_Mantissa + (DIV_Fraction / 8 × (2 – OVER8))
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Universal synchronous asynchronous receiver transmitter (USART)
19.3.1
RM0383
USART character description
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
USART_CR1 register (see Figure 168).
The TX pin is in low state during the start bit. It is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the
next frame which contains data (The number of “1” ‘s will include the number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the
start bit.
Transmission and reception are driven by a common baud rate generator, the clock for each
is generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.
Figure 168. Word length programming
9-bit word length (M bit is set), 1 stop bit
Possible
parity
bit
Data frame
Start
bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Clock
Next data frame
Next
Stop Start
bit
bit
**
Idle frame
Start
bit
Break frame
Stop
bit
Start
bit
** LBCL bit controls last data clock pulse
8-bit word length (M bit is reset), 1 stop bit
Data frame
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Clock
Bit6
Possible
Parity
Bit
Bit7
Next data frame
Stop
bit
Next
start
bit
****
**
Idle frame
Start
bit
Break frame
Stop
bit
Start
bit
** LBCL bit controls last data clock pulse
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RM0383
19.3.2
Universal synchronous asynchronous receiver transmitter (USART)
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the transmit enable bit (TE) is set, the data in the transmit shift register is output on
the TX pin and the corresponding clock pulses are output on the SCLK pin.
Character transmission
During an USART transmission, data shifts out least significant bit first on the TX pin. In this
mode, the USART_DR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 167).
Every character is preceded by a start bit which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.
Note:
The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.
•
1 stop bit: This is the default value of number of stop bits.
•
2 Stop bits: This will be supported by normal USART, single-wire and modem modes.
•
0.5 stop bit: To be used when receiving data in Smartcard mode.
•
1.5 stop bits: To be used when transmitting and receiving data in Smartcard mode.
An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits followed by the configured number of stop bits
(when m = 0) and 11 low bits followed by the configured number of stop bits (when m = 1). It
is not possible to transmit long breaks (break of length greater than 10/11 low bits).
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Figure 169. Configurable stop bits
8-bit Word length (M bit is reset)
Possible
parity
bit
Data frame
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Stop
bit
Bit7
CLOCK
Next data frame
Next
start
bit
****
**
** LBCL bit controls last data clock pulse
a) 1 Stop Bit
Possible
Parity
Bit
Data frame
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
1 1/2 stop bits
Possible
parity
bit
Data frame
Bit0
c) 2 Stop Bits
Start
Bit
Bit0
Next
start
bit
Bit7
b) 1 1/2 stop Bits
Start
Bit
Next data frame
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Possible
Parity
Bit
Data frame
Bit1
Bit2
Bit7
Bit3
Bit4
Bit5
Bit6
Bit7
Next data frame
2 Stop
Bits
Next
Start
Bit
Next data frame
Next
start
bit
1/2 stop bit
d) 1/2 Stop Bit
Procedure:
1.
Enable the USART by writing the UE bit in USART_CR1 register to 1.
2.
Program the M bit in USART_CR1 to define the word length.
3.
Program the number of stop bits in USART_CR2.
4.
Select DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take
place. Configure the DMA register as explained in multibuffer communication.
5.
Select the desired baud rate using the USART_BRR register.
6.
Set the TE bit in USART_CR1 to send an idle frame as first transmission.
7.
Write the data to send in the USART_DR register (this clears the TXE bit). Repeat this
for each data to be transmitted in case of single buffer.
8.
After writing the last data into the USART_DR register, wait until TC=1. This indicates
that the transmission of the last frame is complete. This is required for instance when
the USART is disabled or enters the Halt mode to avoid corrupting the last
transmission.
Single byte communication
Clearing the TXE bit is always performed by a write to the data register.
The TXE bit is set by hardware and it indicates:
•
The data has been moved from TDR to the shift register and the data transmission has
started.
•
The TDR register is empty.
•
The next data can be written in the USART_DR register without overwriting the
previous data.
This flag generates an interrupt if the TXEIE bit is set.
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Universal synchronous asynchronous receiver transmitter (USART)
When a transmission is taking place, a write instruction to the USART_DR register stores
the data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the USART_DR register places
the data directly in the shift register, the data transmission starts, and the TXE bit is
immediately set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data into the USART_DR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low power mode
(see Figure 170: TC/TXE behavior when transmitting).
The TC bit is cleared by the following software sequence:
Note:
1.
A read from the USART_SR register
2.
A write to the USART_DR register
The TC bit can also be cleared by writing a ‘0 to it. This clearing sequence is recommended
only for Multibuffer communication.
Figure 170. TC/TXE behavior when transmitting
Idle preamble
Frame 2
Frame 1
Frame 3
TX line
set by hardware
cleared by software
TXE flag
USART_DR
F1
set by hardware
cleared by software
F2
set by hardware
F3
set
by hardware
TC flag
software
enables the
USART
software waits until TXE=1
and writes F2 into DR
software waits until TXE=1
and writes F1 into DR
TC is not set
because TXE=0
software waits until TXE=1
and writes F3 into DR
TC is not set
because TXE=0
TC is set because
TXE=1
software waits until TC=1
ai17121b
Break characters
Setting the SBK bit transmits a break character. The break frame length depends on the M
bit (see Figure 168).
If the SBK bit is set to ‘1 a break character is sent on the TX line after completing the current
character transmission. This bit is reset by hardware when the break character is completed
(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the
last break frame to guarantee the recognition of the start bit of the next frame.
Note:
If the software resets the SBK bit before the commencement of break transmission, the
break character will not be transmitted. For two consecutive breaks, the SBK bit should be
set after the stop bit of the previous break.
Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.
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Universal synchronous asynchronous receiver transmitter (USART)
19.3.3
RM0383
Receiver
The USART can receive data words of either 8 or 9 bits depending on the M bit in the
USART_CR1 register.
Start bit detection
The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0 X 0 0 0 0.
Figure 171. Start bit detection when oversampling by 16 or 8
RX state
Idle
Start bit
RX line
Ideal
sample
clock
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
sampled values
Real
sample
clock
X
X
X
X
X
X
X
X
9
10
11 12 13 14 15 16
6/16
7/16
7/16
One-bit time
Conditions
to validate 1 1 1 0
the start bit
Falling edge
detection
Note:
X
0
X
0
X
0
At least 2 bits
out of 3 at 0
0
0
0
At least 2 bits
out of 3 at 0
X
X
X
X
X
X
ai15471
If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set) where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled
bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NE noise
flag is set if, for both samplings, at least 2 out of the 3 sampled bits are at 0 (sampling on the
3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits). If this condition is not met,
the start detection aborts and the receiver returns to the idle state (no flag is set).
If, for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th
and 10th bits), 2 out of the 3 bits are found at 0, the start bit is validated but the NE noise
flag bit is set.
Character reception
During an USART reception, data shifts in least significant bit first through the RX pin. In this
mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the
received shift register.
Procedure:
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RM0383
Universal synchronous asynchronous receiver transmitter (USART)
1.
Enable the USART by writing the UE bit in USART_CR1 register to 1.
2.
Program the M bit in USART_CR1 to define the word length.
3.
Program the number of stop bits in USART_CR2.
4.
Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication. STEP 3
5.
Select the desired baud rate using the baud rate register USART_BRR
6.
Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.
When a character is received
Note:
•
The RXNE bit is set. It indicates that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
•
An interrupt is generated if the RXNEIE bit is set.
•
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
•
In multibuffer, RXNE is set after every byte received and is cleared by the DMA read to
the Data Register.
•
In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_DR register. The RXNE flag can also be cleared by writing a zero to it. The
RXNE bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
The RE bit should not be reset while receiving data. If the RE bit is disabled during
reception, the reception of the current byte will be aborted.
Break character
When a break character is received, the USART handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the IDLEIE bit is set.
Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
Note:
•
The ORE bit is set.
•
The RDR content will not be lost. The previous data is available when a read to
USART_DR is performed.
•
The shift register will be overwritten. After that point, any data received during overrun
is lost.
•
An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits
are set.
•
The ORE bit is reset by a read to the USART_SR register followed by a USART_DR
register read operation.
The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
•
if RXNE=1, then the last valid data is stored in the receive register RDR and can be
read,
•
if RXNE=0, then it means that the last valid data has already been read and thus there
is nothing to be read in the RDR. This case can occur when the last valid data is read in
the RDR at the same time as the new (and lost) data is received. It may also occur
when the new data is received during the reading sequence (between the USART_SR
register read access and the USART_DR read access).
Selecting the proper oversampling method
The receiver implements different user-configurable oversampling techniques (except in
synchronous mode) for data recovery by discriminating between valid incoming data and
noise.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 172 and
Figure 173).
Depending on the application:
•
select oversampling by 8 (OVER8=1) to achieve higher speed (up to fPCLK/8). In this
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 19.3.5: USART receiver tolerance to clock deviation on page 521)
•
select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock
deviations. In this case, the maximum speed is limited to maximum fPCLK/16
Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:
•
the majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set
•
a single sample in the center of the received bit
Depending on the application:
508/836
–
select the three samples’ majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 71) because this indicates that a glitch occurred during the sampling.
–
select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver’s tolerance to clock deviations (see Section 19.3.5: USART
DocID026448 Rev 1
RM0383
Universal synchronous asynchronous receiver transmitter (USART)
receiver tolerance to clock deviation on page 521). In this case the NF bit will
never be set.
When noise is detected in a frame:
•
The NF bit is set at the rising edge of the RXNE bit.
•
The invalid data is transferred from the Shift register to the USART_DR register.
•
No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.
The NF bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.
Note:
Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes,
the OVER8 bit is forced to ‘0 by hardware.
Figure 172. Data sampling when oversampling by 16
RX LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
Figure 173. Data sampling when oversampling by 8
RX LINE
sampled values
Sample
clock(x8)
1
2
3
4
5
6
7
8
2/8
3/8
3/8
One bit time
Table 71. Noise detection from sampled data
Sampled value
NE status
Received bit value
000
0
0
001
1
0
010
1
0
011
1
1
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Table 71. Noise detection from sampled data (continued)
Sampled value
NE status
Received bit value
100
1
0
101
1
1
110
1
1
111
0
1
Framing error
A framing error is detected when:
The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise.
When the framing error is detected:
•
The FE bit is set by hardware
•
The invalid data is transferred from the Shift register to the USART_DR register.
•
No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.
The FE bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.
Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
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1.
0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As
a consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
2.
1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
3.
1.5 stop bits (Smartcard mode): When transmitting in smartcard mode, the device
must check that the data is correctly sent. Thus the receiver block must be enabled (RE
=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has
detected a parity error. In the event of a parity error, the smartcard forces the data
signal low during the sampling - NACK signal-, which is flagged as a framing error.
Then, the FE flag is set with the RXNE at the end of the 1.5 stop bit. Sampling for 1.5
stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the
beginning of the stop bit). The 1.5 stop bit can be decomposed into 2 parts: one 0.5
baud clock period during which nothing happens, followed by 1 normal stop bit period
during which sampling occurs halfway through. Refer to Section 19.3.11: Smartcard on
page 529 for more details.
4.
2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the
first stop bit. If a framing error is detected during the first stop bit the framing error flag
will be set. The second stop bit is not checked for framing error. The RXNE flag will be
set at the end of the first stop bit.
DocID026448 Rev 1
RM0383
19.3.4
Universal synchronous asynchronous receiver transmitter (USART)
Fractional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the Mantissa and Fraction values of USARTDIV.
Equation 1: Baud rate for standard USART (SPI mode included)
f CK
Tx/Rx baud = ------------------------------------------------------------------------------------8 × ( 2 – OVER8 ) × USARTDIV
Equation 2: Baud rate in Smartcard, LIN and IrDA modes
f CK
Tx/Rx baud = ---------------------------------------------16 × USARTDIV
USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
Note:
•
When OVER8=0, the fractional part is coded on 4 bits and programmed by the
DIV_fraction[3:0] bits in the USART_BRR register
•
When OVER8=1, the fractional part is coded on 3 bits and programmed by the
DIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction[3] must be kept
cleared.
The baud counters are updated to the new value in the baud registers after a write operation
to USART_BRR. Hence the baud rate register value should not be changed during
communication.
How to derive USARTDIV from USART_BRR register values when OVER8=0
Example 1:
If DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then
Mantissa (USARTDIV) = 0d27
Fraction (USARTDIV) = 12/16 = 0d0.75
Therefore USARTDIV = 0d27.75
Example 2:
To program USARTDIV = 0d25.62
This leads to:
DIV_Fraction = 16*0d0.62 = 0d9.92
The nearest real number is 0d10 = 0xA
DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19
Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625
Example 3:
To program USARTDIV = 0d50.99
This leads to:
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
DIV_Fraction = 16*0d0.99 = 0d15.84
The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000
How to derive USARTDIV from USART_BRR register values when OVER8=1
Example 1:
If DIV_Mantissa = 0x27 and DIV_Fraction[2:0]= 0d6 (USART_BRR = 0x1B6), then
Mantissa (USARTDIV) = 0d27
Fraction (USARTDIV) = 6/8 = 0d0.75
Therefore USARTDIV = 0d27.75
Example 2:
To program USARTDIV = 0d25.62
This leads to:
DIV_Fraction = 8*0d0.62 = 0d4.96
The nearest real number is 0d5 = 0x5
DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19
Then, USART_BRR = 0x195 => USARTDIV = 0d25.625
Example 3:
To program USARTDIV = 0d50.99
This leads to:
DIV_Fraction = 8*0d0.99 = 0d7.92
The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x0330 => USARTDIV = 0d51.000
Table 72. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,
oversampling by 16(1)
Oversampling by 16 (OVER8=0)
Baud rate7
fPCLK = 8 MHz
fPCLK = 12 MHz
Value
% Error =
programmed
(Calculated in the baud Desired) B.rate /
rate register
Desired B.rate
Actual
Value
programmed
in the baud
rate register
% Error
S.No
Desired
Actual
1
1.2 KBps
1.2 KBps
416.6875
0
1.2 KBps
625
0
2
2.4 KBps
2.4 KBps
208.3125
0.01
2.4 KBps
312.5
0
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RM0383
Universal synchronous asynchronous receiver transmitter (USART)
Table 72. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,
oversampling by 16(1) (continued)
Oversampling by 16 (OVER8=0)
Baud rate7
fPCLK = 8 MHz
fPCLK = 12 MHz
Value
% Error =
programmed
(Calculated in the baud Desired) B.rate /
rate register
Desired B.rate
Actual
Value
programmed
in the baud
rate register
% Error
S.No
Desired
Actual
3
9.6 KBps
9.604 KBps
52.0625
0.04
9.6 KBps
78.125
0
4
19.2 KBps
19.185 KBps
26.0625
0.08
19.2 KBps
39.0625
0
5
38.4 KBps
38.462 KBps
13
0.16
38.339 KBps
19.5625
0.16
6
57.6 KBps
57.554 KBps
8.6875
0.08
57.692 KBps
13
0.16
7
115.2 KBps 115.942 KBps
4.3125
0.64
115.385 KBps
6.5
0.16
8
230.4 KBps 228.571 KBps
2.1875
0.79
230.769 KBps
3.25
0.16
9
460.8 KBps 470.588 KBps
1.0625
2.12
461.538 KBps
1.625
0.16
10
921.6 KBps
NA
NA
NA
NA
NA
NA
11
2 MBps
NA
NA
NA
NA
NA
NA
12
3 MBps
NA
NA
NA
NA
NA
NA
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 73. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz,
oversampling by 8(1)
Oversampling by 8 (OVER8 = 1)
Baud rate
fPCLK = 8 MHz
fPCLK = 12 MHz
% Error =
Value
(Calculated programmed
Desired)
in the baud
B.rate /
rate register
Desired
B.rate
Value
programmed
% Error
in the baud
rate register
S.No
Desired
Actual
1
1.2 KBps
1.2 KBps
833.375
0
1.2 KBps
1250
0
2
2.4 KBps
2.4 KBps
416.625
0.01
2.4 KBps
625
0
3
9.6 KBps
9.604 KBps
104.125
0.04
9.6 KBps
156.25
0
4
19.2 KBps
19.185 KBps
52.125
0.08
19.2 KBps
78.125
0
5
38.4 KBps
38.462 KBps
26
0.16
38.339 KBps
39.125
0.16
6
57.6 KBps
57.554 KBps
17.375
0.08
57.692 KBps
26
0.16
7
115.2 KBps
115.942 KBps
8.625
0.64
115.385 KBps
13
0.16
8
230.4 KBps
228.571 KBps
4.375
0.79
230.769 KBps
6.5
0.16
9
460.8 KBps
470.588 KBps
2.125
2.12
461.538 KBps
3.25
0.16
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Actual
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Table 73. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz,
oversampling by 8(1) (continued)
Oversampling by 8 (OVER8 = 1)
Baud rate
fPCLK = 8 MHz
fPCLK = 12 MHz
% Error =
Value
(Calculated programmed
Desired)
in the baud
B.rate /
rate register
Desired
B.rate
Value
programmed
% Error
in the baud
rate register
S.No
Desired
Actual
10
921.6 KBps
888.889 KBps
1.125
3.55
923.077 KBps
1.625
0.16
11
2 MBps
NA
NA
NA
NA
NA
NA
12
3 MBps
NA
NA
NA
NA
NA
NA
Actual
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 74. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,
oversampling by 16(1)
Oversampling by 16 (OVER8 = 0)
Baud rate
fPCLK
= 16 MHz
fPCLK
Value
% Error =
programmed
(Calculated in the baud Desired) B.rate /
rate register Desired B.rate
= 24 MHz
Value
programmed
% Error
in the baud
rate register
S.No
Desired
Actual
1
1.2 KBps
1.2 KBps
833.3125
0
1.2
1250
0
2
2.4 KBps
2.4 KBps
416.6875
0
2.4
625
0
3
9.6 KBps
9.598 KBps
104.1875
0.02
9.6
156.25
0
4
19.2 KBps
19.208 KBps
52.0625
0.04
19.2
78.125
0
5
38.4 KBps
38.369 KBps
26.0625
0.08
38.4
39.0625
0
6
57.6 KBps
57.554 KBps
17.375
0.08
57.554
26.0625
0.08
7
115.2 KBps
115.108 KBps
8.6875
0.08
115.385
13
0.16
8
230.4 KBps
231.884 KBps
4.3125
0.64
230.769
6.5
0.16
9
460.8 KBps
457.143 KBps
2.1875
0.79
461.538
3.25
0.16
10
921.6 KBps
941.176 KBps
1.0625
2.12
923.077
1.625
0.16
11
2 MBps
NA
NA
NA
NA
NA
NA
12
3 MBps
NA
NA
NA
NA
NA
NA
Actual
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
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RM0383
Universal synchronous asynchronous receiver transmitter (USART)
Table 75. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,
oversampling by 8(1)
Oversampling by 8 (OVER8=1)
Baud rate
fPCLK = 16 MHz
fPCLK = 24 MHz
Value
% Error =
programmed
(Calculated in the baud Desired) B.rate /
rate register
Desired B.rate
Value
programmed
% Error
in the baud
rate register
S.No
Desired
Actual
1
1.2 KBps
1.2 KBps
1666.625
0
1.2 KBps
2500
0
2
2.4 KBps
2.4 KBps
833.375
0
2.4 KBps
1250
0
3
9.6 KBps
9.598 KBps
208.375
0.02
9.6 KBps
312.5
0
4
19.2 KBps
19.208 KBps
104.125
0.04
19.2 KBps
156.25
0
5
38.4 KBps
38.369 KBps
52.125
0.08
38.4 KBps
78.125
0
6
57.6 KBps
57.554 KBps
34.75
0.08
57.554 KBps
52.125
0.08
7
115.2 KBps
115.108 KBps
17.375
0.08
115.385 KBps
26
0.16
8
230.4 KBps
231.884 KBps
8.625
0.64
230.769 KBps
13
0.16
9
460.8 KBps
457.143 KBps
4.375
0.79
461.538 KBps
6.5
0.16
10
921.6 KBps
941.176 KBps
2.125
2.12
923.077 KBps
3.25
0.16
11
2 MBps
2000 KBps
1
0
2000 KBps
1.5
0
12
3 MBps
NA
NA
NA
3000 KBps
1
0
Actual
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 76. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 16(1)
Oversampling by 16 (OVER8=0)
Baud rate
S.No
Desired
fPCLK = 8 MHz
Actual
Value
programme
d in the
baud rate
register
% Error =
(Calculated Desired)B.Rate
/Desired B.Rate
fPCLK = 16 MHz
Actual
Value
programmed
% Error
in the baud
rate register
1.
2.4 KBps
2.400 KBps
208.3125
0.00%
2.400 KBps
416.6875
0.00%
2.
9.6 KBps
9.604 KBps
52.0625
0.04%
9.598 KBps
104.1875
0.02%
3.
19.2 KBps
19.185 KBps
26.0625
0.08%
19.208 KBps
52.0625
0.04%
4.
57.6 KBps
57.554 KBps
8.6875
0.08%
57.554 KBps
17.3750
0.08%
5.
115.2 KBps
115.942 KBps 4.3125
0.64%
115.108 KBps
8.6875
0.08%
6.
230.4 KBps
228.571
KBps
0.79%
231.884 KBps
4.3125
0.64%
2.1875
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Table 76. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 16(1) (continued)
Oversampling by 16 (OVER8=0)
Baud rate
S.No
fPCLK = 8 MHz
Desired
Actual
Value
programme
d in the
baud rate
register
fPCLK = 16 MHz
% Error =
(Calculated Desired)B.Rate
/Desired B.Rate
Value
programmed
% Error
in the baud
rate register
Actual
7.
460.8 KBps
470.588
KBps
1.0625
2.12%
457.143 KBps
2.1875
0.79%
8.
896 KBps
NA
NA
NA
888.889 KBps
1.1250
0.79%
9.
921.6 KBps
NA
NA
NA
941.176 KBps
1.0625
2.12%
10.
1.792 MBps
NA
NA
NA
NA
NA
NA
11.
1.8432 MBps NA
NA
NA
NA
NA
NA
12.
3.584 MBps
NA
NA
NA
NA
NA
NA
13.
3.6864 MBps NA
NA
NA
NA
NA
NA
14.
7.168 MBps
NA
NA
NA
NA
NA
NA
15.
7.3728 MBps NA
NA
NA
NA
NA
NA
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 77. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 8(1)
Oversampling by 8 (OVER8=1)
Baud rate
S.No
fPCLK = 8 MHz
Desired
Actual
% Error =
Value
(Calculated programmed
in the baud Desired)B.Rate
rate register /Desired B.Rate
fPCLK = 16 MHz
Actual
Value
programmed
in the baud
rate register
%
Error
1.
2.4 KBps
2.400 KBps
416.625
0.01%
2.400 KBps
833.375
0.00%
2.
9.6 KBps
9.604 KBps
104.125
0.04%
9.598 KBps
208.375
0.02%
3.
19.2 KBps
19.185 KBps
52.125
0.08%
19.208 KBps
104.125
0.04%
4.
57.6 KBps
57.557 KBps
17.375
0.08%
57.554 KBps
34.750
0.08%
5.
115.2 KBps
115.942 KBps 8.625
0.64%
115.108 KBps 17.375
0.08%
6.
230.4 KBps
228.571 KBps 4.375
0.79%
231.884 KBps 8.625
0.64%
7.
460.8 KBps
470.588 KBps 2.125
2.12%
457.143 KBps 4.375
0.79%
8.
896 KBps
888.889 KBps 1.125
0.79%
888.889 KBps 2.250
0.79%
9.
921.6 KBps
888.889 KBps 1.125
3.55%
941.176 KBps 2.125
2.12%
10.
1.792 MBps
NA
NA
1.7777 MBps
0.79%
516/836
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DocID026448 Rev 1
1.125
RM0383
Universal synchronous asynchronous receiver transmitter (USART)
Table 77. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 8(1) (continued)
Oversampling by 8 (OVER8=1)
Baud rate
S.No
fPCLK = 8 MHz
Desired
Actual
fPCLK = 16 MHz
Value
% Error =
programmed
(Calculated in the baud Desired)B.Rate
rate register /Desired B.Rate
Value
programmed
in the baud
rate register
Actual
%
Error
11.
1.8432 MBps
NA
NA
NA
1.7777 MBps
1.125
3.55%
12.
3.584 MBps
NA
NA
NA
NA
NA
NA
13.
3.6864 MBps
NA
NA
NA
NA
NA
NA
14.
7.168 MBps
NA
NA
NA
NA
NA
NA
15.
7.3728 MBps
NA
NA
NA
NA
NA
NA
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 78. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,
oversampling by 16(1)(2)
Oversampling by 16 (OVER8=0)
Baud rate
S.No
fPCLK = 30 MHz
Desired
Actual
Value
programme
d in the
baud rate
register
% Error =
(Calculated Desired)B.Rate
/Desired B.Rate
fPCLK = 60 MHz
Actual
Value
programmed
in the baud
rate register
%
Error
1.
2.4 KBps
2.400 KBps
781.2500
0.00%
2.400 KBps
1562.5000
0.00%
2.
9.6 KBps
9.600 KBps
195.3125
0.00%
9.600 KBps
390.6250
0.00%
3.
19.2 KBps
19.194 KBps
97.6875
0.03%
19.200 KBps
195.3125
0.00%
4.
57.6 KBps
57.582KBps
32.5625
0.03%
57.582 KBps
65.1250
0.03%
5.
115.2 KBps
115.385 KBps
16.2500
0.16%
115.163 KBps 32.5625
0.03%
6.
230.4 KBps
230.769 KBps
8.1250
0.16%
230.769KBps
0.16%
7.
460.8 KBps
461.538 KBps
4.0625
0.16%
461.538 KBps 8.1250
0.16%
8.
896 KBps
909.091 KBps
2.0625
1.46%
895.522 KBps 4.1875
0.05%
9.
921.6 KBps
909.091 KBps
2.0625
1.36%
923.077 KBps 4.0625
0.16%
10.
1.792 MBps
1.1764 MBps
1.0625
1.52%
1.8182 MBps
2.0625
1.36%
11.
1.8432
MBps
1.8750 MBps
1.0000
1.73%
1.8182 MBps
2.0625
1.52%
12.
3.584 MBps
NA
NA
NA
3.2594 MBps
1.0625
1.52%
13.
3.6864
MBps
NA
NA
NA
3.7500 MBps
1.0000
1.73%
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Table 78. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,
oversampling by 16(1)(2) (continued)
Oversampling by 16 (OVER8=0)
Baud rate
S.No
fPCLK = 30 MHz
Desired
Actual
Value
programme
d in the
baud rate
register
% Error =
(Calculated Desired)B.Rate
/Desired B.Rate
fPCLK = 60 MHz
Value
programmed
in the baud
rate register
Actual
%
Error
14.
7.168 MBps
NA
NA
NA
NA
NA
NA
15.
7.3728
MBps
NA
NA
NA
NA
NA
NA
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
Table 79. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,
oversampling by 8(1) (2)
Oversampling by 8 (OVER8=1)
Baud rate
S.No
fPCLK = 30 MHz
Desired
Actual
Value
% Error =
programme
(Calculated d in the
Desired)B.Rate
baud rate
/Desired B.Rate
register
fPCLK =60 MHz
Actual
Value
programmed
in the baud
rate register
%
Error
1.
2.4 KBps
2.400 KBps
1562.5000
0.00%
2.400 KBps
3125.0000
0.00%
2.
9.6 KBps
9.600 KBps
390.6250
0.00%
9.600 KBps
781.2500
0.00%
3.
19.2 KBps
19.194 KBps
195.3750
0.03%
19.200 KBps
390.6250
0.00%
4.
57.6 KBps
57.582 KBps
65.1250
0.16%
57.582 KBps
130.2500
0.03%
5.
115.2 KBps
115.385 KBps
32.5000
0.16%
115.163 KBps 65.1250
0.03%
6.
230.4 KBps
230.769 KBps
16.2500
0.16%
230.769 KBps 32.5000
0.16%
7.
460.8 KBps
461.538 KBps
8.1250
0.16%
461.538 KBps 16.2500
0.16%
8.
896 KBps
909.091 KBps
4.1250
1.46%
895.522 KBps 8.3750
0.05%
9.
921.6 KBps
909.091 KBps
4.1250
1.36%
923.077 KBps 8.1250
0.16%
10.
1.792 MBps
1.7647 MBps
2.1250
1.52%
1.8182 MBps
4.1250
1.46%
11.
1.8432 MBps
1.8750 MBps
2.0000
1.73%
1.8182 MBps
4.1250
1.36%
12.
3.584 MBps
3.7500 MBps
1.0000
4.63%
3.5294 MBps
2.1250
1.52%
13.
3.6864 MBps
3.7500 MBps
1.0000
1.73%
3.7500 MBps
2.0000
1.73%
14.
7.168 MBps
NA
NA
NA
7.5000 MBps
1.0000
4.63%
15.
7.3728 MBps
NA
NA
NA
7.5000 MBps
1.0000
1.73%
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RM0383
Universal synchronous asynchronous receiver transmitter (USART)
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
Table 80. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,
oversampling by 16(1)(2)
Oversampling by 16 (OVER8=0)
Baud rate
fPCLK = 42 MHz
fPCLK = 84 MHz
S.No
Desired
Actual
Value
programme
d in the
baud rate
register
1
1.2 KBps
1.2 KBps
2187.5
0
1.2 KBps
4375
0
2
2.4 KBps
2.4 KBps
1093.75
0
2.4 KBps
2187.5
0
3
9.6 KBps
9.6 KBps
273.4375
0
9.6 KBps
546.875
0
4
19.2 KBps
19.195 KBps
136.75
0.02
19.2 KBps
273.4375
0
5
38.4 KBps
38.391 KBps
68.375
0.02
38.391 KBps
136.75
0.02
6
57.6 KBps
57.613 KBps
45.5625
0.02
57.613 KBps
91.125
0.02
7
115.2 KBps
115.068 KBps
22.8125
0.11
115.226 KBps
45.5625
0.02
8
230.4 KBps
230.769 KBps
11.375
0.16
230.137 KBps
22.8125
0.11
9
460.8 KBps
461.538 KBps
5.6875
0.16
461.538 KBps
11.375
0.16
10
921.6 KBps
913.043 KBps
2.875
0.93
923.076 KBps
5.6875
0.93
11
1.792 MBps
1.826 MBps
1.4375
1.9
1.787 MBps
2.9375
0.27
12
1.8432
MBps
1.826 MBps
1.4375
0.93
1.826 MBps
2.875
0.93
13
3.584 MBps
N.A
N.A
N.A
3.652 MBps
1.4375
1.9
14
3.6864
MBps
N.A
N.A
N.A
3.652 MBps
1.4375
0.93
15
7.168 MBps
N.A
N.A
N.A
N.A
N.A
N.A
16
7.3728
MBps
N.A
N.A
N.A
N.A
N.A
N.A
18
9 MBps
N.A
N.A
N.A
N.A
N.A
N.A
20
10.5 MBps
N.A
N.A
N.A
N.A
N.A
N.A
% Error =
(Calculated Desired)B.Rate
/Desired B.Rate
Actual
Value
programmed
in the baud
rate register
%
Error
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Table 81. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,
oversampling by 8(1)(2)
Oversampling by 8 (OVER8=1)
Baud rate
fPCLK = 42 MHz
fPCLK = 84 MHz
Value
% Error =
programme
(Calculated d in the
Desired)B.Rate
baud rate
/Desired B.Rate
register
Actual
Value
programmed
in the baud
rate register
%
Error
S.No
Desired
Actual
1.
1.2 KBps
1.2 KBps
4375
0
1.2 KBps
8750
0
2.
2.4 KBps
2.4 KBps
2187.5
0
2.4 KBps
4375
0
3.
9.6 KBps
9.6 KBps
546.875
0
9.6 KBps
1093.75
0
4.
19.2 KBps
19.195 KBps
273.5
0.02
19.2 KBps
546.875
0
5.
38.4 KBps
38.391 KBps
136.75
0.02
38.391 KBps
273.5
0.02
6.
57.6 KBps
57.613 KBps
91.125
0.02
57.613 KBps
182.25
0.02
7.
115.2 KBps
115.068 KBps
45.625
0.11
115.226 KBps
91.125
0.02
8.
230.4 KBps
230.769 KBps
22.75
0.11
230.137 KBps
45.625
0.11
9.
460.8 KBps
461.538 KBps
11.375
0.16
461.538 KBps
22.75
0.16
10.
921.6 KBps
913.043 KBps
5.75
0.93
923.076 KBps
11.375
0.93
11.
1.792 MBps
1.826 MBps
2.875
1.9
1.787Mbps
5.875
0.27
12.
1.8432 MBps
1.826 MBps
2.875
0.93
1.826 MBps
5.75
0.93
13.
3.584 MBps
3.5 MBps
1.5
2.34
3.652 MBps
2.875
1.9
14.
3.6864 MBps
3.82 MBps
1.375
3.57
3.652 MBps
2.875
0.93
15.
7.168 MBps
N.A
N.A
N.A
7 MBps
1.5
2.34
16.
7.3728 MBps
N.A
N.A
N.A
7.636 MBps
1.375
3.57
18.
9 MBps
N.A
N.A
N.A
9.333 MBps
1.125
3.7
20.
10.5 MBps
N.A
N.A
N.A
10.5 MBps
1
0
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
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19.3.5
Universal synchronous asynchronous receiver transmitter (USART)
USART receiver tolerance to clock deviation
The USART asynchronous receiver works correctly only if the total clock system deviation is
smaller than the USART receiver’s tolerance. The causes which contribute to the total
deviation are:
•
DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
•
DQUANT: Error due to the baud rate quantization of the receiver
•
DREC: Deviation of the receiver’s local oscillator
•
DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-tolow transition timing)
DTRA + DQUANT + DREC + DTCL < USART receiver’s tolerance
The USART receiver’s tolerance to properly receive data is equal to the maximum tolerated
deviation and depends on the following choices:
•
10- or 11-bit character length defined by the M bit in the USART_CR1 register
•
oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
•
use of fractional baud rate or not
•
use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register
Table 82. USART receiver’s tolerance when DIV fraction is 0
M bit
OVER8 bit = 0
OVER8 bit = 1
ONEBIT=0
ONEBIT=1
ONEBIT=0
ONEBIT=1
0
3.75%
4.375%
2.50%
3.75%
1
3.41%
3.97%
2.27%
3.41%
Table 83. USART receiver tolerance when DIV_Fraction is different from 0
M bit
OVER8 bit = 0
OVER8 bit = 1
ONEBIT=0
ONEBIT=1
ONEBIT=0
ONEBIT=1
0
3.33%
3.88%
2%
3%
1
3.03%
3.53%
1.82%
2.73%
Note:
The figures specified in Table 82 and Table 83 may slightly differ in the special case when
the received frames contain some Idle frames of exactly 10-bit times when M=0 (11-bit times
when M=1).
19.3.6
Multiprocessor communication
There is a possibility of performing multiprocessor communication with the USART (several
USARTs connected in a network). For instance one of the USARTs can be the master, its TX
output is connected to the RX input of the other USART. The others are slaves, their
respective TX outputs are logically ANDed together and connected to the RX input of the
master.
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant USART
service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function.
In mute mode:
•
None of the reception status bits can be set.
•
All the receive interrupts are inhibited.
•
The RWU bit in USART_CR1 register is set to 1. RWU can be controlled automatically
by hardware or written by the software under certain conditions.
The USART can enter or exit from mute mode using one of two methods, depending on the
WAKE bit in the USART_CR1 register:
•
Idle Line detection if the WAKE bit is reset,
•
Address Mark detection if the WAKE bit is set.
Idle line detection (WAKE=0)
The USART enters mute mode when the RWU bit is written to 1.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but
the IDLE bit is not set in the USART_SR register. RWU can also be written to 0 by software.
An example of mute mode behavior using Idle line detection is given in Figure 174.
Figure 174. Mute mode using Idle line detection
RXNE
RX
Data 1
RWU
Data 2
Data 3
Data 4
IDLE
Mute Mode
RWU written to 1
Data 5
RXNE
Data 6
Normal Mode
Idle frame detected
Address mark detection (WAKE=1)
In this mode, bytes are recognized as addresses if their MSB is a ‘1 else they are
considered as data. In an address byte, the address of the targeted receiver is put on the 4
LSB. This 4-bit word is compared by the receiver with its own address which is programmed
in the ADD bits in the USART_CR2 register.
The USART enters mute mode when an address character is received which does not
match its programmed address. In this case, the RWU bit is set by hardware. The RXNE
flag is not set for this address byte and no interrupt nor DMA request is issued as the
USART would have entered mute mode.
It exits from mute mode when an address character is received which matches the
programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE bit is set for the address character since the RWU bit has been
cleared.
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Universal synchronous asynchronous receiver transmitter (USART)
The RWU bit can be written to as 0 or 1 when the receiver buffer contains no data (RXNE=0
in the USART_SR register). Otherwise the write attempt is ignored.
An example of mute mode behavior using address mark detection is given in Figure 175.
Figure 175. Mute mode using address mark detection
In this example, the current address of the receiver is 1
(programmed in the USART_CR2 register)
RX
IDLE
Addr=0
Data 1 Data 2
RXNE
IDLE
Addr=1 Data 3
Mute Mode
RWU
nonmatching address
RXNE
RXNE
Data 4 Addr=2
Normal Mode
Matching address
Data 5
Mute Mode
nonmatching address
RWU written to 1
(RXNE was cleared)
19.3.7
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bit, the possible USART frame formats are as listed in Table 84.
Table 84. Frame formats
M bit
PCE bit
USART frame(1)
0
0
| SB | 8 bit data | STB |
0
1
| SB | 7-bit data | PB | STB |
1
0
| SB | 9-bit data | STB |
1
1
| SB | 8-bit data PB | STB |
1. Legends: SB: start bit, STB: stop bit, PB: parity bit.
Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit in
USART_CR1 = 0).
Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in
USART_CR1 = 1).
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Parity checking in reception
If the parity check fails, the PE flag is set in the USART_SR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software
sequence (a read from the status register followed by a read or write access to the
USART_DR data register).
Note:
In case of wakeup by an address mark: the MSB bit of the data is taken into account to
identify an address but not the parity bit. And the receiver does not check the parity of the
address data (PE is not set in case of a parity error).
Parity generation in transmission
If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register
is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).
Note:
The software routine that manages the transmission can activate the software sequence
which clears the PE flag (a read from the status register followed by a read or write access
to the data register). When operating in half-duplex mode, depending on the software, this
can cause the PE flag to be unexpectedly cleared.
19.3.8
LIN (local interconnection network) mode
The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN
mode, the following bits must be kept cleared:
•
STOP[1:0] and CLKEN in the USART_CR2 register
•
SCEN, HDSEL and IREN in the USART_CR3 register.
LIN transmission
The same procedure explained in Section 19.3.2 has to be applied for LIN Master
transmission than for normal USART transmission with the following differences:
•
Clear the M bit to configure 8-bit word length.
•
Set the LINEN bit to enter LIN mode. In this case, setting the SBK bit sends 13 ‘0 bits
as a break character. Then a bit of value ‘1 is sent to allow the next start detection.
LIN reception
A break detection circuit is implemented on the USART interface. The detection is totally
independent from the normal USART receiver. A break can be detected whenever it occurs,
during Idle state or during a frame.
When the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a
start signal. The method for detecting start bits is the same when searching break
characters or data. After a start bit has been detected, the circuit samples the next bits
exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in
USART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as ‘0,
and are followed by a delimiter character, the LBD flag is set in USART_SR. If the LBDIE
bit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it
signifies that the RX line has returned to a high level.
If a ‘1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the
current detection and searches for a start bit again.
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Universal synchronous asynchronous receiver transmitter (USART)
If the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART,
without taking into account the break detection.
If the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (i.e. stop bit
detected at ‘0, which will be the case for any break frame), the receiver stops until the break
detection circuit receives either a ‘1, if the break word was not complete, or a delimiter
character if a break has been detected.
The behavior of the break detector state machine and the break flag is shown on the
Figure 176: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 525.
Examples of break frames are given on Figure 177: Break detection in LIN mode vs.
Framing error detection on page 526.
Figure 176. Break detection in LIN mode (11-bit break length - LBDL bit is set)
Case 1: break signal not long enough => break discarded, LBD is not set
Break Frame
RX line
Capture Strobe
Break State machine
Idle
Read Samples
Bit0
0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
0
0
0
0
0
0
0
0
0
Bit10
Idle
1
Case 2: break signal just long enough => break detected, LBD is set
Break Frame
RX line
Capture Strobe
delimiter is immediate
Break State machine
Idle
Read Samples
Bit0
0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9 B10
0
0
0
0
0
0
0
0
0
0
Bit10
Idle
LBD
Case 3: break signal long enough => break detected, LBD is set
Break Frame
RX line
Capture Strobe
Break State machine
Read Samples
Idle
Bit0
0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
0
0
0
0
0
0
0
0
0
wait delimiter
Idle
0
LBD
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Universal synchronous asynchronous receiver transmitter (USART)
RM0383
Figure 177. Break detection in LIN mode vs. Framing error detection
In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data)
Case 1: break occurring after an Idle
RX line
data 1
IDLE
BREAK
1 data time
data2 (0x55)
data 3 (header)
1 data time
RXNE / FE
LBD
Case 1: break occurring while a data is being received
RX line
data 1
data 2
BREAK
1 data time
data2 (0x55)
data 3 (header)
1 data time
RXNE / FE
LBD
19.3.9
USART synchronous mode
The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
•
LINEN bit in the USART_CR2 register,
•
SCEN, HDSEL and IREN bits in the USART_CR3 register.
The USART allows the user to control a bidirectional synchronous serial communications in
master mode. The SCLK pin is the output of the USART transmitter clock. No clock pulses
are sent to the SCLK pin during start bit and stop bit. Depending on the state of the LBCL bit
in the USART_CR2 register clock pulses will or will not be generated during the last valid
data bit (address mark). The CPOL bit in the USART_CR2 register allows the user to select
the clock polarity, and the CPHA bit in the USART_CR2 register allows the user to select the
phase of the external clock (see Figure 178, Figure 179 & Figure 180).
During the Idle state, preamble and send break, the external SCLK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as SCLK is
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