doc4265

Features
• EE Programmable 1,048,576 x 1-bit Serial Memory Designed to Store Configuration
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Programs for Field Programmable Gate Arrays (FPGAs)
Very Low-power CMOS EEPROM Process
In-System Programmable (ISP) via Two-Wire Bus
Simple Interface to SRAM FPGAs
Compatible with AT40K Devices
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Programmable Reset Polarity
Low-power Standby Mode
High-reliability
– Endurance: 5,104 Erase/Write Cycles
– Data Retention: 10 Years
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 @125°C
Tested up to a Total Dose of (according to MIL STD 883 Method 1019)
– 20 krads (Si) Read-only mode when Biased
– 60 krads (Si) Read-only mode when Unbiased
Operating Range: 3.0V to 3.6V, -55°C to +125°C
Available in 400 mils Wide 28 Pins DIL Flat Pack
Space FPGA
Configuration
EEPROM
AT17LV010-10DP
Description
The AT17LV010-10DP is a FPGA Configuration Serial EEPROM which provides an
easy-to-use, cost-effective configuration memory for Field Programmable Gate
Arrays. It is packaged in a 28-pin 400 mils wide Flat Pack package. The configurator
uses a simple serial link to configure one or more FPGA devices. The user can select
the polarity of the reset function by programming four EEPROM bytes. Since the
default setting is RESET low and OE high, this document will describe RESET/OE.
The device also supports a write-protection mechanism within its programming mode.
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Block Diagram
SER_EN
WP1
WP2
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
POWER ON
RESET
ROW
DECODER
BIT
COUNTER
EEPROM
CELL
MATRIX
COLUMUN
DECODER
TC
CLK READY
RESET/OE
CE
CEO (A2)
DATA
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly
with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven low, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the
output of the configurator. If CE is held high after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When RESET/OE is subsequently driven high, the
counter and the DATA output pin are enabled. When RESET/OE is driven low again, the
address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
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AT17LV010-10DP
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AT17LV010-10DP
Pin Configuration
RESET/OE
1
28
Reserved
NC
2
27
NC
WP2
3
26
WP1
CE
4
25
CLK
GND
5
24
DATA
NC
6
23
NC
NC
7
22
NC
NC
8
21
NC
NC
9
20
NC
Reserved
10
19
VCC
CE0(A2)
11
18
Reserved
NC
12
17
SER_EN
NC
13
16
NC
READY
14
15
NC
Figure 1. 28-pin Flat Pack
Note:
Package lid is NOT connected to GND
Pin Description
RESET / OE
Output Enable (active high) and RESET (active low) when SER_EN is high. A low level on
RESET/OE resets both the address and bit counters. A high level (with CE low) enables the data
output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. Since almost all FPGAs use RESET low and OE high, this document describes the
pin as RESET/OE. This is the default setting for the device.
WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations.
CE
Chip Enable input (active low). A low level (with RESET/OE high) allows CLK to increment the
address counter and enables the data output driver. A high level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin does not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN
low).
CEO
Chip Enable Output (active low). This output goes low when the address counter has reached its
maximum value. In a daisy chain of AT17LV010-10DP devices, the CEO pin of one device must
be connected to the CE input of the next device in the chain. It stays low as long as CE is low
and RESET/OE is high. It then follows CE until RESET/OE goes low. Thereafter, CEO stays
high until the entire EEPROM is read again.
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A2
Device selection input. This is used to enable (or select) the device during programming (i.e.,
when SER_EN is low). This pin has an internal pull-down resistor.
READY
Open collector reset state indicator. Driven low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used.
SER_EN
Serial enable must be held high during FPGA loading operations. Bringing SER_EN low enables
the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to
VCC.
DATA
Tri-state DATA output for configuration. Open-collector bi-directional pin for programming.
CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations.
VCC
3.3V (±0.3V). A 0.2 µF decoupling capacitor between VCC and GND is recommended
GND
Ground pin.
NC
These pins are not connected internally. It is recommended to connect them to a power supply
(GND or Vcc).
Reserved
These pins are connected internally for manufacturing testing - DO NOT CONNECT.
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AT17LV010-10DP
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AT17LV010-10DP
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial mode.
This section discusses the Atmel AT40KEL applications.
Control of Configuration
Most connections between the FPGA device and the Serial EEPROM are simple and selfexplanatory.
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The DATA output of the configurator drives the DATA input of the FPGA devices.
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The master FPGA CCLK output drives the CLK input of the configurator.
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The FPGA CON output drives the CE input of the configurator.
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The FPGA INIT output drives the RESET/OE input of the configurator.
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The A2 input of the configurator must be left unconnected (thanks to the internal pull down
resistor) or tied to Vcc depending on the TWI address configuration.
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SER_EN must be connected to VCC (except during ISP).
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The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Figure 2. Single Device Configuration Schematic
4.7 K
In-System
Programming
interface
4.7 K
DATA
CLK
4.7 K
RESETn
4.7 K
AT17LV010
DATA
CLK
CE
RESET/OE
SER_EN
CS0
A2/CEO
READY
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Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
CEO output low and disables its DATA line driver. The second configurator recognizes the low
level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (high) level.
Figure 3. Cascaded Devices Configuration Schematic
4.7 K
4.7 K
In-System
Programming
interface
4.7 K
CLK
RESET
DATA
AT17LV010
#1
4.7 K
SER_EN
AT17LV010
CS0
#2
SER_EN
4.7 K
AT17LV010
#3
4.7 K
SER_EN
AT17LV010
CS1
#4
SER_EN
4.7 K
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AT17LV010-10DP
Reset Polarity
The configurator allows the user to program the reset polarity as either RESET/OE or
RESET/OE. This feature is supported by industry-standard programmer algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN low. In this mode the chip can be programmed by the Two-Wire serial bus (TWI). The programming is done at V CC supply only.
Programming super voltages are generated inside the chip. For more information see application note:
http://www.atmel.com/dyn/resources/prod_documents/doc0437.pdf
Standby Mode
The configurator enters a low-power standby mode whenever CE is asserted high. In this mode,
the configurator consumes less than 100 µA of current at 3.3V. The output remains in a highimpedance state regardless of the state of the RESET/OE input.
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Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature....................................-55⋅C to +125⋅C
*NOTICE:
Storage Temperature .......................................-65⋅C to +150⋅C
Voltage on Any Pin
with Respect to Ground .............................. -0.1V to VDD +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those listed under operating conditions is
not implied. Exposure to Absolute Maximum Rating
conditions for extended periods of time may affect
device reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 260⋅C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
3.3V
Symbol
Description
Min
Max
Units
VDD
-55 to +125°C
3.0
3.6
V
DC Characteristics
VDD = 3.3V ± 0.3V
Symbol
8
Description
AT17LV010-10DP
Min
Max
Units
VIH
High-level Input Voltage
2.0
VDD
V
VIL
Low-level Input Voltage
0
0.8
V
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
ICCOP
Supply Current, Active Mode
IL
Input or Output Leakage Current (VIN = VDD or GND)
ICCS
Supply Current, Standby Mode
2.4
-10
V
0.4
V
5
mA
10
µA
150
µA
AT17LV010-10DP
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AT17LV010-10DP
AC Characteristics
CE
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
AC Characteristics when Cascading
RESET/OE
CE
CLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
CEO
TOCE
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AC Characteristics
VCC = 3.3V ± 0.3V
Military
Symbol
Description
Max
Units
OE to Data Delay
55
ns
CE to Data Delay
60
ns
CLK to Data Delay
60
ns
(1)
TCE(1)
TCAC(1)
TOH
Data Hold from CE, OE, or CLK
TOE
TDF
(2)
Min
0
ns
CE or OE to Data Float Delay
50
ns
TLC
CLK Low Time
25
ns
THC
CLK High Time
25
ns
TSCE
CE Setup Time to CLK
(to guarantee proper counting)
35
ns
THCE
CE Hold Time from CLK
(to guarantee proper counting)
0
ns
THOE
OE High Time (guarantees counter is reset)
25
ns
FMAX
Maximum Clock Frequency
Notes:
10
MHz
1. AC test lead = 60 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steadystate active levels.
AC Characteristics when Cascading
VCC = 3.3V ± 0.3V
Military
Symbol
(2)
Min
Max
Units
CLK to Data Float Delay
50
ns
TOCK(1)
CLK to CEO Delay
55
ns
TOCE(1)
CE to CEO Delay
40
ns
TOOE(1)
RESET/OE to CEO Delay
40
ns
FMAX
Maximum Clock Frequency
10
MHz
TCDF
Notes:
10
Description
1. AC test lead = 60 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steadystate active levels.
AT17LV010-10DP
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AT17LV010-10DP
Ordering Information
Memory Size
Ordering Code
Package
Operation Range
1 Mbit
AT17LV010-10DP-E
28-pin Flat Pack
Engineering Samples
1 Mbit
AT17LV010-10DP-MQ
28-pin Flat Pack
Military Level B
1 Mbit
AT17LV010-10DP-SV
28-pin Flat Pack
Space Level B
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Packaging Information
DP (FP28.4)
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AT17LV010-10DP
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AT17LV010-10DP
DOCUMENT REVISION HISTORY
Changes from Rev. C to Rev. D
Update : signal RESET/OE changed to RESET/OE in whole document as the RESET signal is
configured active low by default to be compatible with the dump mode of AT40K devices.
Add-on: Figure 2 on page 5
Add-on: Figure 3 on page 6
Update: document template
Changes from Rev. D to Rev. E
Update: description section on first page
Update: Figure 2 on page 5
Update: Figure 3 on page 6
Udpate: signal RESET/OE changed to RESET/OE on the Block Diagram
Changes from Rev. E to Rev F
Update : Three NC pins renamed as Reserved on Figure 1 on page 3
Update : Notes underneath Figure 1 on page 3 changed
Update : Addition of NC and Reserved in Pin Description section
Changes from Rev. F to Rev G
Update : fixed an error in the endurance parameter definition on page 1
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4265G–AERO–09/14
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