24AA024/24LC024/24AA025/24LC025 2K I2C™ Serial EEPROM Device Selection Table Description: Part Number VCC Range Max Clock 24AA024 1.7V-5.5V 400 kHz(1) 24AA025 1.7V-5.5V (1) I No 24LC024 2.5V-5.5V 400 kHz I, E Yes 2.5V-5.5V 400 kHz I, E No 24LC025 Note 1: 400 kHz Temp. Write Range Protect I Yes 100 kHz for VCC < 2.5V Features: • Single Supply with Operation from 1.7V to 5.5V for 24AA024/24AA025 Devices, 2.5V for 24LC024/24LC025 Devices • Low-Power CMOS Technology: - Read current 1 mA, typical - Standby current 1 μA, typical • 2-Wire Serial Interface, I2C™ Compatible • Cascadable up to Eight Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • Page Write Time 5 ms Maximum • Self-timed Erase/Write Cycle • 16-Byte Page Write Buffer • Hardware Write-Protect on 24XX024 Devices • ESD Protection >4,000V • More than 1 Million Erase/Write Cycles • Data Retention >200 years • Factory Programming Available • Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN and MSOP • 6-Lead SOT-23 Package, 24XX025 only • Pb-Free and RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C The Microchip Technology Inc. 24AA024/24LC024/ 24AA025/24LC025 is a 2 Kbit Serial Electrically Erasable PROM with a voltage range of 1.7V to 5.5V. The device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 1 μA and 1 mA, respectively. The device has a page write capability for up to 16 bytes of data. Functional address lines allow the connection of up to eight 24AA024/24LC024/ 24AA025/24LC025 devices on the same bus for up to 16K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (3.90 mm), TSSOP, 2x3 DFN and TDFN and MSOP packages. The 24AA025/24LC025 is also available in the 6-lead SOT-23 package. Package Types PDIP/SOIC/TSSOP/MSOP A0 1 8 DFN/TDFN A0 1 VCC 8 VCC 7 WP A1 2 A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA 6 SCL A2 3 VSS 4 5 SDA SOT-23 Note: SCL 1 6 VCC VSS 2 5 A0 SDA 3 4 A1 WP pin is not internally connected on the 24XX025. Block Diagram A0 A1 A2 WP* HV Generator I/O Control Logic Memory Control Logic XDEC EEPROM Array SDA SCL VCC VSS Write-Protect Circuitry YDEC Sense Amp. R/W Control © 2009 Microchip Technology Inc. DS21210N-page 1 24AA024/24LC024/24AA025/24LC025 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Characteristic Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V Min. Typ. Max. Units Conditions — A0, A1, A2, SCL, SDA and WP pins — — — — — D1 VIH High-level input voltage 0.7 VCC — — V — D2 VIL Low-level input voltage D3 VHYS Hysteresis of Schmitt Trigger inputs D4 VOL D5 ILI D6 D7 D8 ICC write Operating current — — 0.3 VCC V 0.2 VCC for VCC < 2.5V 0.05 VCC — — V (Note) Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V Input leakage current — — ±1 μA VIN = VSS or VCC ILO Output leakage current — — ±1 μA VOUT = VSS or VCC CIN, COUT Pin capacitance (all inputs/outputs) — — 10 pF VCC = 5.5V (Note) TA = 25°C, FCLK = 1 MHz — 0.1 3 mA VCC = 5.5V, SCL = 400 kHz — 0.05 1 mA — — — 0.01 — 1 5 μA μA Industrial Automotive SDA = SCL = VCC A0, A1, A2, WP = VSS D9 ICC read D10 ICCS Note: Standby current This parameter is periodically sampled and not 100% tested. DS21210N-page 2 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V AC CHARACTERISTICS Param. No. Symbol Characteristic Min. Max. Units Conditions 1 FCLK Clock frequency — — 100 400 kHz 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 2 THIGH Clock high time 4000 600 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 3 TLOW Clock low time 4700 1300 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 4 TR SDA and SCL rise time (Note 1) — — 1000 300 ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 5 TF SDA and SCL fall time (Note 1) — — 1000 300 ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 6 THD:STA Start condition hold time 4000 600 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 7 TSU:STA Start condition setup time 4700 600 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 8 THD:DAT Data input hold time 0 — ns (Note 2) 9 TSU:DAT Data input setup time 250 100 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 10 TSU:STO Stop condition setup time 4000 600 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 11 TSU:WP WP setup time 4000 600 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 12 THD:WP WP hold time 4700 600 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 13 TAA Output valid from clock (Note 2) — — 3500 900 ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 1300 4700 — — ns 1.7V ≤ VCC < 1.8V 1.8V ≤ VCC ≤ 5.5V 16 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns (Note 1 and Note 3) — 17 TWC Write cycle time (byte or page) — 5 ms 18 — Endurance 1M — cycles 25°C, VCC = 5.5V, Block mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. © 2009 Microchip Technology Inc. DS21210N-page 3 24AA024/24LC024/24AA025/24LC025 FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA In 3 4 D4 2 8 10 9 6 16 14 13 SDA Out WP DS21210N-page 4 (protected) (unprotected) 11 12 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 2.0 PIN DESCRIPTIONS Pin Function Table Name PDIP SOIC TSSOP DFN/TDFN MSOP SOT-23 Description A0 1 1 1 1 1 5 Address Pin AO A1 2 2 2 2 2 4 Address Pin A1 A2 3 3 3 3 3 — Address Pin A2 VSS 4 4 4 4 4 2 Ground SDA 5 5 5 5 5 3 Serial Address/Data I/O SCL 6 6 6 6 6 1 Serial Clock WP 7 7 7 7 7 — Write-Protect Input VCC 8 8 8 8 8 6 +1.7 to 5.5V Power Supply 2.1 SDA Serial Data SDA is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal; therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.2 SCL Serial Clock The SCL input is used to synchronize the data transfer from and to the device. 2.3 A0, A1, A2 The levels on the A0, A1 and A2 inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. For the SOT-23 package only, pin A2 is not connected. Up to eight 24AA024/24LC024/24AA025/24LC025 devices (four for the SOT-23 package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. 2.4 2.5 Noise Protection The 24AA024/24LC024/24AA025/24LC025 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5V at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. 3.0 FUNCTIONAL DESCRIPTION The 24AA024/24LC024/24AA025/24LC025 supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as receiver. The bus has to be controlled by a master device that generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24AA024/ 24LC024/24AA025/24LC025 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. WP (24XX024 Only) WP is the hardware write-protect pin. It must be tied to VCC or VSS. If tied to Vcc, hardware write protection is enabled. If WP is tied to Vss, the hardware write protection is disabled. Note that the WP pin is available only on the 24XX024. This pin is not internally connected on the 24LC025. © 2009 Microchip Technology Inc. DS21210N-page 5 24AA024/24LC024/24AA025/24LC025 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is, theoretically, unlimited (though only the last sixteen will be stored when performing a write operation). When an overwrite does occur, it will replace data in a first-in first-out fashion. 4.1 4.5 Bus Not Busy (A) Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Note: Stop Data Transfer (C) Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. FIGURE 4-1: SCL (A) The 24AA024/24LC024/24AA025/24LC025 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2). A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 4.4 Acknowledge DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS (B) (C) (D) (C) (A) SDA Start Condition FIGURE 4-2: Address or Acknowledge Valid Stop Condition Data Allowed to Change ACKNOWLEDGE TIMING Acknowledge Bit 1 SCL SDA 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. DS21210N-page 6 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a four-bit control code. For the 24AA024/24LC024/24AA025/24LC025, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA024/24LC024/24AA025/24LC025 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. For the SOT-23 package, the A2 address pin is not available. During device addressing, the A2 Chip Select bit should be set to ‘0’. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. Following the Start condition, the 24AA024/ 24LC024/24AA025/24LC025 monitors the SDA bus checking the control byte being transmitted. Upon receiving a ‘1010’ code and appropriate Chip Select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA024/24LC024/24AA025/24LC025 will select a read or write operation. © 2009 Microchip Technology Inc. FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 16K bits by adding up to eight 24AA024/24LC024/24AA025/ 24LC025 devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9 and A2 as address bit A10. It is not possible to sequentially read across device boundaries. For the SOT-23 package, up to four 24AA025/24LC025 devices can be added for up to 8K bits of address space. In this case, software can use A0 of the control byte as address bit A8, and A1 as address bit A9. It is not possible to sequentially read across device boundaries. DS21210N-page 7 24AA024/24LC024/24AA025/24LC025 6.0 WRITE OPERATIONS 6.1 Byte Write The higher-order four bits of the word address remain constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte-write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if write protection is enabled. Following the Start signal from the master, the device code(4 bits), the Chip Select bits (3 bits) and the R/W bit (which is a logic-low) is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24AA024/ 24LC024/24AA025/24LC025. After receiving another Acknowledge signal from the 24AA024/24LC024/ 24AA025/24LC025, the master device will transmit the data word to be written into the addressed memory location. The 24AA024/24LC024/24AA025/24LC025 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and, during this time, the 24AA024/24LC024/24AA025/ 24LC025 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection (24XX024 only) has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if write protection is enabled. 6.2 Note: Page Write The write control byte, word address and the first data byte are transmitted to the 24AA024/24LC024/ 24AA025/24LC025 in the same way as in a byte write. However, instead of generating a Stop condition, the master transmits up to 15 additional data bytes to the 24AA024/24LC024/24AA025/24LC025, which are temporarily stored in the on-chip page buffer and will be written into the memory once the master has transmitted a Stop condition. Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by one. FIGURE 6-1: S T A R T SDA LINE S The WP pin (available on 24XX024 only) must be tied to VCC or VSS. If tied to VCC, the entire array will be write-protected. If the WP pin is tied to VSS, write operations to all address locations are allowed. The WP pin is not available on the SOT-23 package. Control Byte Word Address S T O P Data P A C K BUS ACTIVITY FIGURE 6-2: A C K A C K PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S DS21210N-page 8 Write Protection BYTE WRITE BUS ACTIVITY MASTER BUS ACTIVITY 6.3 Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Control Byte Word Address (n) Data (n +1) Data (n) Data (n + 15) S T O P P A C K A C K A C K A C K A C K © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally-timed write cycle, with ACK polling being initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If no ACK is returned, the Start bit and control byte must be re-sent. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation © 2009 Microchip Technology Inc. DS21210N-page 9 24AA024/24LC024/24AA025/24LC025 8.0 READ OPERATIONS Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24AA024/24LC024/24AA025/24LC025 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to ‘1’, the 24AA024/ 24LC024/24AA025/24LC025 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24AA024/24LC024/24AA025/ 24LC025 discontinues transmission (Figure 8-1). 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24AA024/24LC024/24AA025/24LC025 as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24AA024/24LC024/24AA025/ 24LC025 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24AA024/24LC024/24AA025/24LC025 discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. DS21210N-page 10 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24AA024/24LC024/ 24AA025/24LC025 transmits the first data byte, the master issues an acknowledge (as opposed to a Stop condition in a random read). This directs the 24AA024/ 24LC024/24AA025/24LC025 to transmit the next sequentially-addressed 8-bit word (Figure 8-3). To provide sequential reads, the 24AA024/24LC024/ 24AA025/24LC025 contains an internal Address Pointer that is incremented by one upon completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 0FFh to address 000h. FIGURE 8-1: S T BUS ACTIVITY A MASTER R T SDA LINE S BUS ACTIVITY CURRENT ADDRESS READ Control Byte S T O P Data P A C K N O A C K © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 FIGURE 8-2: RANDOM READ BUS ACTIVITY MASTER S T A R T Control Byte S SDA LINE BUS ACTIVITY MASTER Control Byte S T O P Data (n) P S A C K A C K BUS ACTIVITY FIGURE 8-3: S T A R T Word Address (n) N O A C K A C K SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + x) P SDA LINE BUS ACTIVITY © 2009 Microchip Technology Inc. A C K A C K A C K A C K N O A C K DS21210N-page 11 24AA024/24LC024/24AA025/24LC025 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN 8-Lead TSSOP Example: 24LC024I SN e3 0519 13F Example: 4L24 TYWW I519 NNN 13F XXXXT YWWNNN 8-Lead 2x3 DFN XXX YWW NN 8-Lead 2x3 TDFN DS21210N-page 12 24LC024 I/P e3 13F 0519 XXXX 8-Lead MSOP XXX YWW NN Example: Example: 4L24I 51913F Example: 2P4 519 13 Example: AP4 519 13 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 Example: 6-Lead SOT-23 HQEC XXNN 1st Line Marking Codes Part Number DFN TSSOP TDFN SOT-23 MSOP I-TEMP E-TEMP I-TEMP E-TEMP I-TEMP E-TEMP 24AA024 4A24 4A24T 2P1 — AP1 — — — 24LC024 4L24 4L24T 2P4 AP5 AP4 2P5 — — 24AA025 4A25 4A25T 2R1 — AR1 — HQNN HRNN 24LC025 4L25 4L25T 2R4 AR5 AR4 2R5 HMNN HPNN Note: T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN e3 Note: Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. © 2009 Microchip Technology Inc. DS21210N-page 13 24AA024/24LC024/24AA025/24LC025 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"') %! 7,8. 7 7 7: ; < & & & = = ##44!! - 1!& & = = "#& "#>#& . - - ##4>#& . < : 9& -< -? & & 9 - 9#4!! < ) ? ) < 1 = = 69#>#& 9 *9#>#& : *+ 1, - !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#/!# '! #& .0 1,21!'! &$& "! **& "&& ! * ,<1 DS21210N-page 14 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 ! ""#$%& !' 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 6&! '! 9'&! 7"') %! β 99.. 7 7 7: ; < & : 8& = 1, = ##44!! = = &# %%+ = : >#& . ##4>#& . -1, : 9& 1, ?1, ,'%@ & A = 3 &9& 9 = 3 && 9 .3 3 & I B = <B 9#4!! = 9#>#& ) - = #%& D B = B #%&1 && ' E B = B !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,1 © 2009 Microchip Technology Inc. DS21210N-page 15 24AA024/24LC024/24AA025/24LC025 ! ""#$%& !' 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS21210N-page 16 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 () )"* ! (+%+( ! 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; < & : 8& = ?1, = ##44!! < &# %% = : >#& . ##4>#& . - ?1, ##49& - - 3 &9& 9 ? 3 && 9 .3 3 & I B = <B 9#4!! = 9#>#& ) = - !"#$%&"' ()"&'"!&) &#*&&&# '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,<?1 © 2009 Microchip Technology Inc. DS21210N-page 17 24AA024/24LC024/24AA025/24LC025 ," ! *-, , ! 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; < & : 8& = ?1, = ##44!! < &# %% = : >#& . ##4>#& . -1, : 9& -1, 3 &9& 9 3 && 9 1, ? < .3 3 & B = <B 9#4!! < = - 9#>#& ) = !"#$%&"' ()"&'"!&) &#*&&&# '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,1 DS21210N-page 18 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 . $*-,'/00%&. 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 2 NOTE 1 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; < & : 8& < &# %% , &&4!! - .3 : 9& 1, : >#& . .$ !##9& - = .$ !##>#& . = ) - , &&9& 9 - , &&& .$ !## C = = , &&>#& 1, -1, !"#$%&"' ()"&'"!&) &#*&&&# 4' ' $ !#&)!&#! - 4!!*!"&# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,-, © 2009 Microchip Technology Inc. DS21210N-page 19 24AA024/24LC024/24AA025/24LC025 . $*-,'/00%&. 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS21210N-page 20 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 . $*-,/00%12(. 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 © 2009 Microchip Technology Inc. DS21210N-page 21 24AA024/24LC024/24AA025/24LC025 . $*-,/00%12(. 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS21210N-page 22 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 3 ! (""!( !(/ 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; ? & 1, :"&!#9#& 1, : 8& = ##44!! < = - &# %% = : >#& . = - ##4>#& . - = < : 9& = - 3 &9& 9 = ? 3 && 9 - = < 3 & B = -B 9#4!! < = ? 9#>#& ) = '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# '! #& .0 1,2 1!'! &$& "! **& "&& ! * ,<1 © 2009 Microchip Technology Inc. DS21210N-page 23 24AA024/24LC024/24AA025/24LC025 APPENDIX A: REVISION HISTORY Revision F Corrections to Section 1.0, Electrical Characteristics. Revision G Added part number 24AA025 to document. Correction to Section 1.0, Ambient Temperature. Revision H Added DFN package. Revision J (02/2007) Revised Features section; Revised Pin Function Table; Changed 1.8V to 1.7V, Table 1-1 and Table 1-2; Replaced Package Drawings; Replaced On-line Support page; Revised Product ID section. Revision K (03/2007) Replaced Package Drawings (Rev. AM). Revision L (04/2008) Replaced Package Drawings; Added TDFN package; Revised Product ID section. Revision M (10/2009) Added E-temp; Revised Section 1.0; Table 1-2; Figure 1-1; 1st Line Marking Codes table in Section 9.1; Product ID section. Revision N (10/2009) Added 6-lead SOT-23 Package. Revised Sections 5.0, 5.1 and 6.3. DS21210N-page 24 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS21210N-page 25 24AA024/24LC024/24AA025/24LC025 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA024/24LC024/24AA025/24LC025 Literature Number: DS21210N Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21210N-page 26 © 2009 Microchip Technology Inc. 24AA024/24LC024/24AA025/24LC025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Range Device: Package 24AA024: 1.7V, 2 Kbit Addressable Serial EEPROM with WP pin. 24AA024T:1.7V, 2 Kbit Addressable Serial EEPROM (Tape and Reel) with WP pin. 24LC024: 2.5V, 2 Kbit Addressable Serial EEPROM with WP pin. 24LC024T:2.5V, 2 Kbit Addressable Serial EEPROM (Tape and Reel) with WP pin. 24AA025: 1.7V, 2 Kbit Addressable Serial EEPROM with no WP pin. 24AA025T:1.7V, 2 Kbit Addressable Serial EEPROM (Tape and Reel) with no WP pin. 24LC025: 2.5V, 2 Kbit Addressable Serial EEPROM (Tape and Reel) with no WP pin. 24LC025T:2.5V, 2 Kbit Addressable Serial EEPROM (Tape and Reel) with no WP pin. Temperature Range: I E Package: OT = = Examples: a) b) c) d) e) f) 24AA024-I/P: Industrial Temperature, 1.7V, PDIP Package 24AA024-I/SN: Industrial Temperature, 1.7V, SOIC Package 24AA025T-I/ST: Industrial Temperature, 1.7V, TSSOP Package, Tape and Reel 24LC024-I/P: Industrial Temperature, 2.5V, PDIP Package 24LC024-E/MS: Automotive Temperature, 2.5V, MSOP Package, Tape and Reel 24LC025T-I/OT: Industrial Temperature, 2.5V, SOT-23 Package, Tape and Reel -40°C to +85°C -40°C to +125°C = Plastic Small Outline (SOT-23), (Tape and Reel only), (24XX025 only), 6-lead P = Plastic DIP, (300 mil Body), 8-lead SN = Plastic SOIC, (3.90 mm Body) ST = TSSOP, 8-lead MS = MSOP, 8-lead MC = 2x3 DFN, 8-lead MNY(1) = Plastic Dual Flat (TDFN), No lead package, 2x3 mm body, 8-lead Note 1: “Y” indicates a Nickel, Palladium, Gold (NiPdAu) finish. © 2009 Microchip Technology Inc. DS21210N-page 27 24AA024/24LC024/24AA025/24LC025 NOTES: DS21210N-page 28 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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