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RT8101/A
12V Synchronous Buck PWM DC/DC Controller
General Description
Features
The RT8101/A are DC/DC synchronous buck PWM
controllers with embedded driver support up to 12V + 12V
boot-strapped voltage for high efficiency power driving. The
parts are with full functions of voltage regulation, power
monitoring and protection into a single small footprint
packages SOP-8 and SOP-8 (Exposed Pad).
z
Single 12V Bias Supply
z
Drives All Low Cost N-MOSFETs
High-Gain Voltage Model PWM Control
300kHz/600kHz Fixed Frequency Oscillator
Fast Transient Response :
` High-Speed GM Amplifier
` Full 0 to 100% Duty Ratio
` External Compensation in the Control Loop
Internal Soft-Start
Adaptive Non-Overlapping Gate Driver
Over Current Fault Monitor on MOSFET, No
Current Sense Resistor Required
RoHS Compliant and 100% Lead (Pb)-Free
The RT8101/A apply a high-gain voltage mode PWM control
for simple application design. An internal 0.8V reference
allows the output voltage to be precisely regulated to low
voltage requirement. The parts are proposed with two type
including RT8101 and RT8101A with fixed operating
frequency of 300kHz and 600kHz respectively. Based on
the features that RT8101/A offered, the parts provide an
optimum solution between efficiency, total B.O.M. count,
and cost.
z
z
z
z
z
z
z
Applications
z
z
Ordering Information
z
RT8101/A
z
Package Type
S : SOP-8
SP : SOP-8 (Exposed Pad-Option 2)
z
Graphic Card
Motherboard, Desktop Servers
IA Equipments
Telecomm Equipments
High Power DC/DC Regulators
Pin Configurations
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
600kHz
300kHz
Note :
(TOP VIEW)
BOOT
8
PHASE
UGATE
2
7
COMP
GND
3
6
FB
LGATE
4
5
VCC
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
SOP-8
Suitable for use in SnPb or Pb-free soldering processes.
8
BOOT
UGATE
2
GND
3
LGATE
7
GND
6
9
4
5
PHASE
COMP
FB
VCC
SOP-8 (Exposed Pad)
DS8101/A-06 April 2011
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1
RT8101/A
Typical Application Circuit
VIN(+3.3V/+5V/+12V)
RBOOT
12V
CIN
RT8101/A
1
5
6
3
BOOT
UGATE
VCC
PHASE
FB
LGATE
GND
COMP
2
RUGATE
Q1
LOUT
8
4
VOUT
Q2
R
7
COUT
C
PSC
Functional Pin Description
BOOT (Pin 1)
FB (Pin 6)
Bootstrap supply for the upper gate driver. Connect the
bootstrap capacitor between BOOT pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn
on the upper MOSFET.
Buck converter feedback voltage. This pin is the inverting
input of the error amplifier. FB senses the switcher output
through an external resistor divider network.
COMP (Pin 7)
UGATE (Pin 2)
Upper gate driver output. Connect to gate of the highside power N-Channel MOSFET. This pin is monitored by
the adaptive shoot-through protection circuitry to
determine when the upper MOSFET is turned off.
Buck converter external compensation. This pin is used
to compensate the control loop of the buck converter.
PHASE (Pin 8)
Signal ground for the IC.
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. This pin is monitored by
the adaptive shoot-through protection circuitry to
determine when the upper MOSFET is turned off.
LGATE (Pin 4)
Exposed Pad (9)
Lower gate driver output. Connect to the gate of the lowside power N-Channel MOSFET. This pin is monitored by
the adaptive shoot-through protection circuitry to determine
when the lower MOSFET is turned off.
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
GND (Pin 3)
VCC (Pin 5)
Connect this pin to a well-decoupled 12V bias supply. It
is also the positive supply for the lower gate driver, LGATE.
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2
DS8101/A-06 April 2011
RT8101/A
Function Block Diagram
VCC
Enable
-
Bias
5V
Regulator
Power On
Reset (POR)
+
PH_M
+
Voltage
Reference
-
POR
1.5V
0.8V
+
30uA
Soft-Start
&
Fault Logic
UV
-
OC
+
0.4V
5VDD
0.4V
21.6k
SSE
BOOT
INHIBIT
UGATE
0.8V
FB
SS
+
+ EA
-
+
+
-
PWM
Driver
Logic
PHASE
LGATE
Oscillator
COMP
DS8101/A-06 April 2011
GND
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3
RT8101/A
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VCC ---------------------------------------------------------------------------------- 16V
PHASE to GND
DC --------------------------------------------------------------------------------------------------------- −5V to 15V
< 200ns -------------------------------------------------------------------------------------------------- −10V to 30V
z BOOT to PHASE -------------------------------------------------------------------------------------- 15V
z UGATE --------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
z LGATE --------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V)
< 200ns -------------------------------------------------------------------------------------------------- −1.5V to 13.5V
z Input, Output or I/O Voltage ------------------------------------------------------------------------- GND − 0.3V to 7V
z Power Dissipation, PD @ TA = 25°C (Note 2)
SOP-8 ---------------------------------------------------------------------------------------------------- 0.83W
SOP-8 (Exposed Pad) ------------------------------------------------------------------------------- 1.33W
z Package Thermal Resistance
SOP-8, θJA ---------------------------------------------------------------------------------------------- 120°C/W
SOP-8 (Exposed Pad), θJA -------------------------------------------------------------------------- 75°C/W
z Junction Temperature --------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------- 260°C
z Storage Temperature Range ------------------------------------------------------------------------ −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) -------------------------------------------------------------------------- 2kV
MM (Machine Mode) ---------------------------------------------------------------------------------- 200V
z
z
Recommended Operating Conditions
z
z
z
(Note 4)
Supply Voltage, VCC ---------------------------------------------------------------------------------- 12V ± 10%
Junction Temperature Range ------------------------------------------------------------------------ −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------ −40°C to 85°C
Electrical Characteristics
(VCC = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
10.8
12
13.2
V
--
3
--
mA
Supply Input
Supply Voltage
VCC
UGATE and LGATE Open
Supply Current
ICC
VCC = 12V
Power-On Reset
POR Threshold
VCCRTH
8.8
9.6
10.4
V
POR Hysteresis
VCCHYS
--
0.8
1.6
V
V CC = 12V, RT8101
250
300
350
V CC = 12V, RT8101A
500
600
700
--
1.5
--
Oscillator
Free Running Frequency
fOSC
Ramp Amplitude
ΔVOSC
VCC = 12V
kHz
VP-P
To be continued
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DS8101/A-06 April 2011
RT8101/A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.792
0.8
0.808
V
Reference Voltage
PWM Error Amplifier Reference
VREF
Error Amplifier
Open Loop DC Gain
AO
--
88
--
dB
Gain-Bandwidth Product
GBW
--
15
--
MHz
Slew Rate
SR
--
6
--
V/μs
--
300
--
mA
PWM Controller Gate Drivers (VCC = 12V)
VBOOT − VPHASE = 12V,
Upper Gate Source
IUGATE
Upper Gate Source
R UGATE
VBOOT − VPHASE = 12V,
VBOOT − VUGATE = 1V
--
7
10
Ω
Upper Gate Sink
R UGATE
VBOOT − VPHASE = 12V,
VUGATE − VPHASE = 1V
--
4
8
Ω
Lower Gate Source
I LGATE
VCC = 12V, VLGATE = 6V
--
500
--
mA
Lower Gate Source
R LGATE
VCC − VLGATE = 1V
--
4
6
Ω
Lower Gate Sink
R LGATE
VLGATE = 1V
--
2
4
Ω
0.3
0.4
0.5
V
−210
−250
−290
mV
2
3.5
5
ms
VBOOT − VUGATE = 6V
Protection
Under Voltage Protection
Measuring VFB
Over Current Threshold
VOC
Measuring VPHASE
Soft-Start Interval
TSS
COMP pin released to 90% VOUT
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective 4-layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS8101/A-06 April 2011
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5
RT8101/A
Typical Operating Characteristics
Efficiency vs. Output Current
Reference Voltage vs. Temperature
0.8064
1.00
100
0.8043
Reference Voltage (V)
0.95
95
Efficiency (%)
RT8101
0.90
90
0.85
85
RT8101A
0.80
80
0
2.5
5
0.8001
0.7980
0.7959
0.7938
VCC = 12V
VIN = 5V
0.75
75
0.8022
VCC = 12V
VIN = 5V
0.7917
7.5
10
-50
12.5 15 17.5 20 22.5 25
-25
0
RT8101
2.54
2.54
2.53
2.53
Output Voltage (V)
Output Voltage (V)
2.55
2.52
2.51
VIN = 12V
2.49
VIN = 5V
2.48
2.47
2.46
100
125
RT8101A
2.52
2.51
VIN = 12V
2.50
2.49
VIN = 5V
2.48
2.47
2.46
2.45
2.45
0
2.5
5
7.5
10
12.5 15
17.5 20 22.5 25
0
2.5
5
Output Current (A)
7.5
10
12.5 15 17.5 20 22.5 25
Output Current (A)
Frequency vs. Temperature
325
75
Output Voltage vs. Output Current
Output Voltage vs. Output Current
2.50
50
Temperature (°C)
Output Current (A)
2.55
25
Frequency vs. Temperature
640
RT8101
RT8101A
320
620
Frequency (kHz)1
Frequency (kHz)1
315
310
305
300
295
600
580
560
290
540
285
280
520
-40
-10
20
50
80
Temperature (°C)
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6
110
140
-40
-10
20
50
80
110
140
Temperature (°C)
DS8101/A-06 April 2011
RT8101/A
Power On from VCC
Power Off from VCC
VOUT
(2V/Div)
VOUT
(2V/Div)
VIN
(10V/Div)
VIN
(10V/Div)
V CC
(10V/Div)
V CC
(10V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
Time (5ms/Div)
Time (5ms/Div)
Power On from VIN
Power On from VIN
VOUT
(2V/Div)
VOUT
(2V/Div)
VIN
(10V/Div)
VIN
(10V/Div)
V CC
(10V/Div)
V CC
(10V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
Time (5ms/Div)
Time (5ms/Div)
Dead Time (Rising)
Dead Time (Falling)
VCC = 12V
VIN = 12V
IOUT = 25A
VCC = 12V
VIN = 12V
IOUT = 25A
PHASE
PHASE
UGATE
(5V/Div)
(5V/Div)
LGATE
Time (50ns/Div)
DS8101/A-06 April 2011
UGATE
LGATE
Time (25ns/Div)
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RT8101/A
Transient Response (Rising)
Transient Response (Falling)
RT8101, VCC = VIN = 12V, IOUT = 0A to 15A,
f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF
RT8101, VCC = VIN = 12V, IOUT = 15A to 0A,
f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF
VOUT
(100mV/Div)
VOUT
(100mV/Div)
UGATE
UGATE
(20V/Div)
(20V/Div)
IOUT
IOUT
(10A/Div)
(10A/Div)
Time (5μs/Div)
Time (5μs/Div)
Transient Response (Rising)
Transient Response (Falling)
RT8101A, VCC = VIN = 12V, IOUT = 0A to 15A,
f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF
RT8101A, VCC = VIN = 12V, IOUT = 15A to 0A,
f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF
VOUT
(100mV/Div)
VOUT
(100mV/Div)
UGATE
UGATE
(20V/Div)
(20V/Div)
IOUT
IOUT
(10A/Div)
(10A/Div)
Time (5μs/Div)
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8
Time (5μs/Div)
DS8101/A-06 April 2011
RT8101/A
Application Information
Power On Reset
The RT8101/A automatically initializes upon applying of
input power VCC. The power on reset function (POR)
continually monitors the input bias supply voltage at the
VCC pin. The POR trip level is typically 9.6V at VCC
rising.
A 30μA current source flows through the internal resistor
21.6kΩ to PHASE pin causing 0.65V voltage drop across
the resistor. OCP is triggered if the voltage at PHASE pin
(drop of lower MOSFET VDS) is lower than −0.25V when
low side MOSFET conducting. Accordingly inductor
current threshold for OCP is a function of conducting
resistance of lower MOSFET RDS(ON) as :
VIN Detection
After POR the RT8101/A continuously generates a 10kHz
pulse train with 1μs pulse width to turn on the upper
MOSFET for detecting the existence of VIN. RT8101/A
keeps monitoring PHASE pin voltage during the detection
period.
As soon as the PHASE voltage crosses 1.5V two times,
VIN existence is recognized and the RT8101/A initiates
its soft-start cycle as described in next section.
VIN POR_H
+
PHASE_M
-
IOCSET =
30μ A × 21.6k-0.4V
RDS(ON)
If MOSFET with RDS(ON) = 10mΩ is used, the OCP
threshold current is about 25A. Once OCP is triggered,
the RT8101/A enters hiccup mode and re-soft starts again.
The RT8101/A shuts down after OCP hiccups twice.
OCP
PHASE
1.5V
UGATE
1st 2nd PHASE
waveform
Internal Counter will count (VPHASE > 1.5V)
two times (rising & falling) to recognize when
VIN is ready.
Figure 1
UGATE
(10V/Div)
IOUT
(10A/Div)
Soft-Start
A built-in soft-start is used to prevent surge current from
VIN to VOUT during power on. After the existence of VIN is
detected, soft-start (SS) begins automatically. The
feedback voltage (VFB) is clamped by internal linear ramping
up SS voltage, causing PWM pulse width increasing
slowly and thus inducing little surge current. Soft-start
completes when SS voltage exceeds internal reference
voltage (0.8V), the time duration is about 3.2ms.
Over Current Protection
The RT8101/A senses the current flowing through lower
MOSFET for Over Current Protection (OCP) by sensing
the PHASE pin voltage as shown in the Functional Block
Diagram.
Time (2.5ms/Div)
Figure 3. Power On then Shorted
OCP
UGATE
(10V/Div)
IOUT
(10A/Div)
Time (2.5ms/Div)
Figure 4. Shorted then Power On
DS8101/A-06 April 2011
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9
RT8101/A
Feedback Compensation
1) Modulator Frequency Equations
The RT8101/A is a voltage mode controller. The control
loop is a single voltage feedback path including a
compensator and modulator as shown in Figure 5. The
modulator consists of the PWM comparator and power
stage. The PWM comparator compares error amplifier EA
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) with an amplitude
of VIN at the PHASE node. The PWM wave is smoothed
by the output filter LOUT and COUT. The output voltage (VOUT)
is sensed and fed to the inverting input of the error amplifier.
A well-designed compensator regulates the output voltage
to the reference voltage VREF with fast transient response
and good stability.
The modulator transfer function is the small-signal transfer
function of VOUT / VCOMP (output voltage over the error
amplifier output. This transfer function is dominated by a
DC gain, a double pole, and a zero as shown in Figure 7.
The DC gain of the modulator is the input voltage (VIN)
divided by the peak to peak oscillator voltage VOSC. The
output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter is expressed as below:
In order to achieve fast transient response and accurate
output regulation, an adequate compensator design is
necessary. The goal of the compensation network is to
provide adequate phase margin (greater than 45 degrees)
and the highest 0dB crossing frequency. It is also
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of −20dB/dec.
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor should have enough ESR to satisfy
stability requirements. The ESR zero of the output
capacitor is expressed as follows :
Driver
PWM
Comparator
LOUT
-
ΔVOSC
Driver
+
1
2π L OUT × C OUT
fESR =
1
2π × COUT × ESR
2) Compensation Frequency Equations
VIN
OSC
fLC =
VOUT
The compensation network consists of the error amplifier
and the impedance networks ZC and ZF as shown in
Figure 6.
PHASE
COUT
ZF
C1
ESR
ZC
ZFB
C2
R2
COMP
EA
+
R1
ZIN
VOUT
REF
EA
+
COMP
ZFB
C2
C1
ZIN
C3
R2
VREF
RF
R3
Figure 6. Compensation Loop
R1
COMP
FB
EA
+
REF
Figure 5. Closed Loop
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10
VOUT
FB
fZ1 =
1
2π x R2 x C2
fP1 =
1
2π x R2 x C1 x C2
C1 + C2
DS8101/A-06 April 2011
RT8101/A
Figure 7 shows the DC/DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
ZC and ZF to provide a stable, high bandwidth loop. High
crossover frequency is desirable for fast transient
response, but it often jeopardizes the system stability. In
order to cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency. In the experience,
place the zero at 75% LC filter resonant frequency.
Crossover frequency should be higher than the ESR zero
but less than 1/5 of the switching frequency. The second
pole is placed at half of the switching frequency.
TS
Vg1
TON TOFF
Vg2
VIN - VOUT
VL
- VOUT
IL
IL = IOUT
ΔIL
80 80
Loop Gain
60
40 40
Compensation
Gain
Gain (dB)
20
0
IS1
0
-20
Modulator
Gain
IS2
-40-40
-60-60
10Hz
10vdb(vo)
100Hz
vdb(comp2)100
vdb(lo)
1.0KHz
10KHz
100KHz
1k
10k
Frequency (Hz)
Frequency
1.0MHz
100k
1M
Figure 7. Bode Plot
Figure 8. The waveforms of synchronous step-down
converter
Component Selection
1) Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔIL) between 20% and 50% of the output current
is appropriate. Figure 8 shows the typical topology of
synchronous step-down converter and its related
waveforms.
iS1
L
IL
iS2
VIN
S2
+
VOR
-
(1)
Where :
VIN = Maximum input voltage
VOUT = Output Voltage
ΔIL = Inductor current ripple
+
rC
RL
VOUT
+
DS8101/A-06 April 2011
IOUT
iC
+
VOC
-
V
ΔIL
; Δt = D ; D = OUT
VIN
Δt
fs
VOUT
L = (VIN − VOUT ) ×
VIN × fs × ΔIL
VIN − VOUT = L
Δt = S1 turn on time
+ VL S1
According to Figure 8 the ripple current of inductor can be
calculated as follows :
fS = Switching frequency
D = Duty Cycle
COUT
-
rC = Equivalent series resistor of output capacitor
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RT8101/A
2) Output Capacitor
3) Input Capacitor
The selection of output capacitor depends on the output
ripple voltage requirement. Practically, the output ripple
voltage is a function of both capacitance value and the
Equivalent Series Resistance (ESR) rC. Figure 9 shows
the related waveforms of output capacitor.
The selection of input capacitor is mainly based on its
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
the on time of S1 as shown in Figure 8. The RMS value of
ripple current flowing through the input capacitor is
described as :
dIL VIN-VOUT
=
L
dt
IL
VOUT
dIL
dt =
L
Irms = IOUT D(1 - D) (A)
IOUT
(6)
The input capacitor must be capable of handling this ripple
current. Sometimes, for higher efficiency the low ESR
capacitor is necessarily.
TS
IC
1/2ΔIL
Thermal Considerations
ΔIL
0
For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The
maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
VOC
ΔVOC
VOR
PD(MAX) = ( TJ(MAX) − TA ) / θJA
ΔIL x rC
0
t1
Where T J(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance.
t2
Figure 9. The related waveforms of output capacitor
The AC impedance of output capacitor at operating
frequency is quite smaller than the load impedance, so
the ripple current (ΔIL) of the inductor current flows mainly
through output capacitor. The output ripple voltage is
described as :
ΔVOUT = ΔVOR + Δ VOC
ΔVOUT = ΔIL × rC +
1
CO
(2)
t2
∫t1
ΔVOUT = ΔIL × Δ IL × rC +
IC dt
2
1 VOUT
(1 − D)TS
8 C OL
The maximum power dissipation at TA = 25°C can be
calculated by following formula :
(3)
PD(MAX) = ( 125°C − 25°C) / (120°C/W) = 0.83W for
SOP-8 packages
(4)
PD(MAX) = ( 125°C − 25°C) / (75°C/W) = 1.33W for
where ΔVOR is caused by ESR and ΔVOC by capacitance.
For electrolytic capacitor application, typically 90 to 95%
of the output voltage ripple is contributed by the ESR of
output capacitor. So Equation (4) could be simplified as :
ΔVOUT = ΔIL x rC
For recommended operating conditions specification of
RT8101/A, where T J(MAX) is the maximum junction
temperature of the die (125°C) and TA is the maximum
ambient temperature. The junction to ambient thermal
resistance θJA is layout dependent.
(5)
SOP-8 (Exposed Pad) packages
The maximum power dissipation depends on operating
ambient temperature for fixed T J (MAX) and thermal
resistance θJA. For RT8101/A packages, Figure 10 allows
the designer to see the effect of rising ambient temperature
on the maximum power allowed.
Users could connect capacitors in parallel to get calculated
ESR.
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12
DS8101/A-06 April 2011
RT8101/A
The power components and the PWM controller should
be placed firstly. Place the input capacitors, especially
the high-frequency ceramic decoupling capacitors, close
to the power switches. Place the output inductor and
output capacitors between the MOSFETs and the load.
Also locate the PWM controller near by MOSFETs. A
multi-layer printed circuit board is recommended.
Figure 11 shows the connections of the critical
components in the converter. Note that the capacitors CIN
and COUT each of them represents numerous physical
capacitors.
1.4
SOP-8 (Exposed Pad)
Power Dissipation (W)
1.2
1
SOP-8
0.8
0.6
0.4
0.2
0
0
20
40
60
80
100
120
140
Ambient Temperature (°C)
Figure 10. Derating Curves for RT8101/A Packages
PCB Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency and radiate noise, that results
in over voltage stress on devices. Careful component
placement layout and printed circuit design can minimize
the voltage spikes induced in the converter. Consider, as
an example, the turn-off transition of the upper MOSFET
prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side MOSFET
or schottky diode.
VOUT
5V/12V
Q1
+
DS8101/A-06 April 2011
IL
+
There are two sets of critical components in a DC/DC
converter using the RT8101/A. The switching power
components are most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
IQ1
+
Any inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selections, layout of the critical components,
and use shorter and wider PCB traces help in minimizing
the magnitude of voltage spikes.
Use a dedicated grounding plane and use vias to ground
all critical components to this layer. Apply another solid
layer as a power plane and cut this plane into smaller
islands of common voltage levels. The power plane should
support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers
for the PHASE node, but it is not necessary to oversize
this particular island. Since the PHASE node is subjected
to very high dV/dt voltages, the stray capacitance formed
between these islands and the surrounding circuitry will
tend to couple switching noise. Use the remaining printed
circuit layers for small signal routing. The PCB traces
between the PWM controller and the gate of MOSFET
and also the traces connecting source of MOSFETs should
be sized to carry 2A peak currents.
LOAD
IQ2
Q2
GND
GND
LGATE VCC
RT8101/A
UGATE
FB
Figure 11. The connections of the critical components
in the converter
www.richtek.com
13
RT8101/A
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
8-Lead SOP Plastic Package
www.richtek.com
14
DS8101/A-06 April 2011
RT8101/A
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8101/A-06 April 2011
www.richtek.com
15
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