HV9931 DATA SHEET (10/21/2008) DOWNLOAD

HV9931
HV9931 Unity Power Factor LED Lamp Driver
Features
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General Description
The HV9931 is a fixed frequency PWM controller IC designed
to control an LED lamp driver using a single-stage PFC
buckboost-buck topology. It can achieve a unity power factor
and a very high step-down ratio that enables driving a single
high-brightness LED from the 85-264VAC input without a
need for a power transformer. This topology allows reducing
the filter capacitors and using non-electrolytic capacitors to
improve reliability. The HV9931 uses open-loop peak current
control to regulate both the input and the output current. This
control technique eliminates a need for loop compensation,
limits the input inrush current, and is inherently protected from
input under-voltage condition.
Constant output current
Large step-down ratio
Unity power factor
Low input current harmonic distortion
Fixed frequency or fixed off-time operation
Internal 450V linear regulator
Input and output current sensing
Input current limit
Enable, PWM and phase dimming
Applications
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Capacitive isolation protects the LED Lamp from failure of the
switching MOSFET. HV9931 provides a low-frequency PWM
dimming input that can accept an external control signal with a
duty ratio of 0-100% and a frequency of up to a few kilohertz.
The PWM dimming capability enables HV9931 phase control
solutions that can work with standard wall dimmers.
Offline LED lamps and fixtures
Street lamps
Traffic signals
Decorative lighting
Typical Application Circuit
D4
VIN
D1
L1
C1
L2
D2
~AC
~AC
Rref1
D3
Q1
CIN
VO
RS2
RS1
RCS2
RCS1
VIN
GATE
RT
+
Rref2
RT
PWMD
CS1
CS2
GND
VDD
C2
HV9931
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HV9931
Ordering Information
8-Lead SOIC (Narrow Body)
Device
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
HV9931
HV9931LG-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
Absolute Maximum Ratings
Parameter
Value
VIN to GND
-0.5V to +470V
VDD to GND
-0.3V to +13.5V
CS1, CS2, PWMD, GATE, RT to GND
Operating temperature range
-0.3V to (VDD +0.3V)
-40°C to +85°C
Storage temperature range
VIN
1
8
RT
CS1
2
7
CS2
GND
3
6
VDD
GATE
4
5
PWMD
8-Lead SOIC (LG)
-65°C to +150°C
Continuous power dissipation (TA = +25°C)
(top view)
630mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated
in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
Product Marking
Y = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YWW
H9931
LLLL
Thermal Resistance
8-Lead SOIC (LG)
Package
θja
8-Lead SOIC
128OC/W
Electrical Characteristics (The * denotes the specifications which apply over the full operating junction temperature range of
-40°C < TA < +85°C, otherwise the specifications are at TA = 25°C, VIN = 12V, unless otherwise noted)
Sym
Parameter
Min
Typ
Max
Units
Conditions
VINDC
Input DC supply voltage range*
8.0
-
450
V
IINSD
Shut-down mode supply current*
-
0.5
1.0
mA
PWMD connected to GND
7.12
7.50
7.88
V
VIN = 8.0, IDD(EXT) = 0,
GATE = 500pF, RT = 226KΩ
0
-
1.0
V
VIN = 8.0 - 450V, IDD(ext) = 0,
GATE = 500pF, RT = 226kΩ,
VDD rising
Input
DC input voltage
Internal Regulator
VDD
ΔVDD, line
Internally regulated voltage
Line regulation of VDD
UVLO
VDD undervoltage lockout threshold
6.45
6.70
6.95
V
∆UVLO
VDD undervoltage lockout hysteresis
-
500
-
mV
---
PWM Dimming
VPWMD(lo)
PWMD input low voltage
-
-
1.0
V
VIN = 8.0 - 450V
VPWMD(hi)
PWMD input high voltage
2.4
-
-
V
VIN = 8.0 - 450V
PWMD pull-down resistance
50
100
150
kΩ
RPWMD
VPWMD = 5.0V
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2
HV9931
Electrical Characteristics (cont.) (The * denotes the specifications which apply over the full operating junction temperature
range of -40°C < TA < +85°C, otherwise the specifications are at TA = 25°C, VIN = 12V, unless otherwise noted)
Sym
Parameter
Min
Typ
Max
Units
Conditions
GATE
VGATE(hi)
GATE high output voltage*
VDD -0.3
-
VDD
V
IGATE = 10mA, VDD = 7.5V,
VIN open
VGATE(lo)
GATE low output voltage*
0
-
0.3
V
IGATE = -10mA, VDD = 7.5V,
VIN open
TRISE
GATE output rise time
-
30
50
ns
CGATE = 500pF, VDD = 7.5V,
VIN open
TFALL
GATE output fall time
-
30
50
ns
CGATE = 500pF, VDD = 7.5V,
VIN open
TDELAY
Delay from CS trip to GATE
-
150
300
ns
VCS1, VCS2 = -100mV
TBLANK
Blanking delay
150
215
280
ns
VCS1, VCS2 = -100mV
Oscillator frequency
80
100
120
kHz
RT = 226KΩ
-15
-
15
mV
---
Oscillator
FOSC
Comparators
VOFFSET1
VOFFSET2
Comparator input offset voltage*
Functional Block Diagram
VIN
Regulator
VDD
7.5V
Osc
CS1
Leading
Edge
Blanking
RT
S
R Q
GATE
CS2
AGND
PWMD
HV9931
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3
HV9931
Functional Description
Power Topology
The HV9931 is optimized to drive Supertex’s proprietary
single-stage, single-switch, non-isolated topology, cascading
an input power factor correction (PFC) buck-boost stage
and an output buck converter power stage. This power
converter topology offers numerous advantages useful
for driving high-brightness light emitting diodes (HB LED).
These advantages include unity power factor, low harmonic
distortion of the input AC line current, and low output current
ripple. The output load is decoupled from the input voltage
with a capacitor making the driver inherently failure-safe for
the output load. The power converter topology also permits
reducing the size of a filter capacitor needed, enabling use
of non-electrolytic capacitors. The latter advantage greatly
improves reliability of the overall solution.
The HV9931 is a peak current-mode controller that is
specifically designed to drive a constant current buckboost-buck power converter. This patent pending control
scheme features two identical current sense comparators
for detecting negative current signal levels. One of the
comparators regulates the output LED current, while the
other is used for sensing the input inductor current. The
second comparator is mainly responsible for the converter
start-up. The control scheme inherently features low inrush
current and input under-voltage protection. The HV9931 can
operate with programmable constant frequency or constant
off-time. In many cases, the constant off-time operating mode
is preferred, since it improves line regulation of the output
current, reduces voltage stress of the power components
and simplifies regulatory EMI compliance. (See Application
Note AN-H52.)
Input Voltage Regulator
The HV9931 can be powered directly from its VIN pin, and
takes a voltage from 8V to 450V. When a voltage is applied
at the VIN pin, the HV9931 seeks to maintain a constant
7.5V at the VDD pin. The VDD voltage can be also used as a
reference for the current sense comparators. The regulator
is equipped with an under-voltage protection circuit which
shuts off the HV9931 when the voltage at the VDD pin falls
below 6.2V.
The VDD pin must be bypassed by a low ESR capacitor
(≥ 0.1µF) to provide a low impedance path for the high
frequency current of the output GATE driver.
The HV9931 can also be operated by supplying a voltage
at the VDD pin greater than the internally regulated voltage.
This will turn off the internal linear regulator and the HV9931
will function by drawing power from the external voltage
source connected to the VDD pin.
PWM Dimming and Wall Dimmer Compatibility
PWM Dimming can be achieved by applying a TTLcompatible square wave signal at the PWMD pin. When the
PWMD pin is pulled high, the GATE driver is enabled and the
circuit operates normally. When the PWMD pin is left open
or connected to GND, the GATE driver is disabled and the
external MOSFET turns off. The HV9931 is designed so that
the signal at the PWMD pin inhibits the driver only, and the
IC need not go through the entire start-up cycle each time
ensuring a quick response time for the output current.
The power topology requires little filter capacitance at
the output, since the output current of the buck stage is
continuous, and since AC line filtering is accomplished
through the middle capacitor rather than the output one.
Therefore, disabling the HV9931 via its PWMD or VIN pins
can interrupt the output LED current in accordance with
the phase-controlled voltage waveform of a standard wall
dimmer.
Oscillator
Connecting an external resistor from RT pin to GND programs
switching frequency:
FS [kHz ] =
25000
RT [K Ω ]+ 22
Connecting the resistor from the RT pin to the GATE
programs constant off-time:
TOFF [µ s ] =
RT [K Ω ] + 22
25
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4
HV9931
Input and Output Current Feedback
Two current sense comparators are included in the HV9931.
Both comparators have their non-inverting inputs internally
connected to ground (GND). The CS1 and CS2 inputs are
inverting inputs of the comparators. Connecting a resistor
divider into either of these inputs from a positive reference
voltage and a negative current sense signal programs the
current sense threshold of the comparator. The VDD voltage
of the HV9931 can be used as the reference voltage. If more
accuracy is needed, an external reference voltage can be
applied. When either the CS1 or the CS2 pin voltage falls
below GND, the GATE pulse is terminated. A leading edge
blanking delay of 215ns (typ) is added. The GATE voltage
becomes high again upon receiving the next clock pulse of
the oscillator circuit.
Referring to the Functional Circuit Diagram, the CS2
comparator is responsible for regulating output current. The
output LED current can be programmed using the following
equation:
RCS 2 =
1
∆ I L2
2
⋅ RREF 2 ⋅ RS 2
7.5V
Io +
where ∆IL2 is the peak-to-peak current ripple in L2. The CS1
comparator limits the current in the input inductor L1. There
is no charge in the capacitor C1 upon the start-up of the
converter. Therefore, L2 cannot develop the output current,
and the HV9931 starts-up in the input current limiting mode.
The CS1 current threshold must be programmed such that no
input current limiting occurs in normal steady-state operation.
The CS1 threshold can be programmed in accordance with
a similar equation:
RCS 1 =
I L1( PK )
7.5V
⋅ RREF 1 ⋅ RS 1
where IL1(PK) is the maximum peak current in L1.
MOSFET Gate Driver
Typically, the GATE driving capability of the HV9931 is limited
by the amount of power dissipation in its linear regulator.
Thus, care must be taken selecting a switching MOSFET
to be used in the circuit. An optimal trade-off must be found
between the GATE charge and the on-resistance of the
MOSFET to minimize the input regulator current.
Switching Waveform
GATE
VDD
0
t
0
t
iL2
iL1
0
t
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5
HV9931
Functional Circuit Diagram
D1
L1
D4
VIN
iL1
CIN
~AC
+
VC1
L2
D2
_
-
iL2
D3
Q1
~AC
RCS1
C1
RS1
VO
RS2
_ VS1 +
+
RT
VS2
+
_
RCS2
PWMD
GATE
RT
OSC
S Q
R
CS2
CS1
Rref1
Rref2
RE G
VIN
7.5V
VDD
GND
HV9931
CDD
Pin Description
Pin #
Pin Name
Description
1
VIN
This pin is the input of a high voltage regulator.
2
CS1
This pin is used to sense the input and output currents of the converter. It is the inverting input
of the internal comparator.
3
GND
Ground return for all the internal circuitry. This pin must be electrically connected to the ground
of the power train.
4
GATE
This pin is the output GATE driver for an external N-channel power MOSFET.
5
PWMD
When this pin is pulled to GND, switching of the HV9931 is disabled. When the PWMD pin
is released, or external TTL high level is applied to it, switching will resume. This feature is
provided for applications that require PWM dimming of the LED lamp.
6
VDD
This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor
to GND.
7
CS2
This pin is used to sense the input and output currents of the converter. It is the inverting input
of the internal comparator.
8
RT
Oscillator control. A resistor connected between this pin and GND sets the PWM frequency. A
resistor connected between this pin and GATE sets the PWM off-time.
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6
HV9931
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
D
θ1
8
E
E1
L2
Note 1
(Index Area
D/2 x E1/2)
L
1
Top View
View B
A
Note 1
A
θ
L1
Seating
Plane
View B
h
h
A2
Gauge
Plane
Seating
Plane
b
e
A1
A
Side View
View A-A
Note:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
Symbol
Dimension
(mm)
A
A1
A2
b
MIN
1.35*
0.10
1.25
0.31
NOM
-
-
-
-
MAX
1.75
0.25
1.65*
0.51
D
E
E1
4.80* 5.80* 3.80*
4.90
6.00
3.90
5.00* 6.20* 4.00*
e
1.27
BSC
h
L
0.25
0.40
-
-
0.50
1.27
L1
1.04
REF
L2
0.25
BSC
θ
θ1
0O
5O
-
-
8O
15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version H101708.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008
Doc.# DSFP-HV9931
A102108
All rights reserved. Unauthorized use or reproduction is prohibited.
7
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com