TC2320 N- and P-Channel Enhancement-Mode Dual MOSFET Features General Description ► ► ► ► ► ► ► The Supertex TC2320 consists of a high voltage, low threshold N- and P-channel MOSFET in an 8-Lead SOIC package. This low threshold enhancement-mode (normallyoff) transistor utilizes an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Low threshold Low on-resistance Low input capacitance Fast switching speeds Freedom from secondary breakdown Low input and output leakage Independent, electrically isolated N- and P-channels Applications ► ► ► ► ► ► ► Medical ultrasound transmitters High voltage pulsers Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Logic level interface Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Ordering Information Device TC2320 4.90x3.90mm body, 1.75mm height (max) 1.27mm pitch RDS(ON) BVDSS/BVDGS 8-Lead SOIC (Narrow Body) (max) (Ω) (V) N-Channel P-Channel N-Channel P-Channel 200 -200 7.0 12 TC2320TG-G -G indicates package is RoHS compliant (‘Green’) Pin Configuration DP DN DN DP Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature Soldering temperature* -55°C to +150°C +300°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * SN SP GN GP 8-Lead SOIC (TG) Product Marking YYWW C2320 LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or 8-Lead SOIC (TG) Distance of 1.6mm from case for 10 seconds. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com TC2320 N-Channel Electrical Characteristics (T A = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 100µA VGS(th) Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID = 1.0mA Change in VGS(th) with temperature - - -4.5 O mV/ C VGS = VDS, ID = 1.0mA Gate body leakage - - 100 nA VGS = ±20V, VDS = 0V - - 1.0 µA VGS = 0V, VDS = 100V - - 10.0 µA - - 1.0 mA 0.6 - - 1.2 - - Static drain-to-source on-state resistance - - 8.0 - - 7.0 Change in RDS(ON) with temperature - - 1.0 %/ C VGS = 4.5V, ID =150mA 150 - - mmho VDS = 25V, ID = 200mA ΔVGS(th) IGSS IDSS ID(ON) RDS(ON) ΔRDS(ON) Zero gate voltage drain current On-state drain current GFS Forward transconductance CISS Input capacitance - - 110 COSS Common source output capacitance - - 60 CRSS Reverse transfer capacitance - - 23 td(ON) Turn-on delay time - - 20 Rise time - - 15 Turn-off delay time - - 25 Fall time - - 25 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr A Ω O Conditions VGS = 0V, VDS = Max rating VGS = 0V, TA = 125OC VDS = 0.8 Max Rating VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 150mA VGS = 10V, ID = 1.0A pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD =25V, ID = 150mA, RGEN = 25Ω 1.8 V VGS = 0V, ISD = 200mA - ns VGS = 0V, ISD = 200mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. N-Channel Switching Waveforms and Test Circuit 10V 90% INPUT 0V PULSE GENERATOR 10% t(ON) td(ON) VDD VDD t(OFF) tr 10% td(OFF) D.U.T. 10% INPUT 90% OUTPUT RGEN tF OUTPUT 0V RL 90% ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2 TC2320 P-Channel Electrical Characteristics (T A = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA Gate body leakage - - -100 nA VGS = ±20V, VDS = 0V - - -10 µA VGS = 0V, VDS = Max rating - - -1.0 mA VGS = 0V, TA = 125OC, VDS = 0.8 Max Rating -0.25 -0.7 - -0.75 -2.1 - Static drain-to-source on-state resistance - 10 15 - 8.0 12 Change in RDS(ON) with temperature - - 1.7 %/OC VGS = -10V, ID =-200mA 100 250 - mmho VDS = -25V, ID = -200mA ΔVGS(th) IGSS IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) ΔRDS(ON) GFS Forward transconductance CISS Input capacitance - 75 125 COSS Common source output capacitance - 20 85 CRSS Reverse transfer capacitance - 10 35 td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-on delay time - - 20 Fall time - - 15 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr A Ω Conditions VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -4.5V, ID = -100mA VGS = -10V, ID = -200mA pF VGS = 0V, VDS = -25V, f = 1.0MHz ns VDD = -25V, ID = -0.75A, RGEN = 25Ω -1.8 V VGS = 0V, ISD = -0.5A - ns VGS = 0V, ISD = -0.5A Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. P-Channel Switching Waveforms and Test Circuit 0V PULSE GENERATOR 10% INPUT -10V td(ON) RGEN 90% t(OFF) t(ON) td(OFF) tr D.U.T. tF 0V 90% OUTPUT VDD Output INPUT 10% 90% RL 10% VDD ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 3 TC2320 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch D θ1 8 E E1 L2 Note 1 (Index Area D/2 x E1/2) L 1 θ L1 Top View Gauge Plane Seating Plane View B A View B Note 1 h h A A2 Seating Plane b e A1 A Side View View A-A Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 A2 b MIN 1.35* 0.10 1.25 0.31 NOM - - - - MAX 1.75 0.25 1.65* 0.51 D E E1 4.80* 5.80* 3.80* 4.90 6.00 3.90 5.00* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 1.04 REF L2 0.25 BSC θ θ1 0O 5O - - 8O 15O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version H101708. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. ©2008 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TC2320 B122208 4 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com