Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Fiber optics and broadband telecommunications GND 1 19 GND 21 GND 22 GND 20 RF2 18 GND ADRF5040 GND 2 50Ω 50Ω 17 VDD RFC 3 16 V2 GND 4 15 V1 GND 5 14 VSS 50Ω 50Ω GND 6 PACKAGE BASE GND 14290-001 GND 12 RF3 11 9 GND GND 10 8 RF4 13 GND 7 APPLICATIONS 23 RF1 FUNCTIONAL BLOCK DIAGRAM Nonreflective 50 Ω design Positive control: 0 V/3.3 V Low insertion loss: 0.86 dB at 8.0 GHz High isolation: 35 dB at 8.0 GHz High power handling 33 dBm through path 27 dBm terminated path High linearity 1 dB compression (P1dB): 37 dBm typical Input third-order intercept (IIP3): 57 dBm typical ESD rating: 4.5 kV human body model (HBM) 4 mm × 4 mm, 24-lead LFCSP package No low frequency spurious Settling time (0.05 dB margin of final RFOUT): 9 µs 24 GND FEATURES GND Preliminary Technical Data High Isolation, Silicon SP4T, Nonreflective Switch, 9 kHz to 12.0 GHz ADRF5040 Figure 1. GENERAL DESCRIPTION The ADRF5040 is a general-purpose, broadband high isolation, nonreflective single-pole, quad-throw (SP4T) switch in a LFCSP surface mount package. Covering the 9 kHz to 12 GHz range, the switch offers high isolation and low insertion loss. The switch features >34 dB isolation, 0.8 dB insertion loss up to Rev. PrB 8.0 GHz, and a 9 µs settling time of 0.05 dB margin of final RFOUT. The switch operates using positive control voltage of +3.3 V and 0 V and requires +3.3 V and −3.3 V supplies. The ADRF5040 is packaged in a 4 mm × 4 mm, surface mount LFCSP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5040 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................8 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................9 General Description ......................................................................... 1 Input Power Compression and Input Third-Order Intercept ....................................................................................................... 10 Specifications..................................................................................... 3 Electrical Specifications ............................................................... 3 Digital Control Voltages .............................................................. 4 Bias and Supply Current .............................................................. 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Input Power Compression and Input Third-Order Intercept (10 kHz to 1 GHz) ...................................................................... 11 Theory of Operation ...................................................................... 12 Applications Information .............................................................. 13 Evaluation PCB ........................................................................... 13 Outline Dimensions ....................................................................... 14 Interface Schematics..................................................................... 7 Rev. PrB | Page 2 of 14 Preliminary Technical Data ADRF5040 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = -3.3 V, V1 and V2 = 0 V/VDD, TA = 25°C, 50 Ω system, unless otherwise specified. Table 1. Parameter INSERTION LOSS Test Conditions/Comments Min Typ Max Unit 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 0.7 0.8 1.1 2 dB dB dB dB 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 44 34 29.2 20 dB dB dB dB 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 21 19 13.5 8 25 18.6 15.5 14.5 dB dB dB dB dB dB dB dB 50% V1/ V2 to 0.05 dB margin of final RFOUT 50% V1/ V2 to 0.1 dB margin of final RFOUT 9 7 µs µs 10% to 90% RFOUT 50% V1/V2 to 90%/10% RF 9 kHz to 12.0 GHz 1.3 3.5 µs µs 37 34 dBm dBm 62 58 53 dBm dBm dBm ISOLATION, RFC TO RF1 to RF4 (WORST CASE) RETURN LOSS On State Off State RF SETTLING TIME SWITCHING SPEED tRISE/tFALL tON/tOFF INPUT POWER 1 dB Compression (P1dB) 0.1 dB Compression (P0.1dB) INPUT THIRD-ORDER INTERCEPT (IIP3) RECOMMENDED OPERATING CONDITIONS Positive Supply Voltage (VDD) Negative Supply Voltage (VSS) Control Voltage (V1, V2) Range RF Input Power Through Path Termination Path Hot Switch Power Level Case Temperature Range (TCASE) Two-tone input power = 14 dBm at each tone 1 MHz to 2.0 GHz 1 MHz to 8.0 GHz 1 MHz to 12.0 GHz 3.0 −3.6 0 3.6 −3.0 VDD V V V −40 33 27 27 +85 dBm dBm dBm °C VDD = 3.3 V, VSS = −3.3 V, TA = 85°C, frequency = 2 GHz VDD = 3.3 V, TA = 85°C, frequency = 2 GHz Rev. PrB | Page 3 of 14 ADRF5040 Preliminary Technical Data DIGITAL CONTROL VOLTAGES VDD = 3.3 V ± 10%, VSS = −3.3 V ± 10%, TCASE = −40°C to +85°C, unless otherwise specified. Table 2. Parameter INPUT CONTROL VOLTAGE Low (VIL) High (VIH) Symbol Min VIL VIH 0 1.4 Typ Max Unit 0.8 VDD + 0.3 V V Test Condition/Comments <1 µA typical BIAS AND SUPPLY CURRENT TCASE = −40°C to +85°C, unless otherwise specified. Table 3. Parameter SUPPLY CURRENT VDD = 3.3 V VSS = −3.3 V Symbol IDD ISS Min Typ Max Unit 20 20 100 100 µA µA Rev. PrB | Page 4 of 14 Preliminary Technical Data ADRF5040 ABSOLUTE MAXIMUM RATINGS 5 Table 4. POWER DERATING (dBm) 34 dBm 28 dBm 30 dBm 0 –5 –10 –15 −65°C to +150°C 135°C –25 0.01 0.1 1 10 100 1k 10k FREQUENCY (MHz) 14290-002 –20 Figure 2. Power Derating Through Path 5 0 For recommended operating conditions, see Table 1. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. –5 –10 –15 –20 0.01 0.1 1 10 100 1k 10k FREQUENCY (MHz) 14290-003 4 kV (Class 3) 1.25 kV Figure 3. Power Derating Terminated Path 5 POWER DERATING (dBm) 0 –5 –10 –15 –20 0.01 0.1 1 10 100 FREQUENCY (MHz) Figure 4. Power Derating for Hot Switching Power ESD CAUTION Rev. PrB | Page 5 of 14 1k 14290-004 1 Rating −0.3 V to +3.7 V dc −3.7 V to +0.3 V −0.3 V to VDD +0.3 V POWER DERATING (dBm) Parameter Positive Supply Voltage (VDD) Range Negative Supply Voltage (VSS) Range Control Voltage (V1, V2) Range RF Input Power1 (VDD/ V1, V2 = 3.3 V, VSS = −3.3 V, TA = 85°C, Frequency = 2 GHz) Through Path Termination Path Hot Switch Power Level (VDD = 3.3 V, TA = 85°C, Frequency = 2 GHz) Storage Temperature Range Channel Temperature Thermal Resistance (Channel to Package Bottom) Through Path Terminated Path ESD Sensitivity Human Body Model (HBM) Charged Device Model (CDM) ADRF5040 Preliminary Technical Data GND 1 18 GND GND 2 17 VDD RFC 3 ADRF5040 GND 4 TOP VIEW (Not to Scale) 16 V2 RF3 11 GND 12 GND 10 13 GND GND 9 GND 6 RF4 8 15 V1 14 VSS GND 7 GND 5 PACKAGE BASE GND NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PRINTED CIRCUIT BOARD (PCB). 14290-005 20 RF2 19 GND 22 GND 21 GND 24 GND 23 RF1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 2, 4 to 7, 9, 10, 12, 13, 18, 19, 21, 22, 24 3 Mnemonic GND 8 RF4 11 RF3 14 16 15 17 20 VSS V1 V2 VDD RF2 23 RF1 RFC EPAD Description Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF ground. See Figure 6 for the GND interface schematic. RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if RF line potential is not equal to 0 V dc. RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if RF line potential is not equal to 0 V dc. RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if RF line potential is not equal to 0 V dc. Negative Supply Voltage Pin. Control Input Pin 1. See Table 2 and Table 6. Control Input Pin 2. See Table 2 and Table 6. Positive Supply Voltage PIN. RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if RF line potential is not equal to 0 V dc. RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if RF line potential is not equal to 0 V dc. Exposed Pad. The exposed pad must be connected to the RF /dc ground of the printed circuit board (PCB). Table 6. Truth Table V1 Low High Low High Digital Control Inputs V2 Low Low High High Signal Path State RFC to RF1 RFC to RF2 RFC to RF3 RFC to RF4 Rev. PrB | Page 6 of 14 Preliminary Technical Data ADRF5040 INTERFACE SCHEMATICS 14290-006 GND 14290-008 VDD Figure 8. V1 Interface Schematic Figure 6. GND Interface Schematic 14290-007 VDD Figure 7. V2 Interface Schematic Rev. PrB | Page 7 of 14 ADRF5040 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION VDD = 3.3 V, VSS = −3.3 V, TCASE = 25°C, unless otherwise specified. 0 0 –0.5 INSERTION LOSS (dB) –1.0 RFC TO RFC TO RFC TO RFC TO –1.5 RF1 RF2 RF3 RF4 –1.0 –1.5 TCASE TCASE TCASE TCASE –2.0 –2.0 2 4 6 8 10 12 FREQUENCY (GHz) –3.0 14290-009 0 0 2 4 6 8 10 12 FREQUENCY (GHz) Figure 9. Insertion Loss vs. Frequency 14290-012 –2.5 –2.5 Figure 12. Insertion Loss vs. Frequency RFC to RF1 On or RFC to RF4 On 0 0 –20 –0.5 –40 ISOLATION (dB) –1.0 –1.5 TCASE TCASE TCASE TCASE –2.0 = +105°C = +85°C = +25°C = –40°C –2.5 0 2 4 –60 RFC TO RF2 RFC TO RF3 RFC TO RF4 –80 –100 6 8 10 12 FREQUENCY (GHz) –120 14290-010 INSERTION LOSS (dB) = +105°C = +85°C = +25°C = –40°C 0 2 4 6 8 10 12 FREQUENCY (GHz) Figure 10. Insertion Loss vs. Frequency RFC to RF2 On or RFC to RF3 On 14290-013 INSERTION LOSS (dB) –0.5 Figure 13. Isolation vs Frequency RFC to RF1 = On 0 0 –10 –20 –30 ISOLATION (dB) –40 –60 RFC TO RF1 RFC TO RF3 RFC TO RF4 –80 –40 –50 –60 RFC TO RF1 RFC TO RF2 RFC TO RF4 –70 –80 –100 0 2 4 6 8 FREQUENCY (GHz) 10 12 –100 0 2 4 6 8 FREQUENCY (GHz) Figure 11. Isolation vs Frequency RFC to RF2 = On Figure 14. Isolation vs Frequency RFC to RF3 = On Rev. PrB | Page 8 of 14 10 12 14290-014 –90 –120 14290-011 ISOLATION (dB) –20 Preliminary Technical Data ADRF5040 INSERTION LOSS, RETURN LOSS, AND ISOLATION VDD = 3.3 V, VSS = −3.3 V, TCASE = 25°C, unless otherwise specified. 0 0 –10 –20 –20 ISOLATION (dB) –50 –60 RFC TO RF1 RFC TO RF2 RFC TO RF3 –70 –60 –80 –120 –80 0 2 4 6 8 10 12 FREQUENCY (GHz) RF3 RF4 RF4 RF2 RF3 RF4 –140 14290-015 –90 0 2 4 6 8 10 12 FREQUENCY (GHz) Figure 15. Isolation vs Frequency, RFC to RF4 = On Figure 17. Channel to Channel Isolation vs Frequency, RFC to RF1 = On 0 0 –5 –5 –10 RETURN LOSS (dB) –10 –15 –20 –25 RFC –30 –15 –20 –25 –30 CH1, CH2, CH3 AND CH4 (OFF) CH1, CH2, CH3 AND CH4 (ON) –35 –35 –40 –40 0 2 4 6 8 FREQUENCY (GHz) 10 12 –45 14290-016 RETURN LOSS (dB) RF2 TO RF2 TO RF3 TO RF1 TO RF1 TO RF1 TO –100 14290-017 –40 0 2 4 6 8 FREQUENCY (GHz) Figure 16. Return Loss vs Frequency, RFC to RF4 = On Figure 18. Return Loss vs Frequency, RFC to RF4 = On Rev. PrB | Page 9 of 14 10 12 14290-018 ISOLATION (dB) –40 –30 ADRF5040 Preliminary Technical Data 44 44 42 42 40 40 INPUT COMPRESSION (dBm) 38 36 34 32 30 +85°C +25°C –40°C 28 38 36 34 32 28 26 1 2 3 4 5 6 7 8 9 10 11 12 FREQUENCY (GHz) 24 14290-019 0 0 44 42 42 40 40 INPUT COMPRESSION (dBm) 4 5 6 7 8 9 10 11 12 38 36 34 32 +85°C +25°C –40°C 26 38 36 34 32 3.6V 3.3V 3V 30 28 26 0 1 2 3 4 5 6 7 8 9 10 11 12 FREQUENCY (GHz) 24 14290-020 24 0 60 60 IIP3 (dBm) 65 55 TCASE = +85°C TCASE = +25°C TCASE = –40°C 4 6 FREQUENCY (GHz) 8 10 12 5 6 7 8 9 10 11 12 3.6V 3.3V 3V 45 14290-021 2 4 55 50 45 3 Figure 23. 1dB Compression Point vs Frequency over Voltage, TC = 25°C 65 0 2 FREQUENCY (GHz) Figure 20. 1 dB Compression Point vs Frequency over Temperature, VDD = 3.3 V, VSS = −3.3 V 50 1 14290-023 INPUT COMPRESSION (dBm) 3 Figure 22. 0.1 dB Compression Point vs Frequency over Voltage TC = 25°C 44 28 2 FREQUENCY (GHz) Figure 19. 0.1 dB Compression Point vs Frequency over Temperature, VDD = 3.3 V, VSS = −3.3 V 30 1 14290-022 26 24 IIP3 (dBm) 3.6V 3.3V 3V 30 Figure 21. Input Third-Order Intercept (IIP3) Point vs Frequency over Temperature, VDD = 3.3 V, VSS = −3.3 V 0 2 4 6 8 10 12 FREQUENCY (GHz) Figure 24. Input Third-Order Intercept (IP3) Point vs Frequency over Voltage, TC = 25°C Rev. PrB | Page 10 of 14 14290-024 INPUT COMPRESSION (dBm) INPUT POWER COMPRESSION AND INPUT THIRD-ORDER INTERCEPT Preliminary Technical Data ADRF5040 45 70 40 65 60 35 55 30 IIP3 (dBm) 25 20 15 45 40 35 0.1dB COMPRESSION POINT 1dB COMPRESSION POINT 10 30 5 25 0.1 1 10 FREQUENCY (MHz) 100 1k 20 0.01 14290-025 0 0.01 50 Figure 25. Input Compression Point vs Frequency, VDD = 3.3 V, VSS = −3.3 V at TC = 25°C 0.1 1 10 FREQUENCY (MHz) 100 1k 14290-026 INPUT COMPRESSION (dBm) INPUT POWER COMPRESSION AND INPUT THIRD-ORDER INTERCEPT (10 kHz TO 1 GHz) Figure 26. Input Third-Order Intercept (IIP3) Point vs Frequency, VDD = 3.3 V, VSS = −3.3 V at TC = 25°C Rev. PrB | Page 11 of 14 ADRF5040 Preliminary Technical Data THEORY OF OPERATION The ADRF5040 requires a positive supply voltage applied to the VDD pin and a negative voltage supply applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. The ADRF5040 is controlled via two digital control voltages applied to the V1 pin and the V2 pin. A small value bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation. The ADRF5040 does not need any special power up sequencing and relative order to power up VDD and VSS supply is not important. The control signals V1 and V2 can be applied a voltage only after VDD is powered-up, in order not to forward bias and damage the internal ESD protection circuits. Also, turn on the RF signal when the device supply settles to a steady state. The ADRF5040 is internally matched to 50 Ω at the RF input port (RFC) and the RF output ports (RF1, RF2, RF3, and RF4); therefore, no external matching components are required. The RF1 through RF4 pins are dc-coupled, and dc blocking capacitors are required on the RF paths. The design is bidirectional; the input and outputs are interchangeable. Rev. PrB | Page 12 of 14 Preliminary Technical Data ADRF5040 APPLICATIONS INFORMATION EVALUATION PCB The evaluation PCB shown in Figure 27 is designed using proper RF circuit design techniques. Signal lines at the RF port have 50 Ω impedance, and the package ground leads and backside ground slug must be connected directly to the ground plane. The evaluation PCB is available from Analog Devices, Inc. upon request. RF1 RF2 V1 C6 J1 GND C1 U1 RFC VDD V2 RF4 RF3 VSS J3 14290-027 J2 600-00598-00-3 J5 THRU CAL J4 Figure 27. Evaluation PCB Table 7. Bill of Materials for Evaluation Board ADRF5040-EVALZ Item J1 to J5 TP1 to TP5 C1, C6 U1 PCB Description PC mount SMA RF connectors Through hole mount test points 100 pF capacitors, 0402 package ADRF5040 SP4T switch 600-00598-00-3 evaluation PCB, Rogers 4350 circuit board material Rev. PrB | Page 13 of 14 ADRF5040 Preliminary Technical Data OUTLINE DIMENSIONS Figure 28. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body, Very Thin Quad (CP-24-16) Dimensions shown in millimeters ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR14290-0-5/16(PrB) Rev. PrB | Page 14 of 14