Online Documentation Design Resources Sample & Buy Discussion High Isolation, Silicon SPDT, Nonrefective Switch, 9 kHz to 13.0 GHz HMC1118 Data Sheet GND RF1 GND 15 14 13 12 VDD 2 11 LS RFC 3 10 VCTRL GND 4 9 VSS 50Ω PACKAGE BASE GND 12961-001 8 GND 7 50Ω RF2 GND HMC1118 6 1 GND GND GND Nonreflective 50 Ω design Positive control: 0 V/3.3 V Low insertion loss: 0.68 dB at 8.0 GHz High isolation: 48 dB at 8.0 GHz High power handling 35 dBm through path 27 dBm terminated path High linearity 1 dB compression (P1dB): 37 dBm typical Input third-order intercept (IIP3): 62 dBm typical ESD rating: 2 kV human body model (HBM) 3 mm × 3 mm, 16-lead LFCSP package No low frequency spurious Settling time (0.05 dB margin of final RFOUT): 7.5 μs 16 FUNCTIONAL BLOCK DIAGRAM 5 FEATURES GND Product Overview Figure 1. APPLICATIONS Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Fiber optics and broadband telecommunications GENERAL DESCRIPTION The HMC1118 is a general-purpose, broadband, nonreflective single-pole, double-throw (SPDT) switch in a LFCSP surface mount package. Covering the 9 kHz to 13.0 GHz range, the switch offers high isolation and low insertion loss. The switch features >48 dB isolation, 0.68 dB insertion loss up to 8.0 GHz, and a 7.5 μs settling time of 0.05 dB margin of final RFOUT. The switch operates using positive control voltage logic lines of +3.3 V Rev. 0 and 0 V and requires +3.3 V and −2.5 V supplies. The HMC1118 can cover the same operating frequency range with a single positive supply voltage applied and the negative supply voltage (VSS) tied to ground and still maintaining good power handling performance. The HMC1118 is packaged in a 3 mm × 3 mm, surface mount LFCSP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com Product Overview Online Documentation Design Resources HMC1118 Discussion Sample & Buy Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Interface Schematics .....................................................................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................7 Revision History ............................................................................... 2 Input Compression Point and Input Third-Order Intercept ...8 Specifications..................................................................................... 3 Theory of Operation .........................................................................9 Electrical Specifications ............................................................... 3 Applications Information .............................................................. 10 Digital Control Voltages .............................................................. 4 Evaluation PCB ........................................................................... 10 Bias and Supply Current .............................................................. 4 Outline Dimensions ....................................................................... 11 Absolute Maximum Ratings ............................................................ 5 Ordering Guide .......................................................................... 11 ESD Caution .................................................................................. 5 REVISION HISTORY 10/15—Revision 0: Initial Version Rev. 0 | Page 2 of 11 Product Overview Design Resources Online Documentation Sample & Buy Discussion Data Sheet HMC1118 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VCTRL = 0 V/3.3 V dc, VDD = LS = 3.3 V dc, VSS = −2.5 V dc, TA = 25°C, 50 Ω system, unless otherwise specified. Table 1. Parameter INSERTION LOSS Test Conditions/Comments Min 9 kHz to 3.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 13.0 GHz Typ Max Unit 0.5 0.68 0.7 1.3 1.0 1.1 1.3 2.0 dB dB dB dB ISOLATION RFC TO RF1/RF2 (WORST CASE) 9 kHz to 3.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 13.0 GHz RETURN LOSS On State Off State 40 42 28 18 50 48 35 25 dB dB dB dB 9 kHz to 3.0 GHz 9 kHz to 8.0 GHz 9 kHz to 13.0 GHz 9 kHz to 3.0 GHz 9 kHz to 8.0 GHz 9 kHz to 13.0 GHz 26 22 9 26 14 5 dB dB dB dB dB dB 50% VCTRL to 0.05 dB margin of final RFOUT 50% VCTRL to 0.1 dB margin of final RFOUT 7.5 6 µs µs 10%/90% RF 50% VCTRL to 10%/90% RF 1 MHz to 13.0 GHz 0.85 2.7 µs µs 37 35 62 dBm dBm dBm RADIO FREQUENCY (RF) SETTLING TIME SWITCHING SPEED tRISE/tFALL tON/tOFF INPUT POWER 1 dB Compression (P1dB) 0.1 dB Compression (P0.1dB) INPUT THIRD-ORDER INTERCEPT (IIP3) RECOMMENDED OPERATING CONDITIONS 1 Positive Supply Voltage (VDD) Negative Supply Voltage (VSS) Control Voltage (VCTRL) Range Logic Select (LS) Voltage Range RF Input Power Through Path Termination Path Hot Switch Power Level Case Temperature Range (TCASE) 1 35 Two-tone input power = 14 dBm at each tone, 1 MHz to 13.0 GHz 3.0 −2.75 0 0 3.6 −2.25 VDD VDD V V V V +85 dBm dBm dBm °C VDD/VCTRL = 3.3 V, VSS = −2.5 V, TA = 85°C, frequency = 2 GHz 35 27 27 VDD = 3.3 V, TA = 85°C, frequency = 2 GHz −40 These are the recommended values for these parameters. Rev. 0 | Page 3 of 11 Online Documentation Product Overview Design Resources Discussion Sample & Buy HMC1118 Data Sheet DIGITAL CONTROL VOLTAGES VDD = 3.3 V ± 10%, VSS = −2.5 V ± 10%, TCASE = −40°C to +85°C, unless otherwise specified. Table 2. Parameter INPUT CONTROL VOLTAGE Low High Symbol Min VIL VIH −0.3 2.0 Typ Max Unit +0.8 VDD + 0.3 V V Test Condition/Comments <1 µA typical BIAS AND SUPPLY CURRENT Table 3. Parameter SUPPLY CURRENT VDD = 3.3 V VSS = −2.5 V Symbol IDD ISS Min Typ Max Unit 20 0.5 200 10 µA µA Rev. 0 | Page 4 of 11 Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet HMC1118 ABSOLUTE MAXIMUM RATINGS 4 Table 4. 0 POWER (dB) –4 –8 –12 –16 –24 0.01 −65°C to +150°C 260°C 135°C 0.1 1 10 100 Figure 3. Power Derating Through Path (Low Frequency Detail) 4 0 116°C/W 100°C/W 2 kV –4 For recommended operating conditions, see Table 1. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. –8 –12 –16 –20 –24 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 4. Power Derating for Hot Switching Power ESD CAUTION 4 0 –8 –12 –16 –20 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 9 10 12961-002 POWER (dB) –4 –24 1000 FREQUENCY (MHz) 12961-004 –20 Figure 2. Power Derating Through Path Rev. 0 | Page 5 of 11 10000 12961-003 1 Rating −0.3 V to +3.7 V dc −2.8 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V See Figure 2 to Figure 4 37 dBm 28 dBm 30 dBm POWER (dB) Parameter Positive Supply Voltage (VDD) Range Negative Supply Voltage (VSS) Range Control Voltage (VCTRL) Range Logic Select (LS) Voltage Range RF Input Power1 (VDD/VCTRL = 3.3 V, VSS = −2.5 V, TA = 85°C, Frequency = 2 GHz) Through Path Termination Path Hot Switch Power Level (VDD = 3.3 V, TA = 85°C, Frequency = 2 GHz) Storage Temperature Range Maximum Reflow Temperature (MSL3 Rating) Channel Temperature Thermal Resistance (Channel to Package Bottom) Through Path Terminated Path ESD Sensitivity (HBM), Class 2 Product Overview Design Resources Online Documentation Discussion Sample & Buy HMC1118 Data Sheet 12 VDD 11 LS 10 VCTRL 9 VSS GND RF1 GND 15 14 13 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PRINTED CIRCUIT BOARD (PCB). 12961-005 GND 8 4 GND GND 7 3 TOP VIEW (Not to Scale) RF2 RFC HMC1118 6 2 GND GND 5 1 GND GND 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 2, 4 to 6, 8, 13, 15, 16 Mnemonic GND 3 RFC 7 RF2 14 RF1 9 10 11 12 VSS VCTRL LS VDD EPAD Description Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF/dc ground. See Figure 6 for the GND interface schematic. RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. Negative Supply Voltage Pin. Control Input Pin. See Table 1, Table 2, and Table 6. Logic Select Input Pin. See Table 1, Table 2, and Table 6. Positive Supply Voltage Pin. Exposed Pad. The exposed pad must be connected to the RF/dc ground of the printed circuit board (PCB). Table 6. Truth Table LS High High Low Low Control Input VCTRL Low High Low High RFC to RF1 On Off Off On Signal Path State RFC to RF2 Off On On Off INTERFACE SCHEMATICS VDD 12961-006 LS Figure 8. LS Interface Schematic Figure 6. GND Interface Schematic 12961-007 VDD VCTRL 12961-008 GND Figure 7. VCTRL Interface Schematic Rev. 0 | Page 6 of 11 Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet HMC1118 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION 0 0 –20 ISOLATION (dB) –1 –2 –3 0 2 4 6 8 10 12 14 FREQUENCY (GHz) –50 –60 –80 Figure 9. Insertion Loss vs. Frequency 0 –90 RF1 RF2 0 2 4 6 8 10 12 14 FREQUENCY (GHz) Figure 11. Isolation Between RFC and the RF1 and RF2 Ports vs. Frequency 0 RF1, RF2 ON RFC RF1, RF2 OFF –10 –10 –20 ISOLATION (dB) –30 –20 –30 –40 –50 –60 –70 –40 –80 –90 0 2 4 6 8 10 12 FREQUENCY (GHz) 14 –100 RFC TO RF1 ON RFC TO RF2 ON 0 2 4 6 8 10 12 14 FREQUENCY (GHz) Figure 10. Return Loss vs. Frequency Figure 12. Isolation Between RF1 and RF2 Ports vs. Frequency Rev. 0 | Page 7 of 11 12961-012 –50 12961-011 RETURN LOSS (dB) –40 12961-010 –4 –30 –70 TA = +85°C TA = +25°C TA = –40°C 12961-009 INSERTION LOSS (dB) –10 Online Documentation Product Overview Design Resources Sample & Buy Discussion HMC1118 Data Sheet 40 40 38 35 INPUT COMPRESSION (dBm) 36 34 32 2 3 5 4 7 6 8 9 10 11 12 13 35 INPUT COMPRESSION (dBm) 38 36 34 32 2 3 4 5 6 7 9 8 10 11 12 13 FREQUENCY (GHz) 1000 25 20 0.1 1 10 100 1000 Figure 17. 1 dB Input Compression Point vs. Frequency over Temperature (Low Frequency Detail) 65 60 60 INPUT IP3 (dBm) 65 55 TA = +85°C TA = +25°C TA = –40°C FREQUENCY (MHz) Figure 14. 1 dB Input Compression Point vs. Frequency over Temperature 55 50 50 TA = +85°C TA = +25°C TA = –40°C 0 2 4 6 FREQUENCY (GHz) 8 10 12 45 0.1 12961-015 45 100 30 10 0.01 12961-014 1 10 15 TA = +85°C TA = +25°C TA = –40°C 0 1 Figure 16. 0.1 dB and 1 dB Input Compression Point vs. Frequency (Low Frequency Detail) 40 28 0.1 FREQUENCY (MHz) 40 30 0.1dB COMPRESSION POINT 1dB COMPRESSION POINT 12961-017 1 12961-013 0 10 0.01 Figure 13. 0.1 dB and 1 dB Compression Point vs. Frequency INPUT COMPRESSION (dBm) 20 12961-016 0.1dB COMPRESSION POINT 1dB COMPRESSION POINT FREQUENCY (GHz) INPUT IP3 (dBm) 25 15 30 28 30 TA = +85°C TA = +25°C TA = –40°C 1 10 FREQUENCY (MHz) Figure 15. Input Third-Order Intercept (IIP3) Point vs. Frequency over Temperature 100 1000 12961-018 INPUT COMPRESSION (dBm) INPUT COMPRESSION POINT AND INPUT THIRD-ORDER INTERCEPT Figure 18. Input Third-Order Intercept (IIP3) Point vs. Frequency over Temperature (Low Frequency Detail) Rev. 0 | Page 8 of 11 Design Resources Online Documentation Product Overview Data Sheet Discussion Sample & Buy HMC1118 THEORY OF OPERATION The HMC1118 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. The HMC1118 can operate with a single positive supply voltage applied to the VDD pin and the negative voltage input pin (VSS) connected to ground; however, some performance degradations in the input power compression and third-order intercept can occur. The HMC1118 is controlled via two digital control voltages applied to the VCTRL pin and the LS pin. A small value bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation. The HMC1118 is internally matched to 50 Ω at the RF input port (RFC) and the RF output ports (RF1 and RF2); therefore, no external matching components are required. The RF1 and RF2 pins are dc-coupled, and dc blocking capacitors are required on the RF paths if the RF potential is not equal to a commonmode voltage of 0 V. The design is bidirectional; the input and outputs are interchangeable. The logic select (LS) allows the user to define the control input logic sequence for the RF path selections. With the LS pin set to logic high, the RFC to RF1 path turns on when VCTRL is logic low, and the RFC to RF2 path turns on when VCTRL is logic high. With LS set to logic low, the RFC to RF1 path turns on when VCTRL is logic high, and the RFC to RF2 path turns on when VCTRL is logic low. Depending on the logic level applied to the LS and VCTRL pins, one RF output port (for example, RF1) is set to on mode, by which an insertion loss path provides the input to the output. The other RF output port (for example, RF2) is then set to off mode, by which the output is isolated from the input. When the RF output port (RF1 or RF2) is in isolation mode, internally terminate it to 50 Ω, and the port absorbs the applied RF signal (see Table 7). The ideal power-up sequence is as follows: 1. 2. 3. 4. Power up GND. Power up VDD and VSS. The relative order is not important. Power up the digital control inputs. The relative order of the logic control inputs is not important. Powering the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures. Power up the RF input. Table 7. Switch Mode Operation Digital Control Inputs LS VCTRL High Low High High Low Low Low High Signal Mode RFC to RF2 Off mode. The RF2 port is isolation from the RFC port and internally terminated to a 50 Ω load to absorb the applied RF signals. Off mode. The RF1 port is isolation from the RFC On mode. A low insertion loss path from the RFC port to the port and internally terminated to a 50 Ω load to RF2 port. absorb the applied RF signals. Off mode. The RF1 port is isolation from the RFC On mode. A low insertion loss path from the RFC port to the port and internally terminated to a 50 Ω load to RF2 port. absorb the applied RF signals. On mode. A low insertion loss path from the RFC Off mode. The RF2 port is isolation from the RFC port and internally terminated to a 50 Ω load to absorb the applied port to the RF1 port. RF signals. RFC to RF1 On mode. A low insertion loss path from the RFC port to the RF1 port. Rev. 0 | Page 9 of 11 Product Overview Design Resources Online Documentation Discussion HMC1118 Sample & Buy Data Sheet APPLICATIONS INFORMATION EVALUATION PCB 12961-019 Generate the evaluation PCB used in this application with proper RF circuit design techniques. Signal lines at the RF port must have 50 Ω impedance, and the package ground leads and backside ground slug must be connected directly to the ground plane similarly to what is shown in Figure 19. The evaluation board shown in Figure 19 is available from Analog Devices, Inc. upon request. Figure 19. EV1HMC1118LP3D Evaluation PCB Table 8. Bill of Materials for the EV1HMC1118LP3D Evaluation Board1 Item J1 to J3 TP1 to TP5 C1, C5 U1 PCB 1 2 Description PC mount SMA RF connectors Through-hole hold mount test points 100 pF capacitors, 0402 package HMC1118 SPDT switch 600-01012-00-1 evaluation PCB, Rogers 4350 circuit board material Reference this number to order the full evaluation PCB. The blank cells in the manufacturer column are left blank intentionally for they are user-selectable. Rev. 0 | Page 10 of 11 Manufacturer2 Analog Devices, Inc. EV1HMC1118LP3D, Analog Devices, Inc.1 Product Overview Online Documentation Design Resources Sample & Buy Discussion Data Sheet HMC1118 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.25 0.20 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 1.92 1.70 SQ 1.48 EXPOSED PAD 9 TOP VIEW 0.95 0.85 0.75 *0.35 0.30 0.25 4 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-000000 SEATING PLANE 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4 WITH THE EXCEPTION OF PACKAGE EDGE TO LEAD EDGE. 01-08-2015-A 3.10 3.00 SQ 2.90 Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-38) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC1118LP3DE Temperature Range −40°C to +85°C MSL Rating2 MSL3 Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP] Package Option CP-16-38 HMC1118LP3DETR −40°C to +85°C MSL3 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-38 EV1HMC1118LP3D Evaluation Board 1 HMC1118LP3DE and HMC1118LP3DETR are RoHS-Compliant Parts. See the Absolute Maximum Ratings section. 3 XXXX is the 4-digit lot number. 2 ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12961-0-10/15(0) Rev. 0 | Page 11 of 11 Branding3 H1118 XXXX H1118 XXXX