89LV1632 16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM 16 Megabit (512k x 32-bit) SRAM MCM CS 1-4 Address OE, WE Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM I/O 8-15 I/O 16-23 I/O 24-31 Ground 89LV1632 MCM Memory I/O 0-7 Logic Diagram FEATURES: DESCRIPTION: • Four 512k x 8 SRAM die • RAD-PAK® Technology radiation-hardend against natural space radiation • Total dose hardness: - > 100 krad (Si), depending upon space mission • Excellent Single Event Effects: - SEL > 68 MeV-cm2/mg - SEU threshold = 3 MeV-cm2/mg - SEU saturated cross section: 6E-9 cm2/bit • Package: 68-pin quad flat package • Completely static memory - no clock or timing strobe required • Fast Access Time: • -20, 25, 30 ns Access Times • Internal bypass capacitor • High-speed silicon-gate CMOS Technology • 3.3 V ± 10% power supply • Equal address and chip enable access times • Three-state outputs • All inputs and outputs are TTL compatible Maxwell Technologies’ 89LV1632 high-performance 16 Megabit Multi-Chip Module (MCM) Static Random Access Memory features a greater than 100 krad(Si) total dose tolerance, depending upon space mission. The four 4-Megabit SRAM die and bypass capacitors are incorporated into a high-reliable hermetic quad flat-pack ceramic package. With high-performance silicon-gate CMOS technology, the 89LV1632 reduces power consumption and eliminates the need for external clocks or timing strobes. It is equipped with output enable (OE) and four byte chip enables (CS1 - CS4) inputs to allow greater system flexibility. When OE input is high, the output is forced to high impedance. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package.It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. In a GEO orbit, RAD-PAK® packaging provides greater than 100 krad(Si) total radiation dose tolerance. This product is available with screening up to Maxwell Technologies selfdefined Class K. 11.02.15 Rev 5 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com All data sheets are subject to change without notice 1 ©2015 Maxwell Technologies. All rights reserved. 89LV1632 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM TABLE 1. PINOUT DESCRIPTION PIN SYMBOL DESCRIPTION 34-28, 42-36, 62-64, 7, 8 A0-A18 65 WE WriteEnable 66 OE Output Enable 3-6 CS1 - CS4 Chip Enable 43-46, 48-51,53-56, 58-61, 9-12, 14-17, 19-22, 24-27 I/O0-I/O31 Data Input/Output 2, 67, 68 NC No Connection 1, 18, 35, 52 VCC +3.3V Power Supply 13, 23, 47, 57 VSS Ground Address Enable Memory TABLE 2. 89LV1632 ABSOLUTE MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS = 0V) PARAMETER Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC SYMBOL MIN MAX UNITS VCC -0.5 +4.6 V VIN, VOUT -0.5 VCC+0.5 V 42 Grams 3.6 °C/W Weight Thermal Resistance TJC Power Dissipation PD -- 4.0 W Operating Temperature TA -55 +125 °C Storage Temperature TS -65 +150 °C TABLE 3. 89LV1632 RECOMMENDED OPERATING CONDITIONS (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER SYMBOL MIN MAX UNITS Supply Voltage, (Operating Voltage Range) VCC 3.0 3.6 V Input High Voltage VIH 2.2 VCC + 0.5 (1) V Input Low Voltage VIL -0.5 (2) 0.8 V 1. VIH (max) = VCC + 2V ac (pulse width < 10ns) for I < 80 mA. 2. VIL (min) = -2.0V ac; (pulse width < 20 ns) for I < 80 mA. 11.02.15 Rev 5 All data sheets are subject to change without notice 2 ©2015 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 TABLE 4. 89LV1632 DELTA LIMITS PARAMETER VARIATIONL ICC +10% of stated value in table 5 ISB +10% of stated value in table 5 ISB1 +10% of stated value in table 5 ILI +10% of stated value in table 5 TABLE 5. 89LV1632 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER SYMBOL TEST CONDITIONS SUBGROUPS MIN TYP MAX UNITS Input Leakage Current ILI VIN = 0 to VCC 1, 2, 3 -8.0 -- +8.0 uA Output Leakage Current ILO CS = VIH, VOUT = VSS to VCC 1, 2, 3 -8.0 -- +8.0 uA Operating Current : -20 -25 -30 ICC Min. Cycle, 100% Duty, CS = VIL, IOUT = 0 mA VIN = VIH or VIL 1, 2, 3 - - 330 320 310 Standby Power Supply Current ISB CS= VIH, Min Cycle 1, 2, 3 -- -- 240 mA CMOS Standby Power Supply Current ISB1 CS > VCC - 0.2V, f = 0 MHz, VIN > VCC - 0.2V or VIN < 0.2V 1, 2, 3 -- -- 40 mA Output Low Voltage VOL IOL = + 8.0 mA 1, 2, 3 -- -- 0.4 V Output High Voltage VOH IOH = -4.0 mA 1, 2, 3 2.4 -- -- V Input Capacitance1 CS1 - CS4, OE, WE I/O0-7, I/O8-15, I/O16-23, I/O24-31 A0 - A18 CIN VIN = 0 V 4, 5, 6 COUT VI/O = 0 V 4, 5, 6 Memory Output Capacitance1 mA pF 7 28 7 7 32 8 pF 1. Guaranteed by design. TABLE 6. 89LV1632 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER MIN TYP MAX UNITS Input Pulse Level 0.0 -- 3.0 V 11.02.15 Rev 5 All data sheets are subject to change without notice 3 ©2015 Maxwell Technologies. All rights reserved. 89LV1632 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM TABLE 6. 89LV1632 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER MIN TYP MAX UNITS Output Timing Measurement Reference Level -- -- 1.5 V Input Rise/Fall Time -- -- 3.0 ns Input Timing Measurement Reference Level -- -- 1.5 V TABLE 7. 89LV1632 AC CHARACTORISTICS FOR READ CYCLE (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER SYMBOL SUBGROUPS Read Cycle Time -20 -25 -30 tRC 9, 10, 11 Address Access Time -20 -25 -30 tAA 9, 10, 11 Chip Select Access Time -20 -25 -30 tCO 9, 10, 11 Output Enable to Output Valid -20 -25 -30 tOE 9, 10, 11 Chip Enable to Low-Z Output -20 -25 -30 tOLZ 9, 10, 11 Output Enable to Low-Z Output -20 -25 -30 tLZ 9, 10, 11 Chip Enable Deselect to High-Z Output -20 -25 -30 tOHZ 9, 10, 11 Output Enable Deselect to High-Z Output -20 -25 -30 tHZ 9, 10, 11 TYP MAX 20 25 30 ---- ---- ---- ---- 20 25 30 ---- ---- 20 25 30 ---- ---- 10 12 14 ---- 3 3 3 ---- ---- 0 0 0 ---- ---- 5 6 8 ---- ---- 5 6 8 ---- UNITS ns ns Memory 11.02.15 Rev 5 MIN ns ns ns ns ns ns All data sheets are subject to change without notice 4 ©2015 Maxwell Technologies. All rights reserved. 89LV1632 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM TABLE 7. 89LV1632 AC CHARACTORISTICS FOR READ CYCLE (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER SYMBOL SUBGROUPS Output Hold from Address Change -20 -25 -30 tOH 9, 10, 11 Chip Select to Power Up Time -20 -25 -30 TPU 9, 10, 11 Chip Select to Power DownTime -20 -25 -30 TPD 9, 10, 11 MIN TYP MAX 3 5 6 ---- ---- ---- 0 0 0 ---- ---- 10 15 20 ---- UNITS ns ns ns CS WE OE MODE I/O PIN SUPPLY CURRENT H X1 X1 Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L X1 Write DIN ICC L Memory TABLE 8. 89LV1632 FUNCTIONAL DESCRIPTION 1. X = don’t care. TABLE 9. 89LV1632 AC CHARACTORISTICS FOR WRITE CYCLE (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER SYMBOL SUBGROUPS Write Cycle Time -20 -25 -30 tWC 9, 10, 11 Chip Select to End of Write -20 -25 -30 tCW 9, 10, 11 Address Set-up Time -20 -25 -30 tAS 9, 10, 11 11.02.15 Rev 5 MIN TYP MAX 20 25 30 ---- ---- 14 15 17 ---- ---- 0 0 0 ---- ---- UNITS ns ns ns All data sheets are subject to change without notice 5 ©2015 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 TABLE 9. 89LV1632 AC CHARACTORISTICS FOR WRITE CYCLE (VCC = 3.3+ 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED) PARAMETER SUBGROUPS Address Valid to End of Write -20 -25 -30 tAW 9, 10, 11 Write Pulse Width (OE High) -20 -25 -30 tWP 9, 10, 11 Write Pulse Width (OE Low) -20 -25 -30 tWP1 9, 10, 11 Write Recovery Time -20 -25 -30 tWR 9, 10, 11 Write to Output High-Z -20 -25 -30 tWHZ 9, 10, 11 Data to Write Time Overlap -20 -25 -30 tDW 9, 10, 11 Data Hold from Write Time -20 -25 -30 tDH 9, 10, 11 End Write to Output Low-Z -20 -25 -30 tOW 9, 10, 11 11.02.15 Rev 5 MIN TYP MAX 14 15 17 ---- ---- 14 15 17 ---- ---- 20 25 30 ---- ---- 0 0 0 ---- ---- ---- 5 5 6 --- 9 10 11 ---- ---- 0 0 0 ---- ---- ---- 6 7 8 ---- UNITS ns ns ns ns Memory SYMBOL ns ns ns ns All data sheets are subject to change without notice 6 ©2015 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 FIGURE 1. AC TEST LOADS + 3.3V Memory FIGURE 2. TIMING WAVEFORM OF READ CYCLE (1) (ADDRESS CONTROLLED) FIGURE 3. TIMING WAVEFORM OF READ CYCLE (2) (WE = VIH) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 11.02.15 Rev 5 All data sheets are subject to change without notice 7 ©2015 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage conditions, tHZ (max) is less than tLZ (min) both for a given device and from device to device. 5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE (1) (OE CLOCK) Memory FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (2) (OE LOW FIIXED) 11.02.15 Rev 5 All data sheets are subject to change without notice 8 ©2015 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3) (CS CONTROLLED) 1. All write cycle timing is referenced from the last valid address to the first transition address. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10.When CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11.02.15 Rev 5 All data sheets are subject to change without notice 9 ©2015 Maxwell Technologies. All rights reserved. Memory 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low. A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 Memory 68 PIN RAD-PAK® QUAD FLAT PACKAGE DIMENSION SYMBOL MIN NOM MAX A 0.206 0.225 0.244 b 0.015 0.017 0.018 c 0.008 0.009 0.12 D 1.479 1.494 1.509 D1 0.800 e 0.050 BSC S1 -- 0.339 -- F1 1.239 1.244 1.249 F2 1.429 1.434 1.439 L 2.485 2.510 2.545 L1 2.485 2.500 2.505 L2 1.690 1.700 1.710 A1 0.180 0.195 0.210 N 68 Note: All dimensions in inches 11.02.15 Rev 5 All data sheets are subject to change without notice 10 ©2015 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 11.02.15 Rev 5 All data sheets are subject to change without notice 11 ©2015 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 Product Ordering Options Model Number 89LV1632 RP Q X -XX Feature Option Details 20 = 20 ns 25 = 25 ns 30 = 30 ns Screening Flow Multi Chip Module (MCM)1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing at-55°C, +25°C, +125°C) E = Engineering (testing at +25°C) Package Q = Quad Flat Pack Radiation Feature RP = RAD-PAK® Package Base Product Nomenclature 16 Megabit (512K x 32-Bit) MCM SRAM Memory Access Time 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows. 11.02.15 Rev 5 All data sheets are subject to change without notice 12 ©2015 Maxwell Technologies. All rights reserved.