89C1632 - 5.0V SRAM, 16 Mb (512kb x 32) - Obsolete

89C1632
16 Megabit (512K x 32-Bit)
MCM SRAM
16 Megabit (512k x 32-bit) SRAM MCM
CS 1-4
Address
OE, WE
Power
4Mb SRAM
4Mb SRAM
4Mb SRAM
4Mb SRAM
I/O 8-15
I/O 16-23
I/O 24-31
Ground
MCM
Memory
I/O 0-7
Logic Diagram
FEATURES:
DESCRIPTION:
• Four 512k x 8 SRAM architecture
• RAD-PAK® technology hardens against natural space radiation technology
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
- SEL > 101MeV-cm2/mg
- SEU threshold = 3 MeV-cm2/mg
- SEU saturated cross section: 6E-9 cm2/bit
• Package: 68-pin quad flat package
• Fast access time: 20, 25 and 30 ns
• Completely static memory - no clock or timing strobe
required
• Internal bypass capacitor
• High-speed silicon-gate CMOS technology
• 5V or 3V ± 10% power supply
• Equal address and chip enable access times
• Three-state outputs
• All inputs and outputs are TTL compatible
Maxwell Technologies’ 89C1632 high-performance 16 Megabit Multi-Chip Module (MCM) Static Random Access Memory
features a greater than 100 krad (Si) total dose tolerance,
depending upon space mission. The four 4-Megabit SRAM die
and bypass capacitors are incorporated into a high-reliable
hermetic quad flat-pack ceramic package. With high-performance silicon-gate CMOS technology, the 89C1632 reduces
power consumption and eliminates the need for external
clocks or timing strobes. It is equipped with output enable
(OE) and four byte enable (CS1 - CS4) inputs to allow greater
system flexibility. When OE input is high, the output is forced
to high impedance.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. In a GEO orbit, RAD-PAK provides true greater than 100
krad (Si) total radiation dose tolerance, dependent upon space
mission. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a
space mission. This product is available with screening up to
Maxwell Technologies self-defined Class K.
01.10.05 Rev 3
(619) 503-3300 - Fax: (619) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice
1
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
TABLE 1. PINOUT DESCRIPTION
PIN
SYMBOL
DESCRIPTION
34-28, 42-36, 62-64, 7, 8
A0-A18
65
WE
WriteEnable
66
OE
Output Enable
3-6
CS1 - CS4
Chip Enable
43-46, 48-56, 58-61, 9-12,
14-17, 19-22, 24-27
I/O0-I/O31
Data Input/Output
2, 67, 68
NC
No Connection
1, 18, 35, 52
VCC
+5V Power Supply
13, 23, 47, 57
VSS
Ground
Address Enable
Memory
TABLE 2. 89C1632 ABSOLUTE MAXIMUM RATINGS
(VOLTAGE REFERENCED TO VSS = 0V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
VCC
-0.5
+7.0
V
VIN, VOUT
-0.5
VCC+0.5
V
Power Dissipation
PD
--
4.0
W
Operating Temperature
TA
-55
+125
°C
Storage Temperature
TS
-65
+150
°C
UNITS
Power Supply Voltage Relative to VSS
Voltage Relative to VSS for Any Pin Except VCC
TABLE 3. 89C1632 RECOMMENDED OPERATING CONDITIONS
(VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED)
PARAMETER
Supply Voltage, (Operating Voltage Range)
SYMBOL
MIN
MAX
VCC
4.5
5.5
Input High Voltage
VIH
2.2
Input Low Voltage
VIL
-0.5 (2)
VCC + 0.5
0.8
V
(1)
V
V
1. VIH (max) = VCC + 2V ac (pulse width < 10ns) for I < 80 mA.
2. VIL (min) = -2.0V ac; (pulse width < 20 ns) for I < 80 mA.
TABLE 4. 89C1632 DELTA LIMITS
PARAMETER
VARIATIONL
ICC
+10% of stated value in table 5
01.10.05 Rev 3
All data sheets are subject to change without notice
2
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
TABLE 4. 89C1632 DELTA LIMITS
PARAMETER
VARIATIONL
ISB
+10% of stated value in table 5
ISB1
+10% of stated value in table 5
ILI
+10% of stated value in table 5
TABLE 5. 89C1632 DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED)
SYMBOL TEST CONDITIONS
PARAMETER
SUBGROUPS
MIN
TYP
MAX
UNITS
Input Leakage Current
ILI
VIN = 0 to VCC
1, 2, 3
-8.0
--
+8.0
uA
Output Leakage Current
ILO
CS = VIH, VOUT = VSS to VCC
1, 2, 3
-8.0
--
+8.0
uA
Average Operating Current
Cycle Time:
20 ns
25 ns
30 ns
ICC
Min. Cycle, 100% Duty, CS = VIL,
IOUT = 0 mA
VIN = VIH or VIL
1, 2, 3
Standby Power Supply Current
ISB
CS= VIH, cycle time > 25ns
1, 2, 3
--
--
240
mA
CMOS Standby Power Supply
Current
ISB1
CS > VCC - 0.2V, f = 0 MHz, VIN >
VCC - 0.2V or
VIN < 0.2V
1, 2, 3
--
--
60
mA
Output Low Voltage
VOL
IOL = + 8.0 mA
1, 2, 3
--
--
0.4
V
Output High Voltage
VOH
IOH = -4.0 mA
1, 2, 3
2.4
--
--
V
Input
CS1 - CS4,
OE, WE
I/O0-7, I/O8-15, I/O16-23,
I/O24-31
CIN
Input / Output Capacitance1
COUT
----
VIN = 0 V
mA
800
760
720
pF
1, 2, 3
7
28
7
1, 2, 3
VI/O = 0 V
Memory
Capacitance1
--
4, 5, 6
8
pF
1. Guaranteed by design.
TABLE 6. 89C1632 AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED)
PARAMETER
MIN
TYP
MAX
UNITS
Input Pulse Level
0.0
--
3.0
V
Output Timing Measurement Reference Level
--
--
1.5
V
Input Rise/Fall Time
--
--
3.0
ns
01.10.05 Rev 3
All data sheets are subject to change without notice
3
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
TABLE 6. 89C1632 AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED)
PARAMETER
Input Timing Measurement Reference Level
MIN
TYP
MAX
UNITS
--
--
1.5
V
TABLE 7. 89C1632 READ CYCLE
(VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
SUBGROUPS
Read Cycle Time
-20
-25
-30
tRC
9, 10, 11
Address Access Time
-20
-25
-30
tAA
Chip Select to Output
-20
-25
-30
tCO
Output Enable to Output
-20
-25
-30
tOE
Output Enable to Low-Z Output
-20
-25
-30
tOLZ
Chip Enable to Low-Z Output
-20
-25
-30
tLZ
Output Disable to High-Z Output
-20
-25
-30
tOHZ
Chip Disable to High-Z Output
-20
-25
-30
tHZ
Output Hold from Address Change
-20
-25
-30
tOH
MIN
TYP
MAX
20
25
30
----
----
----
----
20
25
30
----
----
20
25
30
----
----
10
12
14
----
0
0
0
----
----
3
3
3
----
----
5
6
8
----
----
5
6
8
----
3
3
3
----
----
ns
ns
9, 10, 11
Memory
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
01.10.05 Rev 3
UNITS
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
TABLE 8. 89C1632 FUNCTIONAL DESCRIPTION
CS
WE
OE
MODE
I/O PIN
SUPPLY CURRENT
H
X1
X1
Not Select
High-Z
ISB, ISB1
L
H
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
L
L
X1
Write
DIN
ICC
1. X = don’t care.
TABLE 9. 89C1632 WRITE CYCLE
(VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED)
PARAMETER
SUBGROUPS
Write Cycle Time
-20
-25
-30
tWC
9, 10, 11
Chip Select to End of Write
-20
-25
-30
tCW
Address Set-up Time
-20
-25
-30
tAS
Address Valid to End of Write
-20
-25
-30
tAW
Write Pulse Width (OE High)
-20
-25
-30
tWP
Write Pulse Width (OE Low)
-20
-25
-30
tWP1
Write Recovery Time
-20
-25
-30
tWR
MIN
TYP
MAX
ns
20
25
30
----
14
17
20
----
0
0
0
----
14
17
20
----
14
17
20
----
20
25
30
----
0
0
0
----
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
ns
9, 10, 11
01.10.05 Rev 3
UNITS
Memory
SYMBOL
All data sheets are subject to change without notice
5
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
TABLE 9. 89C1632 WRITE CYCLE
(VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED)
PARAMETER
SUBGROUPS
Write to Output High-Z
-20
-25
-30
tWHZ
9, 10, 11
Data to Write Time Overlap
-25
-30
tDW
Data Hold from Write Time
-20
-25
-30
tDH
End Write to Output Low-Z
-20
-25
-30
tOW
MIN
TYP
MAX
----
5
7
9
----
ns
ns
9, 10, 11
10
12
14
----
0
0
0
----
ns
9, 10, 11
ns
9, 10, 11
----
01.10.05 Rev 3
UNITS
3
3
3
----
All data sheets are subject to change without notice
Memory
SYMBOL
6
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
FIGURE 1. AC TEST LOADS
Memory
FIGURE 2. TIMING WAVEFORM OF READ CYCLE (1) (ADDRESS CONTROLLED)
FIGURE 3. TIMING WAVEFORM OF READ CYCLE (2) (WE = VIH)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
01.10.05 Rev 3
All data sheets are subject to change without notice
7
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage conditions, tHZ (max) is less than tLZ (min) both for a given device and from device to
device.
5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS = VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE (1) (OE CLOCK)
Memory
FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (2) (OE LOW FIIXED)
01.10.05 Rev 3
All data sheets are subject to change without notice
8
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3) (CS CONTROLLED)
1. All write cycle timing is referenced from the last valid address to the first transition address.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write
cycle.
8. If CS foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10.When CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not
be applied.
01.10.05 Rev 3
All data sheets are subject to change without notice
9
©2005 Maxwell Technologies.
All rights reserved.
Memory
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low.
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end
of write.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
FIGURE 7. SRAM HEAVY ION CROSS SECTION
Memory
FIGURE 8. SRAM PROTON SEU CROSS SECTION STATIC
01.10.05 Rev 3
All data sheets are subject to change without notice
10
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
Memory
68 PIN RAD-PAK® QUAD FLAT PACKAGE
DIMENSION
SYMBOL
MIN
NOM
MAX
A
0.206
0.225
0.244
b
0.015
0.017
0.018
c
0.008
0.009
0.12
D
1.479
1.494
1.509
D1
0.800
e
0.050 BSC
S1
--
0.339
--
F1
1.239
1.244
1.249
F2
1.429
1.434
1.439
L
2.485
2.510
2.545
L1
2.485
2.500
2.505
L2
1.690
1.700
1.710
A1
0.180
0.195
0.210
N
68
Q68-04
Note: All dimensions in inches
01.10.05 Rev 3
All data sheets are subject to change without notice
11
©2005 Maxwell Technologies.
All rights reserved.
16 Megabit (512K x 32-Bit) MCM SRAM
89C1632
Important Notice:
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
Memory
01.10.05 Rev 3
All data sheets are subject to change without notice
12
©2005 Maxwell Technologies.
All rights reserved.
89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
Product Ordering Options
Model Number
89C1632 RP
Q
X
-XX
Option Details
Feature
20 = 20 ns
25 = 25 ns
30 = 30 ns
Screening Flow
Multi Chip Module (MCM)1
K = Maxwell Self-Defined Class K
H = Maxwell Self-Defined Class H
I = Industrial (testing
@ -55°C, +25°C, +125°C)
E = Engineering (testing @ +25°C)
Package
Q = Quad Flat Pack
Radiation Feature
RP = RAD-PAK® package
Base Product
Nomenclature
16 Megabit (512K x 32-Bit) MCM
SRAM
Memory
Access Time
1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K.
01.10.05 Rev 3
All data sheets are subject to change without notice
13
©2005 Maxwell Technologies.
All rights reserved.
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