UM1839
User manual
EVALSTGAP1S: demonstration board for STGAP1S galvanically
isolated single gate driver
Introduction
The STGAP1S gapDRIVE™ is a galvanically isolated single gate driver for N-channel
MOSFETs and IGBTs with advanced protection, configuration and diagnostic features. The
architecture of the STGAP1S isolates the channel from the control and the low voltage
interface circuitry through a true galvanic isolation.
The EVALSTGAP1S board allows evaluating all of the STGAP1S features while driving
a power switch with a voltage rating up to 1500 V. Power switches in both TO-220 and
TO-247 packages can be evaluated, and the board allows the connection of a heatsink in
order to exploit the ability of the STGAP1S to handle very high power applications.
In combination with the STEVAL-PCC009V2 communication board and the gapDRIVE™
evaluation software, the board allows to easily enable, configure or disable all of the driver's
protection and control features through the SPI interface. Advanced diagnostic is also
available thanks to the driver's status registers that can be accessed through the SPI.
Multiple boards can be connected together and share the same logic supply voltage and
control signals in order to evaluate half bridge, interleaved or even more complex
topologies. The board allows implementing the SPI daisy chain when more than one device
is used.
Figure 1. EVALSTGAP1S demonstration board
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Contents
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Contents
1
Hardware description and configuration . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Connection of two EVALSTGAP1S boards . . . . . . . . . . . . . . . . . . . . . . . 6
3
Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
4
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Using EVALSTGAP1S in standalone mode . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1
Check list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.2
EVALSTGAP1S board setup example . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3
EVALSTGAP1S board in standalone mode . . . . . . . . . . . . . . . . . . . . . . 10
3.1.4
EVALSTGAP1S default parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Using EVALSTGAP1S with STEVAL-PCC009V2 and STGAP1S
evaluation software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.1
Check list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2
Single EVALSTGAP1S board setup example . . . . . . . . . . . . . . . . . . . . 11
3.2.3
Connection to STEVAL-PCC009V2 interface board . . . . . . . . . . . . . . . 12
3.2.4
Using two EVALSTGAP1S boards in daisy chain configuration . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Hardware description and configuration
Hardware description and configuration
The STGAP1S features an SPI interface that is used to set the device parameters, enable
or disable the device functions and for advanced diagnostic. However for an easy device
evaluation it is also possible to operate the STGAP1S without using the SPI interface. In this
case the driver works with default configuration values and protections. For more details
refer to Section 3.1: Using EVALSTGAP1S in standalone mode on page 10.
Table 1. STGAP1S electrical specifications
Symbol
Parameter
Min.
Max.
(2)
VH
Positive supply voltage (VH vs. GNDISO)
4.5(1)
VL
Negative supply voltage (VL vs. GNDISO)
GNDISO - 10(3)
VHL
VDD
Differential supply voltage (VH vs. VL)
Integrated 3.3 V voltage regulator input voltage vs.
GND
VLOGIC
Logic pins voltage vs. GND
VIORM
Maximum working voltage across isolation
20
V
GNDISO
V
36
V
4.5
5.5(4)
3
3.6(5)
Vcollector Maximum COLLECTOR-GNDISO voltage
Unit
V
VDD + 0.3
V
1500
V
1200(6)
V
1. When UVLO is enabled this value is VHon_max.
2. This value is limited by maximum gate-source voltage of Q1.
3. When UVLO is enabled this value is VLon_max.
4. When JP6 = OPEN (VDD is not connected to VREG pin, refer to STGAP1S DS).
5. When JP6 = CLOSED (VDD is connected to VREG pin, refer to STGAP1S DS).
6. This value is limited by the voltage rating of Q1 and D5.
Table 2. Connector descriptions
Name
Type
Function
J1
Board extension connector Used to connect an optional slave EVALSTGAP1S board.
J2
Power supply connector
Used to feed supply voltage VH and optional negative supply
voltage VL to the gate driving side.
J3
Control signals connector
Used for control (logic inputs and fault signals interfacing).
J4
Control signals connector
Used for the STGAP1S SPI and diagnostic interfacing.
Connector is suitable for interfacing to the
STEVAL-PCC009V2 universal interface board.
J5
Board extension connector
Used to connect the master EVALSTGAP1S board in 2-board
configuration.
J6
Power supply connector
Used to feed supply voltage VDD to the logic control side.
C plate Load connection
A plate hole for the load current input path (IGBT collector).
E plate
A plate hole for the load current output path (IGBT emitter).
Load connection
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Hardware description and configuration
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In applications requiring galvanic isolation, VH and VL must be generated by an isolated
power supply. If a power supply with suitable isolation is not available the gate driver's
supply voltages can be provided through a battery. In case the evaluation of driver's
performance does not require galvanic isolation, any power supply with suitable functional
isolation may be used.
Figure 2. Jumper and connector locations - top side
Figure 3. Jumper locations - bottom side
JP7
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Hardware description and configuration
Table 3. Jumper descriptions
Name
Type
Function
JP1, JP2 Configuration jumpers IN- and IN+ sharing in 2-board configuration.
JP3
Configuration jumper
For SPI daisy chaining in 2-board configuration.
JP4
Configuration jumper
To feed the STGAP1S with VDD voltage coming from the µC
board.
JP5
Configuration jumper
To connect VL and GNDISO if an optional negative power supply
VL is not used.
JP6
Configuration jumper
To connect VDD and Vreg when working with VDD = 3.3 V.
JP7
Configuration jumper
To bypass shunt resistors when SENSE is not used.
Table 4. Jumper configurations for VDD power supply(1)
.
Operating voltage
Supply voltage source
Jumper configurations
VDD = 5 V
External power supply
(from J6)
JP4 = OPEN
JP6 = OPEN
VDD = 3.3 V
External power supply
(from J6)
JP4 = OPEN
JP6 = CLOSED
VDD = 3.3 V
µC supply voltage
(from J4)
JP4 = CLOSED
JP6 = CLOSED
1. Input signals logic levels shall be coherent with VDD voltage (3.3\5 V).
Table 5. Jumper configurations for VL power supply
Operating voltage
Supply voltage source
-10 V ≤ VL < 0 V
VL not used
Jumper configurations
External power supply (J2)
JP5 = OPEN
VL = GNDISO
JP5 = CLOSED
Table 6. Jumper configurations for SPI and input signals settings
(single EVALSTGAP1S)
Name
Function
Jumper configurations
JP1
IN+ connection to the optional slave
EVALSTGAP1S
DON'T CARE
JP2
IN-/DIAG2 connection to the optional
slave EVALSTGAP1S
DON'T CARE
JP3
Connects the SDO to the µC
CLOSED
Table 7. Jumper configurations for SENSE
SENSE function
Jumper configurations
Used
JP7 = OPEN
Not used
JP7 = CLOSED(1)
1. This configuration is preferred (but not mandatory) to avoid dissipating power on shunt resistors.
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Connection of two EVALSTGAP1S boards
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Connection of two EVALSTGAP1S boards
It is possible to connect two EVALSTGAP1S boards through connectors J1 and J5: the
lower board (master) shall be connected to the µC and the other one (slave) is configured
through the daisy chain connection of the SPI bus.
Figure 4. Relevant jumper and connector locations for 2-board configuration
Connecting two EVALSTGAP1S boards allows implementing independent, half bridge, or
interleaved configuration of power switches Q1m and Q1s.
The logic side power supply VDD shall be fed to the J6 of the master board, that will also
supply the slave board through J1 - J5 connectors. The jumper JP4 and JP6 of each board
shall be properly set (see Table 4). A setting of the JP4slave is not relevant.
Positive VH and optional negative VL power supplies for each board shall be independently
provided by different sources to connectors J2master and J2slave unless an interleaved
operation is required, in which case VH, GNDISO and VL nets of each board shall be
externally connected. The jumper JP5 of each board shall be properly configured (see
Table 5).
Table 8. Jumper configurations for SPI settings using two EVALSTGAP1S boards
Name
Function
Jumper configurations
JP3master
SPI daisy chain configuration
OPEN
JP3slave
SPI daisy chain configuration
CLOSED
Lines SD and DIAG1 of both STGAP1S drivers are shared, whereas it is possible to
independently control IN+ and IN-/DIAG2 pins of each driver through appropriate lines of the
J3master and J3slave.
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Connection of two EVALSTGAP1S boards
If the STGAP1S devices are used in single input configuration both IN-/DIAG2 lines are
independently present on the J4master for interfacing with the µC and diagnostic purposes.
If the two boards are used in half bridge configuration (GNDISOslave and Cmaster plate holes
shall therefore be connected) it is possible to achieve cross conduction prevention by
driving both drivers with only two µC lines as shown in Figure 5.
Figure 5. Half bridge configuration with hardware shoot-through protection
IN+
IN-
µC
gapDRIVE HS
HIN
LIN
IN+
IN-
gapDRIVE LS
In order to use this configuration the STGAP1S shall be used as 2-input device and the JP1
and JP2 jumpers shall be properly set (see Table 9).
Table 9. Jumper configurations for input signal settings
Gate driving configuration
Source of IN+ and IN- control signals
Jumper configurations
Single driver (Figure 6)
J3
JP1master = DON'T CARE
JP2master = DON'T CARE
Half bridge with hardware
shoot-through protection
(Figure 7)
J3master
JP1master = CLOSED
JP2master = CLOSED
Half bridge with independent
input signals (Figure 8)
J3master for master board
J3slave for slave board
JP1master = OPEN
JP2master = OPEN
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Figure 6. Single driver configuration
VH
control
signals
{
INM
INP
JP1 & JP2
don’t care
JP3 close
VDD
Figure 7. Half bridge with hardware shoot-through protection configuration
VH_slave
SLAVE
JP3 closed
(for daisy-chain)
control
signals
{
INM
INP
VH_master
JP1 & JP2
closed
MASTER
JP3 open
(for daisy-chain)
VDD
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Connection of two EVALSTGAP1S boards
Figure 8. Half bridge with independent input signal configurations
VH_slave
control
signals
{
INM
INP
SLAVE
JP3 closed
(for daisy-chain)
control
signals
{
INM
INP
VH_master
JP1 & JP2
open
MASTER
JP3 open
(for daisy-chain)
VDD
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Getting started
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3
Getting started
3.1
Using EVALSTGAP1S in standalone mode
The STGAP1S device can work also without SPI programming using the device default
values.
3.1.1
Check list
EVALSTGAP1S board
Two power supplies (VDD and VH supply voltage)
Power supply for negative gate driving voltage VL is optional
3.1.2
PWM function generator
EVALSTGAP1S board setup example
1.
VDD = 3.3 V or 5 V from external power supply (J6 connector)
2.
VH from external power supply (J2 connector)
3.
VL = GNDISO (JP5 closed)
4.
PWM input signals can be applied to J3 connector (IN-, IN+)
If you have only one PWM signal available:
3.1.3
–
To have gate output in phase with input command: PWM on IN+ and IN- = GND
–
To have gate output out of phase with input command: PWM on IN- and
IN+ = VDD
EVALSTGAP1S board in standalone mode
1.
Connect the power supply to the EVALSTGAP1S VDD (J6 connector) and turn it on.
The DIAG1 LED (DL2) on the EVALSTGAP1S is turned on.
The status of the DIAG2 depends on the voltage level forced on the IN- pin.
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2.
Connect the power supply to the EVALSTGAP1S VH (J2 connector) and turn it on.
3.
Set the SD pin low for at least 105 µs to clear the fault (J3 connector).
4.
Set the SD pin to the 'High' logic level (which depends on VDD value): the DIAG1 LED
(DL2) is switched off.
5.
The device outputs will now follow the input signals coming from IN+ and IN-.
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3.1.4
Getting started
EVALSTGAP1S default parameters
IN-/DIAG2 configured as input
Active Miller clamp enabled
Desaturation detection enabled: VDESATth = 7 V and IDESAT = 250 µA
VDD OVLO function enabled
Thermal shutdown protection enabled
The DIAG1 pin reports the following faults event:
3.2
–
DESAT events
–
VDD supply failures
–
Missing VH
–
Thermal shutdown
–
Register error R and L
All others features are disabled
Using EVALSTGAP1S with STEVAL-PCC009V2 and
STGAP1S evaluation software
Using the EVALSTGAP1S board in connection with the 'STGAP1S evaluation software' and
the STEVAL-PCC009V2 interface board it is possible to evaluate the device functionalities
and driving two EVALSTGAP1S boards implementing independent, half bridge, or
interleaved configuration of power switches.
The software allows saving the device parameters configuration in a dedicated file that can
be reloaded whenever it is necessary, for example after the board power-on. The 'Save' and
'Load' buttons on the bottom-left side of the STGAP1S configuration panel (Figure 10) have
these functions.
3.2.1
3.2.2
Check list
Microsoft® Windows® 7 or Windows® XP PC with a free USB port
EVALSTGAP1S board
STEVAL-PCC009V2 interface board
gapDRIVE™ evaluation software (the right version for your OS)
Power supply
PWM function generator
10-pin flat cable and USB - MiniUSB cable
Single EVALSTGAP1S board setup example
1.
VDD = 3.3 V from the STEVAL-PCC009V2: closing JP4 and JP6
2.
VH from external power supply (J2 connector)
3.
VL = GNDISO (JP5 closed)
4.
PWM input signals can be applied to the J3 connector (IN-, IN+)
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If you have only one PWM signal available:
3.2.3
–
To have gate output in phase with input command: PWM on IN+ and IN- = GND
–
To have gate output out of phase with input command: PWM on IN- and
IN+ = VDD
Connection to STEVAL-PCC009V2 interface board
The EVALSTGAP1S shall be connected to the interface board and the following steps
performed:
1.
Connect the interface board to the PC through the USB cable: the red LED (POWER D2) turns on
2.
Connect the interface board 10-pin connector to the EVALSTGAP1S J4 connector
through the 10-pin flat cable
The DIAG1 red LED (DL2) on the EVALSTGAP1S turns-on
3.
Connect the power supply to VH of the EVALSTGAP1S (J2 connector) and turn it on
4.
Start the EVALSTGAP1S evaluation software
5.
Click the icon 'Connect' on the top left side of the GUI window to establish a connection
between the EVALSTGAP1S and interface boards (see Figure 9)
The DIAG1 LED (DL2) on the EVALSTGAP1S is switched off
6.
Press the 'Refresh' button and verify all fault lights are off. If OK jump to the next point,
otherwise two options are available to clear the faults and make the device operative:
a)
Perform a double transition on SD (high => low => high) clicking on the SD button
b)
Perform a status reset clicking on the 'Reset' button and after set the SD button to
'High'
7.
Set the SD button to 'High'
8.
Connect IN- to GND and applying the PWM on IN+, the device outputs will follow the
input signal
In order to read the device status, use the 'Refresh' button to update the status indicators
according to driver's status registers.
To customize the device parameters and functions open the 'STGAP1S configuration' panel
pushing the relative toolbar icon (refer to Figure 9).
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Figure 9. STGAP1S evaluation software screenshot
In the new window shown in Figure 10, it is possible to enable or disable the device
functionalities and set the device parameters.
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Figure 10. STGAP1S configuration panel
Note:
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The CRC error light will blink if the CRC check is not used ('Use CRC check' not ticked in
the gapDRIVE™ configuration panel) as in the default settings.
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3.2.4
Getting started
Using two EVALSTGAP1S boards in daisy chain configuration
If you want to drive two EVALSTGAP1S boards refer to dedicated Section 2: Connection of
two EVALSTGAP1S boards on page 6 for the board's connection and jumper's settings,
then follow the steps of Section 3.2.3: Connection to STEVAL-PCC009V2 interface board
up to point 5.
It is possible to set the driven device number using the drop down list in the software main
panel.
Figure 11. How to drive two EVALSTGAP1S boards with STGAP1S evaluation software
When the 'Dual' option is selected the devices parameters can be set independently
selecting the 'Device 1' or 'Device 2' in the STGAP1S configuration panel. Otherwise it is
possible to set some parameter values on both devices ticking one or more 'push-pin' boxes
(refer to Figure 12).
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Figure 12. How to set the same parameters in both devices
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Revision history
Revision history
Table 10. Document revision history
Date
Revision
19-Nov-2014
1
Changes
Initial release.
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