TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 Dual-Channel WLED Drivers For Smart Phone Check for Samples: TPS61163 FEATURES DESCRIPTION • • • • The TPS61163 is a dual-channel WLED driver which provide highly integrated solutions for single-cell Liion battery powered smartphone backlight. The device has a built-in high efficiency boost regulator with integrated 1.5A/40V power MOSFET and support as low as 2.7V input voltage. With two high current-matching capability current sink regulators, the devices can drive up to 10s2p WLED diodes. The boost output can automatically adjust to the WLED forward voltage and allow very low voltage headroom control, thus to improve LED strings efficiency effectively. 1 2 • • • • • • • • • • • • • • • • 2.7V to 6.5V Input Voltage Integrated 1.5A/40V MOSFET 1.2MHz Switching Frequency Dual Current Sinks of up to 30mA Current Each 1% Typical Current Matching and Accuracy 37.5V OVP Threshold Adaptive Boost Output to WLED Voltages Very Low Voltage Headroom Control (90mV) Flexible Digital and PWM Brightness Control 1-Wire Control Interface (EasyScale) PWM Dimming Control Interface Up to 100:1 PWM Dimming Ratio Up to 10-bit Dimming Resolution Up to 90% Efficiency Built-in Soft Start Over Voltage Protection Built-in WLED Open/Short Protection Thermal Shutdown Support 4.7uH Inductor Application 9L 1.31 mm x 1.31 mm CSP Package APPLICATIONS • • • • Smart Phones PDAs, Handheld Computers GPS Receivers Backlight for Small and Media Form Factor LCD Display with Single-Cell Battery Input The TPS61163 supports both of the PWM dimming interface and 1-wire digital EasyScale™ dimming interface and can realize 9-bit brightness code programming. The TPS61163 integrates built-in soft start, over voltage/current protection, and thermal shut down protections. The device is available in a space-saving 1.31 mm x 1.31 mm CSP package. TYPICAL APPLICATION L1 4.7µH 2.7V ~ 6.5V D1 VBAT C1 1µF R2 10Ω SW VIN C2 1µ F C3 1µ F Enable / Disable EN PWM Dimming PWM TPS61163 IFB1 COMP IFB2 C4 330nF ISET GND R1 63.4kΩ 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EasyScale is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA PART NUMBER OPEN LED PROTECTION PACKAGE ORDERING (2) PACKAGE MARKING –40°C to 85°C TPS61163 37.5V (typical) 9-ball WSCP TPS61163YFF TPS61163 (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The YFF package is available in tape and reel. Add a R suffix (e.g. TPS61163YFFR) to order quantities of 3000 parts. Add a T suffix (e.g. TPS61163YFFT) to order quantities of 250 parts. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Voltage range (2) MAX VIN, EN, PWM, IFB1, IFB2 –0.3 7 V COMP, ISET –0.3 3 V SW –0.3 40 V 2 kV Machine Mode – (MM) 200 V Charge Device Mode – (CDM) 750 V Human Body Mode – (HBM) ESD rating UNIT MIN PD Continuous power dissipation TJ Operating junction temperature range –40 150 °C TSTG Storage temperature range –65 150 °C (1) (2) See Thermal Information Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL INFORMATION TPS61163 THERMAL METRIC (1) YFF (9-ball WSCP) θJA Junction-to-ambient thermal resistance (2) θJCtop Junction-to-case (top) thermal resistance (3) 0.9 θJB Junction-to-board thermal resistance (4) 18.1 ψJT Junction-to-top characterization parameter (5) 4.0 ψJB Junction-to-board characterization parameter (6) 18 θJCbot Junction-to-case (bottom) thermal resistance (7) NA (1) (2) (3) (4) (5) (6) (7) 2 UNITS 107 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VIN Input voltage range 2.7 6.5 VOUT Output voltage range VIN 38 V V L Inductor 4.7 10 µH CI Input capacitor 1.0 CO Output capacitor 1.0 CCOMP Compensation capacitor FPWM PWM dimming signal frequency 40 TA Operating ambient temperature TJ Operating junction temperature µF 2.2 µF 100 kHz –40 85 °C –40 125 °C 330 nF ELECTRICAL CHARACTERISTICS VIN = 3.6V, EN = high, PWM = high, IFB current = 20mA, TA = -40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VIN Input voltage range VVIN_UVLO Under voltage lockout threshold VVIN_HYS VIN UVLO hysteresis 2.7 VIN falling 6.5 2.2 VIN rising 2.3 2.45 100 Iq Operating quiescent current into VIN Device enable, switching 1.2 MHz and no load, VIN = 3.6V ISD Shutdown current EN = low V V mV 1.2 2 mA 1 2 µA EN and PWM VH EN Logic high 1.2 V VL EN Logic Low VH PWM Logic high VL PWM Logic Low RPD EN pin and PWM pin internal pulldown resistor tPWM_SD PWM logic low width to shutdown PWM high to low 20 ms tEN_SD EN logic low width to shutdown EN high to low 2.5 ms 1.204 0.4 1.2 V 0.4 400 V 800 1600 V kΩ CURRENT REGULATION VISET_full ISET pin voltage Full brightness KISET_full Current multiplier Full brightness IFB_avg Current accuracy KM (IMAX – IAVG) / IAVG IIFB_max Current sink max output current IISET = 20 μA, D = 100%, 0°C to 70°C IISET = 20 µA, D = 100%, –40°C to 85°C 1.229 –2% –2.3% 2.3% 1% D = 25% 1% 2% 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 V 2% D = 100% IISET = 35 μA, each IFBx pin 1.253 1030 mA 3 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.6V, EN = high, PWM = high, IFB current = 20mA, TA = -40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SWITCH RDS(on) Switch MOSFET on-resistance ILEAK_SW Switch MOSFET leakage current VIN = 3.6 V 0.25 VIN = 3.0 V 0.3 VSW = 35 V, TA = 25°C Ω 1 µA 1500 kHz OSCILLATOR fSW Oscillator frequency Dmax Measured on the drive signal of switch MOSFET Maximum duty cycle 1000 1200 91 95 % 90 mV 12 µA BOOST VOLTAGE CONTROL VIFB_reg IFBx feedback regulation voltage Isink COMP pin sink current Isource COMP pin source current Gea Error amplifier transconductance Rea Error amplifier output resistance fea Error amplifier crossover frequency IIFBx = 20mA, measured on IFBx pin which has a lower voltage 5 30 5pF connected to COMP pin 55 µA 80 µmho 45.5 MΩ 1.65 MHz PROTECTION ILIM Switch MOSFET current limit D = Dmax, 0°C to 70°C ILIM_Start Switch MOSFET start up current limit D = Dmax tHalf_LIM Time window for half current limit VOVP_SW SW pin over voltage threshold VOVP_IFB IFBx pin over voltage threshold 1 1.5 2 0.7 A A 5 ms 36 37.5 39 V Measured on IFBx pin 4.2 4.5 4.8 V EASYSCALE INTERFACE tes_delay EasyScale detection delay Measured from EN low to high 100 µs tes_det EasyScale detection time EN pin low time 260 µs 1 ms (1) tes_win EasyScale detection window tstart Start time of program stream Measured from EN low to high 2 tEOS End time of program stream 2 360 µs tH_LB High time of low bit (Logic 0) 2 180 µs tL_LB Low time of low bit (Logic 0) 2 x tH_LB 360 µs tH_HB High time of high bit (Logic 1) 2 x tL_HB 360 µs tL_HB Low time high bit (Logic 1) 2 180 µs tvalACKN Acknowledge valid time tACKN Duration of acknowledge condition VACKNL Acknowledge output voltage low (2) µs Open drain, Rpullup = 15 kΩ to VIN 2 µs 512 µs 0.4 V THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold 160 °C Thys Thermal shutdown hysteresis 15 °C (1) (2) 4 To select EasyScale interface, after tes_delay delay from EN low to high, drive EN pin to low for more than tes_det before tes_win expires Acknowledge condition active 0, this condition is only applied when the RFA bit is set to 1. To use this feature, master must have an open drain output, and the data line needs to be pulled up by the master with a resistor load. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 DEVICE INFORMATION PIN ASSIGNMENT 9 BALL 1.31mm x 1.31mm YFF PACKAGE Bottom View Top View 1 2 3 3 2 1 A ISET IFB2 IFB1 IFB1 IFB2 ISET A B PWM COMP GND GND COMP PWM B C EN VIN SW SW VIN EN C PIN FUNCTIONS PIN I/O DESCRIPTION NUMBER NAME A1 ISET I Full-scale LED current set pin. Connecting a resistor to the pin programs the full-scale LED current A2 IFB2 I Regulated current sink input pin A3 IFB1 I Regulated current sink input pin B1 PWM I PWM dimming signal input B2 COMP O Output of the transconductance error amplifier. Connect external capacitor to this pin to compensate the boost loop B3 GND O Ground C1 EN I Enable control, and 1-wire digital signal input C2 VIN I Supply input pin C3 SW I Drain connection of the internal power MOSFET Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 5 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS Table 1. TABLE OF GRAPHS TITLE DESCRIPTION FIGURE Dimming Efficiency VIN = 3V, 3.6V, 4.2V, 5V; VO = 15V, 5s2p, 20mA/string; PWM Freq = 40kHz; L = 10µH Figure 1 Dimming Efficiency VIN = 3V, 3.6V, 4.2V, 5V; VO = 18V, 6s2p, 20mA/string; PWM Freq = 40kHz; L = 10µH Figure 2 Dimming Efficiency VIN = 3V, 3.6V, 4.2V, 5V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 40kHz; L = 10µH Figure 3 Dimming Efficiency VIN = 3V, 3.6V, 4.2V, 5V; VO = 24V, 8s2p, 20mA/string; PWM Freq = 40kHz; L = 10µH Figure 4 Dimming Efficiency VIN = 3V, 3.6V, 4.2V, 5V; VO = 27V, 9s2p, 20mA/string; PWM Freq = 40kHz; L = 10µH Figure 5 Dimming Efficiency VIN = 3V, 3.6V, 4.2V, 5V; VO = 30V, 10s2p, 20mA/string; PWM Freq = 40kHz; L = 10µH Figure 6 Dimming Linearity VIN = 3V, 3.6V, 4.2V, 5V; VO = 21V, 7s2p; RISET = 63.4kΩ; PWM Freq = 40kHz Figure 7 Switching Waveform VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; Duty = 100%; L = 4.7µH Figure 8 Switching Waveform VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 40kHz, Duty = 20%; L = 4.7µH Figure 9 Startup Waveform VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; Duty = 100%; L = 4.7µH Figure 10 Startup Waveform VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 40kHz, Duty = 50%; L = 4.7µH Figure 11 Shutdown Waveform VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; Duty = 100%; L = 4.7µH Figure 12 Shutdown Waveform VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 40kHz, Duty = 50%; L = 4.7µH Figure 13 EFFICIENCY vs DIMMING DUTY CYCLE EFFICIENCY vs DIMMING DUTY CYCLE 100 100 VIN = 3 V 90 85 85 80 75 70 VO = 15 V, 5s2p, 20 mA/string 65 VSeries2 IN = 3 V VSeries4 IN = 3.6 V 60 55 50 20 40 60 80 75 70 Series4 VIN =5V 0 60 Figure 2. EFFICIENCY vs DIMMING DUTY CYCLE EFFICIENCY vs DIMMING DUTY CYCLE 90 85 85 Efficiency (%) 95 90 80 VIN = 3 V 70 80 VSeries1 IN = 3 V VSeries2 IN = 3.6 V VSeries4 IN = 4.2 V VSeries5 IN = 5 V 55 50 40 60 Dimming Duty Cycle (%) 80 100 C002 70 VO = 24 V, 8s2p, 20 mA/string 60 VSeries1 IN = 3 V VSeries2 IN = 3.6 V VSeries4 IN = 4.2 V VSeries5 IN = 5 V 55 50 100 80 VIN = 3 V 75 65 VO = 21 V, 7s2p, 20 mA/string 20 40 Dimming Duty Cycle (%) Figure 1. 65 0 C003 Figure 3. 6 20 C001 100 0 Series3 VIN = 4.2 V 50 95 60 VIN = 3.6 V Series2 55 100 75 VIN =3V Series1 VO = 18 V, 6s2p, 20 mA/string 60 100 Dimming Duty Cycle (%) Efficiency (%) 80 65 VSeries5 IN = 4.2 V VSeries6 IN = 5 V 0 VIN = 3 V 95 90 Efficiency (%) Efficiency (%) 95 20 40 60 Dimming Duty Cycle (%) 80 100 C004 Figure 4. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 EFFICIENCY vs DIMMING DUTY CYCLE EFFICIENCY vs DIMMING DUTY CYCLE 95 90 90 85 85 Efficiency (%) 100 95 Efficiency (%) 100 80 VIN - 3 V 75 70 65 55 50 0 20 40 60 80 Dimming Duty Cycle (%) 75 VIN = 3 V 70 65 VIN =3V Series1 VIN = 3.6 V Series2 VIN = 4.2 V Series4 VIN =5V Series5 VO= 27 V, 9s2p, 20 mA/string 60 80 VO = 30 V, 10s2p, 20 mA/string 60 55 50 100 0 DIMMING LINEARITY IO - Output Current (mA) 40 40 60 80 100 C006 Figure 6. SWITCHING WAVEFORM VSeries1 IN = 3 V VSeries2 IN = 3.6 V VSeries4 IN = 4.2 V VSeries5 IN = 5 V 45 20 Dimming Duty Cycle (%) C005 Figure 5. 50 VSeries1 IN = 3 V VSeries2 IN = 3.6 V VSeries4 IN = 4.2 V VSeries5 IN = 5 V SW Voltage 20V/div DC Output Voltage 100mV/div AC Inductor Current 500mA/div DC 35 30 25 20 15 10 Output Current 20mA/div DC VIN = 3 V 5 DUTY = 100% 0 0 20 40 60 Dimming Duty Cycle (%) 80 100 t - Time - 1µs/div C007 Figure 7. Figure 8. SWITCHING WAVEFORM STARTUP WAVEFORM SW Voltage 20V/div DC PWM Voltage 2V/div DC Output Voltage 50mV/div AC Inductor Current 500mA/div DC Output Voltage 10V/div DC Output Current 5mA/div DC Inductor Current 500mA/div DC PWM FREQ = 40kHz; DUTY = 20% Output Current 20mA/div DC t - Time - 1µs/div DUTY = 100% t - Time - 10ms/div Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 7 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com STARTUP WAVEFORM SHUTDOWN WAVEFORM PWM Voltage 2V/div DC PWM Voltage 2V/div DC Output Voltage 10V/div DC Output Voltage 10V/div DC Inductor Current 500mA/div DC Inductor Current 500mA/div DC Output Current 20mA/div DC Output Current 20mA/div DC PWM FREQ = 40kHz; DUTY = 50% DUTY = 100% t - Time - 10ms/div t - Time - 10ms/div Figure 11. Figure 12. SHUTDOWN WAVEFORM PWM Voltage 2V/div DC Output Voltage 10V/div DC Inductor Current 500mA/div DC Output Current 20mA/div DC PWM FREQ = 40kHz; DUTY = 50% t - Time - 10ms/div Figure 13. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 FUNCTIONAL BLOCK DIAGRAM D1 L1 VBAT R2 10Ω C1 1µ F VOUT C2 1µF SW VIN C3 1 µF UVLO / Internal Regulator SW OVP R Q S OSC OCP Slope Compensation GND S Comp Error Amp Vref COMP IFBx Voltage Detection C4 330nF IFBx OVP EN Enable / Disable Detection Shutdown Control IFB1 EA PWM Duty Detection ISET Analog Dimming Control IFB1 Current Sink R1 63.4kΩ IFB2 IFB2 Current Sink Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 9 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com DETAILED DESCRIPTION NORMAL OPERATION In order to provide high brightness backlighting for big size or high resolution smartphone panels, more and more white LED diodes are used. Having all LED diodes in a string improves overall current matching; however, the output voltage of a boost converter will be limited when input voltage is low, and normally the efficiency will drop when output voltage goes very high. Thus the LED diodes are arranged in two parallel strings. The TPS61163 is a high efficiency, dual-channel white LED driver for such smart phone backlighting applications. Two current sink regulators of high current-matching capability are integrated in the TPS61163 to support dual LED strings connection and to improve the current balance and protect the LED dioeds when either LED string is open or short. TPS61163 has integrated all of the key function blocks to power and control up to 20 white LED diodes. It includes a 40V/1.5A boost converter, two current sink regulators and protection circuit for over-current, overvoltage and thermal shutdown protection. BOOST CONVERTER The boost converter of the TPS61163 integrates 40V 1.5A low side switch MOSFET and has a fixed switching frequency of 1.2MHz. The control architecture is based on traditional current-mode PWM control. For operation see the block diagram. Two current sinks regulate the dual-channel current and the boost output is automatically set by regulating IFBx pin’s voltage. The output of error amplifier and the sensed current of switch MOSFET are applied to a control comparator to generate the boost switching duty cycle; slope compensation is added to the current signal to allow stable operation for duty cycles larger than 50%. The forward voltages of two LED strings are normally different due to the LED diode forward voltage inconsistency, thus the IFB1 and IFB2 voltages are normally different. The TPS61163 can select out the IFBx pin which has a lower voltage than the other and regulates its voltage to a very low value (90mV typical), which is enough for the two current sinks' headroom. In this way, the output voltage of the boost converter is automatically set and adaptive to LED strings' forward voltages, and the power dissipation of the current sink regulators can be reduced remarkably with this very low headroom voltage. IFBx PIN UNUSED If only one channel is needed, a user can easily disable the unused channel by connecting its IFBx pin to ground. If both IFBx pins are connected to ground, the IC will not start up. ENABLE AND STARTUP In order to enable the IC from shutdown mode, three conditions have to be met: 1. POR (Power On Reset, that is, VIN voltage is higher than UVLO threshold), 2. Logic high on EN pin, 3. PWM signal (logic high or PWM pulses) on PWM pin. When these conditions are all met, an internal LDO linear regulator is enabled to provide supply to internal circuits and the IC can start up. The TPS61163 supports two dimming interfaces: 1-wire digital interface (EasyScale interface) and PWM interface. TPS61163 begins an EasyScale detection window after startup to detect which interface is selected. If the EasyScale interface is needed, signals of a specific pattern should be input into EN pin during the EasyScale detection window; otherwise, PWM dimming interface will be enabled (see details in 1-Wire Digital Interface (EasyScale Interface) ). After the EasyScale detection window, the TPS61163 checks the status of IFBx pins. If one IFBx pin is detected to connect to ground, the corresponding channel will be disabled and removed from the control loop. Then the soft-start begins and the boost converter starts switching. If both IFBx pins are shorted to ground, the TPS61163 will not start up. Either pulling EN pin low for more than 2.5ms or pulling PWM pin low for more than 20ms can disable the device and the TPS61163 enters into shutdown mode. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 SOFTSTART Soft-start is implemented internally to prevent voltage over-shoot and in-rush current. After the IFBx pin status detection, the COMP pin voltage starts ramp up and the boost starts switching. During the beginning 5ms (tHalf_LIM) of the switching, the peak current of the switch MOSFET is limited at ILIM_Start (0.7A typical) to avoid the input inrush current. After the 5ms, the current limit is changed to ILIM (1.5A typical) to allow the normal operation of the boost converter. FULL-SCALE CURRENT PROGRAM The dual channels of the TPS61163 can provide up to 30 mA current each. No matter either EasyScale interface or PWM interface is selected, the full-scale current (current when dimming duty cycle is 100%) of each channel should be programmed by an external resistor RISET at ISET pin according to Equation 1. VISET _ full IFB _ full = ´ KISET _ full RISET (1) Where: IFB_full, full-scale current of each channel KISET_full = 1030 (Current multiple when dimming duty cycle = 100%) VISET_full = 1.229V (ISET pin voltage when dimming duty cycle = 100%) RISET = ISET pin resistor BRIGHTNESS CONTROL The TPS61163 controls the DC current of the dual channels to realize the brightness dimming. The DC current control is normally referred to as analog dimming mode. When the DC current of LED diode is reduced, the brightness is dimmed. The TPS61163 can receive either the PWM signals at the PWM pin (PWM interface) or digital commands at the EN pin (EasyScale interface) for brightness dimming. If the EasyScale interface is selected, the PWM pin should be kept high; if PWM interface is selected, the EN pin should be kept high. 1-Wire Digital Interface (EasyScale Interface) The EN pin features a simple digital interface to allow digital brightness control. The digital dimming interface can save the processor power and battery life as it does not require PWM signals all the time, and the processor can enter idle mode if possible. In order to enable the EasyScale interface, the following conditions must be satisfied and the specific digital pattern on the EN pin must be recognized by the IC every time the TPS61163 starts up from shutdown mode. 1. VIN voltage is higher than UVLO threshold and PWM pin is pulled high 2. Pull EN pin from low to high to enable the TPS61163. At this moment, the EasyScale detection window starts 3. After EasyScale detection delay time (tes_delay, 100µs), drive EN to low for more than EasyScale detection time (tes_detect, 260µs). The third step must be finished before the EasyScale detection window (tes_win, 1ms) expires, and once this step is finished, the EasyScale interface is enabled and the EasyScale communication can start. Refer to the Figure 14 for a graphical explanation. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 11 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com Insert battery PWM Signal high PWM low Enter ES mode ES Detection Window Programming code Programming code high EN low ES detect time EasyScale mode Shutdown Ramp up delay ES detect delay IFBx Ramp up Programmed value (if not programmed, full current default ) IC Shutdown Startup delay Startup delay Figure 14. EasyScale Interface Detection The TPS61163 supports 9-bit brightness code programming. By the EasyScale interface, a master can program the 9-bit code D8(MSB) to D0(LSB) to any of 511 steps with a single command. The default code value of D8~D0 is “111111111” when the device is first enabled, and the programmed value will be stored in an internal register and set the dual-channel current according to Equation 2. The code will be reset to default value when the IC is shut down or disabled. Code I FBx = IFB_full ´ 511 (2) Where IFB_full: the full-scale LED current set by the RISET at ISET pin Code: the 9-bit brightness code D8~D0 programmed by EasyScale interface When the 1-wire digital interface at EN pin is selected, the PWM pin can be connected to either VIN pin or a GPIO (refer to ADDITIONAL APPLICATION CIRCUITS). If PWM pin is connected to VIN pin, EN pin alone can enable and disable the IC: pulling EN pin low for more than 2.5ms disables the IC; if PWM pin is connected to a GPIO, both PWM and EN signals should be high to enable the IC, and either pulling EN pin low for more than 2.5ms or pulling PWM pin low for more than 20ms disables the IC. EasyScale Programming EasyScale is a simple but flexible one pin interface to configure the current of the dual channels. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor and the IC is the slave. Figure 15 and Table 2 give an overview of the protocol used by TPS61163. A command consists of 24 bits, including an 8-bit device address byte and a 16-bit data byte. All of the 24 bits should be transmitted together each time, and the LSB bit should be transmitted first. The device address byte D7(MSB)~D0(LSB) is fixed to 0x8F. The data byte includes 9 bits D8(MSB)~D0(LSB) for brightness information and an RFA bit. The RFA bit set to "1" indicates the Request for Acknowledge condition. The Acknowledge condition is only applied when the protocol is received correctly. The advantage of EasyScale compared with other one pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec. 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 DATA IN Data Byte Start D0 D1 D2 D3 D4 D5 D6 Address Byte D7 D8 Bit 9 RFA Bit 11 ~ Bit 15 D0 1 D1 1 D2 1 D3 1 D4 0 D5 0 D6 0 D7 1 EOS DATA OUT ACK Figure 15. EasyScaleTM Protocol Overview Table 2. EasyScaleTM Bit Description BYTE Device Address Byte (0x8F) Data Byte TRANSMISSION DIRECTION BIT NUMBER NAME 23 (MSB) DA7 DA7 = 1, MSB of device address 22 DA6 DA6 = 0 21 DA5 DA5 = 0 20 DA4 19 DA3 18 DA2 DA2 = 1 17 DA1 DA1 = 1 16 DA0 DA0 = 1, LSB of device address 15 Bit 15 No information. Write 0 to this bit. 14 Bit 14 No information. Write 0 to this bit. 13 Bit 13 No information. Write 0 to this bit. 12 Bit 12 No information. Write 0 to this bit. 11 Bit 11 No information. Write 0 to this bit. 10 RFA Request for acknowledge. If set to 1, IC will pull low the data line when it receives the command well. This feature can only be used when the master has an open drain output stage and the data line needs to be pulled high by the master with a pullup resistor; otherwise, acknowledge condition is not allowed and don't set this bit to 1. 9 Bit 9 8 D8 Data bit 8, MSB of brightness code 7 D7 Data bit 7 6 D6 Data bit 6 5 D5 Data bit 5 4 D4 Data bit 4 3 D3 Data bit 3 2 D2 Data bit 2 1 D1 Data bit 1 0 (LSB) D0 Data bit 0, LSB of brightness code DA4 = 0 IN DA3 = 1 IN t start DESCRIPTION No information. Write 0 to this bit. Data Byte Address Byte Static High Static High DATA IN D0 D8 Bit 9 RFA Bit 15 DA0 DA7 1 0 0 0 0 1 1 tEOS Figure 16. EasyScale Timing, with RFA = 0 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 13 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com t start DATA IN Data Byte Address Byte Static High Static High D0 D8 Bit 9 RFA Bit 15 DA0 DA7 1 0 0 1 0 1 1 tvalACK Acknowledge true, Data line ACKN pulled down by the IC DATA OUT (ACKN) Master needs to pull up Data line via a pullup resistor to detect ACKN DATA OUT (ACK) ACK Acknowledge false, no pull down Figure 17. EasyScale Timing, with RFA = 1 tLow tHigh tLow Low Bit (Logic 0) tHigh High Bit (Logic 1) Figure 18. EasyScale — Bit Coding The 24-bit command should be transmitted with LSB first and MSB last. Figure 16 shows the protocol without acknowledge request (Bit RFA = 0), Figure 17 with acknowledge request (Bit RFA = 1). Before the command transmission, a start condition must be applied. For this, the EN pin must be pulled high for at least tstart (2μs) before the bit transmission starts with the falling edge. If the EN pin is already at high level, no start condition is needed. The transmission of each command is closed with an End of Stream condition for at least tEOS (2μs). The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and tHIGH (refer to Figure 18). It can be simplified to: Low Bit (Logic 0): tLOW ≥ 2 x tHIGH High Bit (Logic 1): tHIGH ≥ 2 x tLOW The bit detection starts with a falling edge on the EN pin and ends with the next falling edge. Depending on the relation between tHIGH and tLOW, the logic 0 or 1 is detected. The acknowledge condition is only applied if: • Acknowledge is requested by setting RFA bit to 1. • The transmitted device address matches with the device address of the IC. • Total 24 bits are received correctly. If above conditions are met, after tvalACK delay from the moment when the last falling edge of the protocol is detected, an internal ACKN-MOSFET is turned on to pull the EN pin low for the time tACKN, which is 512μs maximum, then the Acknowledge condition is valid. During the tvalACK delay, the master controller keeps the line low; after the delay, it should release the line by outputting high impedance and then detect the acknowledge condition. If it reads back a logic 0, it means the IC has received the command correctly. The EN pin can be used again by the master when the acknowledge condition ends after tACKN time. Note that the acknowledge condition can only be requested when the master device has an open drain output. For a push-pull output stage, the use of a series resistor in the EN line to limit the current to 500μA is recommended to for such cases as: • An accidentally requested acknowledge, or • To protect the internal ACKN-MOSFET. 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 PWM Control Interface The PWM control interface is automatically enabled if the EasyScale interface fails to be enabled during startup. In this case, the TPS61163 receives PWM dimming signals on the PWM pin to control the backlight brightness. When using PWM interface, the EN pin can be connected to VIN pin or a GPIO (refer to ADDITIONAL APPLICATION CIRCUITS). If EN pin is connected to VIN pin, PWM pin alone is used to enable and disable the IC: pulling PWM pin high or apply PWM signals at PWM pin to enable the IC and pulling PWM pin low for more than 20ms to disable the IC; if EN pin is connected to a GPIO, either pulling EN pin low for more than 2.5ms or pulling PWM pin low for more than 20ms can disable the IC. Only after both EN and PWM signals are applied, the TPS61163 can start up. Refer to Figure 19 for a graphical explanation. Insert battery Insert battery EN signal EN signal high high EN low low PWM signal PWM signal high high PWM PWM low low PWM mode Startup delay Ramp up Startup delay Shutdown delay Full current x PWM Duty IFBx Ramp up t Shutdown delay Full current x PWM Duty Shut down by PWM signal Shut down by EN signal IFBx t Figure 19. PWM Control Interface Detection When the PWM pin is constantly high, the dual channel current is regulated to full-scale according to Equation 1. The PWM pin allows PWM signals to reduce this regulation current according to the PWM duty cycle; therefore, it achieves LED brightness dimming. The relationship between the PWM duty cycle and IFBx current is given by Equation 3. I FBx = IFB_full ´ Duty (3) Where IFBx is the current of each current sink, IFB_full is the full-scale LED current, Duty is the duty cycle information detected from the PWM signals. UNDERVOLTAGE LOCKOUT An undervoltage lockout circuit prevents the operation of the device at input voltages below undervoltage threshold (2.2V typical). When the input voltage is below the threshold, the device is shutdown. If the input voltage rises by undervoltage lockout hysteresis, the IC restarts. OVERVOLTAGE PROTECTION Over voltage protection circuitry prevents IC damage as the result of white LED string disconnection or shortage. The TPS61163 monitors the voltages at SW pin and IFBx pin during each switching cycle. No matter either SW OVP threshold VOVP_SW or IFBx OVP threshold VOVP_FB is reached due to the LED string open or short issue, the protection circuitry will be triggered. Refer to Figure 20 and Figure 21 for the protection actions. If one LED string is open, its IFBx pin voltage drops, and the boost output voltage is increased by the control loop as it tries to regulate this lower IFBx voltage to the target value (90mV typical). For the normal string, its current is still under regulation but its IFBx voltage increases along with the output voltage. During the process, either the SW voltage reaches its OVP threshold VOVP_SW or the normal string’s IFBx pin voltage reaches the IFBx OVP threshold VOVP_FB, then the protection circuitry will be triggered accordingly. If both LED strings are open, both IFBx pins’ voltages drop to ground, and the boost output voltage is increased by the control loop until reaching the SW OVP threshold VOVP_SW, the SW OVP protection circuitry is triggered, and the IC is latched off. Only VIN POR or EN/PWM pin toggling can restart the IC. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 15 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com One LED diode short in a string is allowed for the TPS61163. If one LED diode in a string is short, the normal string’s IFBx voltage is regulated to about 90mV, and the abnormal string’s IFBx pin voltage will be higher. Normally with only one diode short, the higher IFBx pin voltage does not reach the IFBx OVP threshold VOVP_FB, so the protection circuitry will not be triggered. If more than one LED diodes are short in a string, as the boost loop regulates the normal string’s IFBx voltage to 90mV, this abnormal string’s IFBx pin voltage is much higher and will reach VOVP_FB, then the protection circuitry is triggered. The SW OVP protection will also be triggered when the forward voltage drop of an LED string exceeds the SW OVP threshold. In this case, the device turns off the switch FET and shuts down. Soft Start / Normal Operation SW > VOVP for 16~32 switching cycles? No Yes Latch off Figure 20. SW OVP Protection Action Normal Operation IFBx > VIFB_OVP for 24~32 switching cycles? No (caused by transient) Yes Another string is no use? Yes (single string application, caused by transient) Boost stops switching, current sink(s) keep on No No (dual string application, caused by transient) Another VIFBx < 0.5V? Yes (caused by open string or more than two LED diodes short in a string) Boost stops switching, disable the current sink with VIFBx < 0.5V VIFBx < VIFB_OVP_hys? Yes (to recover boost switching) Figure 21. VIFBx OVP Protection Action 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 OVER CURRENT PROTECTION The TPS61163 has a pulse-by-pulse over-current limit. The boost switch turns off when the inductor current reaches this current threshold and it remains off until the beginning of the next switching cycle. This protects the TPS61163 and external component under overload conditions. THERMAL SHUTDOWN An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The device is released from shutdown automatically when the junction temperature decreases by 15°C. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 17 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com APPLICATION INFORMATION INDUCTOR SELECTION Because the selection of inductor affects power supply’s steady state operation, transient behavior, loop stability and the boost converter efficiency, the inductor is one of the most important components in switching power regulator design. There are three specifications most important to the performance of the inductor: inductor value, DC resistance, and saturation current. The TPS61163 is designed to work with inductor values from 4.7µH to 10µH to support all applications. A 4.7µH inductor is typically available in a smaller or lower profile package, while a 10µH inductor produces lower inductor ripple. If the boost output current is limited by the over-current protection of the IC, using a 10µH inductor may maximize the controller’s output current capability. A 22uH inductor can also be used for some applications, such as 6s2p and 7s2p, but may cause stability issue when more than eight WLED diodes are connected per string. Therefore, customers need to verify the inductor in their application if it is different from the values in RECOMMENDED OPERATING CONDITIONS. Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor defines saturation. When selecting an inductor, please make sure its rated current, especially the saturation current, is larger than its peak current during the operation. Follow Equation 4 to Equation 6 to calculate the inductor’s peak current. To calculate the current in the worst case, use the minimum input voltage, maximum output voltage and maximum load current of the application. In order to leave enough design margin, the minimum switching frequency (1MHz for TPS61163), the inductor value with -30% tolerance, and a low power conversion efficiency, such as 80% or lower are recommended for the calculation. In a boost regulator, the inductor DC current can be calculated as Equation 4. V ´I IDC = OUT OUT VIN ´ h (4) Where VOUT = boost output voltage IOUT = boost output current VIN = boost input voltage η = boost power conversion efficiency The inductor current peak to peak ripple can be calculated as Equation 5. 1 IPP = æ 1 1 ö + L´ç ÷ ´ FS è VOUT - VIN VIN ø (5) Where IPP = inductor peak-to-peak ripple L = inductor value FS = boost switching frequency VOUT = boost output voltage VIN = boost input voltage Therefore, the peak current IP seen by the inductor is calculated with Equation 6. IP = IDC + IPP 2 (6) Select an inductor with saturation current over the calculated peak current. If the calculated peak current is larger than the switch MOSFET current limit ILIM, use a larger inductor, such as 10µH, and make sure its peak current is below ILIM. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 Boost converter efficiency is dependent on the resistance of its current path, the switching losses associated with the switch MOSFET and power diode and the inductor’s core loss. The TPS61163 has optimized the internal switch resistance, however, the overall efficiency is affected a lot by the inductor’s DC Resistance (DCR), Equivalent Series Resistance (ESR) at the switching frequency and the core loss. Core loss is related to the core material and different inductors have different core loss. For a certain inductor, larger current ripple generates higher DCR/ESR conduction losses as well as higher core loss. Normally a datasheet of an inductor does not provide the ESR and core loss information. If needed, consult the inductor vendor for detailed information. Generally, an inductor with lower DCR/ESR is recommended for TPS61163 application. However, there is a trade off among inductor’s inductance, DCR/ESR resistance, and its footprint; furthermore, shielded inductors typically have higher DCR than unshielded ones. Table 3 lists some recommended inductors for the TPS61163. Verify whether the recommended inductor can support your target application by the calculations above as well as bench validation. Table 3. Recommended Inductors PART NUMBER L (uH) DCR MAX (mΩ) SATURATION CURRENT (A) Size (L x W x H mm) VENDOR LPS4018-472ML 4.7 125 1.9 4 x 4 x 1.8 Coilcraft LPS4018-682ML 6.8 150 1.3 4 x 4 x 1.8 Coilcraft LPS4018-103ML 10 200 1.3 4 x 4 x 1.8 Coilcraft PCMB051B-4R7M 4.7 163 2.7 5.4 x 5.2 x 1.2 Cyntec PCMB051B-6R8M 6.8 250 2.3 5.4 x 5.2 x 1.2 Cyntec SCHOTTKY DIODE SELECTION The TPS61163 demands a low forward voltage, high-speed and low capacitance schottky diode for optimum efficiency. Ensure that the diode average and peak current rating exceeds the average output current and peak inductor current. In addition, the diode’s reverse breakdown voltage must exceed the open LED protection voltage. ONSemi MBR0540 and NSR05F40, and Vishay MSS1P4 are recommended for the TPS61163. COMPENSATION CAPACITOR SELECTION The compensation capacitor C4 (refer to ADDITIONAL APPLICATION CIRCUITS) connected from the COMP pin to GND, is used to stabilize the feedback loop of the TPS61163. A 330nF ceramic capacitor for C4 is suitable for most applications. A 470nF is also OK for some applications and customers are suggested to verify it in their applications. OUTPUT CAPACITOR SELECTION The output capacitor is mainly selected to meet the requirement for the output ripple and loop stability. A 1µF to 2.2µF capacitor is recommended for the loop stability consideration. This ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Due to its low ESR, Vripple_ESR could be neglected for ceramic capacitors. Assuming a capacitor with zero ESR, the output ripple can be calculated with Equation 7. (V - VIN ) ´ IOUT Vripple = OUT VOUT ´ FS ´ COUT (7) Where: Vripple = peak-to-peak output ripple. The additional part of ripple caused by the ESR is calculated using Vripple_ESR = IOUT x RESR and can be ignored for ceramic capacitors. Note that capacitor degradation increases the ripple much. Select the capacitor with 50V rated voltage to reduce the degradation at the output voltage. If the output ripple is too large, change a capacitor with less degradation effect or with higher rated voltage could be helpful. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 19 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com LAYOUT CONSIDERATION As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C1 in ADDITIONAL APPLICATION CIRCUITS, needs to be close to the inductor, as well as the VIN pin and GND pin in order to reduce the input ripple seen by the IC. If possible, choose higher capacitance value for it. If the ripple seen at VIN pin is so large that it affects the boost loop stability or internal circuits operation, R2 and C3 are recommended to filter and decouple the noise. In this case, C3 should be placed as close as possible to the VIN and GND pins. The SW pin carries high current with fast rising and falling edges. Therefore, the connection between the SW pin to the inductor and schottky diode should be kept as short and wide as possible. The trace between schottky diode and the output capacitor C2 should also be as short and wide as possible. It is also beneficial to have the ground of the output capacitor C2 close to the GND pin since there is a large ground return current flowing between them. When laying out signal grounds, it is recommended to use short traces separated from power ground traces, and connect them together at a single point close to the GND pin. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 ADDITIONAL APPLICATION CIRCUITS L1 4.7µH 2.7V ~ 6.5V D1 VBAT R2 10Ω C1 1µF C2 1 µF SW VIN C3 1µF Enable / Disable EN PWM Dimming PWM TPS61163 IFB1 COMP IFB2 C4 330nF ISET R1 63.4kΩ GND Figure 22. TPS61163 Typical Application (PWM interface enabled, EN pin can be used to enable or disable the IC) L1 4.7µH 2.7V ~ 6.5V D1 VBAT R2 10Ω C1 1 µF SW VIN C2 1µF C3 1µF EN TPS61163 PWM Dimming PWM IFB1 COMP IFB2 C4 330nF ISET GND R1 63.4kΩ Figure 23. TPS61163 Typical Application (PWM interface enabled, EN pin connected to VIN, only PWM signal is used to enable or disable the IC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 21 TPS61163 SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 www.ti.com L1 4.7µH 2.7V ~ 6.5V D1 VBAT C1 1µF R2 10Ω SW VIN C2 1µF C3 1 µF EasyScale Command EN TPS61163 Enable / Disable PWM IFB1 COMP IFB2 C4 330nF ISET R1 63.4kΩ GND Figure 24. TPS61163 Typical Application (1-wire digital interface enabled, PWM pin can be used to enable or disable the IC) L1 4.7µH 2.7V ~ 6.5V D1 VBAT C1 1 µF R2 10Ω SW VIN C2 1 µF C3 1µF EasyScale Command EN TPS61163 PWM IFB1 COMP IFB2 C4 330nF ISET GND R1 63.4kΩ Figure 25. TPS61163 Typical Application (1-wire digital interface enabled, PWM pin connected to VIN, only EN signal is used to enable or disable the IC) 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 TPS61163 www.ti.com SLVSBQ2C – JANUARY 2013 – REVISED AUGUST 2013 REVISION HISTORY Changes from Original (January 2013) to Revision A • Page Changes to the Product Preview device ............................................................................................................................... 1 Changes from Revision A (February 2013) to Revision B • Page Initial release of the device ................................................................................................................................................... 1 Changes from Revision B (March 2013) to Revision C Page • Deleted TPS61162 from data sheet ..................................................................................................................................... 1 • Changed PWM Freq = 20kHz to PWM Freq = 40kHz in the descriptions of Figure 1 - Figure 7, Figure 9, Figure 11, and Figure 13 in Table 1 ....................................................................................................................................................... 6 • Changed PWM FREQ = 20kHz to PWM FREQ = 40kHz in Figure 9 .................................................................................. 7 • Changed PWM FREQ = 20kHz to PWM FREQ = 40kHz in Figure 11 ................................................................................ 7 • Changed PWM FREQ = 20kHz to PWM FREQ = 40kHz in Figure 13 ................................................................................ 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS61163 23 PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS61163YFFR ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YFF 9 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) SNAGCU Level-1-260C-UNLIM (4/5) -40 to 150 TPS 61163 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS61163YFFR Package Package Pins Type Drawing SPQ DSBGA 3000 YFF 9 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 8.4 Pack Materials-Page 1 1.45 B0 (mm) K0 (mm) P1 (mm) 1.45 0.8 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61163YFFR DSBGA YFF 9 3000 210.0 185.0 35.0 Pack Materials-Page 2 D: Max = 1.336 mm, Min =1.276 mm E: Max = 1.336 mm, Min =1.276 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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