Download Datasheet

STAP08DP05
Low voltage 8-bit constant current LED sink driver with output error
detection for automotive applications
Datasheet - production data
Description
The STAP08DP05 is a monolithic, low voltage,
low current power 8-bit shift register designed for
LED panel displays. The STAP08DP05 contains
an 8-bit serial-in, parallel-out shift register that
feeds an 8-bit D-type storage register. In the
output stage, eight regulated current sources are
designed to provide 5-100 mA constant current to
drive the LEDs.
TSSOP16
(Exposed pad)
The detection circuit checks 3 different conditions
that can occur on the output line: short to GND,
short to VO or open line. The data detection
results are loaded in the shift register and shifted
out via the serial line output.
Features
• AECQ100 qualification
• Low voltage power supply down to 3 V
• 8 constant current output channels
• Adjustable output current through external
resistor
• Short and open output error detection
• Serial data IN/parallel data OUT
• Able to drive 3.3 V microcontroller
• Output current: 5-100 mA
• 30 MHz clock frequency
• Available in high thermal efficiency TSSOP
exposed pad
STAP08DP05 detection functionality is
implemented without increasing the pin number.
Through a secondary function of the output
enable and latch pin (DM1 and DM2 respectively),
a dedicated logic sequence allows the device to
enter or leave detection mode. Through an
external resistor, users can adjust the output
current of the STAP08DP05, thus controlling the
light intensity of the LEDs. In addition, the user
can adjust the intensity of the brightness of the
LEDs from 0% to 100% through the OE/DM2 pin.
The STAP08DP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high clock frequency, 30
MHz, also satisfies the system requirement of
Applications
high volume data transmission. The 3.3 V of
• Dashboard and infotainment backlighting
voltage supply is very useful for applications that
interface any microcontroller from 3.3 V.
• Exterior/interior lighting
Compared with a standard TSSOP package, the
• DTRLs
TSSOP exposed pad increases the capability of
heat dissipation by a factor of 2.5.
Table 1. Device summary
• ESD protection 2.5 kV HBM
Order code
Package
Packing
STAP08DP5XTTR
TSSOP16 exposed-pad (Tape and reel)
2500 parts per reel
November 2015
This is information on a product in full production.
DocID024305 Rev 6
1/28
www.st.com
Contents
STAP08DP05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Pin connections and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7
Truth table and timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.2
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
8
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10
Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/28
10.1
Phase one: “entering error detection mode“ . . . . . . . . . . . . . . . . . . . . . . . 19
10.2
Phase two: “error detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.3
Phase three: “resuming normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.4
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DocID024305 Rev 6
STAP08DP05
11
12
Contents
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1
HTSSOP16 exposed pad package information . . . . . . . . . . . . . . . . . . . . 23
11.2
HTSSOP16 exposed pad packing information . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID024305 Rev 6
3/28
28
Summary description
1
STAP08DP05
Summary description
Table 2. Typical current accuracy
Current accuracy
Output voltage
Output current
Between bits
Between ICs
±1.5%
±6%
≥1.3 V
1.1
20 to 100 mA
Pin connections and description
Figure 1. Pin connections
Note:
The exposed pad is electrically connected to a metal layer electrically isolated or connected
to ground.
Table 3. Pin description
4/28
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE/DM1
Latch input terminal
5-12
OUT 0-7
Output terminal
13
OE/DM2
Output enable input terminal (active low)
14
SDO
15
R-EXT
16
VDD
Serial data out terminal
Constant current programming
5 V supply voltage terminal
DocID024305 Rev 6
STAP08DP05
2
Block diagram
Block diagram
Figure 2. Normal mode - block diagram
DocID024305 Rev 6
5/28
28
Maximum rating
3
STAP08DP05
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
0 to 7
V
VDD
Supply voltage IGND
VO
Output voltage
-0.5 to 20
V
IO
Output current
100
mA
IGND
GND terminal current
800
mA
fCLK
Clock frequency
50
MHz
TOPR
Operating temperature range
-40 to +150
°C
TSTG
Storage temperature range
-55 to +150
°C
Value (1)
Unit
37.5
°C/W
Thermal data
Table 5. Thermal data
Symbol
RthJA
Parameter
Thermal resistance junction-ambient
1. The exposed pad should be soldered to the PCB in order to derive the thermal benefits (according to Jedec
51-7).
6/28
DocID024305 Rev 6
STAP08DP05
3.3
Maximum rating
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
3.0
-
5.5
V
-
20
V
-
100
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SERIAL-OUT
-
+1
mA
IOL
Output current
SERIAL-OUT
-
-1
mA
VIH
Input voltage
0.7
VDD
-
VDD+0.3
V
VIL
Input voltage
-0.3
-
0.3VDD
V
5
twLAT
LE/DM1 pulse width
20
-
ns
twCLK
CLK pulse width
20
-
ns
twEN
OE/DM2 pulse width
200
-
ns
7
-
ns
tHOLD(D) Hold time for DATA
4
-
ns
tSETUP(L) Setup time for LATCH
15
-
ns
VDD = 3.0 to 5.0 V
tSETUP(D) Setup time for DATA
fCLK
Clock frequency
Cascade operation (1)
-
30
MHz
1. If the device is connected in cascade, it may not be possible to achieve the maximum data transfer. Please
consider the timings carefully.
DocID024305 Rev 6
7/28
28
Electrical characteristics
4
STAP08DP05
Electrical characteristics
VDD = 5 V, Tj = -40 °C to 125 °C, unless otherwise specified.
Table 7. Electrical characteristics
Symbol
Parameter
VIH
Input voltage high level
0.7•VDD
VDD
VIL
Input voltage
low level
GND
0.3•VDD
VOL
VOH
IOH
Test conditions
Min
Typ
Max
V
Serial data output voltage
(SDO)
IOL = + 1 mA
Output leakage current
Vo =19 V, Outn = OFF
IOH = - 1 mA
0.03
0.4
0.5
2
VDD-0.4
VDD = 3.3 V, VO = 0.3 V
Rext = 3.9 kΩ
8
VDD = 3.3 V, VO = 0.4 V
Rext = 980 Ω
4
ΔIOL3
VDD = 3.3 V, VO = 1.3 V
Rext = 200 Ω
4
ΔIOL2
VDD = 3.3 V, VO = 0.4 V
Rext = 980 Ω
6
VDD = 3.3 V, VO = 1.3 V
Rext = 200 Ω
6
ΔIOL1
ΔIOL2
ΔIOL3
Current accuracy channelto-channel (1) (2)
Current accuracy deviceto-device (1)
RIN(up)
Pull-up resistor for OE pin
150
300
600
RIN(down)
Pull-down resistor for LE
pin
100
200
400
R ext = 980 Ω, LE = low,
OUT0 to OUT7 = OFF
4
6.5
IDD(OFF2)
Rext = 200 Ω, LE = low,
OUT0 to OUT15 = OFF
11
16
IDD(ON1)
Rext = 980 Ω, LE = low,
OUT0 to OUT15 = ON
4.5
6.5
Rext = 200 Ω, LE = low,
OUT0 to OUT15 = ON
12
16
IDD(OFF1)
Supply current (OFF)
Supply current (ON)
IDD(ON2)
Tsd
Thermal shutdown (3)
170
2. ΔIOL+ = ((IOLmax - IOLmean)/ IOLmean)*100, ΔIOL- = ((IOLmin - IOLmean)/ IOLmean)*100, where IOLmean =
(IOLout1+IOLout2+…+IOLout16) / 16.
3. Not tested, guaranteed by design.
DocID024305 Rev 6
µA
%
kΩ
mA
1. Test performed with all outputs turned on, but only one output loaded at a time.
8/28
Unit
°C
STAP08DP05
5
Switching characteristics
Switching characteristics
VDD = 5 V, Tj = 25 °C, unless otherwise specified.
Table 8. Switching characteristics(1)(2)
Symbol
Parameter
Test conditions
fclk
Clock frequency
Cascade operation
tPLH1
tPLH2
tPLH3
tPLH
tPHL1
tPHL2
tPHL3
tPHL
CLK-OUTn
LE\DM1 = H
OE\DM2 = L
LE\DM1-OUTn
OE\DM2 = L
OE\DM2-OUTn
LE\DM1 = H
Min
Typ
Max
Unit
30
MHz
VDD = 3.3 V
36
50
VDD = 5 V
19
25
VDD = 3.3 V
38
50
VDD = 5 V
21
30
VDD = 3.3 V
42
55
VDD = 5 V
23
30
VDD = 3.3 V
22
30
VDD = 5 V
18
25
VDD = 3.3 V
9
12
VDD = 5 V
5
7
VDD = 3.3 V
4
6
VDD = 5 V
3
5
VDD = 3.3 V
6
8
VDD = 5 V
3
5
VDD = 3.3 V
25
33
VDD = 5 V
20
26
ns
ns
Propagation
delay time
(“L” to “H”)
ns
CLK - SDO
ns
CLK-OUTn
LE\DM1 = H
OE\DM2 = L
LE\DM1-OUTn
OE\DM2 = L
OE\DM2-OUTn
LE\DM1 = H
Propagation
delay time
(“H” to “L”)
VIH = VDD
VIL = GND
CL = 10 pF
Io = 20 mA
VL = 3 V
REXT = 1 KΩ
RL = 60 Ω
ns
ns
ns
CLK - SDO
ns
Output rise time
10~90% of voltage
waveform
VDD = 3.3 V
30
40
tON
VDD = 5 V
15
20
Output fall time
90~10% of voltage
waveform
VDD = 3.3 V
7
10
tOFF
VDD = 5 V
6
8
tr
CLK rise time (3)
5
tf
(3)
5
CLK fall time
ns
ns
µs
1. All table limits are guaranteed by design.
2. Not tested in production.
3. If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer
between two cascaded devices.
DocID024305 Rev 6
9/28
28
Equivalent circuit and outputs
6
STAP08DP05
Equivalent circuit and outputs
Figure 3. OE/DM2 terminal
$0Y
Figure 4. LE/DM1 terminal
$0Y
Figure 5. CLK, SDI terminal
$0Y
Figure 6. SDO terminal
9
''
WK67$*(
6'2
*1'
$0Y
10/28
DocID024305 Rev 6
STAP08DP05
Truth table and timing diagrams
7
Truth table and timing diagrams
7.1
Truth table
Table 9. Truth table
Clock
LE/DM1
OE/DM2
SDI
OUT0 ........ OUT0 ........ OUT7
SDO
H
L
Dn
Dn ..... Dn -5 ..... Dn -7
Dn -7
L
L
Dn + 1
No change
Dn -7
H
L
Dn + 2
Dn +2 ..... Dn -3 ..... Dn -5
Dn -5
X
L
Dn + 3
Dn +2 ..... Dn -3 ..... Dn -5
Dn -5
X
H
Dn + 3
OFF
Dn -5
Note:
OUT0 to OUT7 = ON when Dn = H; OUT0 to OUT7 = OFF when Dn = L.
7.2
Timing diagrams
Figure 7. Timing diagram - normal mode
DocID024305 Rev 6
11/28
28
Truth table and timing diagrams
STAP08DP05
Figure 8. Clock, serial-in, serial-out
Figure 9. Clock, serial-in, latch, enable, outputs
12/28
DocID024305 Rev 6
STAP08DP05
Truth table and timing diagrams
Figure 10. Outputs
$0Y
DocID024305 Rev 6
13/28
28
Typical characteristics
8
STAP08DP05
Typical characteristics
Figure 11. Output current - REXT resistor
8000
7000
Rext (Ohm)
6000
5000
4000
3000
2000
1000
0
0
10 20
30 40 50 60
70 80 90 100 110 120 130 140
Ouput current (mA)
TA = 25 °C, Vdrop = 0.3 V; 1.2 V, Iset = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA, Max
AM13673v1
Table 10. Output current - REXT resistor, TA = 25 °C
Parameter
Note:
14/28
Value
Output current (mA)
3
5
10
20
50
80
130
Rext (Ω)
6740
3930
1913
963
386
241
124
Maximum output current setting was 130 mA applying Rext = 124 Ω.
DocID024305 Rev 6
STAP08DP05
Typical characteristics
Figure 12. ISET vs. drop-out voltage (VDROP @ 25 °C)
910
810
Vdrop (mV)
710
610
Vdd 5.0V
Vdd 3.0V
510
410
310
210
110
10
0
10
20
30
40
50
60
70
80
90
100 110
Iset (mA)
Table 11. ISET vs. drop-out voltage (VDROP @ 25 °C)
Vdd
(V)
3
5
I set
(mA)
Rext
(Ω)
Vdrop min
(mV)
Vdrop max
(mV)
Vdrop AVG
(mV)
3
6470
30.6
31.2
30.93
5
3930
46.5
52.9
48.63
10
1910
80.9
100
82.26
20
963
150
161
157
50
386
392
396
394.3
80
241
636
646
640.3
100
192
846
850
848
3
6470
25.6
29
26.96
5
3930
40.8
41.7
41.16
10
1910
80.1
105
89.2
20
963
153
154
154
50
386
379
386
382
80
241
618
626
621
100
192
825
830
827
DocID024305 Rev 6
15/28
28
Typical characteristics
STAP08DP05
Figure 13. Power dissipation vs. package temperature
Note:
16/28
The exposed pad should be soldered to the PCB in order to derive the thermal benefits
(according to Jedec 51-7).
DocID024305 Rev 6
STAP08DP05
9
Test circuit
Test circuit
Figure 14. DC characteristics
Figure 15. AC characteristics
DocID024305 Rev 6
17/28
28
Test circuit
STAP08DP05
Figure 16. Timing example for open line and/or short detection
18/28
DocID024305 Rev 6
STAP08DP05
Detection mode functionality
10
Detection mode functionality
10.1
Phase one: “entering error detection mode“
From the “normal mode” condition the device can switch to “error detection mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins as shown in the following table and diagram.
Table 12. Entering error detection mode truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 17. Entering error detection mode timing diagram
After these five CLK cycles the device goes into the “error detection mode” and at the 6th
rising edge of CLK, the SDI data are ready for sampling.
DocID024305 Rev 6
19/28
28
Detection mode functionality
10.2
STAP08DP05
Phase two: “error detection mode“
The eight data bits must be set to “1” in order to set ON all the outputs during detection. The
data are latched by LE/DM1 and after that the outputs are ready for the detection process.
When the microcontroller switches OE/DM2 to LOW, the device drives the LEDs in order to
analyze if an OPEN or SHORT condition has occurred.
Figure 18. Detection diagram
The status of the LEDs will be detected in 1 microsecond (minimum) and after this time the
microcontroller sets OE\DM2 in HIGH state and the output data detection result will go to the
microprocessor via SDO.
Detection mode and normal mode both use the same data format. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status, the device must go back in normal mode and re-enter
error detection mode.
20/28
DocID024305 Rev 6
STAP08DP05
10.3
Detection mode functionality
Phase three: “resuming normal mode”
The sequence for re-entering normal mode is shown in the following table and diagram.
Table 13. Resuming normal mode truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
Figure 19. Resuming normal mode timing diagram
AM13661V1
Note:
For proper device operation the “entering error detection mode” sequence must be followed
by a “resume mode” sequence, it is not possible to insert consecutive equal sequences.
DocID024305 Rev 6
21/28
28
Detection mode functionality
10.4
STAP08DP05
Error detection conditions
VDD = 3.3 to 5 V temperature range 25 °C.
Table 14. Detection conditions
Configuration
Note:
Detect mode
Detection results
SW-1 or SW-3b
No error
Open line or output
==> IODEC ≤ 0.5 x IO
detected
short to GND detected
==> IODEC ≥ 0.5 x IO
SW-2 or SW-3a
Short on LED or short
==> VO ≥ 2.5V
to V-LED detected
==> VO ≤ 2.2 V
No error
detected
Where: IO = the output current programmed by the REXT, IODEC = the detected output
current in detection mode.
Figure 20. Detection circuit
V-LED
V-LED
SW-2
SW-3a
SW-3b
SW-1
OUT-0
1
2
3
4
5
STAP08DP05
AM13662V1
22/28
DocID024305 Rev 6
STAP08DP05
11
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
11.1
HTSSOP16 exposed pad package information
Figure 21. HTSSOP16 exposed pad package outline
DocID024305 Rev 6
23/28
28
Package information
STAP08DP05
Table 15. HTSSOP16 exposed pad mechanical data
(mm)
Dim.
Min.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
4.90
5.00
5.10
D1
2.8
3
3.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
2.8
3
3.2
e
L
k
1.00
1.05
0.65
0.45
L1
0.60
0.75
1.00
0.00
aaa
24/28
Typ.
8.00
0.10
DocID024305 Rev 6
STAP08DP05
11.2
Package information
HTSSOP16 exposed pad packing information
Figure 22. HTSSOP16 tape and reel outline
DocID024305 Rev 6
25/28
28
Package information
STAP08DP05
Table 16. HTSSOP16 tape and reel mechanical data
(mm)
Dim.
Min.
A
Max.
330
C
12.8
D
20.2
N
60
T
26/28
Typ.
13.2
22.4
Ao
6.7
6.9
Bo
5.3
5.5
Ko
1.6
1.8
Po
3.9
4.1
P
7.9
8.1
DocID024305 Rev 6
STAP08DP05
12
Revision history
Revision history
Table 17. Document revision history
Date
Revision
Changes
12-Mar-2013
1
First release.
01-Jul-2013
2
Added footnote in Table 8: Switching characteristics.
11-Oct-2013
3
Modified TOPR value in Table 4: Absolute maximum ratings.
07-Jan-2014
4
Updated the Description in cover page, tablefootnote in
Table 5: Thermal data, note in Figure 13: Power dissipation
vs. package temperature, Figure 3: OE/DM2 terminal,
Figure 4: LE/DM1 terminal, Figure 5: CLK, SDI terminal and
Figure 6: SDO terminal.
06-Mar-2014
5
Modified footnote 1 in Table 8: Switching characteristics.
Added footnote 2 in Table 8: Switching characteristics.
06-Nov-2015
6
Updated features in cover page.
Minor text changes.
DocID024305 Rev 6
27/28
28
STAP08DP05
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
28/28
DocID024305 Rev 6
Similar pages